// SPDX-License-Identifier: GPL-2.0 /* * r8a77470 Clock Pulse Generator / Module Standby and Software Reset * * Copyright (C) 2018 Renesas Electronics Corp. #include <linux/device.h>#include <linux/init.h>#include <linux/kernel.h>#include <linux/soc/renesas/rcar-rst.h>#include <dt-bindings/clock/r8a77470-cpg-mssr.h>#include "renesas-cpg-mssr.h" #include "rcar-gen2-cpg.h" enum clk_ids {/* Core Clock Outputs exported to DT */ /* External Input Clocks */ /* Internal Core Clocks */ /* Module Clocks */ static const struct cpg_core_clk r8a77470_core_clks[] __initconst = {/* External Clock Inputs */ "extal" , CLK_EXTAL),"usb_extal" , CLK_USB_EXTAL),/* Internal Core Clocks */ ".main" , CLK_MAIN, CLK_TYPE_GEN2_MAIN, CLK_EXTAL),".pll0" , CLK_PLL0, CLK_TYPE_GEN2_PLL0, CLK_MAIN),".pll1" , CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN),".pll3" , CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN),".pll1_div2" , CLK_PLL1_DIV2, CLK_PLL1, 2 , 1 ),/* Core Clock Outputs */ "sdh" , R8A77470_CLK_SDH, CLK_TYPE_GEN2_SDH, CLK_PLL1),"sd0" , R8A77470_CLK_SD0, CLK_TYPE_GEN2_SD0, CLK_PLL1),"sd1" , R8A77470_CLK_SD1, CLK_TYPE_GEN2_SD1, CLK_PLL1),"qspi" , R8A77470_CLK_QSPI, CLK_TYPE_GEN2_QSPI, CLK_PLL1_DIV2),"rcan" , R8A77470_CLK_RCAN, CLK_TYPE_GEN2_RCAN, CLK_USB_EXTAL),"z2" , R8A77470_CLK_Z2, CLK_PLL0, 1 , 1 ),"zx" , R8A77470_CLK_ZX, CLK_PLL1, 3 , 1 ),"zs" , R8A77470_CLK_ZS, CLK_PLL1, 6 , 1 ),"hp" , R8A77470_CLK_HP, CLK_PLL1, 12 , 1 ),"b" , R8A77470_CLK_B, CLK_PLL1, 12 , 1 ),"lb" , R8A77470_CLK_LB, CLK_PLL1, 24 , 1 ),"p" , R8A77470_CLK_P, CLK_PLL1, 24 , 1 ),"cl" , R8A77470_CLK_CL, CLK_PLL1, 48 , 1 ),"cp" , R8A77470_CLK_CP, CLK_PLL1, 48 , 1 ),"m2" , R8A77470_CLK_M2, CLK_PLL1, 8 , 1 ),"zb3" , R8A77470_CLK_ZB3, CLK_PLL3, 4 , 1 ),"mp" , R8A77470_CLK_MP, CLK_PLL1_DIV2, 15 , 1 ),"cpex" , R8A77470_CLK_CPEX, CLK_EXTAL, 2 , 1 ),"r" , R8A77470_CLK_R, CLK_PLL1, 49152 , 1 ),"osc" , R8A77470_CLK_OSC, CLK_PLL1, 12288 , 1 ),"sd2" , R8A77470_CLK_SD2, CLK_PLL1_DIV2, 0 x078),static const struct mssr_mod_clk r8a77470_mod_clks[] __initconst = {"msiof0" , 0 , R8A77470_CLK_MP),"vcp0" , 101 , R8A77470_CLK_ZS),"vpc0" , 103 , R8A77470_CLK_ZS),"tmu1" , 111 , R8A77470_CLK_P),"3dg" , 112 , R8A77470_CLK_ZS),"2d-dmac" , 115 , R8A77470_CLK_ZS),"fdp1-0" , 119 , R8A77470_CLK_ZS),"tmu3" , 121 , R8A77470_CLK_P),"tmu2" , 122 , R8A77470_CLK_P),"cmt0" , 124 , R8A77470_CLK_R),"vsp1du0" , 128 , R8A77470_CLK_ZS),"vsps" , 131 , R8A77470_CLK_ZS),"msiof2" , 205 , R8A77470_CLK_MP),"msiof1" , 208 , R8A77470_CLK_MP),"sys-dmac1" , 218 , R8A77470_CLK_ZS),"sys-dmac0" , 219 , R8A77470_CLK_ZS),"sdhi2" , 312 , R8A77470_CLK_SD2),"sdhi1" , 313 , R8A77470_CLK_SD1),"sdhi0" , 314 , R8A77470_CLK_SD0),"usbhs-dmac0-ch1" , 326 , R8A77470_CLK_HP),"usbhs-dmac1-ch1" , 327 , R8A77470_CLK_HP),"cmt1" , 329 , R8A77470_CLK_R),"usbhs-dmac0-ch0" , 330 , R8A77470_CLK_HP),"usbhs-dmac1-ch0" , 331 , R8A77470_CLK_HP),"rwdt" , 402 , R8A77470_CLK_R),"irqc" , 407 , R8A77470_CLK_CP),"intc-sys" , 408 , R8A77470_CLK_ZS),"audio-dmac0" , 502 , R8A77470_CLK_HP),"pwm" , 523 , R8A77470_CLK_P),"usb-ehci-0" , 703 , R8A77470_CLK_MP),"usbhs-0" , 704 , R8A77470_CLK_HP),"usb-ehci-1" , 705 , R8A77470_CLK_MP),"usbhs-1" , 706 , R8A77470_CLK_HP),"hscif2" , 713 , R8A77470_CLK_ZS),"scif5" , 714 , R8A77470_CLK_P),"scif4" , 715 , R8A77470_CLK_P),"hscif1" , 716 , R8A77470_CLK_ZS),"hscif0" , 717 , R8A77470_CLK_ZS),"scif3" , 718 , R8A77470_CLK_P),"scif2" , 719 , R8A77470_CLK_P),"scif1" , 720 , R8A77470_CLK_P),"scif0" , 721 , R8A77470_CLK_P),"du1" , 723 , R8A77470_CLK_ZX),"du0" , 724 , R8A77470_CLK_ZX),"ipmmu-sgx" , 800 , R8A77470_CLK_ZX),"etheravb" , 812 , R8A77470_CLK_HP),"ether" , 813 , R8A77470_CLK_P),"gpio5" , 907 , R8A77470_CLK_CP),"gpio4" , 908 , R8A77470_CLK_CP),"gpio3" , 909 , R8A77470_CLK_CP),"gpio2" , 910 , R8A77470_CLK_CP),"gpio1" , 911 , R8A77470_CLK_CP),"gpio0" , 912 , R8A77470_CLK_CP),"can1" , 915 , R8A77470_CLK_P),"can0" , 916 , R8A77470_CLK_P),"qspi_mod-1" , 917 , R8A77470_CLK_QSPI),"qspi_mod-0" , 918 , R8A77470_CLK_QSPI),"i2c4" , 927 , R8A77470_CLK_HP),"i2c3" , 928 , R8A77470_CLK_HP),"i2c2" , 929 , R8A77470_CLK_HP),"i2c1" , 930 , R8A77470_CLK_HP),"i2c0" , 931 , R8A77470_CLK_HP),"ssi-all" , 1005 , R8A77470_CLK_P),"ssi9" , 1006 , MOD_CLK_ID(1005 )),"ssi8" , 1007 , MOD_CLK_ID(1005 )),"ssi7" , 1008 , MOD_CLK_ID(1005 )),"ssi6" , 1009 , MOD_CLK_ID(1005 )),"ssi5" , 1010 , MOD_CLK_ID(1005 )),"ssi4" , 1011 , MOD_CLK_ID(1005 )),"ssi3" , 1012 , MOD_CLK_ID(1005 )),"ssi2" , 1013 , MOD_CLK_ID(1005 )),"ssi1" , 1014 , MOD_CLK_ID(1005 )),"ssi0" , 1015 , MOD_CLK_ID(1005 )),"scu-all" , 1017 , R8A77470_CLK_P),"scu-dvc1" , 1018 , MOD_CLK_ID(1017 )),"scu-dvc0" , 1019 , MOD_CLK_ID(1017 )),"scu-ctu1-mix1" , 1020 , MOD_CLK_ID(1017 )),"scu-ctu0-mix0" , 1021 , MOD_CLK_ID(1017 )),"scu-src6" , 1025 , MOD_CLK_ID(1017 )),"scu-src5" , 1026 , MOD_CLK_ID(1017 )),"scu-src4" , 1027 , MOD_CLK_ID(1017 )),"scu-src3" , 1028 , MOD_CLK_ID(1017 )),"scu-src2" , 1029 , MOD_CLK_ID(1017 )),"scu-src1" , 1030 , MOD_CLK_ID(1017 )),static const unsigned int r8a77470_crit_mod_clks[] __initconst = {402 ), /* RWDT */ 408 ), /* INTC-SYS (GIC) */ /* * CPG Clock Data /* * MD EXTAL PLL0 PLL1 PLL3 * 14 13 (MHz) *1 *2 *--------------------------------------------------- * 0 0 20 x80 x78 x50 * 0 1 26 x60 x60 x56 * 1 0 Prohibited setting * 1 1 30 x52 x52 x50 * * *1 : Table 7.4 indicates VCO output (PLL0 = VCO) * *2 : Table 7.4 indicates VCO output (PLL1 = VCO) #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14 )) >> 13 ) | \13 )) >> 13 ))static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[4 ] __initconst = {/* EXTAL div PLL1 mult x2 PLL3 mult */ 1 , 156 , 50 , },1 , 120 , 56 , },/* Invalid*/ }, 1 , 104 , 50 , },static int __init r8a77470_cpg_mssr_init(struct device *dev)const struct rcar_gen2_cpg_pll_config *cpg_pll_config;int error;if (error)return error;return rcar_gen2_cpg_init(cpg_pll_config, 2 , cpg_mode);const struct cpg_mssr_info r8a77470_cpg_mssr_info __initconst = {/* Core Clocks */ /* Module Clocks */ 12 * 32 ,/* Critical Module Clocks */ /* Callbacks */
Messung V0.5 in Prozent C=94 H=94 G=93
¤ Dauer der Verarbeitung: 0.10 Sekunden
(vorverarbeitet am 2026-06-06)
¤ *© Formatika GbR, Deutschland
