// SPDX-License-Identifier: GPL-2.0-only /* * Pistachio SoC clock controllers * * Copyright (C) 2014 Google, Inc. #include <linux/clk-provider.h>#include <linux/init.h>#include <linux/io.h>#include <linux/kernel.h>#include <linux/of.h>#include <dt-bindings/clock/pistachio-clk.h>#include "clk.h" static struct pistachio_gate pistachio_gates[] __initdata = {"mips" , "mips_div" , 0 x104, 0 ),"audio_in" , "audio_clk_in_gate" , 0 x104, 1 ),"audio" , "audio_div" , 0 x104, 2 ),"i2s" , "i2s_div" , 0 x104, 3 ),"spdif" , "spdif_div" , 0 x104, 4 ),"audio_dac" , "audio_dac_div" , 0 x104, 5 ),"rpu_v" , "rpu_v_div" , 0 x104, 6 ),"rpu_l" , "rpu_l_div" , 0 x104, 7 ),"rpu_sleep" , "rpu_sleep_div" , 0 x104, 8 ),"wifi_pll_gate" , "wifi_pll_mux" , 0 x104, 9 ),"rpu_core" , "rpu_core_div" , 0 x104, 10 ),"wifi_adc" , "wifi_div8_mux" , 0 x104, 11 ),"wifi_dac" , "wifi_div4_mux" , 0 x104, 12 ),"usb_phy" , "usb_phy_div" , 0 x104, 13 ),"enet_in" , "enet_clk_in_gate" , 0 x104, 14 ),"enet" , "enet_div" , 0 x104, 15 ),"uart0" , "uart0_div" , 0 x104, 16 ),"uart1" , "uart1_div" , 0 x104, 17 ),"periph_sys" , "sys_internal_div" , 0 x104, 18 ),"spi0" , "spi0_div" , 0 x104, 19 ),"spi1" , "spi1_div" , 0 x104, 20 ),"event_timer" , "event_timer_div" , 0 x104, 21 ),"aux_adc_internal" , "sys_internal_div" ,0 x104, 22 ),"aux_adc" , "aux_adc_div" , 0 x104, 23 ),"sd_host" , "sd_host_div" , 0 x104, 24 ),"bt" , "bt_div" , 0 x104, 25 ),"bt_div4" , "bt_div4_div" , 0 x104, 26 ),"bt_div8" , "bt_div8_div" , 0 x104, 27 ),"bt_1mhz" , "bt_1mhz_div" , 0 x104, 28 ),static struct pistachio_fixed_factor pistachio_ffs[] __initdata = {"wifi_div4" , "wifi_pll" , 4 ),"wifi_div8" , "wifi_pll" , 8 ),static struct pistachio_div pistachio_divs[] __initdata = {"mips_internal_div" , "mips_pll_mux" ,0 x204, 2 ),"mips_div" , "mips_internal_div" , 0 x208, 8 ),"audio_div" , "audio_mux" ,0 x20c, 8 , CLK_DIVIDER_ROUND_CLOSEST),"i2s_div" , "audio_pll_mux" ,0 x210, 8 , CLK_DIVIDER_ROUND_CLOSEST),"spdif_div" , "audio_pll_mux" ,0 x214, 8 , CLK_DIVIDER_ROUND_CLOSEST),"audio_dac_div" , "audio_pll_mux" ,0 x218, 8 , CLK_DIVIDER_ROUND_CLOSEST),"rpu_v_div" , "rpu_v_pll_mux" , 0 x21c, 2 ),"rpu_l_div" , "rpu_l_mux" , 0 x220, 2 ),"rpu_sleep_div" , "xtal" , 0 x224, 10 ),"rpu_core_div" , "rpu_core_mux" , 0 x228, 3 ),"usb_phy_div" , "sys_internal_div" , 0 x22c, 6 ),"enet_div" , "enet_mux" , 0 x230, 6 ),"uart0_internal_div" , "sys_pll_mux" ,0 x234, 3 , CLK_DIVIDER_ROUND_CLOSEST),"uart0_div" , "uart0_internal_div" , 0 x238, 10 ,"uart1_internal_div" , "sys_pll_mux" ,0 x23c, 3 , CLK_DIVIDER_ROUND_CLOSEST),"uart1_div" , "uart1_internal_div" , 0 x240, 10 ,"sys_internal_div" , "sys_pll_mux" , 0 x244, 3 ),"spi0_internal_div" , "sys_pll_mux" ,0 x248, 3 ),"spi0_div" , "spi0_internal_div" , 0 x24c, 7 ),"spi1_internal_div" , "sys_pll_mux" ,0 x250, 3 ),"spi1_div" , "spi1_internal_div" , 0 x254, 7 ),"event_timer_internal_div" ,"event_timer_mux" , 0 x258, 3 ),"event_timer_div" , "event_timer_internal_div" ,0 x25c, 12 ),"aux_adc_internal_div" ,"aux_adc_internal" , 0 x260, 3 ),"aux_adc_div" , "aux_adc_internal_div" , 0 x264, 10 ),"sd_host_div" , "sd_host_mux" , 0 x268, 6 ),"bt_div" , "bt_pll_mux" , 0 x26c, 6 ),"bt_div4_div" , "bt_pll_mux" , 0 x270, 6 ),"bt_div8_div" , "bt_pll_mux" , 0 x274, 6 ),"bt_1mhz_internal_div" , "bt_pll_mux" ,0 x278, 3 ),"bt_1mhz_div" , "bt_1mhz_internal_div" , 0 x27c, 10 ),"xtal" , "audio_clk_in_gate" };"xtal" , "mips_pll" };"xtal" , "audio_pll" , "audio_in" };"audio_pll_mux" , "debug_mux" };"xtal" , "rpu_v_pll" };"xtal" , "rpu_l_pll" };"rpu_l_pll_mux" , "mips_pll_mux" };"xtal" , "wifi_pll" };"xtal" , "wifi_div4" };"xtal" , "wifi_div8" };"wifi_pll_gate" , "wifi_div4_mux" ,"rpu_l_pll_mux" };"xtal" , "sys_pll" };"sys_internal_div" , "enet_in" };"audio_pll_mux" , "sys_internal_div" };"sys_internal_div" , "bt_pll_mux" };"xtal" , "bt_pll" };static struct pistachio_mux pistachio_muxes[] __initdata = {"audio_refclk_mux" , mux_xtal_audio_refclk,0 x200, 0 ),"mips_pll_mux" , mux_xtal_mips, 0 x200, 1 ),"audio_pll_mux" , mux_xtal_audio, 0 x200, 2 ),"audio_mux" , mux_audio_debug, 0 x200, 4 ),"rpu_v_pll_mux" , mux_xtal_rpu_v, 0 x200, 5 ),"rpu_l_pll_mux" , mux_xtal_rpu_l, 0 x200, 6 ),"rpu_l_mux" , mux_rpu_l_mips, 0 x200, 7 ),"wifi_pll_mux" , mux_xtal_wifi, 0 x200, 8 ),"wifi_div4_mux" , mux_xtal_wifi_div4, 0 x200, 9 ),"wifi_div8_mux" , mux_xtal_wifi_div8, 0 x200, 10 ),"rpu_core_mux" , mux_wifi_div4_rpu_l, 0 x200, 11 ),"sys_pll_mux" , mux_xtal_sys, 0 x200, 13 ),"enet_mux" , mux_sys_enet, 0 x200, 14 ),"event_timer_mux" , mux_audio_sys, 0 x200, 15 ),"sd_host_mux" , mux_sys_bt, 0 x200, 16 ),"bt_pll_mux" , mux_xtal_bt, 0 x200, 17 ),static struct pistachio_pll pistachio_plls[] __initdata = {"mips_pll" , "xtal" , PLL_GF40LP_LAINT, 0 x0),"audio_pll" , "audio_refclk_mux" ,0 xc),"rpu_v_pll" , "xtal" , PLL_GF40LP_LAINT, 0 x20),"rpu_l_pll" , "xtal" , PLL_GF40LP_LAINT, 0 x2c),"sys_pll" , "xtal" , PLL_GF40LP_FRAC, 0 x38),"wifi_pll" , "xtal" , PLL_GF40LP_FRAC, 0 x4c),"bt_pll" , "xtal" , PLL_GF40LP_LAINT, 0 x60),"mips_pll_mux" , "rpu_v_pll_mux" ,"rpu_l_pll_mux" , "sys_pll_mux" ,"wifi_pll_mux" , "bt_pll_mux" };static const u32 mux_debug_idx[] = { 0 x0, 0 x1, 0 x2, 0 x4, 0 x8, 0 x10 };static unsigned int pistachio_critical_clks_core[] __initdata = {static unsigned int pistachio_critical_clks_sys[] __initdata = {static void __init pistachio_clk_init(struct device_node *np)struct pistachio_clk_provider *p;struct clk *debug_clk;if (!p)return ;"debug_mux" , mux_debug,0 x200, 18 , 0 x1f, 0 ,"img,pistachio-clk" , pistachio_clk_init);static struct pistachio_gate pistachio_periph_gates[] __initdata = {"sys" , "periph_sys" , 0 x100, 0 ),"bus_sys" , "periph_sys" , 0 x100, 1 ),"ddr" , "periph_sys" , 0 x100, 2 ),"rom" , "rom_div" , 0 x100, 3 ),"counter_fast" , "counter_fast_div" ,0 x100, 4 ),"counter_slow" , "counter_slow_div" ,0 x100, 5 ),"ir" , "ir_div" , 0 x100, 6 ),"wd" , "wd_div" , 0 x100, 7 ),"pdm" , "pdm_div" , 0 x100, 8 ),"pwm" , "pwm_div" , 0 x100, 9 ),"i2c0" , "i2c0_div" , 0 x100, 10 ),"i2c1" , "i2c1_div" , 0 x100, 11 ),"i2c2" , "i2c2_div" , 0 x100, 12 ),"i2c3" , "i2c3_div" , 0 x100, 13 ),static struct pistachio_div pistachio_periph_divs[] __initdata = {"rom_div" , "periph_sys" , 0 x10c, 7 ),"counter_fast_div" , "periph_sys" ,0 x110, 7 ),"counter_slow_pre_div" ,"periph_sys" , 0 x114, 7 ),"counter_slow_div" ,"counter_slow_pre_div" , 0 x118, 7 ),"ir_pre_div" , "periph_sys" , 0 x11c, 7 ,"ir_div" , "ir_pre_div" , 0 x120, 7 ,"wd_pre_div" , "periph_sys" , 0 x124, 7 ,"wd_div" , "wd_pre_div" , 0 x128, 7 ,"pdm_pre_div" , "periph_sys" , 0 x12c, 7 ),"pdm_div" , "pdm_pre_div" , 0 x130, 7 ),"pwm_pre_div" , "periph_sys" , 0 x134, 7 ),"pwm_div" , "pwm_pre_div" , 0 x138, 7 ),"i2c0_pre_div" , "periph_sys" , 0 x13c, 7 ),"i2c0_div" , "i2c0_pre_div" , 0 x140, 7 ),"i2c1_pre_div" , "periph_sys" , 0 x144, 7 ),"i2c1_div" , "i2c1_pre_div" , 0 x148, 7 ),"i2c2_pre_div" , "periph_sys" , 0 x14c, 7 ),"i2c2_div" , "i2c2_pre_div" , 0 x150, 7 ),"i2c3_pre_div" , "periph_sys" , 0 x154, 7 ),"i2c3_div" , "i2c3_pre_div" , 0 x158, 7 ),static void __init pistachio_clk_periph_init(struct device_node *np)struct pistachio_clk_provider *p;if (!p)return ;"img,pistachio-clk-periph" ,static struct pistachio_gate pistachio_sys_gates[] __initdata = {"i2c0_sys" , "sys" , 0 x8, 0 ),"i2c1_sys" , "sys" , 0 x8, 1 ),"i2c2_sys" , "sys" , 0 x8, 2 ),"i2c3_sys" , "sys" , 0 x8, 3 ),"i2s_in_sys" , "sys" , 0 x8, 4 ),"paud_out_sys" , "sys" , 0 x8, 5 ),"spdif_out_sys" , "sys" , 0 x8, 6 ),"spi0_master_sys" , "sys" , 0 x8, 7 ),"spi0_slave_sys" , "sys" , 0 x8, 8 ),"pwm_sys" , "sys" , 0 x8, 9 ),"uart0_sys" , "sys" , 0 x8, 10 ),"uart1_sys" , "sys" , 0 x8, 11 ),"spi1_sys" , "sys" , 0 x8, 12 ),"mdc_sys" , "sys" , 0 x8, 13 ),"sd_host_sys" , "sys" , 0 x8, 14 ),"enet_sys" , "sys" , 0 x8, 15 ),"ir_sys" , "sys" , 0 x8, 16 ),"wd_sys" , "sys" , 0 x8, 17 ),"timer_sys" , "sys" , 0 x8, 18 ),"i2s_out_sys" , "sys" , 0 x8, 24 ),"spdif_in_sys" , "sys" , 0 x8, 25 ),"event_timer_sys" , "sys" , 0 x8, 26 ),"hash_sys" , "sys" , 0 x8, 27 ),static void __init pistachio_cr_periph_init(struct device_node *np)struct pistachio_clk_provider *p;if (!p)return ;"img,pistachio-cr-periph" ,static struct pistachio_gate pistachio_ext_gates[] __initdata = {"enet_clk_in_gate" , "enet_clk_in" , 0 x58, 5 ),"audio_clk_in_gate" , "audio_clk_in" , 0 x58, 8 )static void __init pistachio_cr_top_init(struct device_node *np)struct pistachio_clk_provider *p;if (!p)return ;"img,pistachio-cr-top" ,
Messung V0.5 in Prozent C=96 H=100 G=97
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(vorverarbeitet am 2026-06-07)
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