// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2022 MediaTek Inc. * Author: Garmin Chang <garmin.chang@mediatek.com> #include <linux/clk-provider.h>#include <linux/mod_devicetable.h>#include <linux/platform_device.h>#include <dt-bindings/clock/mediatek,mt8188-clk.h>#include "clk-gate.h" #include "clk-mtk.h" static const struct mtk_gate_regs vdo1_0_cg_regs = {static const struct mtk_gate_regs vdo1_1_cg_regs = {static const struct mtk_gate_regs vdo1_2_cg_regs = {static const struct mtk_gate_regs vdo1_3_cg_regs = {static const struct mtk_gate_regs vdo1_4_cg_regs = {static const struct mtk_gate_regs vdo1_5_cg_regs = {#define GATE_VDO1_0(_id, _name, _parent, _shift) \#define GATE_VDO1_1(_id, _name, _parent, _shift) \#define GATE_VDO1_2(_id, _name, _parent, _shift) \#define GATE_VDO1_3(_id, _name, _parent, _shift) \#define GATE_VDO1_3_FLAGS(_id, _name, _parent, _shift, _flags) \#define GATE_VDO1_4(_id, _name, _parent, _shift) \#define GATE_VDO1_5(_id, _name, _parent, _shift) \static const struct mtk_gate vdo1_clks[] = {/* VDO1_0 */ "vdo1_smi_larb2" , "top_vpp" , 0),"vdo1_smi_larb3" , "top_vpp" , 1),"vdo1_gals" , "top_vpp" , 2),"vdo1_fake_eng0" , "top_vpp" , 3),"vdo1_fake_eng1" , "top_vpp" , 4),"vdo1_mdp_rdma0" , "top_vpp" , 5),"vdo1_mdp_rdma1" , "top_vpp" , 6),"vdo1_mdp_rdma2" , "top_vpp" , 7),"vdo1_mdp_rdma3" , "top_vpp" , 8),"vdo1_vpp_merge0" , "top_vpp" , 9),"vdo1_vpp_merge1" , "top_vpp" , 10),"vdo1_vpp_merge2" , "top_vpp" , 11),/* VDO1_1 */ "vdo1_vpp_merge3" , "top_vpp" , 0),"vdo1_vpp_merge4" , "top_vpp" , 1),"vdo1_vpp2_to_vdo1_dl_async" , "top_vpp" , 2),"vdo1_vpp3_to_vdo1_dl_async" , "top_vpp" , 3),"vdo1_disp_mutex" , "top_vpp" , 4),"vdo1_mdp_rdma4" , "top_vpp" , 5),"vdo1_mdp_rdma5" , "top_vpp" , 6),"vdo1_mdp_rdma6" , "top_vpp" , 7),"vdo1_mdp_rdma7" , "top_vpp" , 8),"vdo1_dp_intf0_mmck" , "top_vpp" , 9),"vdo1_dpi0_mm_ck" , "top_vpp" , 10),"vdo1_dpi1_mm_ck" , "top_vpp" , 11),"vdo1_merge0_dl_async" , "top_vpp" , 13),"vdo1_merge1_dl_async" , "top_vpp" , 14),"vdo1_merge2_dl_async" , "top_vpp" , 15),"vdo1_merge3_dl_async" , "top_vpp" , 16),"vdo1_merge4_dl_async" , "top_vpp" , 17),"vdo1_dsc_vdo1_dl_async" , "top_vpp" , 18),"vdo1_merge_vdo1_dl_async" , "top_vpp" , 19),"vdo1_padding0" , "top_vpp" , 20),"vdo1_padding1" , "top_vpp" , 21),"vdo1_padding2" , "top_vpp" , 22),"vdo1_padding3" , "top_vpp" , 23),"vdo1_padding4" , "top_vpp" , 24),"vdo1_padding5" , "top_vpp" , 25),"vdo1_padding6" , "top_vpp" , 26),"vdo1_padding7" , "top_vpp" , 27),"vdo1_disp_rsz0" , "top_vpp" , 28),"vdo1_disp_rsz1" , "top_vpp" , 29),"vdo1_disp_rsz2" , "top_vpp" , 30),"vdo1_disp_rsz3" , "top_vpp" , 31),/* VDO1_2 */ "vdo1_hdr_vdo_fe0" , "top_vpp" , 0),"vdo1_hdr_gfx_fe0" , "top_vpp" , 1),"vdo1_hdr_vdo_be" , "top_vpp" , 2),"vdo1_hdr_vdo_fe1" , "top_vpp" , 16),"vdo1_hdr_gfx_fe1" , "top_vpp" , 17),"vdo1_disp_mixer" , "top_vpp" , 18),"vdo1_hdr_vdo_fe0_dl_async" , "top_vpp" , 19),"vdo1_hdr_vdo_fe1_dl_async" , "top_vpp" , 20),"vdo1_hdr_gfx_fe0_dl_async" , "top_vpp" , 21),"vdo1_hdr_gfx_fe1_dl_async" , "top_vpp" , 22),"vdo1_hdr_vdo_be_dl_async" , "top_vpp" , 23),/* VDO1_3 */ "vdo1_dpi0_ck" , "top_vpp" , 0),"vdo1_disp_monitor_dpi0_ck" , "top_vpp" , 1),"vdo1_dpi1_ck" , "top_vpp" , 8),"vdo1_disp_monitor_dpi1_ck" , "top_vpp" , 9),"vdo1_dpintf" , "top_dp" , 16, CLK_SET_RATE_PARENT),"vdo1_disp_monitor_dpintf_ck" , "top_vpp" , 17),/* VDO1_4 */ "vdo1_26m_slow_ck" , "clk26m" , 8),/* VDO1_5 */ "vdo1_dpi1_hdmi" , "hdmi_txpll" , 0),static const struct mtk_clk_desc vdo1_desc = {static const struct platform_device_id clk_mt8188_vdo1_id_table[] = {"clk-mt8188-vdo1" , .driver_data = (kernel_ulong_t)&vdo1_desc },/* sentinel */ } static struct platform_driver clk_mt8188_vdo1_drv = {"clk-mt8188-vdo1" ,"MediaTek MT8188 Video Output 1 clocks driver" );"GPL" );
Messung V0.5 C=98 H=92 G=94
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