// SPDX-License-Identifier: GPL-2.0-or-later /* * ata_piix.c - Intel PATA/SATA controllers * * Maintained by: Tejun Heo <tj@kernel.org> * Please ALWAYS copy linux-ide@vger.kernel.org * on emails. * * Copyright 2003-2005 Red Hat Inc * Copyright 2003-2005 Jeff Garzik * * Copyright header from piix.c: * * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org> * Copyright (C) 2003 Red Hat Inc * * libata documentation is available via 'make {ps|pdf}docs', * as Documentation/driver-api/libata.rst * * Hardware documentation available at http://developer.intel.com/ * * Documentation * Publicly available from Intel web site. Errata documentation * is also publicly available. As an aide to anyone hacking on this * driver the list of errata that are relevant is below, going back to * PIIX4. Older device documentation is now a bit tricky to find. * * The chipsets all follow very much the same design. The original Triton * series chipsets do _not_ support independent device timings, but this * is fixed in Triton II. With the odd mobile exception the chips then * change little except in gaining more modes until SATA arrives. This * driver supports only the chips with independent timing (that is those * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix * for the early chip drivers. * * Errata of note: * * Unfixable * PIIX4 errata #9 - Only on ultra obscure hw * ICH3 errata #13 - Not observed to affect real hw * by Intel * * Things we must deal with * PIIX4 errata #10 - BM IDE hang with non UDMA * (must stop/start dma to recover) * 440MX errata #15 - As PIIX4 errata #10 * PIIX4 errata #15 - Must not read control registers * during a PIO transfer * 440MX errata #13 - As PIIX4 errata #15 * ICH2 errata #21 - DMA mode 0 doesn't work right * ICH0/1 errata #55 - As ICH2 errata #21 * ICH2 spec c #9 - Extra operations needed to handle * drive hotswap [NOT YET SUPPORTED] * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary * and must be dword aligned * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3 * ICH7 errata #16 - MWDMA1 timings are incorrect * * Should have been BIOS fixed: * 450NX: errata #19 - DMA hangs on old 450NX * 450NX: errata #20 - DMA hangs on old 450NX * 450NX: errata #25 - Corruption with DMA on old 450NX * ICH3 errata #15 - IDE deadlock under high load * (BIOS must set dev 31 fn 0 bit 23) * ICH3 errata #18 - Don't use native mode
*/
enum piix_controller_ids { /* controller IDs */
piix_pata_mwdma, /* PIIX3 MWDMA only */
piix_pata_33, /* PIIX4 at 33Mhz */
ich_pata_33, /* ICH up to UDMA 33 only */
ich_pata_66, /* ICH up to 66 Mhz */
ich_pata_100, /* ICH up to UDMA 100 */
ich_pata_100_nomwdma1, /* ICH up to UDMA 100 but with no MWDMA1*/
ich5_sata,
ich6_sata,
ich6m_sata,
ich8_sata,
ich8_2port_sata,
ich8m_apple_sata, /* locks up on second port enable */
tolapai_sata,
piix_pata_vmw, /* PIIX4 for VMware, spurious DMA_ERR */
ich8_sata_snb,
ich8_2port_sata_snb,
ich8_2port_sata_byt,
};
/* Map 01b isn't specified in the doc but some notebooks use * it anyway. MAP 01b have been spotted on both ICH6M and * ICH7M.
*/
.map = { /* PM PS SM SS MAP */
{ P0, P2, NA, NA }, /* 00b */
{ IDE, IDE, P1, P3 }, /* 01b */
{ P0, P2, IDE, IDE }, /* 10b */
{ RV, RV, RV, RV },
},
};
MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
MODULE_VERSION(DRV_VERSION);
/** * ich_pata_cable_detect - Probe host controller cable detect info * @ap: Port for which cable detect info is desired * * Read 80c cable indicator from ATA PCI device's PCI config * register. This register is normally set by firmware (BIOS). * * LOCKING: * None (inherited from caller).
*/
if (pio >= 2)
control |= 1; /* TIME1 enable */ if (ata_pio_need_iordy(adev))
control |= 2; /* IE enable */ /* Intel specifies that the PPE functionality is for disk only */ if (adev->class == ATA_DEV_ATA)
control |= 4; /* PPE enable */ /* * If the drive MWDMA is faster than it can do PIO then * we must force PIO into PIO0
*/ if (adev->pio_mode < XFER_PIO_0 + pio) /* Enable DMA timing only */
control |= 8; /* PIO cycles in PIO0 */
spin_lock_irqsave(&piix_lock, flags);
/* PIO configuration clears DTE unconditionally. It will be * programmed in set_dmamode which is guaranteed to be called * after set_piomode if any DMA mode is available.
*/
pci_read_config_word(dev, master_port, &master_data); if (is_slave) { /* clear TIME1|IE1|PPE1|DTE1 */
master_data &= 0xff0f; /* enable PPE1, IE1 and TIME1 as needed */
master_data |= (control << 4);
pci_read_config_byte(dev, slave_port, &slave_data);
slave_data &= (ap->port_no ? 0x0f : 0xf0); /* Load the timing nibble for this slave */
slave_data |= ((timings[pio][0] << 2) | timings[pio][1])
<< (ap->port_no ? 4 : 0);
} else { /* clear ISP|RCT|TIME0|IE0|PPE0|DTE0 */
master_data &= 0xccf0; /* Enable PPE, IE and TIME as appropriate */
master_data |= control; /* load ISP and RCT */
master_data |=
(timings[pio][0] << 12) |
(timings[pio][1] << 8);
}
/** * piix_set_piomode - Initialize host controller PATA PIO timings * @ap: Port whose timings we are configuring * @adev: Drive in question * * Set PIO mode for device, in host controller PCI config space. * * LOCKING: * None (inherited from caller).
*/
/** * do_pata_set_dmamode - Initialize host controller PATA PIO timings * @ap: Port whose timings we are configuring * @adev: Drive in question * @isich: set if the chip is an ICH device * * Set UDMA mode for device, in host controller PCI config space. * * LOCKING: * None (inherited from caller).
*/
if (isich) { /* Select a 33/66/100Mhz clock */
pci_read_config_word(dev, 0x54, &ideconf);
ideconf &= ~(0x1001 << devid);
ideconf |= u_clock << devid; /* For ICH or later we should set bit 10 for better
performance (WR_PingPong_En) */
pci_write_config_word(dev, 0x54, ideconf);
}
pci_write_config_byte(dev, 0x48, udma_enable);
spin_unlock_irqrestore(&piix_lock, flags);
} else { /* MWDMA is driven by the PIO timings. */ unsignedint mwdma = speed - XFER_MW_DMA_0; constunsignedint needed_pio[3] = {
XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
}; int pio = needed_pio[mwdma] - XFER_PIO_0;
/* XFER_PIO_0 is never used currently */
piix_set_timings(ap, adev, pio);
}
}
/** * piix_set_dmamode - Initialize host controller PATA DMA timings * @ap: Port whose timings we are configuring * @adev: um * * Set MW/UDMA mode for device, in host controller PCI config space. * * LOCKING: * None (inherited from caller).
*/
/* * Serial ATA Index/Data Pair Superset Registers access * * Beginning from ICH8, there's a sane way to access SCRs using index * and data register pair located at BAR5 which means that we have * separate SCRs for master and slave. This is handled using libata * slave_link facility.
*/ staticconstint piix_sidx_map[] = {
[SCR_STATUS] = 0,
[SCR_ERROR] = 2,
[SCR_CONTROL] = 1,
};
/* TECRA M4 sometimes forgets its identify and reports bogus * DMI information. As the bogus information is a bit * generic, match as many entries as possible. This manual * matching is necessary because dmi_system_id.matches is * limited to four entries.
*/ if (dmi_match(DMI_SYS_VENDOR, "TOSHIBA") &&
dmi_match(DMI_PRODUCT_NAME, "000000") &&
dmi_match(DMI_PRODUCT_VERSION, "000000") &&
dmi_match(DMI_PRODUCT_SERIAL, "000000") &&
dmi_match(DMI_BOARD_VENDOR, "TOSHIBA") &&
dmi_match(DMI_BOARD_NAME, "Portable PC") &&
dmi_match(DMI_BOARD_VERSION, "Version A0")) return1;
/* Some braindamaged ACPI suspend implementations expect the * controller to be awake on entry; otherwise, it burns cpu * cycles and power trying to do something to the sleeping * beauty.
*/ if (piix_broken_suspend() && (mesg.event & PM_EVENT_SLEEP)) {
pci_save_state(pdev);
/* mark its power state as "unknown", since we don't * know if e.g. the BIOS will change its device state * when we suspend.
*/ if (pdev->current_state == PCI_D0)
pdev->current_state = PCI_UNKNOWN;
/* tell resume that it's waking up from broken suspend */
spin_lock_irqsave(&host->lock, flags);
host->flags |= PIIX_HOST_BROKEN_SUSPEND;
spin_unlock_irqrestore(&host->lock, flags);
} else
ata_pci_device_do_suspend(pdev, mesg);
/** * piix_check_450nx_errata - Check for problem 450NX setup * @ata_dev: the PCI device to check * * Check for the present of 450NX errata #19 and errata #25. If * they are found return an error code so we can turn off DMA
*/
while ((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL) { /* Look for 450NX PXB. Check for problem configurations
A PCI quirk checks bit 6 already */
pci_read_config_word(pdev, 0x41, &cfg); /* Only on the original revision: IDE DMA can hang */ if (pdev->revision == 0x00)
no_piix_dma = 1; /* On all revisions below 5 PXB bus lock must be disabled for IDE */ elseif (cfg & (1<<14) && pdev->revision < 5)
no_piix_dma = 2;
} if (no_piix_dma)
dev_warn(&ata_dev->dev, "450NX errata present, disabling IDE DMA%s\n",
no_piix_dma == 2 ? " - a BIOS update may resolve this"
: "");
/* * Samsung DB-P70 only has three ATA ports exposed and * curiously the unconnected first port reports link online * while not responding to SRST protocol causing excessive * detection delay. * * Unfortunately, the system doesn't carry enough DMI * information to identify the machine but does have subsystem * vendor and device set. As it's unclear whether the * subsystem vendor/device is used only for this specific * board, the port can't be disabled solely with the * information; however, turning off SIDPR access works around * the problem. Turn it off. * * This problem is reported in bnc#441240. * * https://bugzilla.novell.com/show_bug.cgi?id=441420
*/ if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2920 &&
pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG &&
pdev->subsystem_device == 0xb049) {
dev_warn(host->dev, "Samsung DB-P70 detected, disabling SIDPR\n"); returntrue;
}
/* SCR access via SIDPR doesn't work on some configurations. * Give it a test drive by inhibiting power save modes which * we'll do anyway.
*/
piix_sidpr_scr_read(link0, SCR_CONTROL, &scontrol);
/* if IPM is already 3, SCR access is probably working. Don't * un-inhibit power save modes as BIOS might have inhibited * them for a reason.
*/ if ((scontrol & 0xf00) != 0x300) {
scontrol |= 0x300;
piix_sidpr_scr_write(link0, SCR_CONTROL, scontrol);
piix_sidpr_scr_read(link0, SCR_CONTROL, &scontrol);
if ((scontrol & 0xf00) != 0x300) {
dev_info(host->dev, "SCR access via SIDPR is available but doesn't work\n"); return0;
}
}
/* okay, SCRs available, set ops and ask libata for slave_link */ for (i = 0; i < 2; i++) { struct ata_port *ap = host->ports[i];
ap->ops = &piix_sidpr_sata_ops;
if (ap->flags & ATA_FLAG_SLAVE_POSS) {
rc = ata_slave_link_init(ap); if (rc) return rc;
}
}
return0;
}
staticvoid piix_iocfg_bit18_quirk(struct ata_host *host)
{ staticconststruct dmi_system_id sysids[] = {
{ /* Clevo M570U sets IOCFG bit 18 if the cdrom * isn't used to boot the system which * disables the channel.
*/
.ident = "M570U",
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "Clevo Co."),
DMI_MATCH(DMI_PRODUCT_NAME, "M570U"),
},
},
/* The datasheet says that bit 18 is NOOP but certain systems * seem to use it to disable a channel. Clear the bit on the * affected systems.
*/ if (hpriv->saved_iocfg & (1 << 18)) {
dev_info(&pdev->dev, "applying IOCFG bit18 quirk\n");
pci_write_config_dword(pdev, PIIX_IOCFG,
hpriv->saved_iocfg & ~(1 << 18));
}
}
if (dmi) { unsignedlong slot = (unsignedlong)dmi->driver_data; /* apply the quirk only to on-board controllers */ return slot == PCI_SLOT(pdev->devfn);
}
returnfalse;
}
staticint prefer_ms_hyperv = 1;
module_param(prefer_ms_hyperv, int, 0);
MODULE_PARM_DESC(prefer_ms_hyperv, "Prefer Hyper-V paravirtualization drivers instead of ATA, " "0 - Use ATA drivers, " "1 (Default) - Use the paravirtualization drivers.");
staticvoid piix_ignore_devices_quirk(struct ata_host *host)
{ #if IS_ENABLED(CONFIG_HYPERV_STORAGE) staticconststruct dmi_system_id ignore_hyperv[] = {
{ /* On Hyper-V hypervisors the disks are exposed on * both the emulated SATA controller and on the * paravirtualised drivers. The CD/DVD devices * are only exposed on the emulated controller. * Request we ignore ATA devices on this host.
*/
.ident = "Hyper-V Virtual Machine",
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "Microsoft Corporation"),
DMI_MATCH(DMI_PRODUCT_NAME, "Virtual Machine"),
},
},
{ } /* terminate list */
}; staticconststruct dmi_system_id allow_virtual_pc[] = {
{ /* In MS Virtual PC guests the DMI ident is nearly * identical to a Hyper-V guest. One difference is the * product version which is used here to identify * a Virtual PC guest. This entry allows ata_piix to * drive the emulated hardware.
*/
.ident = "MS Virtual PC 2007",
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "Microsoft Corporation"),
DMI_MATCH(DMI_PRODUCT_NAME, "Virtual Machine"),
DMI_MATCH(DMI_PRODUCT_VERSION, "VS2005R2"),
},
},
{ } /* terminate list */
}; conststruct dmi_system_id *ignore = dmi_first_match(ignore_hyperv); conststruct dmi_system_id *allow = dmi_first_match(allow_virtual_pc);
/** * piix_init_one - Register PIIX ATA PCI device with kernel services * @pdev: PCI device to register * @ent: Entry in piix_pci_tbl matching with @pdev * * Called from kernel PCI layer. We probe for combined mode (sigh), * and then hand over control to libata, for it to do the rest. * * LOCKING: * Inherited from PCI layer (may sleep). * * RETURNS: * Zero on success, or -ERRNO value.
*/
/* enable device and prepare host */
rc = pcim_enable_device(pdev); if (rc) return rc;
hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL); if (!hpriv) return -ENOMEM;
/* Save IOCFG, this will be used for cable detection, quirk * detection and restoration on detach. This is necessary * because some ACPI implementations mess up cable related * bits on _STM. Reported on kernel bz#11879.
*/
pci_read_config_dword(pdev, PIIX_IOCFG, &hpriv->saved_iocfg);
/* ICH6R may be driven by either ata_piix or ahci driver * regardless of BIOS configuration. Make sure AHCI mode is * off.
*/ if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2652) {
rc = piix_disable_ahci(pdev); if (rc) return rc;
}
/* SATA map init can change port_info, do it before prepping host */ if (port_flags & ATA_FLAG_SATA)
hpriv->map = piix_init_sata_map(pdev, port_info,
piix_map_db_table[ent->driver_data]);
/* On ICH5, some BIOSen disable the interrupt using the * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3. * On ICH6, this bit has the same effect, but only when * MSI is disabled (and it is disabled, as we don't use * message-signalled interrupts currently).
*/ if (port_flags & PIIX_FLAG_CHECKINTR)
pcim_intx(pdev, 1);
if (piix_check_450nx_errata(pdev)) { /* This writes into the master table but it does not really matter for this errata as we will apply it to
all the PIIX devices on the board */
host->ports[0]->mwdma_mask = 0;
host->ports[0]->udma_mask = 0;
host->ports[1]->mwdma_mask = 0;
host->ports[1]->udma_mask = 0;
}
host->flags |= ATA_HOST_PARALLEL_SCAN;
/* Allow hosts to specify device types to ignore when scanning. */
piix_ignore_devices_quirk(host);
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