/* Within the user mapped array, decoder entries start post all the ARC related * entries
*/ #define USR_MAPPED_BLK_DEC_START_IDX \
(NUM_ARC_CPUS + NUM_OF_USER_ACP_BLOCKS + \
(NIC_NUMBER_OF_ENGINES * NUM_OF_USER_NIC_UMR_BLOCKS))
/* * HBM virtual address space * Gaudi2 has 6 HBM devices, each supporting 16GB total of 96GB at most. * No core separation is supported so we can have one chunk of virtual address * space just above the physical ones. * The virtual address space starts immediately after the end of the physical * address space which is determined at run-time.
*/ #define VA_HBM_SPACE_END 0x1002000000000000ull
/* * Gaudi2 subtitute TPCs Numbering * At most- two faulty TPCs are allowed * First replacement to a faulty TPC will be TPC24, second- TPC23
*/ enum substitude_tpc {
FAULTY_TPC_SUBTS_1_TPC_24,
FAULTY_TPC_SUBTS_2_TPC_23,
MAX_FAULTY_TPCS
};
/* User interrupt count is aligned with HW CQ count. * We have 64 CQ's per dcore, CQ0 in dcore 0 is reserved for legacy mode
*/ #define GAUDI2_NUM_USER_INTERRUPTS 64 #define GAUDI2_NUM_RESERVED_INTERRUPTS 1 #define GAUDI2_TOTAL_USER_INTERRUPTS (GAUDI2_NUM_USER_INTERRUPTS + GAUDI2_NUM_RESERVED_INTERRUPTS)
/** * struct dup_block_ctx - context to initialize unit instances across multiple * blocks where block can be either a dcore of duplicated * common module. this code relies on constant offsets * of blocks and unit instances in a block. * @instance_cfg_fn: instance specific configuration function. * @data: private configuration data. * @base: base address of the first instance in the first block. * @block_off: subsequent blocks address spacing. * @instance_off: subsequent block's instances address spacing. * @enabled_mask: mask of enabled instances (1- enabled, 0- disabled). * @blocks: number of blocks. * @instances: unit instances per block.
*/ struct dup_block_ctx { void (*instance_cfg_fn)(struct hl_device *hdev, u64 base, void *data); void *data;
u64 base;
u64 block_off;
u64 instance_off;
u64 enabled_mask; unsignedint blocks; unsignedint instances;
};
/** * struct gaudi2_queues_test_info - Holds the address of a the messages used for testing the * device queues. * @dma_addr: the address used by the HW for accessing the message. * @kern_addr: The address used by the driver for accessing the message.
*/ struct gaudi2_queues_test_info {
dma_addr_t dma_addr; void *kern_addr;
};
/** * struct gaudi2_device - ASIC specific manage structure. * @cpucp_info_get: get information on device from CPU-CP * @mapped_blocks: array that holds the base address and size of all blocks * the user can map. * @lfsr_rand_seeds: array of MME ACC random seeds to set. * @hw_queues_lock: protects the H/W queues from concurrent access. * @scratchpad_kernel_address: general purpose PAGE_SIZE contiguous memory, * this memory region should be write-only. * currently used for HBW QMAN writes which is * redundant. * @scratchpad_bus_address: scratchpad bus address * @virt_msix_db_cpu_addr: host memory page for the virtual MSI-X doorbell. * @virt_msix_db_dma_addr: bus address of the page for the virtual MSI-X doorbell. * @dram_bar_cur_addr: current address of DRAM PCI bar. * @hw_cap_initialized: This field contains a bit per H/W engine. When that * engine is initialized, that bit is set by the driver to * signal we can use this engine in later code paths. * Each bit is cleared upon reset of its corresponding H/W * engine. * @active_hw_arc: This field contains a bit per ARC of an H/W engine with * exception of TPC and NIC engines. Once an engine arc is * initialized, its respective bit is set. Driver can uniquely * identify each initialized ARC and use this information in * later code paths. Each respective bit is cleared upon reset * of its corresponding ARC of the H/W engine. * @dec_hw_cap_initialized: This field contains a bit per decoder H/W engine. * When that engine is initialized, that bit is set by * the driver to signal we can use this engine in later * code paths. * Each bit is cleared upon reset of its corresponding H/W * engine. * @tpc_hw_cap_initialized: This field contains a bit per TPC H/W engine. * When that engine is initialized, that bit is set by * the driver to signal we can use this engine in later * code paths. * Each bit is cleared upon reset of its corresponding H/W * engine. * @active_tpc_arc: This field contains a bit per ARC of the TPC engines. * Once an engine arc is initialized, its respective bit is * set. Each respective bit is cleared upon reset of its * corresponding ARC of the TPC engine. * @nic_hw_cap_initialized: This field contains a bit per nic H/W engine. * @active_nic_arc: This field contains a bit per ARC of the NIC engines. * Once an engine arc is initialized, its respective bit is * set. Each respective bit is cleared upon reset of its * corresponding ARC of the NIC engine. * @hw_events: array that holds all H/W events that are defined valid. * @events_stat: array that holds histogram of all received events. * @events_stat_aggregate: same as events_stat but doesn't get cleared on reset. * @num_of_valid_hw_events: used to hold the number of valid H/W events. * @nic_ports: array that holds all NIC ports manage structures. * @nic_macros: array that holds all NIC macro manage structures. * @core_info: core info to be used by the Ethernet driver. * @aux_ops: functions for core <-> aux drivers communication. * @flush_db_fifo: flag to force flush DB FIFO after a write. * @hbm_cfg: HBM subsystem settings * @hw_queues_lock_mutex: used by simulator instead of hw_queues_lock. * @queues_test_info: information used by the driver when testing the HW queues.
*/ struct gaudi2_device { int (*cpucp_info_get)(struct hl_device *hdev);
struct user_mapped_block mapped_blocks[NUM_USER_MAPPED_BLOCKS]; int lfsr_rand_seeds[MME_NUM_OF_LFSR_SEEDS];
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