// SPDX-License-Identifier: GPL-2.0 /* * Copyright 2020-2022 HabanaLabs, Ltd. * All Rights Reserved. #include "gaudi2P.h" #include "gaudi2_masks.h" #include "../include/gaudi2/gaudi2_special_blocks.h" #include "../include/hw_ip/mmu/mmu_general.h" #include "../include/hw_ip/mmu/mmu_v2_0.h" #include "../include/gaudi2/gaudi2_packets.h" #include "../include/gaudi2/gaudi2_reg_map.h" #include "../include/gaudi2/gaudi2_async_ids_map_extended.h" #include "../include/gaudi2/arc/gaudi2_arc_common_packets.h" #include <linux/module.h>#include <linux/pci.h>#include <linux/hwmon.h>#include <linux/iommu.h>#define GAUDI2_DMA_POOL_BLK_SIZE SZ_256 /* 256 bytes */ #define GAUDI2_RESET_TIMEOUT_MSEC 2000 /* 2000ms */ #define GAUDI2_RESET_POLL_TIMEOUT_USEC 500000 /* 500ms */ #define GAUDI2_PLDM_HRESET_TIMEOUT_MSEC 25000 /* 25s */ #define GAUDI2_PLDM_SRESET_TIMEOUT_MSEC 25000 /* 25s */ #define GAUDI2_PLDM_RESET_POLL_TIMEOUT_USEC 3000000 /* 3s */ #define GAUDI2_RESET_POLL_CNT 3#define GAUDI2_RESET_WAIT_MSEC 1 /* 1ms */ #define GAUDI2_CPU_RESET_WAIT_MSEC 100 /* 100ms */ #define GAUDI2_PLDM_RESET_WAIT_MSEC 1000 /* 1s */ #define GAUDI2_CB_POOL_CB_CNT 512#define GAUDI2_CB_POOL_CB_SIZE SZ_128K /* 128KB */ #define GAUDI2_MSG_TO_CPU_TIMEOUT_USEC 4000000 /* 4s */ #define GAUDI2_WAIT_FOR_BL_TIMEOUT_USEC 25000000 /* 25s */ #define GAUDI2_TEST_QUEUE_WAIT_USEC 100000 /* 100ms */ #define GAUDI2_PLDM_TEST_QUEUE_WAIT_USEC 1000000 /* 1s */ #define GAUDI2_ALLOC_CPU_MEM_RETRY_CNT 3/* * since the code already has built-in support for binning of up to MAX_FAULTY_TPCS TPCs * and the code relies on that value (for array size etc..) we define another value * for MAX faulty TPCs which reflects the cluster binning requirements #define MAX_CLUSTER_BINNING_FAULTY_TPCS 1#define MAX_FAULTY_XBARS 1#define MAX_FAULTY_EDMAS 1#define MAX_FAULTY_DECODERS 1#define GAUDI2_TPC_FULL_MASK 0x1FFFFFF#define GAUDI2_HIF_HMMU_FULL_MASK 0xFFFF#define GAUDI2_DECODER_FULL_MASK 0x3FF#define GAUDI2_NA_EVENT_CAUSE 0xFF#define GAUDI2_NUM_OF_QM_ERR_CAUSE 18#define GAUDI2_NUM_OF_LOWER_QM_ERR_CAUSE 25#define GAUDI2_NUM_OF_QM_ARB_ERR_CAUSE 3#define GAUDI2_NUM_OF_ARC_SEI_ERR_CAUSE 14#define GAUDI2_NUM_OF_CPU_SEI_ERR_CAUSE 3#define GAUDI2_NUM_OF_QM_SEI_ERR_CAUSE 2#define GAUDI2_NUM_OF_ROT_ERR_CAUSE 22#define GAUDI2_NUM_OF_TPC_INTR_CAUSE 31#define GAUDI2_NUM_OF_DEC_ERR_CAUSE 25#define GAUDI2_NUM_OF_MME_ERR_CAUSE 16#define GAUDI2_NUM_OF_MME_WAP_ERR_CAUSE 7#define GAUDI2_NUM_OF_DMA_CORE_INTR_CAUSE 8#define GAUDI2_NUM_OF_MMU_SPI_SEI_CAUSE 19#define GAUDI2_NUM_OF_HBM_SEI_CAUSE 9#define GAUDI2_NUM_OF_SM_SEI_ERR_CAUSE 3#define GAUDI2_NUM_OF_PCIE_ADDR_DEC_ERR_CAUSE 3#define GAUDI2_NUM_OF_PMMU_FATAL_ERR_CAUSE 2#define GAUDI2_NUM_OF_HIF_FATAL_ERR_CAUSE 2#define GAUDI2_NUM_OF_AXI_DRAIN_ERR_CAUSE 2#define GAUDI2_NUM_OF_HBM_MC_SPI_CAUSE 5#define GAUDI2_MMU_CACHE_INV_TIMEOUT_USEC (MMU_CONFIG_TIMEOUT_USEC * 10)#define GAUDI2_PLDM_MMU_TIMEOUT_USEC (MMU_CONFIG_TIMEOUT_USEC * 200)#define GAUDI2_ARB_WDT_TIMEOUT (0x1000000)#define GAUDI2_VDEC_TIMEOUT_USEC 10000 /* 10ms */ #define GAUDI2_PLDM_VDEC_TIMEOUT_USEC (GAUDI2_VDEC_TIMEOUT_USEC * 100)#define KDMA_TIMEOUT_USEC USEC_PER_SEC#define IS_DMA_IDLE(dma_core_sts0) \#define IS_DMA_HALTED(dma_core_sts1) \#define IS_MME_IDLE(mme_arch_sts) (((mme_arch_sts) & MME_ARCH_IDLE_MASK) == MME_ARCH_IDLE_MASK)#define IS_TPC_IDLE(tpc_cfg_sts) (((tpc_cfg_sts) & (TPC_IDLE_MASK)) == (TPC_IDLE_MASK))#define IS_QM_IDLE(qm_glbl_sts0, qm_glbl_sts1, qm_cgm_sts) \#define PCIE_DEC_EN_MASK 0x300#define DEC_WORK_STATE_IDLE 0#define DEC_WORK_STATE_PEND 3#define IS_DEC_IDLE(dec_swreg15) \IDLE || \END)/* HBM MMU address scrambling parameters */ #define GAUDI2_HBM_MMU_SCRM_MEM_SIZE SZ_8M#define GAUDI2_HBM_MMU_SCRM_DIV_SHIFT 26#define GAUDI2_HBM_MMU_SCRM_MOD_SHIFT 0#define GAUDI2_HBM_MMU_SCRM_ADDRESS_MASK DRAM_VA_HINT_MASK#define GAUDI2_COMPENSATE_TLB_PAGE_SIZE_FACTOR 16#define MMU_RANGE_INV_VA_LSB_SHIFT 12#define MMU_RANGE_INV_VA_MSB_SHIFT 44#define MMU_RANGE_INV_EN_SHIFT 0#define MMU_RANGE_INV_ASID_EN_SHIFT 1#define MMU_RANGE_INV_ASID_SHIFT 2/* The last SPI_SEI cause bit, "burst_fifo_full", is expected to be triggered in PMMU because it has * a 2 entries FIFO, and hence it is not enabled for it. #define GAUDI2_PMMU_SPI_SEI_ENABLE_MASK GENMASK(GAUDI2_NUM_OF_MMU_SPI_SEI_CAUSE - 2, 0)#define GAUDI2_HMMU_SPI_SEI_ENABLE_MASK GENMASK(GAUDI2_NUM_OF_MMU_SPI_SEI_CAUSE - 1, 0)#define GAUDI2_MAX_STRING_LEN 64#define GAUDI2_VDEC_MSIX_ENTRIES (GAUDI2_IRQ_NUM_SHARED_DEC1_ABNRM - \#define ENGINE_ID_DCORE_OFFSET (GAUDI2_DCORE1_ENGINE_ID_EDMA_0 - GAUDI2_DCORE0_ENGINE_ID_EDMA_0)/* RAZWI initiator coordinates */ #define RAZWI_GET_AXUSER_XY(x) \#define RAZWI_GET_AXUSER_LOW_XY(x) \#define RAZWI_INITIATOR_AXUER_L_X_SHIFT 0#define RAZWI_INITIATOR_AXUER_L_X_MASK 0x1F#define RAZWI_INITIATOR_AXUER_L_Y_SHIFT 5#define RAZWI_INITIATOR_AXUER_L_Y_MASK 0xF#define RAZWI_INITIATOR_AXUER_H_X_SHIFT 23#define RAZWI_INITIATOR_AXUER_H_X_MASK 0x1F#define RAZWI_INITIATOR_ID_X_Y_LOW(x, y) \#define RAZWI_INITIATOR_ID_X_HIGH(x) \#define RAZWI_INITIATOR_ID_X_Y(xl, yl, xh) \#define PSOC_RAZWI_ENG_STR_SIZE 128#define PSOC_RAZWI_MAX_ENG_PER_RTR 5/* HW scrambles only bits 0-25 */ #define HW_UNSCRAMBLED_BITS_MASK GENMASK_ULL(63, 26)#define GAUDI2_GLBL_ERR_MAX_CAUSE_NUM 17struct gaudi2_razwi_info {char *eng_name;static struct gaudi2_razwi_info common_razwi_info[] = {"DEC0" },"DEC1" },"DEC2" },"DEC3" },"DEC4" },"DEC5" },"DEC6" },"DEC7" },"DEC8" },"DEC9" },"TPC0" },"TPC1" },"TPC2" },"TPC3" },"TPC4" },"TPC5" },"TPC6" },"TPC7" },"TPC8" },"TPC9" },"TPC10" },"TPC11" },"TPC12" },"TPC13" },"TPC14" },"TPC15" },"TPC16" },"TPC17" },"TPC18" },"TPC19" },"TPC20" },"TPC21" },"TPC22" },"TPC23" },"TPC24" },"NIC0" },"NIC1" },"NIC2" },"NIC3" },"NIC4" },"NIC5" },"NIC6" },"NIC7" },"NIC8" },"NIC9" },"NIC10" },"NIC11" },"PDMA0" },"PDMA1" },"PMMU" },"PCIE" },"ARC_FARM" },"KDMA" },"EDMA0" },"EDMA1" },"EDMA2" },"EDMA3" },"EDMA4" },"EDMA5" },"EDMA6" },"EDMA7" },"HMMU0" },"HMMU1" },"HMMU2" },"HMMU3" },"HMMU4" },"HMMU5" },"HMMU6" },"HMMU7" },"HMMU8" },"HMMU9" },"HMMU10" },"HMMU11" },"HMMU12" },"HMMU13" },"HMMU14" },"HMMU15" },"ROT0" },"ROT1" },"CPU" },"PSOC" }static struct gaudi2_razwi_info mme_razwi_info[] = {/* MME X high coordinate is N/A, hence using only low coordinates */ "MME0_WAP0" },"MME0_WAP1" },"MME0_CTRL_WR" },"MME0_CTRL_RD" },"MME0_SBTE0" },"MME0_SBTE1" },"MME0_SBTE2" },"MME0_SBTE3" },"MME0_SBTE4" },"MME1_WAP0" },"MME1_WAP1" },"MME1_CTRL_WR" },"MME1_CTRL_RD" },"MME1_SBTE0" },"MME1_SBTE1" },"MME1_SBTE2" },"MME1_SBTE3" },"MME1_SBTE4" },"MME2_WAP0" },"MME2_WAP1" },"MME2_CTRL_WR" },"MME2_CTRL_RD" },"MME2_SBTE0" },"MME2_SBTE1" },"MME2_SBTE2" },"MME2_SBTE3" },"MME2_SBTE4" },"MME3_WAP0" },"MME3_WAP1" },"MME3_CTRL_WR" },"MME3_CTRL_RD" },"MME3_SBTE0" },"MME3_SBTE1" },"MME3_SBTE2" },"MME3_SBTE3" },"MME3_SBTE4" }enum hl_pmmu_fatal_cause {enum hl_pcie_drain_ind_cause {static const u32 cluster_hmmu_hif_enabled_mask[GAUDI2_HBM_NUM] = {static const u8 xbar_edge_to_hbm_cluster[EDMA_ID_SIZE] = {static const u8 edma_to_hbm_cluster[EDMA_ID_SIZE] = {static const int gaudi2_qman_async_event_id[] = {static const int gaudi2_dma_core_async_event_id[] = {static const char * const gaudi2_qm_sei_error_cause[GAUDI2_NUM_OF_QM_SEI_ERR_CAUSE] = {"qman sei intr" ,"arc sei intr" static const char * const gaudi2_cpu_sei_error_cause[GAUDI2_NUM_OF_CPU_SEI_ERR_CAUSE] = {"AXI_TERMINATOR WR" ,"AXI_TERMINATOR RD" ,"AXI SPLIT SEI Status" static const char * const gaudi2_arc_sei_error_cause[GAUDI2_NUM_OF_ARC_SEI_ERR_CAUSE] = {"cbu_bresp_sei_intr_cause" ,"cbu_rresp_sei_intr_cause" ,"lbu_bresp_sei_intr_cause" ,"lbu_rresp_sei_intr_cause" ,"cbu_axi_split_intr_cause" ,"lbu_axi_split_intr_cause" ,"arc_ip_excptn_sei_intr_cause" ,"dmi_bresp_sei_intr_cause" ,"aux2apb_err_sei_intr_cause" ,"cfg_lbw_wr_terminated_intr_cause" ,"cfg_lbw_rd_terminated_intr_cause" ,"cfg_dccm_wr_terminated_intr_cause" ,"cfg_dccm_rd_terminated_intr_cause" ,"cfg_hbw_rd_terminated_intr_cause" static const char * const gaudi2_dec_error_cause[GAUDI2_NUM_OF_DEC_ERR_CAUSE] = {"msix_vcd_hbw_sei" ,"msix_l2c_hbw_sei" ,"msix_nrm_hbw_sei" ,"msix_abnrm_hbw_sei" ,"msix_vcd_lbw_sei" ,"msix_l2c_lbw_sei" ,"msix_nrm_lbw_sei" ,"msix_abnrm_lbw_sei" ,"apb_vcd_lbw_sei" ,"apb_l2c_lbw_sei" ,"apb_nrm_lbw_sei" ,"apb_abnrm_lbw_sei" ,"dec_sei" ,"dec_apb_sei" ,"trc_apb_sei" ,"lbw_mstr_if_sei" ,"axi_split_bresp_err_sei" ,"hbw_axi_wr_viol_sei" ,"hbw_axi_rd_viol_sei" ,"lbw_axi_wr_viol_sei" ,"lbw_axi_rd_viol_sei" ,"vcd_spi" ,"l2c_spi" ,"nrm_spi" ,"abnrm_spi" ,static const char * const gaudi2_qman_error_cause[GAUDI2_NUM_OF_QM_ERR_CAUSE] = {"PQ AXI HBW error" ,"CQ AXI HBW error" ,"CP AXI HBW error" ,"CP error due to undefined OPCODE" ,"CP encountered STOP OPCODE" ,"CP AXI LBW error" ,"CP WRREG32 or WRBULK returned error" ,"N/A" ,"FENCE 0 inc over max value and clipped" ,"FENCE 1 inc over max value and clipped" ,"FENCE 2 inc over max value and clipped" ,"FENCE 3 inc over max value and clipped" ,"FENCE 0 dec under min value and clipped" ,"FENCE 1 dec under min value and clipped" ,"FENCE 2 dec under min value and clipped" ,"FENCE 3 dec under min value and clipped" ,"CPDMA Up overflow" ,"PQC L2H error" static const char * const gaudi2_lower_qman_error_cause[GAUDI2_NUM_OF_LOWER_QM_ERR_CAUSE] = {"RSVD0" ,"CQ AXI HBW error" ,"CP AXI HBW error" ,"CP error due to undefined OPCODE" ,"CP encountered STOP OPCODE" ,"CP AXI LBW error" ,"CP WRREG32 or WRBULK returned error" ,"N/A" ,"FENCE 0 inc over max value and clipped" ,"FENCE 1 inc over max value and clipped" ,"FENCE 2 inc over max value and clipped" ,"FENCE 3 inc over max value and clipped" ,"FENCE 0 dec under min value and clipped" ,"FENCE 1 dec under min value and clipped" ,"FENCE 2 dec under min value and clipped" ,"FENCE 3 dec under min value and clipped" ,"CPDMA Up overflow" ,"RSVD17" ,"CQ_WR_IFIFO_CI_ERR" ,"CQ_WR_CTL_CI_ERR" ,"ARC_CQF_RD_ERR" ,"ARC_CQ_WR_IFIFO_CI_ERR" ,"ARC_CQ_WR_CTL_CI_ERR" ,"ARC_AXI_ERR" ,"CP_SWITCH_WDT_ERR" static const char * const gaudi2_qman_arb_error_cause[GAUDI2_NUM_OF_QM_ARB_ERR_CAUSE] = {"Choice push while full error" ,"Choice Q watchdog error" ,"MSG AXI LBW returned with error" static const char * const guadi2_rot_error_cause[GAUDI2_NUM_OF_ROT_ERR_CAUSE] = {"qm_axi_err" ,"qm_trace_fence_events" ,"qm_sw_err" ,"qm_cp_sw_stop" ,"lbw_mstr_rresp_err" ,"lbw_mstr_bresp_err" ,"lbw_msg_slverr" ,"hbw_msg_slverr" ,"wbc_slverr" ,"hbw_mstr_rresp_err" ,"hbw_mstr_bresp_err" ,"sb_resp_intr" ,"mrsb_resp_intr" ,"core_dw_status_0" ,"core_dw_status_1" ,"core_dw_status_2" ,"core_dw_status_3" ,"core_dw_status_4" ,"core_dw_status_5" ,"core_dw_status_6" ,"core_dw_status_7" ,"async_arc2cpu_sei_intr" ,static const char * const gaudi2_tpc_interrupts_cause[GAUDI2_NUM_OF_TPC_INTR_CAUSE] = {"tpc_address_exceed_slm" ,"tpc_div_by_0" ,"tpc_spu_mac_overflow" ,"tpc_spu_addsub_overflow" ,"tpc_spu_abs_overflow" ,"tpc_spu_fma_fp_dst_nan" ,"tpc_spu_fma_fp_dst_inf" ,"tpc_spu_convert_fp_dst_nan" ,"tpc_spu_convert_fp_dst_inf" ,"tpc_spu_fp_dst_denorm" ,"tpc_vpu_mac_overflow" ,"tpc_vpu_addsub_overflow" ,"tpc_vpu_abs_overflow" ,"tpc_vpu_convert_fp_dst_nan" ,"tpc_vpu_convert_fp_dst_inf" ,"tpc_vpu_fma_fp_dst_nan" ,"tpc_vpu_fma_fp_dst_inf" ,"tpc_vpu_fp_dst_denorm" ,"tpc_assertions" ,"tpc_illegal_instruction" ,"tpc_pc_wrap_around" ,"tpc_qm_sw_err" ,"tpc_hbw_rresp_err" ,"tpc_hbw_bresp_err" ,"tpc_lbw_rresp_err" ,"tpc_lbw_bresp_err" ,"st_unlock_already_locked" ,"invalid_lock_access" ,"LD_L protection violation" ,"ST_L protection violation" ,"D$ L0CS mismatch" ,static const char * const guadi2_mme_error_cause[GAUDI2_NUM_OF_MME_ERR_CAUSE] = {"agu_resp_intr" ,"qman_axi_err" ,"wap sei (wbc axi err)" ,"arc sei" ,"cfg access error" ,"qm_sw_err" ,"sbte_dbg_intr_0" ,"sbte_dbg_intr_1" ,"sbte_dbg_intr_2" ,"sbte_dbg_intr_3" ,"sbte_dbg_intr_4" ,"sbte_prtn_intr_0" ,"sbte_prtn_intr_1" ,"sbte_prtn_intr_2" ,"sbte_prtn_intr_3" ,"sbte_prtn_intr_4" ,static const char * const guadi2_mme_wap_error_cause[GAUDI2_NUM_OF_MME_WAP_ERR_CAUSE] = {"WBC ERR RESP_0" ,"WBC ERR RESP_1" ,"AP SOURCE POS INF" ,"AP SOURCE NEG INF" ,"AP SOURCE NAN" ,"AP RESULT POS INF" ,"AP RESULT NEG INF" ,static const char * const gaudi2_dma_core_interrupts_cause[GAUDI2_NUM_OF_DMA_CORE_INTR_CAUSE] = {"HBW Read returned with error RRESP" ,"HBW write returned with error BRESP" ,"LBW write returned with error BRESP" ,"descriptor_fifo_overflow" ,"KDMA SB LBW Read returned with error" ,"KDMA WBC LBW Write returned with error" ,"TRANSPOSE ENGINE DESC FIFO OVERFLOW" ,"WRONG CFG FOR COMMIT IN LIN DMA" static const char * const gaudi2_kdma_core_interrupts_cause[GAUDI2_NUM_OF_DMA_CORE_INTR_CAUSE] = {"HBW/LBW Read returned with error RRESP" ,"HBW/LBW write returned with error BRESP" ,"LBW write returned with error BRESP" ,"descriptor_fifo_overflow" ,"KDMA SB LBW Read returned with error" ,"KDMA WBC LBW Write returned with error" ,"TRANSPOSE ENGINE DESC FIFO OVERFLOW" ,"WRONG CFG FOR COMMIT IN LIN DMA" struct gaudi2_sm_sei_cause_data {const char *cause_name;const char *log_name;static const struct gaudi2_sm_sei_cause_data"calculated SO value overflow/underflow" , "SOB ID" },"payload address of monitor is not aligned to 4B" , "monitor addr" },"armed monitor write got BRESP (SLVERR or DECERR)" , "AXI id" },static const char * const "LATENCY_RD_OUT_FIFO_OVERRUN" ,"LATENCY_WR_OUT_FIFO_OVERRUN" ,static const char * const "LATENCY_RD_OUT_FIFO_OVERRUN" ,"LATENCY_WR_OUT_FIFO_OVERRUN" ,static const char * const "AXI drain HBW" ,"AXI drain LBW" ,static const char * const "HBW error response" ,"LBW error response" ,"TLP is blocked by RR" static const int gaudi2_queue_id_to_engine_id[] = {const u32 gaudi2_qm_blocks_bases[GAUDI2_QUEUE_ID_SIZE] = {static const u32 gaudi2_arc_blocks_bases[NUM_ARC_CPUS] = {
Messung V0.5 C=99 H=100 G=99
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