if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE) return kvm_s390_inject_program_int(vcpu, PGM_PRIVILEGED_OP);
op2 = kvm_s390_get_base_disp_s(vcpu, &ar); if (op2 & 7) /* Operand must be on a doubleword boundary */ return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION);
rc = read_guest(vcpu, op2, ar, >od.tod, sizeof(gtod.tod)); if (rc) return kvm_s390_inject_prog_cond(vcpu, rc);
VCPU_EVENT(vcpu, 3, "SCK: setting guest TOD to 0x%llx", gtod.tod); /* * To set the TOD clock the kvm lock must be taken, but the vcpu lock * is already held in handle_set_clock. The usual lock order is the * opposite. As SCK is deprecated and should not be used in several * cases, for example when the multiple epoch facility or TOD clock * steering facility is installed (see Principles of Operation), a * slow path can be used. If the lock can not be taken via try_lock, * the instruction will be retried via -EAGAIN at a later point in * time.
*/ if (!kvm_s390_try_set_tod_clock(vcpu->kvm, >od)) {
kvm_s390_retry_instr(vcpu); return -EAGAIN;
}
if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE) return kvm_s390_inject_program_int(vcpu, PGM_PRIVILEGED_OP);
operand2 = kvm_s390_get_base_disp_s(vcpu, &ar);
/* must be word boundary */ if (operand2 & 3) return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION);
/* get the value */
rc = read_guest(vcpu, operand2, ar, &address, sizeof(address)); if (rc) return kvm_s390_inject_prog_cond(vcpu, rc);
address &= 0x7fffe000u;
/* * Make sure the new value is valid memory. We only need to check the * first page, since address is 8k aligned and memory pieces are always * at least 1MB aligned and have at least a size of 1MB.
*/ if (!kvm_is_gpa_in_memslot(vcpu->kvm, address)) return kvm_s390_inject_program_int(vcpu, PGM_ADDRESSING);
staticint try_handle_skey(struct kvm_vcpu *vcpu)
{ int rc;
rc = kvm_s390_skey_check_enable(vcpu); if (rc) return rc; if (vcpu->kvm->arch.use_skf) { /* with storage-key facility, SIE interprets it for us */
kvm_s390_retry_instr(vcpu);
VCPU_EVENT(vcpu, 4, "%s", "retrying storage key operation"); return -EAGAIN;
} return 0;
}
staticint handle_iske(struct kvm_vcpu *vcpu)
{ unsignedlong gaddr, vmaddr; unsignedchar key; int reg1, reg2; bool unlocked; int rc;
vcpu->stat.instruction_iske++;
if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE) return kvm_s390_inject_program_int(vcpu, PGM_PRIVILEGED_OP);
if (!kvm_is_gpa_in_memslot(vcpu->kvm, addr)) return kvm_s390_inject_program_int(vcpu, PGM_ADDRESSING); /* * We don't expect errors on modern systems, and do not care * about storage keys (yet), so let's just clear the page.
*/ if (kvm_clear_guest(vcpu->kvm, addr, PAGE_SIZE)) return -EFAULT;
kvm_s390_set_psw_cc(vcpu, 0);
vcpu->run->s.regs.gprs[0] = 0; return 0;
}
inti = kvm_s390_get_io_int(vcpu->kvm, vcpu->arch.sie_block->gcr[6], 0); if (!inti) {
kvm_s390_set_psw_cc(vcpu, 0); return 0;
}
tpi_data[0] = inti->io.subchannel_id << 16 | inti->io.subchannel_nr;
tpi_data[1] = inti->io.io_int_parm;
tpi_data[2] = inti->io.io_int_word; if (addr) { /* * Store the two-word I/O interruption code into the * provided area.
*/
len = sizeof(tpi_data) - 4;
rc = write_guest(vcpu, addr, ar, &tpi_data, len); if (rc) {
rc = kvm_s390_inject_prog_cond(vcpu, rc); goto reinject_interrupt;
}
} else { /* * Store the three-word I/O interruption code into * the appropriate lowcore area.
*/
len = sizeof(tpi_data); if (write_guest_lc(vcpu, __LC_SUBCHANNEL_ID, &tpi_data, len)) { /* failed writes to the low core are not recoverable */
rc = -EFAULT; goto reinject_interrupt;
}
}
/* irq was successfully handed to the guest */
kfree(inti);
kvm_s390_set_psw_cc(vcpu, 1); return 0;
reinject_interrupt: /* * If we encounter a problem storing the interruption code, the * instruction is suppressed from the guest's view: reinject the * interrupt.
*/ if (kvm_s390_reinject_io_int(vcpu->kvm, inti)) {
kfree(inti);
rc = -EFAULT;
} /* don't set the cc, a pgm irq was injected or we drop to user space */ return rc ? -EFAULT : 0;
}
/* a valid schid has at least one bit set */ if (vcpu->run->s.regs.gprs[1])
inti = kvm_s390_get_io_int(vcpu->kvm, isc_mask,
vcpu->run->s.regs.gprs[1]);
/* * Prepare exit to userspace. * We indicate whether we dequeued a pending I/O interrupt * so that userspace can re-inject it if the instruction gets * a program check. While this may re-order the pending I/O * interrupts, this is no problem since the priority is kept * intact.
*/
vcpu->run->exit_reason = KVM_EXIT_S390_TSCH;
vcpu->run->s390_tsch.dequeued = !!inti; if (inti) {
vcpu->run->s390_tsch.subchannel_id = inti->io.subchannel_id;
vcpu->run->s390_tsch.subchannel_nr = inti->io.subchannel_nr;
vcpu->run->s390_tsch.io_int_parm = inti->io.io_int_parm;
vcpu->run->s390_tsch.io_int_word = inti->io.io_int_word;
}
vcpu->run->s390_tsch.ipb = vcpu->arch.sie_block->ipb;
kfree(inti); return -EREMOTE;
}
if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE) return kvm_s390_inject_program_int(vcpu, PGM_PRIVILEGED_OP);
if (vcpu->kvm->arch.css_support) { /* * Most I/O instructions will be handled by userspace. * Exceptions are tpi and the interrupt portion of tsch.
*/ if (vcpu->arch.sie_block->ipa == 0xb236) return handle_tpi(vcpu); if (vcpu->arch.sie_block->ipa == 0xb235) return handle_tsch(vcpu); /* Handle in userspace. */
vcpu->stat.instruction_io_other++; return -EOPNOTSUPP;
} else { /* * Set condition code 3 to stop the guest from issuing channel * I/O instructions.
*/
kvm_s390_set_psw_cc(vcpu, 3); return 0;
}
}
/* * handle_pqap: Handling pqap interception * @vcpu: the vcpu having issue the pqap instruction * * We now support PQAP/AQIC instructions and we need to correctly * answer the guest even if no dedicated driver's hook is available. * * The intercepting code calls a dedicated callback for this instruction * if a driver did register one in the CRYPTO satellite of the * SIE block. * * If no callback is available, the queues are not available, return this * response code to the caller and set CC to 3. * Else return the response code returned by the callback.
*/ staticint handle_pqap(struct kvm_vcpu *vcpu)
{ struct ap_queue_status status = {};
crypto_hook pqap_hook; unsignedlong reg0; int ret;
uint8_t fc;
/* Verify that the AP instruction are available */ if (!ap_instructions_available()) return -EOPNOTSUPP; /* Verify that the guest is allowed to use AP instructions */ if (!(vcpu->arch.sie_block->eca & ECA_APIE)) return -EOPNOTSUPP; /* * The only possibly intercepted functions when AP instructions are * available for the guest are AQIC and TAPQ with the t bit set * since we do not set IC.3 (FIII) we currently will only intercept * the AQIC function code. * Note: running nested under z/VM can result in intercepts for other * function codes, e.g. PQAP(QCI). We do not support this and bail out.
*/
reg0 = vcpu->run->s.regs.gprs[0];
fc = (reg0 >> 24) & 0xff; if (fc != 0x03) return -EOPNOTSUPP;
/* PQAP instruction is allowed for guest kernel only */ if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE) return kvm_s390_inject_program_int(vcpu, PGM_PRIVILEGED_OP);
/* Common PQAP instruction specification exceptions */ /* bits 41-47 must all be zeros */ if (reg0 & 0x007f0000UL) return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION); /* APFT not install and T bit set */ if (!test_kvm_facility(vcpu->kvm, 15) && (reg0 & 0x00800000UL)) return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION); /* APXA not installed and APID greater 64 or APQI greater 16 */ if (!(vcpu->kvm->arch.crypto.crycbd & 0x02) && (reg0 & 0x0000c0f0UL)) return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION);
/* AQIC function code specific exception */ /* facility 65 not present for AQIC function code */ if (!test_kvm_facility(vcpu->kvm, 65)) return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION);
/* * If the hook callback is registered, there will be a pointer to the * hook function pointer in the kvm_s390_crypto structure. Lock the * owner, retrieve the hook function pointer and call the hook.
*/
down_read(&vcpu->kvm->arch.crypto.pqap_hook_rwsem); if (vcpu->kvm->arch.crypto.pqap_hook) {
pqap_hook = *vcpu->kvm->arch.crypto.pqap_hook;
ret = pqap_hook(vcpu); if (!ret) { if (vcpu->run->s.regs.gprs[1] & 0x00ff0000)
kvm_s390_set_psw_cc(vcpu, 3); else
kvm_s390_set_psw_cc(vcpu, 0);
}
up_read(&vcpu->kvm->arch.crypto.pqap_hook_rwsem); return ret;
}
up_read(&vcpu->kvm->arch.crypto.pqap_hook_rwsem); /* * A vfio_driver must register a hook. * No hook means no driver to enable the SIE CRYCB and no queues. * We send this response to the guest.
*/
status.response_code = 0x01;
memcpy(&vcpu->run->s.regs.gprs[1], &status, sizeof(status));
kvm_s390_set_psw_cc(vcpu, 3); return 0;
}
staticint handle_stfl(struct kvm_vcpu *vcpu)
{ int rc; unsignedint fac;
vcpu->stat.instruction_stfl++;
if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE) return kvm_s390_inject_program_int(vcpu, PGM_PRIVILEGED_OP);
/* * We need to shift the lower 32 facility bits (bit 0-31) from a u64 * into a u32 memory representation. They will remain bits 0-31.
*/
fac = *vcpu->kvm->arch.model.fac_list >> 32;
rc = write_guest_lc(vcpu, offsetof(struct lowcore, stfl_fac_list),
&fac, sizeof(fac)); if (rc) return rc;
VCPU_EVENT(vcpu, 3, "STFL: store facility list 0x%x", fac);
trace_kvm_s390_handle_stfl(vcpu, fac); return 0;
}
if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE) return kvm_s390_inject_program_int(vcpu, PGM_PRIVILEGED_OP);
/* Bailout forbidden function codes */ if (fc > 3 && fc != 15) goto out_no_data;
/* * fc 15 is provided only with * - PTF/CPU topology support through facility 15 * - KVM_CAP_S390_USER_STSI
*/ if (fc == 15 && (!test_kvm_facility(vcpu->kvm, 11) ||
!vcpu->kvm->arch.user_stsi)) goto out_no_data;
if (!kvm_s390_pv_cpu_is_protected(vcpu) && (operand2 & 0xfff)) return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION);
switch (fc) { case 1: /* same handling for 1 and 2 */ case 2:
mem = get_zeroed_page(GFP_KERNEL_ACCOUNT); if (!mem) goto out_no_data; if (stsi((void *) mem, fc, sel1, sel2)) goto out_no_data; break; case 3: if (sel1 != 2 || sel2 != 2) goto out_no_data;
mem = get_zeroed_page(GFP_KERNEL_ACCOUNT); if (!mem) goto out_no_data;
handle_stsi_3_2_2(vcpu, (void *) mem); break; case 15: /* fc 15 is fully handled in userspace */
insert_stsi_usr_data(vcpu, operand2, ar, fc, sel1, sel2);
trace_kvm_s390_handle_stsi(vcpu, fc, sel1, sel2, operand2); return -EREMOTE;
} if (kvm_s390_pv_cpu_is_protected(vcpu)) {
memcpy(sida_addr(vcpu->arch.sie_block), (void *)mem, PAGE_SIZE);
rc = 0;
} else {
rc = write_guest(vcpu, operand2, ar, (void *)mem, PAGE_SIZE);
} if (rc) {
rc = kvm_s390_inject_prog_cond(vcpu, rc); goto out;
} if (vcpu->kvm->arch.user_stsi) {
insert_stsi_usr_data(vcpu, operand2, ar, fc, sel1, sel2);
rc = -EREMOTE;
}
trace_kvm_s390_handle_stsi(vcpu, fc, sel1, sel2, operand2);
free_page(mem);
kvm_s390_set_psw_cc(vcpu, 0);
vcpu->run->s.regs.gprs[0] = 0; return rc;
out_no_data:
kvm_s390_set_psw_cc(vcpu, 3);
out:
free_page(mem); return rc;
}
int kvm_s390_handle_b2(struct kvm_vcpu *vcpu)
{ switch (vcpu->arch.sie_block->ipa & 0x00ff) { case 0x02: return handle_stidp(vcpu); case 0x04: return handle_set_clock(vcpu); case 0x10: return handle_set_prefix(vcpu); case 0x11: return handle_store_prefix(vcpu); case 0x12: return handle_store_cpu_address(vcpu); case 0x14: return kvm_s390_handle_vsie(vcpu); case 0x21: case 0x50: return handle_ipte_interlock(vcpu); case 0x29: return handle_iske(vcpu); case 0x2a: return handle_rrbe(vcpu); case 0x2b: return handle_sske(vcpu); case 0x2c: return handle_test_block(vcpu); case 0x30: case 0x31: case 0x32: case 0x33: case 0x34: case 0x35: case 0x36: case 0x37: case 0x38: case 0x39: case 0x3a: case 0x3b: case 0x3c: case 0x5f: case 0x74: case 0x76: return handle_io_inst(vcpu); case 0x56: return handle_sthyi(vcpu); case 0x7d: return handle_stsi(vcpu); case 0xaf: return handle_pqap(vcpu); case 0xb1: return handle_stfl(vcpu); case 0xb2: return handle_lpswe(vcpu); default: return -EOPNOTSUPP;
}
}
staticint handle_epsw(struct kvm_vcpu *vcpu)
{ int reg1, reg2;
vcpu->stat.instruction_epsw++;
kvm_s390_get_regs_rre(vcpu, ®1, ®2);
/* This basically extracts the mask half of the psw. */
vcpu->run->s.regs.gprs[reg1] &= 0xffffffff00000000UL;
vcpu->run->s.regs.gprs[reg1] |= vcpu->arch.sie_block->gpsw.mask >> 32; if (reg2) {
vcpu->run->s.regs.gprs[reg2] &= 0xffffffff00000000UL;
vcpu->run->s.regs.gprs[reg2] |=
vcpu->arch.sie_block->gpsw.mask & 0x00000000ffffffffUL;
} return 0;
}
if (!test_kvm_facility(vcpu->kvm, 8)) return kvm_s390_inject_program_int(vcpu, PGM_OPERATION);
if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE) return kvm_s390_inject_program_int(vcpu, PGM_PRIVILEGED_OP);
if (vcpu->run->s.regs.gprs[reg1] & PFMF_RESERVED) return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION);
/* Only provide non-quiescing support if enabled for the guest */ if (vcpu->run->s.regs.gprs[reg1] & PFMF_NQ &&
!test_kvm_facility(vcpu->kvm, 14)) return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION);
/* Only provide conditional-SSKE support if enabled for the guest */ if (vcpu->run->s.regs.gprs[reg1] & PFMF_SK &&
test_kvm_facility(vcpu->kvm, 10)) {
mr = vcpu->run->s.regs.gprs[reg1] & PFMF_MR;
mc = vcpu->run->s.regs.gprs[reg1] & PFMF_MC;
}
if (vcpu->run->s.regs.gprs[reg1] & PFMF_CF) { if (kvm_s390_check_low_addr_prot_real(vcpu, start)) return kvm_s390_inject_prog_irq(vcpu, &vcpu->arch.pgm);
}
switch (vcpu->run->s.regs.gprs[reg1] & PFMF_FSC) { case 0x00000000: /* only 4k frames specify a real address */
start = kvm_s390_real_to_abs(vcpu, start);
end = (start + PAGE_SIZE) & ~(PAGE_SIZE - 1); break; case 0x00001000:
end = (start + _SEGMENT_SIZE) & ~(_SEGMENT_SIZE - 1); break; case 0x00002000: /* only support 2G frame size if EDAT2 is available and we are
not in 24-bit addressing mode */ if (!test_kvm_facility(vcpu->kvm, 78) ||
psw_bits(vcpu->arch.sie_block->gpsw).eaba == PSW_BITS_AMODE_24BIT) return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION);
end = (start + _REGION3_SIZE) & ~(_REGION3_SIZE - 1); break; default: return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION);
}
if (kvm_is_error_hva(hva)) return kvm_s390_inject_program_int(vcpu, PGM_ADDRESSING);
nappended = pgste_perform_essa(vcpu->kvm->mm, hva, orc, &ptev, &pgstev); if (nappended < 0) {
res = orc ? 0x10 : 0;
vcpu->run->s.regs.gprs[r1] = res; /* Exception Indication */ return 0;
}
res = (pgstev & _PGSTE_GPS_USAGE_MASK) >> 22; /* * Set the block-content state part of the result. 0 means resident, so * nothing to do if the page is valid. 2 is for preserved pages * (non-present and non-zero), and 3 for zero pages (non-present and * zero).
*/ if (ptev & _PAGE_INVALID) {
res |= 2; if (pgstev & _PGSTE_GPS_ZERO)
res |= 1;
} if (pgstev & _PGSTE_GPS_NODAT)
res |= 0x20;
vcpu->run->s.regs.gprs[r1] = res; /* * It is possible that all the normal 511 slots were full, in which case * we will now write in the 512th slot, which is reserved for host use. * In both cases we let the normal essa handling code process all the * slots, including the reserved one, if needed.
*/ if (nappended > 0) {
cbrlo = phys_to_virt(vcpu->arch.sie_block->cbrlo & PAGE_MASK);
cbrlo[entries] = gfn << PAGE_SHIFT;
}
if (orc) { struct kvm_memory_slot *ms = gfn_to_memslot(vcpu->kvm, gfn);
/* Increment only if we are really flipping the bit */ if (ms && !test_and_set_bit(gfn - ms->base_gfn, kvm_second_dirty_bitmap(ms)))
atomic64_inc(&vcpu->kvm->arch.cmma_dirty_pages);
}
if (!vcpu->kvm->arch.migration_mode) { /* * CMMA is enabled in the KVM settings, but is disabled in * the SIE block and in the mm_context, and we are not doing * a migration. Enable CMMA in the mm_context. * Since we need to take a write lock to write to the context * to avoid races with storage keys handling, we check if the * value really needs to be written to; if the value is * already correct, we do nothing and avoid the lock.
*/ if (vcpu->kvm->mm->context.uses_cmm == 0) {
mmap_write_lock(vcpu->kvm->mm);
vcpu->kvm->mm->context.uses_cmm = 1;
mmap_write_unlock(vcpu->kvm->mm);
} /* * If we are here, we are supposed to have CMMA enabled in * the SIE block. Enabling CMMA works on a per-CPU basis, * while the context use_cmma flag is per process. * It's possible that the context flag is enabled and the * SIE flag is not, so we set the flag always; if it was * already set, nothing changes, otherwise we enable it * on this CPU too.
*/
vcpu->arch.sie_block->ecb2 |= ECB2_CMMA; /* Retry the ESSA instruction */
kvm_s390_retry_instr(vcpu);
} else {
mmap_read_lock(vcpu->kvm->mm);
i = __do_essa(vcpu, orc);
mmap_read_unlock(vcpu->kvm->mm); if (i < 0) return i; /* Account for the possible extra cbrl entry */
entries += i;
}
vcpu->arch.sie_block->cbrlo &= PAGE_MASK; /* reset nceo */
cbrlo = phys_to_virt(vcpu->arch.sie_block->cbrlo);
mmap_read_lock(gmap->mm); for (i = 0; i < entries; ++i)
__gmap_zap(gmap, cbrlo[i]);
mmap_read_unlock(gmap->mm); return 0;
}
int kvm_s390_handle_b9(struct kvm_vcpu *vcpu)
{ switch (vcpu->arch.sie_block->ipa & 0x00ff) { case 0x8a: case 0x8e: case 0x8f: return handle_ipte_interlock(vcpu); case 0x8d: return handle_epsw(vcpu); case 0xab: return handle_essa(vcpu); case 0xaf: return handle_pfmf(vcpu); default: return -EOPNOTSUPP;
}
}
int kvm_s390_handle_lctl(struct kvm_vcpu *vcpu)
{ int reg1 = (vcpu->arch.sie_block->ipa & 0x00f0) >> 4; int reg3 = vcpu->arch.sie_block->ipa & 0x000f; int reg, rc, nr_regs;
u32 ctl_array[16];
u64 ga;
u8 ar;
vcpu->stat.instruction_lctl++;
if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE) return kvm_s390_inject_program_int(vcpu, PGM_PRIVILEGED_OP);
ga = kvm_s390_get_base_disp_rs(vcpu, &ar);
if (ga & 3) return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION);
int kvm_s390_handle_eb(struct kvm_vcpu *vcpu)
{ switch (vcpu->arch.sie_block->ipb & 0x000000ff) { case 0x25: return handle_stctg(vcpu); case 0x2f: return handle_lctlg(vcpu); case 0x60: case 0x61: case 0x62: return handle_ri(vcpu); case 0x71: return handle_lpswey(vcpu); default: return -EOPNOTSUPP;
}
}
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