Quelle  cv1812h.dtsi   Sprache: unbekannt

// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com>
 */

#define SOC_PERIPHERAL_IRQ(nr) ((nr) + 16)

#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/pinctrl-cv1812h.h>
#include "cv180x-cpus.dtsi"
#include "cv180x.dtsi"
#include "cv181x.dtsi"

/ {
 compatible = "sophgo,cv1812h";

 memory@80000000 {
  device_type = "memory";
  reg = <0x80000000 0x10000000>;
 };

 soc {
  interrupt-parent = <&plic>;
  dma-noncoherent;

  pinctrl: pinctrl@3001000 {
   compatible = "sophgo,cv1812h-pinctrl";
   reg = <0x03001000 0x1000>,
         <0x05027000 0x1000>;
   reg-names = "sys", "rtc";
  };

  clk: clock-controller@3002000 {
   compatible = "sophgo,cv1812h-clk";
   reg = <0x03002000 0x1000>;
   clocks = <&osc>;
   #clock-cells = <1>;
  };

  plic: interrupt-controller@70000000 {
   compatible = "sophgo,cv1812h-plic", "thead,c900-plic";
   reg = <0x70000000 0x4000000>;
   interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
   interrupt-controller;
   #address-cells = <0>;
   #interrupt-cells = <2>;
   riscv,ndev = <101>;
  };

  clint: timer@74000000 {
   compatible = "sophgo,cv1812h-clint", "thead,c900-clint";
   reg = <0x74000000 0x10000>;
   interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
  };
 };
};