Quelle t4fw_api.h
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/* * This file is part of the Chelsio T4 Ethernet driver for Linux. * * Copyright (c) 2009-2016 Chelsio Communications, Inc. All rights reserved. * * This software is available to you under a choice of one of two * licenses. You may choose to be licensed under the terms of the GNU * General Public License (GPL) Version 2, available from the file * COPYING in the main directory of this source tree, or the * OpenIB.org BSD license below: * * Redistribution and use in source and binary forms, with or * without modification, are permitted provided that the following * conditions are met: * * - Redistributions of source code must retain the above * copyright notice, this list of conditions and the following * disclaimer. * * - Redistributions in binary form must reproduce the above * copyright notice, this list of conditions and the following * disclaimer in the documentation and/or other materials * provided with the distribution. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. #ifndef _T4FW_INTERFACE_H_#define _T4FW_INTERFACE_H_enum fw_retval {0 , /* completed successfully */ 1 , /* operation not permitted */ 2 , /* no such file or directory */ 5 , /* input/output error; hw bad */ 8 , /* exec format error; inv microcode */ 11 , /* try again */ 12 , /* out of memory */ 14 , /* bad address; fw bad */ 16 , /* resource busy */ 17 , /* file exists */ 19 , /* no such device */ 22 , /* invalid argument */ 28 , /* no space left on device */ 38 , /* functionality not implemented */ 61 , /* no data available */ 71 , /* protocol error */ 98 , /* address already in use */ 99 , /* cannot assigned requested address */ 100 , /* network is down */ 101 , /* network is unreachable */ 105 , /* no buffer space available */ 110 , /* timeout */ 115 , /* fw internal */ 128 , /* */ 129 , /* */ 130 , /* */ 131 , /* */ 132 , /* */ 133 , /* */ 134 , /* */ 135 , /* */ 136 , /* */ 137 , /* */ 138 , /* */ 139 , /* */ 140 , /* */ 141 , /* DDP error*/ 142 , /* No SCSI tasks available */ #define FW_T4VF_SGE_BASE_ADDR 0 x0000#define FW_T4VF_MPS_BASE_ADDR 0 x0100#define FW_T4VF_PL_BASE_ADDR 0 x0200#define FW_T4VF_MBDATA_BASE_ADDR 0 x0240#define FW_T4VF_CIM_BASE_ADDR 0 x0300enum fw_wr_opcodes {0 x02,0 x04,0 x05,0 x08,0 x1c,0 x2f,0 x0a,0 x0b,0 x10,0 x11,0 x0c,0 x0d,0 x14,0 x15,0 x16,0 x17,0 x18,0 x19,0 x20,0 x21,0 x1a,0 x45,0 x46,0 x68,0 X6d,0 x70,0 x77struct fw_wr_hdr {/* work request opcode (hi) */ #define FW_WR_OP_S 24 #define FW_WR_OP_M 0 xff#define FW_WR_OP_V(x) ((x) << FW_WR_OP_S)#define FW_WR_OP_G(x) (((x) >> FW_WR_OP_S) & FW_WR_OP_M)/* atomic flag (hi) - firmware encapsulates CPLs in CPL_BARRIER */ #define FW_WR_ATOMIC_S 23 #define FW_WR_ATOMIC_V(x) ((x) << FW_WR_ATOMIC_S)/* flush flag (hi) - firmware flushes flushable work request buffered * in the flow context. #define FW_WR_FLUSH_S 22 #define FW_WR_FLUSH_V(x) ((x) << FW_WR_FLUSH_S)/* completion flag (hi) - firmware generates a cpl_fw6_ack */ #define FW_WR_COMPL_S 21 #define FW_WR_COMPL_V(x) ((x) << FW_WR_COMPL_S)#define FW_WR_COMPL_F FW_WR_COMPL_V(1 U)/* work request immediate data length (hi) */ #define FW_WR_IMMDLEN_S 0 #define FW_WR_IMMDLEN_M 0 xff#define FW_WR_IMMDLEN_V(x) ((x) << FW_WR_IMMDLEN_S)/* egress queue status update to associated ingress queue entry (lo) */ #define FW_WR_EQUIQ_S 31 #define FW_WR_EQUIQ_V(x) ((x) << FW_WR_EQUIQ_S)#define FW_WR_EQUIQ_F FW_WR_EQUIQ_V(1 U)/* egress queue status update to egress queue status entry (lo) */ #define FW_WR_EQUEQ_S 30 #define FW_WR_EQUEQ_V(x) ((x) << FW_WR_EQUEQ_S)#define FW_WR_EQUEQ_F FW_WR_EQUEQ_V(1 U)/* flow context identifier (lo) */ #define FW_WR_FLOWID_S 8 #define FW_WR_FLOWID_V(x) ((x) << FW_WR_FLOWID_S)/* length in units of 16-bytes (lo) */ #define FW_WR_LEN16_S 0 #define FW_WR_LEN16_V(x) ((x) << FW_WR_LEN16_S)#define HW_TPL_FR_MT_PR_IV_P_FC 0 X32B#define HW_TPL_FR_MT_PR_OV_P_FC 0 X327/* filter wr reply code in cookie in CPL_SET_TCB_RPL */ enum fw_filter_wr_cookie {struct fw_filter_wr {16 ];16 ];16 ];16 ];6 ];struct fw_filter2_wr {16 ];16 ];16 ];16 ];6 ];16 ];16 ];#define FW_FILTER_WR_TID_S 12 #define FW_FILTER_WR_TID_M 0 xfffff#define FW_FILTER_WR_TID_V(x) ((x) << FW_FILTER_WR_TID_S)#define FW_FILTER_WR_TID_G(x) \#define FW_FILTER_WR_RQTYPE_S 11 #define FW_FILTER_WR_RQTYPE_M 0 x1#define FW_FILTER_WR_RQTYPE_V(x) ((x) << FW_FILTER_WR_RQTYPE_S)#define FW_FILTER_WR_RQTYPE_G(x) \#define FW_FILTER_WR_RQTYPE_F FW_FILTER_WR_RQTYPE_V(1 U)#define FW_FILTER_WR_NOREPLY_S 10 #define FW_FILTER_WR_NOREPLY_M 0 x1#define FW_FILTER_WR_NOREPLY_V(x) ((x) << FW_FILTER_WR_NOREPLY_S)#define FW_FILTER_WR_NOREPLY_G(x) \#define FW_FILTER_WR_NOREPLY_F FW_FILTER_WR_NOREPLY_V(1 U)#define FW_FILTER_WR_IQ_S 0 #define FW_FILTER_WR_IQ_M 0 x3ff#define FW_FILTER_WR_IQ_V(x) ((x) << FW_FILTER_WR_IQ_S)#define FW_FILTER_WR_IQ_G(x) \#define FW_FILTER_WR_DEL_FILTER_S 31 #define FW_FILTER_WR_DEL_FILTER_M 0 x1#define FW_FILTER_WR_DEL_FILTER_V(x) ((x) << FW_FILTER_WR_DEL_FILTER_S)#define FW_FILTER_WR_DEL_FILTER_G(x) \#define FW_FILTER_WR_DEL_FILTER_F FW_FILTER_WR_DEL_FILTER_V(1 U)#define FW_FILTER_WR_RPTTID_S 25 #define FW_FILTER_WR_RPTTID_M 0 x1#define FW_FILTER_WR_RPTTID_V(x) ((x) << FW_FILTER_WR_RPTTID_S)#define FW_FILTER_WR_RPTTID_G(x) \#define FW_FILTER_WR_RPTTID_F FW_FILTER_WR_RPTTID_V(1 U)#define FW_FILTER_WR_DROP_S 24 #define FW_FILTER_WR_DROP_M 0 x1#define FW_FILTER_WR_DROP_V(x) ((x) << FW_FILTER_WR_DROP_S)#define FW_FILTER_WR_DROP_G(x) \#define FW_FILTER_WR_DROP_F FW_FILTER_WR_DROP_V(1 U)#define FW_FILTER_WR_DIRSTEER_S 23 #define FW_FILTER_WR_DIRSTEER_M 0 x1#define FW_FILTER_WR_DIRSTEER_V(x) ((x) << FW_FILTER_WR_DIRSTEER_S)#define FW_FILTER_WR_DIRSTEER_G(x) \#define FW_FILTER_WR_DIRSTEER_F FW_FILTER_WR_DIRSTEER_V(1 U)#define FW_FILTER_WR_MASKHASH_S 22 #define FW_FILTER_WR_MASKHASH_M 0 x1#define FW_FILTER_WR_MASKHASH_V(x) ((x) << FW_FILTER_WR_MASKHASH_S)#define FW_FILTER_WR_MASKHASH_G(x) \#define FW_FILTER_WR_MASKHASH_F FW_FILTER_WR_MASKHASH_V(1 U)#define FW_FILTER_WR_DIRSTEERHASH_S 21 #define FW_FILTER_WR_DIRSTEERHASH_M 0 x1#define FW_FILTER_WR_DIRSTEERHASH_V(x) ((x) << FW_FILTER_WR_DIRSTEERHASH_S)#define FW_FILTER_WR_DIRSTEERHASH_G(x) \#define FW_FILTER_WR_DIRSTEERHASH_F FW_FILTER_WR_DIRSTEERHASH_V(1 U)#define FW_FILTER_WR_LPBK_S 20 #define FW_FILTER_WR_LPBK_M 0 x1#define FW_FILTER_WR_LPBK_V(x) ((x) << FW_FILTER_WR_LPBK_S)#define FW_FILTER_WR_LPBK_G(x) \#define FW_FILTER_WR_LPBK_F FW_FILTER_WR_LPBK_V(1 U)#define FW_FILTER_WR_DMAC_S 19 #define FW_FILTER_WR_DMAC_M 0 x1#define FW_FILTER_WR_DMAC_V(x) ((x) << FW_FILTER_WR_DMAC_S)#define FW_FILTER_WR_DMAC_G(x) \#define FW_FILTER_WR_DMAC_F FW_FILTER_WR_DMAC_V(1 U)#define FW_FILTER_WR_SMAC_S 18 #define FW_FILTER_WR_SMAC_M 0 x1#define FW_FILTER_WR_SMAC_V(x) ((x) << FW_FILTER_WR_SMAC_S)#define FW_FILTER_WR_SMAC_G(x) \#define FW_FILTER_WR_SMAC_F FW_FILTER_WR_SMAC_V(1 U)#define FW_FILTER_WR_INSVLAN_S 17 #define FW_FILTER_WR_INSVLAN_M 0 x1#define FW_FILTER_WR_INSVLAN_V(x) ((x) << FW_FILTER_WR_INSVLAN_S)#define FW_FILTER_WR_INSVLAN_G(x) \#define FW_FILTER_WR_INSVLAN_F FW_FILTER_WR_INSVLAN_V(1 U)#define FW_FILTER_WR_RMVLAN_S 16 #define FW_FILTER_WR_RMVLAN_M 0 x1#define FW_FILTER_WR_RMVLAN_V(x) ((x) << FW_FILTER_WR_RMVLAN_S)#define FW_FILTER_WR_RMVLAN_G(x) \#define FW_FILTER_WR_RMVLAN_F FW_FILTER_WR_RMVLAN_V(1 U)#define FW_FILTER_WR_HITCNTS_S 15 #define FW_FILTER_WR_HITCNTS_M 0 x1#define FW_FILTER_WR_HITCNTS_V(x) ((x) << FW_FILTER_WR_HITCNTS_S)#define FW_FILTER_WR_HITCNTS_G(x) \#define FW_FILTER_WR_HITCNTS_F FW_FILTER_WR_HITCNTS_V(1 U)#define FW_FILTER_WR_TXCHAN_S 13 #define FW_FILTER_WR_TXCHAN_M 0 x3#define FW_FILTER_WR_TXCHAN_V(x) ((x) << FW_FILTER_WR_TXCHAN_S)#define FW_FILTER_WR_TXCHAN_G(x) \#define FW_FILTER_WR_PRIO_S 12 #define FW_FILTER_WR_PRIO_M 0 x1#define FW_FILTER_WR_PRIO_V(x) ((x) << FW_FILTER_WR_PRIO_S)#define FW_FILTER_WR_PRIO_G(x) \#define FW_FILTER_WR_PRIO_F FW_FILTER_WR_PRIO_V(1 U)#define FW_FILTER_WR_L2TIX_S 0 #define FW_FILTER_WR_L2TIX_M 0 xfff#define FW_FILTER_WR_L2TIX_V(x) ((x) << FW_FILTER_WR_L2TIX_S)#define FW_FILTER_WR_L2TIX_G(x) \#define FW_FILTER_WR_FRAG_S 7 #define FW_FILTER_WR_FRAG_M 0 x1#define FW_FILTER_WR_FRAG_V(x) ((x) << FW_FILTER_WR_FRAG_S)#define FW_FILTER_WR_FRAG_G(x) \#define FW_FILTER_WR_FRAG_F FW_FILTER_WR_FRAG_V(1 U)#define FW_FILTER_WR_FRAGM_S 6 #define FW_FILTER_WR_FRAGM_M 0 x1#define FW_FILTER_WR_FRAGM_V(x) ((x) << FW_FILTER_WR_FRAGM_S)#define FW_FILTER_WR_FRAGM_G(x) \#define FW_FILTER_WR_FRAGM_F FW_FILTER_WR_FRAGM_V(1 U)#define FW_FILTER_WR_IVLAN_VLD_S 5 #define FW_FILTER_WR_IVLAN_VLD_M 0 x1#define FW_FILTER_WR_IVLAN_VLD_V(x) ((x) << FW_FILTER_WR_IVLAN_VLD_S)#define FW_FILTER_WR_IVLAN_VLD_G(x) \#define FW_FILTER_WR_IVLAN_VLD_F FW_FILTER_WR_IVLAN_VLD_V(1 U)#define FW_FILTER_WR_OVLAN_VLD_S 4 #define FW_FILTER_WR_OVLAN_VLD_M 0 x1#define FW_FILTER_WR_OVLAN_VLD_V(x) ((x) << FW_FILTER_WR_OVLAN_VLD_S)#define FW_FILTER_WR_OVLAN_VLD_G(x) \#define FW_FILTER_WR_OVLAN_VLD_F FW_FILTER_WR_OVLAN_VLD_V(1 U)#define FW_FILTER_WR_IVLAN_VLDM_S 3 #define FW_FILTER_WR_IVLAN_VLDM_M 0 x1#define FW_FILTER_WR_IVLAN_VLDM_V(x) ((x) << FW_FILTER_WR_IVLAN_VLDM_S)#define FW_FILTER_WR_IVLAN_VLDM_G(x) \#define FW_FILTER_WR_IVLAN_VLDM_F FW_FILTER_WR_IVLAN_VLDM_V(1 U)#define FW_FILTER_WR_OVLAN_VLDM_S 2 #define FW_FILTER_WR_OVLAN_VLDM_M 0 x1#define FW_FILTER_WR_OVLAN_VLDM_V(x) ((x) << FW_FILTER_WR_OVLAN_VLDM_S)#define FW_FILTER_WR_OVLAN_VLDM_G(x) \#define FW_FILTER_WR_OVLAN_VLDM_F FW_FILTER_WR_OVLAN_VLDM_V(1 U)#define FW_FILTER_WR_RX_CHAN_S 15 #define FW_FILTER_WR_RX_CHAN_M 0 x1#define FW_FILTER_WR_RX_CHAN_V(x) ((x) << FW_FILTER_WR_RX_CHAN_S)#define FW_FILTER_WR_RX_CHAN_G(x) \#define FW_FILTER_WR_RX_CHAN_F FW_FILTER_WR_RX_CHAN_V(1 U)#define FW_FILTER_WR_RX_RPL_IQ_S 0 #define FW_FILTER_WR_RX_RPL_IQ_M 0 x3ff#define FW_FILTER_WR_RX_RPL_IQ_V(x) ((x) << FW_FILTER_WR_RX_RPL_IQ_S)#define FW_FILTER_WR_RX_RPL_IQ_G(x) \#define FW_FILTER2_WR_FILTER_TYPE_S 1 #define FW_FILTER2_WR_FILTER_TYPE_M 0 x1#define FW_FILTER2_WR_FILTER_TYPE_V(x) ((x) << FW_FILTER2_WR_FILTER_TYPE_S)#define FW_FILTER2_WR_FILTER_TYPE_G(x) \#define FW_FILTER2_WR_FILTER_TYPE_F FW_FILTER2_WR_FILTER_TYPE_V(1 U)#define FW_FILTER2_WR_NATMODE_S 5 #define FW_FILTER2_WR_NATMODE_M 0 x7#define FW_FILTER2_WR_NATMODE_V(x) ((x) << FW_FILTER2_WR_NATMODE_S)#define FW_FILTER2_WR_NATMODE_G(x) \#define FW_FILTER2_WR_NATFLAGCHECK_S 4 #define FW_FILTER2_WR_NATFLAGCHECK_M 0 x1#define FW_FILTER2_WR_NATFLAGCHECK_V(x) ((x) << FW_FILTER2_WR_NATFLAGCHECK_S)#define FW_FILTER2_WR_NATFLAGCHECK_G(x) \#define FW_FILTER2_WR_NATFLAGCHECK_F FW_FILTER2_WR_NATFLAGCHECK_V(1 U)#define FW_FILTER2_WR_ULP_TYPE_S 0 #define FW_FILTER2_WR_ULP_TYPE_M 0 xf#define FW_FILTER2_WR_ULP_TYPE_V(x) ((x) << FW_FILTER2_WR_ULP_TYPE_S)#define FW_FILTER2_WR_ULP_TYPE_G(x) \#define FW_FILTER_WR_MACI_S 23 #define FW_FILTER_WR_MACI_M 0 x1ff#define FW_FILTER_WR_MACI_V(x) ((x) << FW_FILTER_WR_MACI_S)#define FW_FILTER_WR_MACI_G(x) \#define FW_FILTER_WR_MACIM_S 14 #define FW_FILTER_WR_MACIM_M 0 x1ff#define FW_FILTER_WR_MACIM_V(x) ((x) << FW_FILTER_WR_MACIM_S)#define FW_FILTER_WR_MACIM_G(x) \#define FW_FILTER_WR_FCOE_S 13 #define FW_FILTER_WR_FCOE_M 0 x1#define FW_FILTER_WR_FCOE_V(x) ((x) << FW_FILTER_WR_FCOE_S)#define FW_FILTER_WR_FCOE_G(x) \#define FW_FILTER_WR_FCOE_F FW_FILTER_WR_FCOE_V(1 U)#define FW_FILTER_WR_FCOEM_S 12 #define FW_FILTER_WR_FCOEM_M 0 x1#define FW_FILTER_WR_FCOEM_V(x) ((x) << FW_FILTER_WR_FCOEM_S)#define FW_FILTER_WR_FCOEM_G(x) \#define FW_FILTER_WR_FCOEM_F FW_FILTER_WR_FCOEM_V(1 U)#define FW_FILTER_WR_PORT_S 9 #define FW_FILTER_WR_PORT_M 0 x7#define FW_FILTER_WR_PORT_V(x) ((x) << FW_FILTER_WR_PORT_S)#define FW_FILTER_WR_PORT_G(x) \#define FW_FILTER_WR_PORTM_S 6 #define FW_FILTER_WR_PORTM_M 0 x7#define FW_FILTER_WR_PORTM_V(x) ((x) << FW_FILTER_WR_PORTM_S)#define FW_FILTER_WR_PORTM_G(x) \#define FW_FILTER_WR_MATCHTYPE_S 3 #define FW_FILTER_WR_MATCHTYPE_M 0 x7#define FW_FILTER_WR_MATCHTYPE_V(x) ((x) << FW_FILTER_WR_MATCHTYPE_S)#define FW_FILTER_WR_MATCHTYPE_G(x) \#define FW_FILTER_WR_MATCHTYPEM_S 0 #define FW_FILTER_WR_MATCHTYPEM_M 0 x7#define FW_FILTER_WR_MATCHTYPEM_V(x) ((x) << FW_FILTER_WR_MATCHTYPEM_S)#define FW_FILTER_WR_MATCHTYPEM_G(x) \struct fw_ulptx_wr {#define FW_ULPTX_WR_DATA_S 28 #define FW_ULPTX_WR_DATA_M 0 x1#define FW_ULPTX_WR_DATA_V(x) ((x) << FW_ULPTX_WR_DATA_S)#define FW_ULPTX_WR_DATA_G(x) \#define FW_ULPTX_WR_DATA_F FW_ULPTX_WR_DATA_V(1 U)struct fw_tp_wr {struct fw_eth_tx_pkt_wr {enum fw_eth_tx_eo_type {0 ,struct fw_eth_tx_eo_wr {union fw_eth_tx_eo {struct fw_eth_tx_eo_udpseg {struct fw_eth_tx_eo_tcpseg {#define FW_ETH_TX_EO_WR_IMMDLEN_S 0 #define FW_ETH_TX_EO_WR_IMMDLEN_M 0 x1ff#define FW_ETH_TX_EO_WR_IMMDLEN_V(x) ((x) << FW_ETH_TX_EO_WR_IMMDLEN_S)#define FW_ETH_TX_EO_WR_IMMDLEN_G(x) \struct fw_ofld_connection_wr {struct fw_ofld_connection_le {union fw_ofld_connection_leip {struct fw_ofld_connection_le_ipv4 {struct fw_ofld_connection_le_ipv6 {struct fw_ofld_connection_tcb {#define FW_OFLD_CONNECTION_WR_VERSION_S 31 #define FW_OFLD_CONNECTION_WR_VERSION_M 0 x1#define FW_OFLD_CONNECTION_WR_VERSION_V(x) \#define FW_OFLD_CONNECTION_WR_VERSION_G(x) \#define FW_OFLD_CONNECTION_WR_VERSION_F \1 U)#define FW_OFLD_CONNECTION_WR_CPL_S 30 #define FW_OFLD_CONNECTION_WR_CPL_M 0 x1#define FW_OFLD_CONNECTION_WR_CPL_V(x) ((x) << FW_OFLD_CONNECTION_WR_CPL_S)#define FW_OFLD_CONNECTION_WR_CPL_G(x) \#define FW_OFLD_CONNECTION_WR_CPL_F FW_OFLD_CONNECTION_WR_CPL_V(1 U)#define FW_OFLD_CONNECTION_WR_T_STATE_S 28 #define FW_OFLD_CONNECTION_WR_T_STATE_M 0 xf#define FW_OFLD_CONNECTION_WR_T_STATE_V(x) \#define FW_OFLD_CONNECTION_WR_T_STATE_G(x) \#define FW_OFLD_CONNECTION_WR_RCV_SCALE_S 24 #define FW_OFLD_CONNECTION_WR_RCV_SCALE_M 0 xf#define FW_OFLD_CONNECTION_WR_RCV_SCALE_V(x) \#define FW_OFLD_CONNECTION_WR_RCV_SCALE_G(x) \#define FW_OFLD_CONNECTION_WR_ASTID_S 0 #define FW_OFLD_CONNECTION_WR_ASTID_M 0 xffffff#define FW_OFLD_CONNECTION_WR_ASTID_V(x) \#define FW_OFLD_CONNECTION_WR_ASTID_G(x) \#define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_S 15 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_M 0 x1#define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_V(x) \#define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_G(x) \#define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_F \1 U)#define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_S 14 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_M 0 x1#define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_V(x) \#define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_G(x) \#define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_F \1 U)enum fw_flowc_mnem_tcpstate {0 , /* illegal */ 1 , /* illegal */ 2 , /* illegal */ 3 , /* illegal */ 4 , /* default */ 5 , /* got peer close already */ 6 , /* haven't gotten ACK for FIN and * will resend FIN - equiv ESTAB 7 , /* haven't gotten ACK for FIN and * will resend FIN but have * received FIN 8 , /* haven't gotten ACK for FIN and * will resend FIN but have * received FIN 9 , /* sent FIN and got FIN + ACK, * waiting for FIN 10 , /* not expected */ enum fw_flowc_mnem_eostate {1 , /* default */ /* graceful close, after sending outstanding payload */ 2 ,enum fw_flowc_mnem {/* PFN [15:8] VFN [7:0] */ struct fw_flowc_mnemval {3 ];struct fw_flowc_wr {struct fw_flowc_mnemval mnemval[];#define FW_FLOWC_WR_NPARAMS_S 0 #define FW_FLOWC_WR_NPARAMS_V(x) ((x) << FW_FLOWC_WR_NPARAMS_S)struct fw_ofld_tx_data_wr {#define FW_OFLD_TX_DATA_WR_ALIGNPLD_S 30 #define FW_OFLD_TX_DATA_WR_ALIGNPLD_V(x) ((x) << FW_OFLD_TX_DATA_WR_ALIGNPLD_S)#define FW_OFLD_TX_DATA_WR_ALIGNPLD_F FW_OFLD_TX_DATA_WR_ALIGNPLD_V(1 U)#define FW_OFLD_TX_DATA_WR_SHOVE_S 29 #define FW_OFLD_TX_DATA_WR_SHOVE_V(x) ((x) << FW_OFLD_TX_DATA_WR_SHOVE_S)#define FW_OFLD_TX_DATA_WR_SHOVE_F FW_OFLD_TX_DATA_WR_SHOVE_V(1 U)#define FW_OFLD_TX_DATA_WR_TUNNEL_S 19 #define FW_OFLD_TX_DATA_WR_TUNNEL_V(x) ((x) << FW_OFLD_TX_DATA_WR_TUNNEL_S)#define FW_OFLD_TX_DATA_WR_SAVE_S 18 #define FW_OFLD_TX_DATA_WR_SAVE_V(x) ((x) << FW_OFLD_TX_DATA_WR_SAVE_S)#define FW_OFLD_TX_DATA_WR_FLUSH_S 17 #define FW_OFLD_TX_DATA_WR_FLUSH_V(x) ((x) << FW_OFLD_TX_DATA_WR_FLUSH_S)#define FW_OFLD_TX_DATA_WR_FLUSH_F FW_OFLD_TX_DATA_WR_FLUSH_V(1 U)#define FW_OFLD_TX_DATA_WR_URGENT_S 16 #define FW_OFLD_TX_DATA_WR_URGENT_V(x) ((x) << FW_OFLD_TX_DATA_WR_URGENT_S)#define FW_OFLD_TX_DATA_WR_MORE_S 15 #define FW_OFLD_TX_DATA_WR_MORE_V(x) ((x) << FW_OFLD_TX_DATA_WR_MORE_S)#define FW_OFLD_TX_DATA_WR_ULPMODE_S 10 #define FW_OFLD_TX_DATA_WR_ULPMODE_V(x) ((x) << FW_OFLD_TX_DATA_WR_ULPMODE_S)#define FW_OFLD_TX_DATA_WR_ULPSUBMODE_S 6 #define FW_OFLD_TX_DATA_WR_ULPSUBMODE_V(x) \struct fw_cmd_wr {#define FW_CMD_WR_DMA_S 17 #define FW_CMD_WR_DMA_V(x) ((x) << FW_CMD_WR_DMA_S)struct fw_eth_tx_pkt_vm_wr {2 ];#define FW_CMD_MAX_TIMEOUT 10000 /* * If a host driver does a HELLO and discovers that there's already a MASTER * selected, we may have to wait for that MASTER to finish issuing RESET, * configuration and INITIALIZE commands. Also, there's a possibility that * our own HELLO may get lost if it happens right as the MASTER is issuign a * RESET command, so we need to be willing to make a few retries of our HELLO. #define FW_CMD_HELLO_TIMEOUT (3 * FW_CMD_MAX_TIMEOUT)#define FW_CMD_HELLO_RETRIES 3 enum fw_cmd_opcodes {0 x01,0 x03,0 x04,0 x05,0 x06,0 x07,0 x08,0 x09,0 x10,0 x11,0 x12,0 x13,0 x21,0 x14,0 x15,0 x16,0 x17,0 x18,0 x19,0 x1a,0 x1b,0 x1c,0 x1d,0 x1e,0 x1f,0 x20,0 x22,0 x23,0 x24,0 x25,0 x28,0 x3e,0 x3f,0 x40,0 x80,0 x81,enum fw_cmd_cap {0 x01,0 x02,0 x04,0 x08,0 x10,0 x80,/* * Generic command header flit0 struct fw_cmd_hdr {#define FW_CMD_OP_S 24 #define FW_CMD_OP_M 0 xff#define FW_CMD_OP_V(x) ((x) << FW_CMD_OP_S)#define FW_CMD_OP_G(x) (((x) >> FW_CMD_OP_S) & FW_CMD_OP_M)#define FW_CMD_REQUEST_S 23 #define FW_CMD_REQUEST_V(x) ((x) << FW_CMD_REQUEST_S)#define FW_CMD_REQUEST_F FW_CMD_REQUEST_V(1 U)#define FW_CMD_READ_S 22 #define FW_CMD_READ_V(x) ((x) << FW_CMD_READ_S)#define FW_CMD_READ_F FW_CMD_READ_V(1 U)#define FW_CMD_WRITE_S 21 #define FW_CMD_WRITE_V(x) ((x) << FW_CMD_WRITE_S)#define FW_CMD_WRITE_F FW_CMD_WRITE_V(1 U)#define FW_CMD_EXEC_S 20 #define FW_CMD_EXEC_V(x) ((x) << FW_CMD_EXEC_S)#define FW_CMD_EXEC_F FW_CMD_EXEC_V(1 U)#define FW_CMD_RAMASK_S 20 #define FW_CMD_RAMASK_V(x) ((x) << FW_CMD_RAMASK_S)#define FW_CMD_RETVAL_S 8 #define FW_CMD_RETVAL_M 0 xff#define FW_CMD_RETVAL_V(x) ((x) << FW_CMD_RETVAL_S)#define FW_CMD_RETVAL_G(x) (((x) >> FW_CMD_RETVAL_S) & FW_CMD_RETVAL_M)#define FW_CMD_LEN16_S 0 #define FW_CMD_LEN16_V(x) ((x) << FW_CMD_LEN16_S)#define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof (fw_struct) / 16 )enum fw_ldst_addrspc {0 x0001,0 x0008,0 x0009,0 x000a,0 x000b,0 x0010,0 x0011,0 x0012,0 x0018,0 x0020,0 x0028,0 x0029,0 x0038,enum fw_ldst_mps_fid {enum fw_ldst_func_access_ctl {enum fw_ldst_func_mod_index {struct fw_ldst_cmd {union fw_ldst {struct fw_ldst_addrval {struct fw_ldst_idctxt {struct fw_ldst_mdio {struct fw_ldst_cim_rq {8 ];8 ];8 ];8 ];2 ];union fw_ldst_mps {struct fw_ldst_mps_rplc {struct fw_ldst_mps_atrb {3 ];2 ];16 ];struct fw_ldst_func {struct fw_ldst_pcie {12 ];struct fw_ldst_i2c_deprecated {struct fw_ldst_i2c {48 ];struct fw_ldst_le {33 ];7 ];#define FW_LDST_CMD_ADDRSPACE_S 0 #define FW_LDST_CMD_ADDRSPACE_V(x) ((x) << FW_LDST_CMD_ADDRSPACE_S)#define FW_LDST_CMD_MSG_S 31 #define FW_LDST_CMD_MSG_V(x) ((x) << FW_LDST_CMD_MSG_S)#define FW_LDST_CMD_CTXTFLUSH_S 30 #define FW_LDST_CMD_CTXTFLUSH_V(x) ((x) << FW_LDST_CMD_CTXTFLUSH_S)#define FW_LDST_CMD_CTXTFLUSH_F FW_LDST_CMD_CTXTFLUSH_V(1 U)#define FW_LDST_CMD_PADDR_S 8 #define FW_LDST_CMD_PADDR_V(x) ((x) << FW_LDST_CMD_PADDR_S)#define FW_LDST_CMD_MMD_S 0 #define FW_LDST_CMD_MMD_V(x) ((x) << FW_LDST_CMD_MMD_S)#define FW_LDST_CMD_FID_S 15 #define FW_LDST_CMD_FID_V(x) ((x) << FW_LDST_CMD_FID_S)#define FW_LDST_CMD_IDX_S 0 #define FW_LDST_CMD_IDX_V(x) ((x) << FW_LDST_CMD_IDX_S)#define FW_LDST_CMD_RPLCPF_S 0 #define FW_LDST_CMD_RPLCPF_V(x) ((x) << FW_LDST_CMD_RPLCPF_S)#define FW_LDST_CMD_LC_S 4 #define FW_LDST_CMD_LC_V(x) ((x) << FW_LDST_CMD_LC_S)#define FW_LDST_CMD_LC_F FW_LDST_CMD_LC_V(1 U)#define FW_LDST_CMD_FN_S 0 #define FW_LDST_CMD_FN_V(x) ((x) << FW_LDST_CMD_FN_S)#define FW_LDST_CMD_NACCESS_S 0 #define FW_LDST_CMD_NACCESS_V(x) ((x) << FW_LDST_CMD_NACCESS_S)struct fw_reset_cmd {#define FW_RESET_CMD_HALT_S 31 #define FW_RESET_CMD_HALT_M 0 x1#define FW_RESET_CMD_HALT_V(x) ((x) << FW_RESET_CMD_HALT_S)#define FW_RESET_CMD_HALT_G(x) \#define FW_RESET_CMD_HALT_F FW_RESET_CMD_HALT_V(1 U)enum fw_hellow_cmd {0 x0struct fw_hello_cmd {#define FW_HELLO_CMD_ERR_S 31 #define FW_HELLO_CMD_ERR_V(x) ((x) << FW_HELLO_CMD_ERR_S)#define FW_HELLO_CMD_ERR_F FW_HELLO_CMD_ERR_V(1 U)#define FW_HELLO_CMD_INIT_S 30 #define FW_HELLO_CMD_INIT_V(x) ((x) << FW_HELLO_CMD_INIT_S)#define FW_HELLO_CMD_INIT_F FW_HELLO_CMD_INIT_V(1 U)#define FW_HELLO_CMD_MASTERDIS_S 29 #define FW_HELLO_CMD_MASTERDIS_V(x) ((x) << FW_HELLO_CMD_MASTERDIS_S)#define FW_HELLO_CMD_MASTERFORCE_S 28 #define FW_HELLO_CMD_MASTERFORCE_V(x) ((x) << FW_HELLO_CMD_MASTERFORCE_S)#define FW_HELLO_CMD_MBMASTER_S 24 #define FW_HELLO_CMD_MBMASTER_M 0 xfU#define FW_HELLO_CMD_MBMASTER_V(x) ((x) << FW_HELLO_CMD_MBMASTER_S)#define FW_HELLO_CMD_MBMASTER_G(x) \#define FW_HELLO_CMD_MBASYNCNOTINT_S 23 #define FW_HELLO_CMD_MBASYNCNOTINT_V(x) ((x) << FW_HELLO_CMD_MBASYNCNOTINT_S)#define FW_HELLO_CMD_MBASYNCNOT_S 20 #define FW_HELLO_CMD_MBASYNCNOT_V(x) ((x) << FW_HELLO_CMD_MBASYNCNOT_S)#define FW_HELLO_CMD_STAGE_S 17 #define FW_HELLO_CMD_STAGE_V(x) ((x) << FW_HELLO_CMD_STAGE_S)#define FW_HELLO_CMD_CLEARINIT_S 16 #define FW_HELLO_CMD_CLEARINIT_V(x) ((x) << FW_HELLO_CMD_CLEARINIT_S)#define FW_HELLO_CMD_CLEARINIT_F FW_HELLO_CMD_CLEARINIT_V(1 U)struct fw_bye_cmd {struct fw_initialize_cmd {enum fw_caps_config_hm {0 x00000001,0 x00000002,0 x00000004,0 x00000008,0 x00000010,0 x00000020,0 x00000040,0 x00000080,0 x00000100,0 x00000200,0 x00000400,0 x00000800,0 x00001000,0 x00002000,0 x00004000,0 x00008000,0 x00010000,0 x00020000,0 x00040000,0 x00080000,0 x00100000,0 x00200000,0 x00400000,0 x00800000,enum fw_caps_config_nbm {0 x00000001,0 x00000002,enum fw_caps_config_link {0 x00000001,0 x00000002,0 x00000004,enum fw_caps_config_switch {0 x00000001,0 x00000002,enum fw_caps_config_nic {0 x00000001,0 x00000002,0 x00000020,0 x00000040,enum fw_caps_config_ofld {0 x00000001,enum fw_caps_config_rdma {0 x00000001,0 x00000002,enum fw_caps_config_iscsi {0 x00000001,0 x00000002,0 x00000004,0 x00000008,enum fw_caps_config_crypto {0 x00000001,0 x00000002,0 x00000004,0 x00000008,enum fw_caps_config_fcoe {0 x00000001,0 x00000002,0 x00000004,enum fw_memtype_cf {0 x0,0 x1,0 x2,0 x4,0 x5,0 x6,0 x7,struct fw_caps_config_cmd {#define FW_CAPS_CONFIG_CMD_CFVALID_S 27 #define FW_CAPS_CONFIG_CMD_CFVALID_V(x) ((x) << FW_CAPS_CONFIG_CMD_CFVALID_S)#define FW_CAPS_CONFIG_CMD_CFVALID_F FW_CAPS_CONFIG_CMD_CFVALID_V(1 U)#define FW_CAPS_CONFIG_CMD_MEMTYPE_CF_S 24 #define FW_CAPS_CONFIG_CMD_MEMTYPE_CF_V(x) \#define FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_S 16 #define FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_V(x) \/* * params command mnemonics enum fw_params_mnem {1 , /* device params */ 2 , /* function params */ 3 , /* limited register access */ 4 , /* dma queue params */ 5 , /* chnet params */ /* * device parameters #define FW_PARAMS_PARAM_FILTER_MODE_S 16 #define FW_PARAMS_PARAM_FILTER_MODE_M 0 xffff#define FW_PARAMS_PARAM_FILTER_MODE_V(x) \#define FW_PARAMS_PARAM_FILTER_MODE_G(x) \#define FW_PARAMS_PARAM_FILTER_MASK_S 0 #define FW_PARAMS_PARAM_FILTER_MASK_M 0 xffff#define FW_PARAMS_PARAM_FILTER_MASK_V(x) \#define FW_PARAMS_PARAM_FILTER_MASK_G(x) \enum fw_params_param_dev {0 x00, /* chip core clock in khz */ 0 x01, /* the port vector */ 0 x02, /* reads the number of TIDs * allocated by the device's * Lookup Engine 0 x03,0 x04,0 x05,0 x06,0 x07,0 x08,0 x09,0 x0A,0 x0B,0 x0C,0 x0D,0 x0F,0 x11,0 x13, /* max supported QP IRD/ORD */ 0 x14, /* max supported adap IRD */ 0 x17,0 x18,0 x1A,0 x1B,0 x1C,0 x1D,0 x1E,0 x1F,0 x20,0 x21,0 x23,0 x24,0 x26,0 x27,0 x28,0 x29,0 x2A,0 x2B,0 x2E,0 x31,/* * physical and virtual function parameters enum fw_params_param_pfvf {0 x00,0 x01,0 x02,0 x03,0 x04,0 x05,0 x06,0 x07,0 x08,0 x09,0 x0A,0 x0B,0 x0C,0 x0D,0 x0E,0 x1F,0 x10,0 x11,0 x12,0 x13,0 x14,0 x15,0 x16,0 x17,0 x18,0 x19,0 x1A,0 x20,0 x24,0 x25,0 x26,0 x27,0 x28,0 x29,0 x2A,0 x2B,0 x2C,0 x2D,0 x2E,0 x2F,0 x30,0 x31,0 x32,0 x33,0 x34,0 x35,0 x36,0 x37,0 x39,0 x3A,0 x3B,0 x3C,0 x40,/* Virtual link state as seen by the specified VF */ enum vf_link_states {0 x00,0 x01,0 x02,/* * dma queue parameters enum fw_params_param_dmaq {0 x00,0 x01,0 x10,0 x11,0 x12,0 x13,0 x15,0 x20,enum fw_params_param_dev_ktls_hw {0 x00,0 x01,0 x01,enum fw_params_param_dev_phyfw {0 x00,0 x01,enum fw_params_param_dev_diag {0 x00,0 x01,0 x02,enum fw_params_param_dev_filter {0 x00,0 x01,enum fw_params_param_dev_fwcache {0 x00,0 x01,#define FW_PARAMS_MNEM_S 24 #define FW_PARAMS_MNEM_V(x) ((x) << FW_PARAMS_MNEM_S)#define FW_PARAMS_PARAM_X_S 16 #define FW_PARAMS_PARAM_X_V(x) ((x) << FW_PARAMS_PARAM_X_S)#define FW_PARAMS_PARAM_Y_S 8 #define FW_PARAMS_PARAM_Y_M 0 xffU#define FW_PARAMS_PARAM_Y_V(x) ((x) << FW_PARAMS_PARAM_Y_S)#define FW_PARAMS_PARAM_Y_G(x) (((x) >> FW_PARAMS_PARAM_Y_S) &\#define FW_PARAMS_PARAM_Z_S 0 #define FW_PARAMS_PARAM_Z_M 0 xffu#define FW_PARAMS_PARAM_Z_V(x) ((x) << FW_PARAMS_PARAM_Z_S)#define FW_PARAMS_PARAM_Z_G(x) (((x) >> FW_PARAMS_PARAM_Z_S) &\#define FW_PARAMS_PARAM_XYZ_S 0 #define FW_PARAMS_PARAM_XYZ_V(x) ((x) << FW_PARAMS_PARAM_XYZ_S)#define FW_PARAMS_PARAM_YZ_S 0 #define FW_PARAMS_PARAM_YZ_V(x) ((x) << FW_PARAMS_PARAM_YZ_S)struct fw_params_cmd {struct fw_params_param {7 ];#define FW_PARAMS_CMD_PFN_S 8 #define FW_PARAMS_CMD_PFN_V(x) ((x) << FW_PARAMS_CMD_PFN_S)#define FW_PARAMS_CMD_VFN_S 0 #define FW_PARAMS_CMD_VFN_V(x) ((x) << FW_PARAMS_CMD_VFN_S)struct fw_pfvf_cmd {#define FW_PFVF_CMD_PFN_S 8 #define FW_PFVF_CMD_PFN_V(x) ((x) << FW_PFVF_CMD_PFN_S)#define FW_PFVF_CMD_VFN_S 0 #define FW_PFVF_CMD_VFN_V(x) ((x) << FW_PFVF_CMD_VFN_S)#define FW_PFVF_CMD_NIQFLINT_S 20 #define FW_PFVF_CMD_NIQFLINT_M 0 xfff#define FW_PFVF_CMD_NIQFLINT_V(x) ((x) << FW_PFVF_CMD_NIQFLINT_S)#define FW_PFVF_CMD_NIQFLINT_G(x) \#define FW_PFVF_CMD_NIQ_S 0 #define FW_PFVF_CMD_NIQ_M 0 xfffff#define FW_PFVF_CMD_NIQ_V(x) ((x) << FW_PFVF_CMD_NIQ_S)#define FW_PFVF_CMD_NIQ_G(x) \#define FW_PFVF_CMD_TYPE_S 31 #define FW_PFVF_CMD_TYPE_M 0 x1#define FW_PFVF_CMD_TYPE_V(x) ((x) << FW_PFVF_CMD_TYPE_S)#define FW_PFVF_CMD_TYPE_G(x) \#define FW_PFVF_CMD_TYPE_F FW_PFVF_CMD_TYPE_V(1 U)#define FW_PFVF_CMD_CMASK_S 24 #define FW_PFVF_CMD_CMASK_M 0 xf#define FW_PFVF_CMD_CMASK_V(x) ((x) << FW_PFVF_CMD_CMASK_S)#define FW_PFVF_CMD_CMASK_G(x) \#define FW_PFVF_CMD_PMASK_S 20 #define FW_PFVF_CMD_PMASK_M 0 xf#define FW_PFVF_CMD_PMASK_V(x) ((x) << FW_PFVF_CMD_PMASK_S)#define FW_PFVF_CMD_PMASK_G(x) \#define FW_PFVF_CMD_NEQ_S 0 #define FW_PFVF_CMD_NEQ_M 0 xfffff#define FW_PFVF_CMD_NEQ_V(x) ((x) << FW_PFVF_CMD_NEQ_S)#define FW_PFVF_CMD_NEQ_G(x) \#define FW_PFVF_CMD_TC_S 24 #define FW_PFVF_CMD_TC_M 0 xff#define FW_PFVF_CMD_TC_V(x) ((x) << FW_PFVF_CMD_TC_S)#define FW_PFVF_CMD_TC_G(x) (((x) >> FW_PFVF_CMD_TC_S) & FW_PFVF_CMD_TC_M)#define FW_PFVF_CMD_NVI_S 16 #define FW_PFVF_CMD_NVI_M 0 xff#define FW_PFVF_CMD_NVI_V(x) ((x) << FW_PFVF_CMD_NVI_S)#define FW_PFVF_CMD_NVI_G(x) (((x) >> FW_PFVF_CMD_NVI_S) & FW_PFVF_CMD_NVI_M)#define FW_PFVF_CMD_NEXACTF_S 0 #define FW_PFVF_CMD_NEXACTF_M 0 xffff#define FW_PFVF_CMD_NEXACTF_V(x) ((x) << FW_PFVF_CMD_NEXACTF_S)#define FW_PFVF_CMD_NEXACTF_G(x) \#define FW_PFVF_CMD_R_CAPS_S 24 #define FW_PFVF_CMD_R_CAPS_M 0 xff#define FW_PFVF_CMD_R_CAPS_V(x) ((x) << FW_PFVF_CMD_R_CAPS_S)#define FW_PFVF_CMD_R_CAPS_G(x) \#define FW_PFVF_CMD_WX_CAPS_S 16 #define FW_PFVF_CMD_WX_CAPS_M 0 xff#define FW_PFVF_CMD_WX_CAPS_V(x) ((x) << FW_PFVF_CMD_WX_CAPS_S)#define FW_PFVF_CMD_WX_CAPS_G(x) \#define FW_PFVF_CMD_NETHCTRL_S 0 #define FW_PFVF_CMD_NETHCTRL_M 0 xffff#define FW_PFVF_CMD_NETHCTRL_V(x) ((x) << FW_PFVF_CMD_NETHCTRL_S)#define FW_PFVF_CMD_NETHCTRL_G(x) \enum fw_iq_type {enum fw_iq_iqtype {struct fw_iq_cmd {#define FW_IQ_CMD_PFN_S 8 #define FW_IQ_CMD_PFN_V(x) ((x) << FW_IQ_CMD_PFN_S)#define FW_IQ_CMD_VFN_S 0 #define FW_IQ_CMD_VFN_V(x) ((x) << FW_IQ_CMD_VFN_S)#define FW_IQ_CMD_ALLOC_S 31 #define FW_IQ_CMD_ALLOC_V(x) ((x) << FW_IQ_CMD_ALLOC_S)#define FW_IQ_CMD_ALLOC_F FW_IQ_CMD_ALLOC_V(1 U)#define FW_IQ_CMD_FREE_S 30 #define FW_IQ_CMD_FREE_V(x) ((x) << FW_IQ_CMD_FREE_S)#define FW_IQ_CMD_FREE_F FW_IQ_CMD_FREE_V(1 U)#define FW_IQ_CMD_MODIFY_S 29 #define FW_IQ_CMD_MODIFY_V(x) ((x) << FW_IQ_CMD_MODIFY_S)#define FW_IQ_CMD_MODIFY_F FW_IQ_CMD_MODIFY_V(1 U)#define FW_IQ_CMD_IQSTART_S 28 #define FW_IQ_CMD_IQSTART_V(x) ((x) << FW_IQ_CMD_IQSTART_S)#define FW_IQ_CMD_IQSTART_F FW_IQ_CMD_IQSTART_V(1 U)#define FW_IQ_CMD_IQSTOP_S 27 #define FW_IQ_CMD_IQSTOP_V(x) ((x) << FW_IQ_CMD_IQSTOP_S)#define FW_IQ_CMD_IQSTOP_F FW_IQ_CMD_IQSTOP_V(1 U)#define FW_IQ_CMD_TYPE_S 29 #define FW_IQ_CMD_TYPE_V(x) ((x) << FW_IQ_CMD_TYPE_S)#define FW_IQ_CMD_IQASYNCH_S 28 #define FW_IQ_CMD_IQASYNCH_V(x) ((x) << FW_IQ_CMD_IQASYNCH_S)#define FW_IQ_CMD_VIID_S 16 #define FW_IQ_CMD_VIID_V(x) ((x) << FW_IQ_CMD_VIID_S)#define FW_IQ_CMD_IQANDST_S 15 #define FW_IQ_CMD_IQANDST_V(x) ((x) << FW_IQ_CMD_IQANDST_S)#define FW_IQ_CMD_IQANUS_S 14 #define FW_IQ_CMD_IQANUS_V(x) ((x) << FW_IQ_CMD_IQANUS_S)#define FW_IQ_CMD_IQANUD_S 12 #define FW_IQ_CMD_IQANUD_V(x) ((x) << FW_IQ_CMD_IQANUD_S)#define FW_IQ_CMD_IQANDSTINDEX_S 0 #define FW_IQ_CMD_IQANDSTINDEX_V(x) ((x) << FW_IQ_CMD_IQANDSTINDEX_S)#define FW_IQ_CMD_IQDROPRSS_S 15 #define FW_IQ_CMD_IQDROPRSS_V(x) ((x) << FW_IQ_CMD_IQDROPRSS_S)#define FW_IQ_CMD_IQDROPRSS_F FW_IQ_CMD_IQDROPRSS_V(1 U)#define FW_IQ_CMD_IQGTSMODE_S 14 #define FW_IQ_CMD_IQGTSMODE_V(x) ((x) << FW_IQ_CMD_IQGTSMODE_S)#define FW_IQ_CMD_IQGTSMODE_F FW_IQ_CMD_IQGTSMODE_V(1 U)#define FW_IQ_CMD_IQPCIECH_S 12 #define FW_IQ_CMD_IQPCIECH_V(x) ((x) << FW_IQ_CMD_IQPCIECH_S)#define FW_IQ_CMD_IQDCAEN_S 11 #define FW_IQ_CMD_IQDCAEN_V(x) ((x) << FW_IQ_CMD_IQDCAEN_S)#define FW_IQ_CMD_IQDCACPU_S 6 #define FW_IQ_CMD_IQDCACPU_V(x) ((x) << FW_IQ_CMD_IQDCACPU_S)#define FW_IQ_CMD_IQINTCNTTHRESH_S 4 #define FW_IQ_CMD_IQINTCNTTHRESH_V(x) ((x) << FW_IQ_CMD_IQINTCNTTHRESH_S)#define FW_IQ_CMD_IQO_S 3 #define FW_IQ_CMD_IQO_V(x) ((x) << FW_IQ_CMD_IQO_S)#define FW_IQ_CMD_IQO_F FW_IQ_CMD_IQO_V(1 U)#define FW_IQ_CMD_IQCPRIO_S 2 #define FW_IQ_CMD_IQCPRIO_V(x) ((x) << FW_IQ_CMD_IQCPRIO_S)#define FW_IQ_CMD_IQESIZE_S 0 #define FW_IQ_CMD_IQESIZE_V(x) ((x) << FW_IQ_CMD_IQESIZE_S)#define FW_IQ_CMD_IQNS_S 31 #define FW_IQ_CMD_IQNS_V(x) ((x) << FW_IQ_CMD_IQNS_S)#define FW_IQ_CMD_IQRO_S 30 #define FW_IQ_CMD_IQRO_V(x) ((x) << FW_IQ_CMD_IQRO_S)#define FW_IQ_CMD_IQFLINTIQHSEN_S 28 #define FW_IQ_CMD_IQFLINTIQHSEN_V(x) ((x) << FW_IQ_CMD_IQFLINTIQHSEN_S)#define FW_IQ_CMD_IQFLINTCONGEN_S 27 #define FW_IQ_CMD_IQFLINTCONGEN_V(x) ((x) << FW_IQ_CMD_IQFLINTCONGEN_S)#define FW_IQ_CMD_IQFLINTCONGEN_F FW_IQ_CMD_IQFLINTCONGEN_V(1 U)#define FW_IQ_CMD_IQFLINTISCSIC_S 26 #define FW_IQ_CMD_IQFLINTISCSIC_V(x) ((x) << FW_IQ_CMD_IQFLINTISCSIC_S)#define FW_IQ_CMD_IQTYPE_S 24 #define FW_IQ_CMD_IQTYPE_M 0 x3#define FW_IQ_CMD_IQTYPE_V(x) ((x) << FW_IQ_CMD_IQTYPE_S)#define FW_IQ_CMD_IQTYPE_G(x) \#define FW_IQ_CMD_FL0CNGCHMAP_S 20 #define FW_IQ_CMD_FL0CNGCHMAP_V(x) ((x) << FW_IQ_CMD_FL0CNGCHMAP_S)#define FW_IQ_CMD_FL0CACHELOCK_S 15 #define FW_IQ_CMD_FL0CACHELOCK_V(x) ((x) << FW_IQ_CMD_FL0CACHELOCK_S)#define FW_IQ_CMD_FL0DBP_S 14 #define FW_IQ_CMD_FL0DBP_V(x) ((x) << FW_IQ_CMD_FL0DBP_S)#define FW_IQ_CMD_FL0DATANS_S 13 #define FW_IQ_CMD_FL0DATANS_V(x) ((x) << FW_IQ_CMD_FL0DATANS_S)#define FW_IQ_CMD_FL0DATARO_S 12 #define FW_IQ_CMD_FL0DATARO_V(x) ((x) << FW_IQ_CMD_FL0DATARO_S)#define FW_IQ_CMD_FL0DATARO_F FW_IQ_CMD_FL0DATARO_V(1 U)#define FW_IQ_CMD_FL0CONGCIF_S 11 #define FW_IQ_CMD_FL0CONGCIF_V(x) ((x) << FW_IQ_CMD_FL0CONGCIF_S)#define FW_IQ_CMD_FL0CONGCIF_F FW_IQ_CMD_FL0CONGCIF_V(1 U)#define FW_IQ_CMD_FL0ONCHIP_S 10 #define FW_IQ_CMD_FL0ONCHIP_V(x) ((x) << FW_IQ_CMD_FL0ONCHIP_S)#define FW_IQ_CMD_FL0STATUSPGNS_S 9 #define FW_IQ_CMD_FL0STATUSPGNS_V(x) ((x) << FW_IQ_CMD_FL0STATUSPGNS_S)#define FW_IQ_CMD_FL0STATUSPGRO_S 8 #define FW_IQ_CMD_FL0STATUSPGRO_V(x) ((x) << FW_IQ_CMD_FL0STATUSPGRO_S)#define FW_IQ_CMD_FL0FETCHNS_S 7 #define FW_IQ_CMD_FL0FETCHNS_V(x) ((x) << FW_IQ_CMD_FL0FETCHNS_S)#define FW_IQ_CMD_FL0FETCHRO_S 6 #define FW_IQ_CMD_FL0FETCHRO_V(x) ((x) << FW_IQ_CMD_FL0FETCHRO_S)#define FW_IQ_CMD_FL0FETCHRO_F FW_IQ_CMD_FL0FETCHRO_V(1 U)#define FW_IQ_CMD_FL0HOSTFCMODE_S 4 #define FW_IQ_CMD_FL0HOSTFCMODE_V(x) ((x) << FW_IQ_CMD_FL0HOSTFCMODE_S)#define FW_IQ_CMD_FL0CPRIO_S 3 #define FW_IQ_CMD_FL0CPRIO_V(x) ((x) << FW_IQ_CMD_FL0CPRIO_S)#define FW_IQ_CMD_FL0PADEN_S 2 #define FW_IQ_CMD_FL0PADEN_V(x) ((x) << FW_IQ_CMD_FL0PADEN_S)#define FW_IQ_CMD_FL0PADEN_F FW_IQ_CMD_FL0PADEN_V(1 U)#define FW_IQ_CMD_FL0PACKEN_S 1 #define FW_IQ_CMD_FL0PACKEN_V(x) ((x) << FW_IQ_CMD_FL0PACKEN_S)#define FW_IQ_CMD_FL0PACKEN_F FW_IQ_CMD_FL0PACKEN_V(1 U)#define FW_IQ_CMD_FL0CONGEN_S 0 #define FW_IQ_CMD_FL0CONGEN_V(x) ((x) << FW_IQ_CMD_FL0CONGEN_S)#define FW_IQ_CMD_FL0CONGEN_F FW_IQ_CMD_FL0CONGEN_V(1 U)#define FW_IQ_CMD_FL0DCAEN_S 15 #define FW_IQ_CMD_FL0DCAEN_V(x) ((x) << FW_IQ_CMD_FL0DCAEN_S)#define FW_IQ_CMD_FL0DCACPU_S 10 #define FW_IQ_CMD_FL0DCACPU_V(x) ((x) << FW_IQ_CMD_FL0DCACPU_S)#define FW_IQ_CMD_FL0FBMIN_S 7 #define FW_IQ_CMD_FL0FBMIN_V(x) ((x) << FW_IQ_CMD_FL0FBMIN_S)#define FW_IQ_CMD_FL0FBMAX_S 4 #define FW_IQ_CMD_FL0FBMAX_V(x) ((x) << FW_IQ_CMD_FL0FBMAX_S)#define FW_IQ_CMD_FL0CIDXFTHRESHO_S 3 #define FW_IQ_CMD_FL0CIDXFTHRESHO_V(x) ((x) << FW_IQ_CMD_FL0CIDXFTHRESHO_S)#define FW_IQ_CMD_FL0CIDXFTHRESHO_F FW_IQ_CMD_FL0CIDXFTHRESHO_V(1 U)#define FW_IQ_CMD_FL0CIDXFTHRESH_S 0 #define FW_IQ_CMD_FL0CIDXFTHRESH_V(x) ((x) << FW_IQ_CMD_FL0CIDXFTHRESH_S)#define FW_IQ_CMD_FL1CNGCHMAP_S 20 #define FW_IQ_CMD_FL1CNGCHMAP_V(x) ((x) << FW_IQ_CMD_FL1CNGCHMAP_S)#define FW_IQ_CMD_FL1CACHELOCK_S 15 #define FW_IQ_CMD_FL1CACHELOCK_V(x) ((x) << FW_IQ_CMD_FL1CACHELOCK_S)#define FW_IQ_CMD_FL1DBP_S 14 #define FW_IQ_CMD_FL1DBP_V(x) ((x) << FW_IQ_CMD_FL1DBP_S)#define FW_IQ_CMD_FL1DATANS_S 13 #define FW_IQ_CMD_FL1DATANS_V(x) ((x) << FW_IQ_CMD_FL1DATANS_S)#define FW_IQ_CMD_FL1DATARO_S 12 #define FW_IQ_CMD_FL1DATARO_V(x) ((x) << FW_IQ_CMD_FL1DATARO_S)#define FW_IQ_CMD_FL1CONGCIF_S 11 #define FW_IQ_CMD_FL1CONGCIF_V(x) ((x) << FW_IQ_CMD_FL1CONGCIF_S)#define FW_IQ_CMD_FL1ONCHIP_S 10 #define FW_IQ_CMD_FL1ONCHIP_V(x) ((x) << FW_IQ_CMD_FL1ONCHIP_S)#define FW_IQ_CMD_FL1STATUSPGNS_S 9 #define FW_IQ_CMD_FL1STATUSPGNS_V(x) ((x) << FW_IQ_CMD_FL1STATUSPGNS_S)#define FW_IQ_CMD_FL1STATUSPGRO_S 8 #define FW_IQ_CMD_FL1STATUSPGRO_V(x) ((x) << FW_IQ_CMD_FL1STATUSPGRO_S)#define FW_IQ_CMD_FL1FETCHNS_S 7 #define FW_IQ_CMD_FL1FETCHNS_V(x) ((x) << FW_IQ_CMD_FL1FETCHNS_S)#define FW_IQ_CMD_FL1FETCHRO_S 6 #define FW_IQ_CMD_FL1FETCHRO_V(x) ((x) << FW_IQ_CMD_FL1FETCHRO_S)#define FW_IQ_CMD_FL1HOSTFCMODE_S 4 #define FW_IQ_CMD_FL1HOSTFCMODE_V(x) ((x) << FW_IQ_CMD_FL1HOSTFCMODE_S)#define FW_IQ_CMD_FL1CPRIO_S 3 #define FW_IQ_CMD_FL1CPRIO_V(x) ((x) << FW_IQ_CMD_FL1CPRIO_S)#define FW_IQ_CMD_FL1PADEN_S 2 #define FW_IQ_CMD_FL1PADEN_V(x) ((x) << FW_IQ_CMD_FL1PADEN_S)#define FW_IQ_CMD_FL1PADEN_F FW_IQ_CMD_FL1PADEN_V(1 U)#define FW_IQ_CMD_FL1PACKEN_S 1 #define FW_IQ_CMD_FL1PACKEN_V(x) ((x) << FW_IQ_CMD_FL1PACKEN_S)#define FW_IQ_CMD_FL1PACKEN_F FW_IQ_CMD_FL1PACKEN_V(1 U)#define FW_IQ_CMD_FL1CONGEN_S 0 #define FW_IQ_CMD_FL1CONGEN_V(x) ((x) << FW_IQ_CMD_FL1CONGEN_S)#define FW_IQ_CMD_FL1CONGEN_F FW_IQ_CMD_FL1CONGEN_V(1 U)#define FW_IQ_CMD_FL1DCAEN_S 15 #define FW_IQ_CMD_FL1DCAEN_V(x) ((x) << FW_IQ_CMD_FL1DCAEN_S)#define FW_IQ_CMD_FL1DCACPU_S 10 #define FW_IQ_CMD_FL1DCACPU_V(x) ((x) << FW_IQ_CMD_FL1DCACPU_S)#define FW_IQ_CMD_FL1FBMIN_S 7 #define FW_IQ_CMD_FL1FBMIN_V(x) ((x) << FW_IQ_CMD_FL1FBMIN_S)#define FW_IQ_CMD_FL1FBMAX_S 4 #define FW_IQ_CMD_FL1FBMAX_V(x) ((x) << FW_IQ_CMD_FL1FBMAX_S)#define FW_IQ_CMD_FL1CIDXFTHRESHO_S 3 #define FW_IQ_CMD_FL1CIDXFTHRESHO_V(x) ((x) << FW_IQ_CMD_FL1CIDXFTHRESHO_S)#define FW_IQ_CMD_FL1CIDXFTHRESHO_F FW_IQ_CMD_FL1CIDXFTHRESHO_V(1 U)#define FW_IQ_CMD_FL1CIDXFTHRESH_S 0 #define FW_IQ_CMD_FL1CIDXFTHRESH_V(x) ((x) << FW_IQ_CMD_FL1CIDXFTHRESH_S)struct fw_eq_eth_cmd {#define FW_EQ_ETH_CMD_PFN_S 8 #define FW_EQ_ETH_CMD_PFN_V(x) ((x) << FW_EQ_ETH_CMD_PFN_S)#define FW_EQ_ETH_CMD_VFN_S 0 #define FW_EQ_ETH_CMD_VFN_V(x) ((x) << FW_EQ_ETH_CMD_VFN_S)#define FW_EQ_ETH_CMD_ALLOC_S 31 #define FW_EQ_ETH_CMD_ALLOC_V(x) ((x) << FW_EQ_ETH_CMD_ALLOC_S)#define FW_EQ_ETH_CMD_ALLOC_F FW_EQ_ETH_CMD_ALLOC_V(1 U)#define FW_EQ_ETH_CMD_FREE_S 30 #define FW_EQ_ETH_CMD_FREE_V(x) ((x) << FW_EQ_ETH_CMD_FREE_S)#define FW_EQ_ETH_CMD_FREE_F FW_EQ_ETH_CMD_FREE_V(1 U)#define FW_EQ_ETH_CMD_MODIFY_S 29 #define FW_EQ_ETH_CMD_MODIFY_V(x) ((x) << FW_EQ_ETH_CMD_MODIFY_S)#define FW_EQ_ETH_CMD_MODIFY_F FW_EQ_ETH_CMD_MODIFY_V(1 U)#define FW_EQ_ETH_CMD_EQSTART_S 28 #define FW_EQ_ETH_CMD_EQSTART_V(x) ((x) << FW_EQ_ETH_CMD_EQSTART_S)#define FW_EQ_ETH_CMD_EQSTART_F FW_EQ_ETH_CMD_EQSTART_V(1 U)#define FW_EQ_ETH_CMD_EQSTOP_S 27 #define FW_EQ_ETH_CMD_EQSTOP_V(x) ((x) << FW_EQ_ETH_CMD_EQSTOP_S)#define FW_EQ_ETH_CMD_EQSTOP_F FW_EQ_ETH_CMD_EQSTOP_V(1 U)#define FW_EQ_ETH_CMD_EQID_S 0 #define FW_EQ_ETH_CMD_EQID_M 0 xfffff#define FW_EQ_ETH_CMD_EQID_V(x) ((x) << FW_EQ_ETH_CMD_EQID_S)#define FW_EQ_ETH_CMD_EQID_G(x) \#define FW_EQ_ETH_CMD_PHYSEQID_S 0 #define FW_EQ_ETH_CMD_PHYSEQID_M 0 xfffff#define FW_EQ_ETH_CMD_PHYSEQID_V(x) ((x) << FW_EQ_ETH_CMD_PHYSEQID_S)#define FW_EQ_ETH_CMD_PHYSEQID_G(x) \#define FW_EQ_ETH_CMD_FETCHSZM_S 26 #define FW_EQ_ETH_CMD_FETCHSZM_V(x) ((x) << FW_EQ_ETH_CMD_FETCHSZM_S)#define FW_EQ_ETH_CMD_FETCHSZM_F FW_EQ_ETH_CMD_FETCHSZM_V(1 U)#define FW_EQ_ETH_CMD_STATUSPGNS_S 25 #define FW_EQ_ETH_CMD_STATUSPGNS_V(x) ((x) << FW_EQ_ETH_CMD_STATUSPGNS_S)#define FW_EQ_ETH_CMD_STATUSPGRO_S 24 #define FW_EQ_ETH_CMD_STATUSPGRO_V(x) ((x) << FW_EQ_ETH_CMD_STATUSPGRO_S)#define FW_EQ_ETH_CMD_FETCHNS_S 23 #define FW_EQ_ETH_CMD_FETCHNS_V(x) ((x) << FW_EQ_ETH_CMD_FETCHNS_S)#define FW_EQ_ETH_CMD_FETCHRO_S 22 #define FW_EQ_ETH_CMD_FETCHRO_V(x) ((x) << FW_EQ_ETH_CMD_FETCHRO_S)#define FW_EQ_ETH_CMD_FETCHRO_F FW_EQ_ETH_CMD_FETCHRO_V(1 U)#define FW_EQ_ETH_CMD_HOSTFCMODE_S 20 #define FW_EQ_ETH_CMD_HOSTFCMODE_V(x) ((x) << FW_EQ_ETH_CMD_HOSTFCMODE_S)#define FW_EQ_ETH_CMD_CPRIO_S 19 #define FW_EQ_ETH_CMD_CPRIO_V(x) ((x) << FW_EQ_ETH_CMD_CPRIO_S)#define FW_EQ_ETH_CMD_ONCHIP_S 18 #define FW_EQ_ETH_CMD_ONCHIP_V(x) ((x) << FW_EQ_ETH_CMD_ONCHIP_S)#define FW_EQ_ETH_CMD_PCIECHN_S 16 #define FW_EQ_ETH_CMD_PCIECHN_V(x) ((x) << FW_EQ_ETH_CMD_PCIECHN_S)#define FW_EQ_ETH_CMD_IQID_S 0 #define FW_EQ_ETH_CMD_IQID_V(x) ((x) << FW_EQ_ETH_CMD_IQID_S)#define FW_EQ_ETH_CMD_DCAEN_S 31 #define FW_EQ_ETH_CMD_DCAEN_V(x) ((x) << FW_EQ_ETH_CMD_DCAEN_S)#define FW_EQ_ETH_CMD_DCACPU_S 26 #define FW_EQ_ETH_CMD_DCACPU_V(x) ((x) << FW_EQ_ETH_CMD_DCACPU_S)#define FW_EQ_ETH_CMD_FBMIN_S 23 #define FW_EQ_ETH_CMD_FBMIN_V(x) ((x) << FW_EQ_ETH_CMD_FBMIN_S)#define FW_EQ_ETH_CMD_FBMAX_S 20 #define FW_EQ_ETH_CMD_FBMAX_V(x) ((x) << FW_EQ_ETH_CMD_FBMAX_S)#define FW_EQ_ETH_CMD_CIDXFTHRESHO_S 19 #define FW_EQ_ETH_CMD_CIDXFTHRESHO_V(x) ((x) << FW_EQ_ETH_CMD_CIDXFTHRESHO_S)#define FW_EQ_ETH_CMD_CIDXFTHRESH_S 16 #define FW_EQ_ETH_CMD_CIDXFTHRESH_V(x) ((x) << FW_EQ_ETH_CMD_CIDXFTHRESH_S)#define FW_EQ_ETH_CMD_EQSIZE_S 0 #define FW_EQ_ETH_CMD_EQSIZE_V(x) ((x) << FW_EQ_ETH_CMD_EQSIZE_S)#define FW_EQ_ETH_CMD_AUTOEQUIQE_S 31 #define FW_EQ_ETH_CMD_AUTOEQUIQE_V(x) ((x) << FW_EQ_ETH_CMD_AUTOEQUIQE_S)#define FW_EQ_ETH_CMD_AUTOEQUIQE_F FW_EQ_ETH_CMD_AUTOEQUIQE_V(1 U)#define FW_EQ_ETH_CMD_AUTOEQUEQE_S 30 #define FW_EQ_ETH_CMD_AUTOEQUEQE_V(x) ((x) << FW_EQ_ETH_CMD_AUTOEQUEQE_S)#define FW_EQ_ETH_CMD_AUTOEQUEQE_F FW_EQ_ETH_CMD_AUTOEQUEQE_V(1 U)#define FW_EQ_ETH_CMD_VIID_S 16 #define FW_EQ_ETH_CMD_VIID_V(x) ((x) << FW_EQ_ETH_CMD_VIID_S)#define FW_EQ_ETH_CMD_TIMEREN_S 3 #define FW_EQ_ETH_CMD_TIMEREN_M 0 x1#define FW_EQ_ETH_CMD_TIMEREN_V(x) ((x) << FW_EQ_ETH_CMD_TIMEREN_S)#define FW_EQ_ETH_CMD_TIMEREN_G(x) \#define FW_EQ_ETH_CMD_TIMEREN_F FW_EQ_ETH_CMD_TIMEREN_V(1 U)#define FW_EQ_ETH_CMD_TIMERIX_S 0 #define FW_EQ_ETH_CMD_TIMERIX_M 0 x7#define FW_EQ_ETH_CMD_TIMERIX_V(x) ((x) << FW_EQ_ETH_CMD_TIMERIX_S)#define FW_EQ_ETH_CMD_TIMERIX_G(x) \struct fw_eq_ctrl_cmd {#define FW_EQ_CTRL_CMD_PFN_S 8 #define FW_EQ_CTRL_CMD_PFN_V(x) ((x) << FW_EQ_CTRL_CMD_PFN_S)#define FW_EQ_CTRL_CMD_VFN_S 0 #define FW_EQ_CTRL_CMD_VFN_V(x) ((x) << FW_EQ_CTRL_CMD_VFN_S)#define FW_EQ_CTRL_CMD_ALLOC_S 31 #define FW_EQ_CTRL_CMD_ALLOC_V(x) ((x) << FW_EQ_CTRL_CMD_ALLOC_S)#define FW_EQ_CTRL_CMD_ALLOC_F FW_EQ_CTRL_CMD_ALLOC_V(1 U)#define FW_EQ_CTRL_CMD_FREE_S 30 #define FW_EQ_CTRL_CMD_FREE_V(x) ((x) << FW_EQ_CTRL_CMD_FREE_S)#define FW_EQ_CTRL_CMD_FREE_F FW_EQ_CTRL_CMD_FREE_V(1 U)#define FW_EQ_CTRL_CMD_MODIFY_S 29 #define FW_EQ_CTRL_CMD_MODIFY_V(x) ((x) << FW_EQ_CTRL_CMD_MODIFY_S)#define FW_EQ_CTRL_CMD_MODIFY_F FW_EQ_CTRL_CMD_MODIFY_V(1 U)#define FW_EQ_CTRL_CMD_EQSTART_S 28 #define FW_EQ_CTRL_CMD_EQSTART_V(x) ((x) << FW_EQ_CTRL_CMD_EQSTART_S)#define FW_EQ_CTRL_CMD_EQSTART_F FW_EQ_CTRL_CMD_EQSTART_V(1 U)#define FW_EQ_CTRL_CMD_EQSTOP_S 27 #define FW_EQ_CTRL_CMD_EQSTOP_V(x) ((x) << FW_EQ_CTRL_CMD_EQSTOP_S)#define FW_EQ_CTRL_CMD_EQSTOP_F FW_EQ_CTRL_CMD_EQSTOP_V(1 U)#define FW_EQ_CTRL_CMD_CMPLIQID_S 20 #define FW_EQ_CTRL_CMD_CMPLIQID_V(x) ((x) << FW_EQ_CTRL_CMD_CMPLIQID_S)#define FW_EQ_CTRL_CMD_EQID_S 0 #define FW_EQ_CTRL_CMD_EQID_M 0 xfffff#define FW_EQ_CTRL_CMD_EQID_V(x) ((x) << FW_EQ_CTRL_CMD_EQID_S)#define FW_EQ_CTRL_CMD_EQID_G(x) \#define FW_EQ_CTRL_CMD_PHYSEQID_S 0 #define FW_EQ_CTRL_CMD_PHYSEQID_M 0 xfffff#define FW_EQ_CTRL_CMD_PHYSEQID_G(x) \#define FW_EQ_CTRL_CMD_FETCHSZM_S 26 #define FW_EQ_CTRL_CMD_FETCHSZM_V(x) ((x) << FW_EQ_CTRL_CMD_FETCHSZM_S)#define FW_EQ_CTRL_CMD_FETCHSZM_F FW_EQ_CTRL_CMD_FETCHSZM_V(1 U)#define FW_EQ_CTRL_CMD_STATUSPGNS_S 25 #define FW_EQ_CTRL_CMD_STATUSPGNS_V(x) ((x) << FW_EQ_CTRL_CMD_STATUSPGNS_S)#define FW_EQ_CTRL_CMD_STATUSPGNS_F FW_EQ_CTRL_CMD_STATUSPGNS_V(1 U)#define FW_EQ_CTRL_CMD_STATUSPGRO_S 24 #define FW_EQ_CTRL_CMD_STATUSPGRO_V(x) ((x) << FW_EQ_CTRL_CMD_STATUSPGRO_S)#define FW_EQ_CTRL_CMD_STATUSPGRO_F FW_EQ_CTRL_CMD_STATUSPGRO_V(1 U)#define FW_EQ_CTRL_CMD_FETCHNS_S 23 #define FW_EQ_CTRL_CMD_FETCHNS_V(x) ((x) << FW_EQ_CTRL_CMD_FETCHNS_S)#define FW_EQ_CTRL_CMD_FETCHNS_F FW_EQ_CTRL_CMD_FETCHNS_V(1 U)#define FW_EQ_CTRL_CMD_FETCHRO_S 22 #define FW_EQ_CTRL_CMD_FETCHRO_V(x) ((x) << FW_EQ_CTRL_CMD_FETCHRO_S)#define FW_EQ_CTRL_CMD_FETCHRO_F FW_EQ_CTRL_CMD_FETCHRO_V(1 U)#define FW_EQ_CTRL_CMD_HOSTFCMODE_S 20 #define FW_EQ_CTRL_CMD_HOSTFCMODE_V(x) ((x) << FW_EQ_CTRL_CMD_HOSTFCMODE_S)#define FW_EQ_CTRL_CMD_CPRIO_S 19 #define FW_EQ_CTRL_CMD_CPRIO_V(x) ((x) << FW_EQ_CTRL_CMD_CPRIO_S)#define FW_EQ_CTRL_CMD_ONCHIP_S 18 #define FW_EQ_CTRL_CMD_ONCHIP_V(x) ((x) << FW_EQ_CTRL_CMD_ONCHIP_S)#define FW_EQ_CTRL_CMD_PCIECHN_S 16 #define FW_EQ_CTRL_CMD_PCIECHN_V(x) ((x) << FW_EQ_CTRL_CMD_PCIECHN_S)#define FW_EQ_CTRL_CMD_IQID_S 0 #define FW_EQ_CTRL_CMD_IQID_V(x) ((x) << FW_EQ_CTRL_CMD_IQID_S)#define FW_EQ_CTRL_CMD_DCAEN_S 31 #define FW_EQ_CTRL_CMD_DCAEN_V(x) ((x) << FW_EQ_CTRL_CMD_DCAEN_S)#define FW_EQ_CTRL_CMD_DCACPU_S 26 #define FW_EQ_CTRL_CMD_DCACPU_V(x) ((x) << FW_EQ_CTRL_CMD_DCACPU_S)#define FW_EQ_CTRL_CMD_FBMIN_S 23 #define FW_EQ_CTRL_CMD_FBMIN_V(x) ((x) << FW_EQ_CTRL_CMD_FBMIN_S)#define FW_EQ_CTRL_CMD_FBMAX_S 20 #define FW_EQ_CTRL_CMD_FBMAX_V(x) ((x) << FW_EQ_CTRL_CMD_FBMAX_S)#define FW_EQ_CTRL_CMD_CIDXFTHRESHO_S 19 #define FW_EQ_CTRL_CMD_CIDXFTHRESHO_V(x) \#define FW_EQ_CTRL_CMD_CIDXFTHRESH_S 16 #define FW_EQ_CTRL_CMD_CIDXFTHRESH_V(x) ((x) << FW_EQ_CTRL_CMD_CIDXFTHRESH_S)#define FW_EQ_CTRL_CMD_EQSIZE_S 0 #define FW_EQ_CTRL_CMD_EQSIZE_V(x) ((x) << FW_EQ_CTRL_CMD_EQSIZE_S)struct fw_eq_ofld_cmd {#define FW_EQ_OFLD_CMD_PFN_S 8 #define FW_EQ_OFLD_CMD_PFN_V(x) ((x) << FW_EQ_OFLD_CMD_PFN_S)#define FW_EQ_OFLD_CMD_VFN_S 0 #define FW_EQ_OFLD_CMD_VFN_V(x) ((x) << FW_EQ_OFLD_CMD_VFN_S)#define FW_EQ_OFLD_CMD_ALLOC_S 31 #define FW_EQ_OFLD_CMD_ALLOC_V(x) ((x) << FW_EQ_OFLD_CMD_ALLOC_S)#define FW_EQ_OFLD_CMD_ALLOC_F FW_EQ_OFLD_CMD_ALLOC_V(1 U)#define FW_EQ_OFLD_CMD_FREE_S 30 #define FW_EQ_OFLD_CMD_FREE_V(x) ((x) << FW_EQ_OFLD_CMD_FREE_S)#define FW_EQ_OFLD_CMD_FREE_F FW_EQ_OFLD_CMD_FREE_V(1 U)#define FW_EQ_OFLD_CMD_MODIFY_S 29 #define FW_EQ_OFLD_CMD_MODIFY_V(x) ((x) << FW_EQ_OFLD_CMD_MODIFY_S)#define FW_EQ_OFLD_CMD_MODIFY_F FW_EQ_OFLD_CMD_MODIFY_V(1 U)#define FW_EQ_OFLD_CMD_EQSTART_S 28 #define FW_EQ_OFLD_CMD_EQSTART_V(x) ((x) << FW_EQ_OFLD_CMD_EQSTART_S)#define FW_EQ_OFLD_CMD_EQSTART_F FW_EQ_OFLD_CMD_EQSTART_V(1 U)#define FW_EQ_OFLD_CMD_EQSTOP_S 27 #define FW_EQ_OFLD_CMD_EQSTOP_V(x) ((x) << FW_EQ_OFLD_CMD_EQSTOP_S)#define FW_EQ_OFLD_CMD_EQSTOP_F FW_EQ_OFLD_CMD_EQSTOP_V(1 U)#define FW_EQ_OFLD_CMD_EQID_S 0 #define FW_EQ_OFLD_CMD_EQID_M 0 xfffff#define FW_EQ_OFLD_CMD_EQID_V(x) ((x) << FW_EQ_OFLD_CMD_EQID_S)#define FW_EQ_OFLD_CMD_EQID_G(x) \#define FW_EQ_OFLD_CMD_PHYSEQID_S 0 #define FW_EQ_OFLD_CMD_PHYSEQID_M 0 xfffff#define FW_EQ_OFLD_CMD_PHYSEQID_G(x) \#define FW_EQ_OFLD_CMD_FETCHSZM_S 26 #define FW_EQ_OFLD_CMD_FETCHSZM_V(x) ((x) << FW_EQ_OFLD_CMD_FETCHSZM_S)#define FW_EQ_OFLD_CMD_STATUSPGNS_S 25 #define FW_EQ_OFLD_CMD_STATUSPGNS_V(x) ((x) << FW_EQ_OFLD_CMD_STATUSPGNS_S)#define FW_EQ_OFLD_CMD_STATUSPGRO_S 24 #define FW_EQ_OFLD_CMD_STATUSPGRO_V(x) ((x) << FW_EQ_OFLD_CMD_STATUSPGRO_S)#define FW_EQ_OFLD_CMD_FETCHNS_S 23 #define FW_EQ_OFLD_CMD_FETCHNS_V(x) ((x) << FW_EQ_OFLD_CMD_FETCHNS_S)#define FW_EQ_OFLD_CMD_FETCHRO_S 22 #define FW_EQ_OFLD_CMD_FETCHRO_V(x) ((x) << FW_EQ_OFLD_CMD_FETCHRO_S)#define FW_EQ_OFLD_CMD_FETCHRO_F FW_EQ_OFLD_CMD_FETCHRO_V(1 U)#define FW_EQ_OFLD_CMD_HOSTFCMODE_S 20 #define FW_EQ_OFLD_CMD_HOSTFCMODE_V(x) ((x) << FW_EQ_OFLD_CMD_HOSTFCMODE_S)#define FW_EQ_OFLD_CMD_CPRIO_S 19 #define FW_EQ_OFLD_CMD_CPRIO_V(x) ((x) << FW_EQ_OFLD_CMD_CPRIO_S)#define FW_EQ_OFLD_CMD_ONCHIP_S 18 #define FW_EQ_OFLD_CMD_ONCHIP_V(x) ((x) << FW_EQ_OFLD_CMD_ONCHIP_S)#define FW_EQ_OFLD_CMD_PCIECHN_S 16 #define FW_EQ_OFLD_CMD_PCIECHN_V(x) ((x) << FW_EQ_OFLD_CMD_PCIECHN_S)#define FW_EQ_OFLD_CMD_IQID_S 0 #define FW_EQ_OFLD_CMD_IQID_V(x) ((x) << FW_EQ_OFLD_CMD_IQID_S)#define FW_EQ_OFLD_CMD_DCAEN_S 31 #define FW_EQ_OFLD_CMD_DCAEN_V(x) ((x) << FW_EQ_OFLD_CMD_DCAEN_S)#define FW_EQ_OFLD_CMD_DCACPU_S 26 #define FW_EQ_OFLD_CMD_DCACPU_V(x) ((x) << FW_EQ_OFLD_CMD_DCACPU_S)#define FW_EQ_OFLD_CMD_FBMIN_S 23 #define FW_EQ_OFLD_CMD_FBMIN_V(x) ((x) << FW_EQ_OFLD_CMD_FBMIN_S)#define FW_EQ_OFLD_CMD_FBMAX_S 20 #define FW_EQ_OFLD_CMD_FBMAX_V(x) ((x) << FW_EQ_OFLD_CMD_FBMAX_S)#define FW_EQ_OFLD_CMD_CIDXFTHRESHO_S 19 #define FW_EQ_OFLD_CMD_CIDXFTHRESHO_V(x) \#define FW_EQ_OFLD_CMD_CIDXFTHRESH_S 16 #define FW_EQ_OFLD_CMD_CIDXFTHRESH_V(x) ((x) << FW_EQ_OFLD_CMD_CIDXFTHRESH_S)#define FW_EQ_OFLD_CMD_EQSIZE_S 0 #define FW_EQ_OFLD_CMD_EQSIZE_V(x) ((x) << FW_EQ_OFLD_CMD_EQSIZE_S)/* * Macros for VIID parsing: * VIID - [10:8] PFN, [7] VI Valid, [6:0] VI number #define FW_VIID_PFN_S 8 #define FW_VIID_PFN_M 0 x7#define FW_VIID_PFN_G(x) (((x) >> FW_VIID_PFN_S) & FW_VIID_PFN_M)#define FW_VIID_VIVLD_S 7 #define FW_VIID_VIVLD_M 0 x1#define FW_VIID_VIVLD_G(x) (((x) >> FW_VIID_VIVLD_S) & FW_VIID_VIVLD_M)#define FW_VIID_VIN_S 0 #define FW_VIID_VIN_M 0 x7F#define FW_VIID_VIN_G(x) (((x) >> FW_VIID_VIN_S) & FW_VIID_VIN_M)struct fw_vi_cmd {6 ];6 ];6 ];6 ];6 ];#define FW_VI_CMD_PFN_S 8 #define FW_VI_CMD_PFN_V(x) ((x) << FW_VI_CMD_PFN_S)#define FW_VI_CMD_VFN_S 0 #define FW_VI_CMD_VFN_V(x) ((x) << FW_VI_CMD_VFN_S)#define FW_VI_CMD_ALLOC_S 31 #define FW_VI_CMD_ALLOC_V(x) ((x) << FW_VI_CMD_ALLOC_S)#define FW_VI_CMD_ALLOC_F FW_VI_CMD_ALLOC_V(1 U)#define FW_VI_CMD_FREE_S 30 #define FW_VI_CMD_FREE_V(x) ((x) << FW_VI_CMD_FREE_S)#define FW_VI_CMD_FREE_F FW_VI_CMD_FREE_V(1 U)#define FW_VI_CMD_VFVLD_S 24 #define FW_VI_CMD_VFVLD_M 0 x1#define FW_VI_CMD_VFVLD_V(x) ((x) << FW_VI_CMD_VFVLD_S)#define FW_VI_CMD_VFVLD_G(x) \#define FW_VI_CMD_VFVLD_F FW_VI_CMD_VFVLD_V(1 U)#define FW_VI_CMD_VIN_S 16 #define FW_VI_CMD_VIN_M 0 xff#define FW_VI_CMD_VIN_V(x) ((x) << FW_VI_CMD_VIN_S)#define FW_VI_CMD_VIN_G(x) \#define FW_VI_CMD_VIID_S 0 #define FW_VI_CMD_VIID_M 0 xfff#define FW_VI_CMD_VIID_V(x) ((x) << FW_VI_CMD_VIID_S)#define FW_VI_CMD_VIID_G(x) (((x) >> FW_VI_CMD_VIID_S) & FW_VI_CMD_VIID_M)#define FW_VI_CMD_PORTID_S 4 #define FW_VI_CMD_PORTID_M 0 xf#define FW_VI_CMD_PORTID_V(x) ((x) << FW_VI_CMD_PORTID_S)#define FW_VI_CMD_PORTID_G(x) \#define FW_VI_CMD_RSSSIZE_S 0 #define FW_VI_CMD_RSSSIZE_M 0 x7ff#define FW_VI_CMD_RSSSIZE_G(x) \/* Special VI_MAC command index ids */ #define FW_VI_MAC_ADD_MAC 0 x3FF#define FW_VI_MAC_ADD_PERSIST_MAC 0 x3FE#define FW_VI_MAC_MAC_BASED_FREE 0 x3FD#define FW_VI_MAC_ID_BASED_FREE 0 x3FC#define FW_CLS_TCAM_NUM_ENTRIES 336 enum fw_vi_mac_smac {enum fw_vi_mac_result {enum fw_vi_mac_entry_types {struct fw_vi_mac_cmd {union fw_vi_mac {struct fw_vi_mac_exact {6 ];7 ];struct fw_vi_mac_hash {struct fw_vi_mac_raw {2 ];2 ];struct fw_vi_mac_vni {6 ];6 ];2 ];#define FW_VI_MAC_CMD_SMTID_S 12 #define FW_VI_MAC_CMD_SMTID_M 0 xff#define FW_VI_MAC_CMD_SMTID_V(x) ((x) << FW_VI_MAC_CMD_SMTID_S)#define FW_VI_MAC_CMD_SMTID_G(x) \#define FW_VI_MAC_CMD_VIID_S 0 #define FW_VI_MAC_CMD_VIID_V(x) ((x) << FW_VI_MAC_CMD_VIID_S)#define FW_VI_MAC_CMD_FREEMACS_S 31 #define FW_VI_MAC_CMD_FREEMACS_V(x) ((x) << FW_VI_MAC_CMD_FREEMACS_S)#define FW_VI_MAC_CMD_ENTRY_TYPE_S 23 #define FW_VI_MAC_CMD_ENTRY_TYPE_M 0 x7#define FW_VI_MAC_CMD_ENTRY_TYPE_V(x) ((x) << FW_VI_MAC_CMD_ENTRY_TYPE_S)#define FW_VI_MAC_CMD_ENTRY_TYPE_G(x) \#define FW_VI_MAC_CMD_HASHVECEN_S 23 #define FW_VI_MAC_CMD_HASHVECEN_V(x) ((x) << FW_VI_MAC_CMD_HASHVECEN_S)#define FW_VI_MAC_CMD_HASHVECEN_F FW_VI_MAC_CMD_HASHVECEN_V(1 U)#define FW_VI_MAC_CMD_HASHUNIEN_S 22 #define FW_VI_MAC_CMD_HASHUNIEN_V(x) ((x) << FW_VI_MAC_CMD_HASHUNIEN_S)#define FW_VI_MAC_CMD_VALID_S 15 #define FW_VI_MAC_CMD_VALID_V(x) ((x) << FW_VI_MAC_CMD_VALID_S)#define FW_VI_MAC_CMD_VALID_F FW_VI_MAC_CMD_VALID_V(1 U)#define FW_VI_MAC_CMD_PRIO_S 12 #define FW_VI_MAC_CMD_PRIO_V(x) ((x) << FW_VI_MAC_CMD_PRIO_S)#define FW_VI_MAC_CMD_SMAC_RESULT_S 10 #define FW_VI_MAC_CMD_SMAC_RESULT_M 0 x3#define FW_VI_MAC_CMD_SMAC_RESULT_V(x) ((x) << FW_VI_MAC_CMD_SMAC_RESULT_S)#define FW_VI_MAC_CMD_SMAC_RESULT_G(x) \#define FW_VI_MAC_CMD_IDX_S 0 #define FW_VI_MAC_CMD_IDX_M 0 x3ff#define FW_VI_MAC_CMD_IDX_V(x) ((x) << FW_VI_MAC_CMD_IDX_S)#define FW_VI_MAC_CMD_IDX_G(x) \#define FW_VI_MAC_CMD_RAW_IDX_S 16 #define FW_VI_MAC_CMD_RAW_IDX_M 0 xffff#define FW_VI_MAC_CMD_RAW_IDX_V(x) ((x) << FW_VI_MAC_CMD_RAW_IDX_S)#define FW_VI_MAC_CMD_RAW_IDX_G(x) \#define FW_VI_MAC_CMD_LOOKUP_TYPE_S 31 #define FW_VI_MAC_CMD_LOOKUP_TYPE_M 0 x1#define FW_VI_MAC_CMD_LOOKUP_TYPE_V(x) ((x) << FW_VI_MAC_CMD_LOOKUP_TYPE_S)#define FW_VI_MAC_CMD_LOOKUP_TYPE_G(x) \#define FW_VI_MAC_CMD_LOOKUP_TYPE_F FW_VI_MAC_CMD_LOOKUP_TYPE_V(1 U)#define FW_VI_MAC_CMD_DIP_HIT_S 30 #define FW_VI_MAC_CMD_DIP_HIT_M 0 x1#define FW_VI_MAC_CMD_DIP_HIT_V(x) ((x) << FW_VI_MAC_CMD_DIP_HIT_S)#define FW_VI_MAC_CMD_DIP_HIT_G(x) \#define FW_VI_MAC_CMD_DIP_HIT_F FW_VI_MAC_CMD_DIP_HIT_V(1 U)#define FW_VI_MAC_CMD_VNI_S 0 #define FW_VI_MAC_CMD_VNI_M 0 xffffff#define FW_VI_MAC_CMD_VNI_V(x) ((x) << FW_VI_MAC_CMD_VNI_S)#define FW_VI_MAC_CMD_VNI_G(x) \#define FW_VI_MAC_CMD_VNI_MASK_S 0 #define FW_VI_MAC_CMD_VNI_MASK_M 0 xffffff#define FW_VI_MAC_CMD_VNI_MASK_V(x) ((x) << FW_VI_MAC_CMD_VNI_MASK_S)#define FW_VI_MAC_CMD_VNI_MASK_G(x) \#define FW_RXMODE_MTU_NO_CHG 65535 struct fw_vi_rxmode_cmd {#define FW_VI_RXMODE_CMD_VIID_S 0 #define FW_VI_RXMODE_CMD_VIID_V(x) ((x) << FW_VI_RXMODE_CMD_VIID_S)#define FW_VI_RXMODE_CMD_MTU_S 16 #define FW_VI_RXMODE_CMD_MTU_M 0 xffff#define FW_VI_RXMODE_CMD_MTU_V(x) ((x) << FW_VI_RXMODE_CMD_MTU_S)#define FW_VI_RXMODE_CMD_PROMISCEN_S 14 #define FW_VI_RXMODE_CMD_PROMISCEN_M 0 x3#define FW_VI_RXMODE_CMD_PROMISCEN_V(x) ((x) << FW_VI_RXMODE_CMD_PROMISCEN_S)#define FW_VI_RXMODE_CMD_ALLMULTIEN_S 12 #define FW_VI_RXMODE_CMD_ALLMULTIEN_M 0 x3#define FW_VI_RXMODE_CMD_ALLMULTIEN_V(x) \#define FW_VI_RXMODE_CMD_BROADCASTEN_S 10 #define FW_VI_RXMODE_CMD_BROADCASTEN_M 0 x3#define FW_VI_RXMODE_CMD_BROADCASTEN_V(x) \#define FW_VI_RXMODE_CMD_VLANEXEN_S 8 #define FW_VI_RXMODE_CMD_VLANEXEN_M 0 x3#define FW_VI_RXMODE_CMD_VLANEXEN_V(x) ((x) << FW_VI_RXMODE_CMD_VLANEXEN_S)struct fw_vi_enable_cmd {#define FW_VI_ENABLE_CMD_VIID_S 0 #define FW_VI_ENABLE_CMD_VIID_V(x) ((x) << FW_VI_ENABLE_CMD_VIID_S)#define FW_VI_ENABLE_CMD_IEN_S 31 #define FW_VI_ENABLE_CMD_IEN_V(x) ((x) << FW_VI_ENABLE_CMD_IEN_S)#define FW_VI_ENABLE_CMD_EEN_S 30 #define FW_VI_ENABLE_CMD_EEN_V(x) ((x) << FW_VI_ENABLE_CMD_EEN_S)#define FW_VI_ENABLE_CMD_LED_S 29 #define FW_VI_ENABLE_CMD_LED_V(x) ((x) << FW_VI_ENABLE_CMD_LED_S)#define FW_VI_ENABLE_CMD_LED_F FW_VI_ENABLE_CMD_LED_V(1 U)#define FW_VI_ENABLE_CMD_DCB_INFO_S 28 #define FW_VI_ENABLE_CMD_DCB_INFO_V(x) ((x) << FW_VI_ENABLE_CMD_DCB_INFO_S)/* VI VF stats offset definitions */ #define VI_VF_NUM_STATS 16 enum fw_vi_stats_vf_index {/* VI PF stats offset definitions */ #define VI_PF_NUM_STATS 17 enum fw_vi_stats_pf_index {struct fw_vi_stats_cmd {union fw_vi_stats {struct fw_vi_stats_ctl {struct fw_vi_stats_pf {struct fw_vi_stats_vf {#define FW_VI_STATS_CMD_VIID_S 0 #define FW_VI_STATS_CMD_VIID_V(x) ((x) << FW_VI_STATS_CMD_VIID_S)#define FW_VI_STATS_CMD_NSTATS_S 12 #define FW_VI_STATS_CMD_NSTATS_V(x) ((x) << FW_VI_STATS_CMD_NSTATS_S)#define FW_VI_STATS_CMD_IX_S 0 #define FW_VI_STATS_CMD_IX_V(x) ((x) << FW_VI_STATS_CMD_IX_S)struct fw_acl_mac_cmd {7 ];6 ];6 ];6 ];6 ];#define FW_ACL_MAC_CMD_PFN_S 8 #define FW_ACL_MAC_CMD_PFN_V(x) ((x) << FW_ACL_MAC_CMD_PFN_S)#define FW_ACL_MAC_CMD_VFN_S 0 #define FW_ACL_MAC_CMD_VFN_V(x) ((x) << FW_ACL_MAC_CMD_VFN_S)#define FW_ACL_MAC_CMD_EN_S 31 #define FW_ACL_MAC_CMD_EN_V(x) ((x) << FW_ACL_MAC_CMD_EN_S)struct fw_acl_vlan_cmd {6 ];16 ];#define FW_ACL_VLAN_CMD_PFN_S 8 #define FW_ACL_VLAN_CMD_PFN_V(x) ((x) << FW_ACL_VLAN_CMD_PFN_S)#define FW_ACL_VLAN_CMD_VFN_S 0 #define FW_ACL_VLAN_CMD_VFN_V(x) ((x) << FW_ACL_VLAN_CMD_VFN_S)#define FW_ACL_VLAN_CMD_EN_S 31 #define FW_ACL_VLAN_CMD_EN_M 0 x1#define FW_ACL_VLAN_CMD_EN_V(x) ((x) << FW_ACL_VLAN_CMD_EN_S)#define FW_ACL_VLAN_CMD_EN_G(x) \#define FW_ACL_VLAN_CMD_EN_F FW_ACL_VLAN_CMD_EN_V(1 U)#define FW_ACL_VLAN_CMD_DROPNOVLAN_S 7 #define FW_ACL_VLAN_CMD_DROPNOVLAN_V(x) ((x) << FW_ACL_VLAN_CMD_DROPNOVLAN_S)#define FW_ACL_VLAN_CMD_DROPNOVLAN_F FW_ACL_VLAN_CMD_DROPNOVLAN_V(1 U)#define FW_ACL_VLAN_CMD_FM_S 6 #define FW_ACL_VLAN_CMD_FM_M 0 x1#define FW_ACL_VLAN_CMD_FM_V(x) ((x) << FW_ACL_VLAN_CMD_FM_S)#define FW_ACL_VLAN_CMD_FM_G(x) \#define FW_ACL_VLAN_CMD_FM_F FW_ACL_VLAN_CMD_FM_V(1 U)/* old 16-bit port capabilities bitmap (fw_port_cap16_t) */ enum fw_port_cap {0 x0001,0 x0002,0 x0004,0 x0008,0 x0010,0 x0020,0 x0040,0 x0080,0 x0100,0 x0200,0 x0400,0 x0800,0 x1000,0 x2000,0 x4000,0 x8000,#define FW_PORT_CAP_SPEED_S 0 #define FW_PORT_CAP_SPEED_M 0 x3f#define FW_PORT_CAP_SPEED_V(x) ((x) << FW_PORT_CAP_SPEED_S)#define FW_PORT_CAP_SPEED_G(x) \enum fw_port_mdi {#define FW_PORT_CAP_MDI_S 9 #define FW_PORT_CAP_MDI_V(x) ((x) << FW_PORT_CAP_MDI_S)/* new 32-bit port capabilities bitmap (fw_port_cap32_t) */ #define FW_PORT_CAP32_SPEED_100M 0 x00000001UL#define FW_PORT_CAP32_SPEED_1G 0 x00000002UL#define FW_PORT_CAP32_SPEED_10G 0 x00000004UL#define FW_PORT_CAP32_SPEED_25G 0 x00000008UL#define FW_PORT_CAP32_SPEED_40G 0 x00000010UL#define FW_PORT_CAP32_SPEED_50G 0 x00000020UL#define FW_PORT_CAP32_SPEED_100G 0 x00000040UL#define FW_PORT_CAP32_SPEED_200G 0 x00000080UL#define FW_PORT_CAP32_SPEED_400G 0 x00000100UL#define FW_PORT_CAP32_SPEED_RESERVED1 0 x00000200UL#define FW_PORT_CAP32_SPEED_RESERVED2 0 x00000400UL#define FW_PORT_CAP32_SPEED_RESERVED3 0 x00000800UL#define FW_PORT_CAP32_RESERVED1 0 x0000f000UL#define FW_PORT_CAP32_FC_RX 0 x00010000UL#define FW_PORT_CAP32_FC_TX 0 x00020000UL#define FW_PORT_CAP32_802_3_PAUSE 0 x00040000UL#define FW_PORT_CAP32_802_3_ASM_DIR 0 x00080000UL#define FW_PORT_CAP32_ANEG 0 x00100000UL#define FW_PORT_CAP32_MDIAUTO 0 x00200000UL#define FW_PORT_CAP32_MDISTRAIGHT 0 x00400000UL#define FW_PORT_CAP32_FEC_RS 0 x00800000UL#define FW_PORT_CAP32_FEC_BASER_RS 0 x01000000UL#define FW_PORT_CAP32_FEC_RESERVED1 0 x02000000UL#define FW_PORT_CAP32_FEC_RESERVED2 0 x04000000UL#define FW_PORT_CAP32_FEC_RESERVED3 0 x08000000UL#define FW_PORT_CAP32_FORCE_PAUSE 0 x10000000UL#define FW_PORT_CAP32_RESERVED2 0 xe0000000UL#define FW_PORT_CAP32_SPEED_S 0 #define FW_PORT_CAP32_SPEED_M 0 xfff#define FW_PORT_CAP32_SPEED_V(x) ((x) << FW_PORT_CAP32_SPEED_S)#define FW_PORT_CAP32_SPEED_G(x) \#define FW_PORT_CAP32_FC_S 16 #define FW_PORT_CAP32_FC_M 0 x3#define FW_PORT_CAP32_FC_V(x) ((x) << FW_PORT_CAP32_FC_S)#define FW_PORT_CAP32_FC_G(x) \#define FW_PORT_CAP32_802_3_S 18 #define FW_PORT_CAP32_802_3_M 0 x3#define FW_PORT_CAP32_802_3_V(x) ((x) << FW_PORT_CAP32_802_3_S)#define FW_PORT_CAP32_802_3_G(x) \#define FW_PORT_CAP32_ANEG_S 20 #define FW_PORT_CAP32_ANEG_M 0 x1#define FW_PORT_CAP32_ANEG_V(x) ((x) << FW_PORT_CAP32_ANEG_S)#define FW_PORT_CAP32_ANEG_G(x) \enum fw_port_mdi32 {#define FW_PORT_CAP32_MDI_S 21 #define FW_PORT_CAP32_MDI_M 3 #define FW_PORT_CAP32_MDI_V(x) ((x) << FW_PORT_CAP32_MDI_S)#define FW_PORT_CAP32_MDI_G(x) \#define FW_PORT_CAP32_FEC_S 23 #define FW_PORT_CAP32_FEC_M 0 x1f#define FW_PORT_CAP32_FEC_V(x) ((x) << FW_PORT_CAP32_FEC_S)#define FW_PORT_CAP32_FEC_G(x) \/* macros to isolate various 32-bit Port Capabilities sub-fields */ #define CAP32_SPEED(__cap32) \#define CAP32_FEC(__cap32) \enum fw_port_action {0 x0001,0 x0002,0 x0003,0 x0004,0 x0005,0 x0006,0 x0007,0 x0008,0 x0009,0 x000a,0 x0010,0 x0011,0 x0012,0 x0020,0 x0021,0 x0022,0 x0023,0 x0024,0 x0025,0 x0040,0 x0041,0 x0042,0 x0043,0 x0044,0 x0045enum fw_port_l2cfg_ctlbf {0 x01,0 x02,0 x04,0 x08,0 x10,0 x20enum fw_port_dcb_versions {7 enum fw_port_dcb_cfg {0 x01,0 x02,0 x04enum fw_port_dcb_cfg_rc {0 x0,0 x1enum fw_port_dcb_type {0 x00,0 x01,0 x02,0 x03,0 x04,0 x05,enum fw_port_dcb_feature_state {0 x0,0 x1,0 x2,0 x3,struct fw_port_cmd {union fw_port {struct fw_port_l1cfg {struct fw_port_l2cfg {struct fw_port_info {struct fw_port_diags {3 ];union fw_port_dcb {struct fw_port_dcb_pgid {2 ];struct fw_port_dcb_pgrate {5 ];8 ];8 ];struct fw_port_dcb_priorate {6 ];8 ];struct fw_port_dcb_pfc {5 ];struct fw_port_app_priority {2 ];struct fw_port_dcb_control {struct fw_port_l1cfg32 {struct fw_port_info32 {#define FW_PORT_CMD_READ_S 22 #define FW_PORT_CMD_READ_V(x) ((x) << FW_PORT_CMD_READ_S)#define FW_PORT_CMD_READ_F FW_PORT_CMD_READ_V(1 U)#define FW_PORT_CMD_PORTID_S 0 #define FW_PORT_CMD_PORTID_M 0 xf#define FW_PORT_CMD_PORTID_V(x) ((x) << FW_PORT_CMD_PORTID_S)#define FW_PORT_CMD_PORTID_G(x) \#define FW_PORT_CMD_ACTION_S 16 #define FW_PORT_CMD_ACTION_M 0 xffff#define FW_PORT_CMD_ACTION_V(x) ((x) << FW_PORT_CMD_ACTION_S)#define FW_PORT_CMD_ACTION_G(x) \#define FW_PORT_CMD_OVLAN3_S 7 #define FW_PORT_CMD_OVLAN3_V(x) ((x) << FW_PORT_CMD_OVLAN3_S)#define FW_PORT_CMD_OVLAN2_S 6 #define FW_PORT_CMD_OVLAN2_V(x) ((x) << FW_PORT_CMD_OVLAN2_S)#define FW_PORT_CMD_OVLAN1_S 5 #define FW_PORT_CMD_OVLAN1_V(x) ((x) << FW_PORT_CMD_OVLAN1_S)#define FW_PORT_CMD_OVLAN0_S 4 #define FW_PORT_CMD_OVLAN0_V(x) ((x) << FW_PORT_CMD_OVLAN0_S)#define FW_PORT_CMD_IVLAN0_S 3 #define FW_PORT_CMD_IVLAN0_V(x) ((x) << FW_PORT_CMD_IVLAN0_S)#define FW_PORT_CMD_TXIPG_S 3 #define FW_PORT_CMD_TXIPG_V(x) ((x) << FW_PORT_CMD_TXIPG_S)#define FW_PORT_CMD_LSTATUS_S 31 #define FW_PORT_CMD_LSTATUS_M 0 x1#define FW_PORT_CMD_LSTATUS_V(x) ((x) << FW_PORT_CMD_LSTATUS_S)#define FW_PORT_CMD_LSTATUS_G(x) \#define FW_PORT_CMD_LSTATUS_F FW_PORT_CMD_LSTATUS_V(1 U)#define FW_PORT_CMD_LSPEED_S 24 #define FW_PORT_CMD_LSPEED_M 0 x3f#define FW_PORT_CMD_LSPEED_V(x) ((x) << FW_PORT_CMD_LSPEED_S)#define FW_PORT_CMD_LSPEED_G(x) \#define FW_PORT_CMD_TXPAUSE_S 23 #define FW_PORT_CMD_TXPAUSE_V(x) ((x) << FW_PORT_CMD_TXPAUSE_S)#define FW_PORT_CMD_TXPAUSE_F FW_PORT_CMD_TXPAUSE_V(1 U)#define FW_PORT_CMD_RXPAUSE_S 22 #define FW_PORT_CMD_RXPAUSE_V(x) ((x) << FW_PORT_CMD_RXPAUSE_S)#define FW_PORT_CMD_RXPAUSE_F FW_PORT_CMD_RXPAUSE_V(1 U)#define FW_PORT_CMD_MDIOCAP_S 21 #define FW_PORT_CMD_MDIOCAP_V(x) ((x) << FW_PORT_CMD_MDIOCAP_S)#define FW_PORT_CMD_MDIOCAP_F FW_PORT_CMD_MDIOCAP_V(1 U)#define FW_PORT_CMD_MDIOADDR_S 16 #define FW_PORT_CMD_MDIOADDR_M 0 x1f#define FW_PORT_CMD_MDIOADDR_G(x) \#define FW_PORT_CMD_LPTXPAUSE_S 15 #define FW_PORT_CMD_LPTXPAUSE_V(x) ((x) << FW_PORT_CMD_LPTXPAUSE_S)#define FW_PORT_CMD_LPTXPAUSE_F FW_PORT_CMD_LPTXPAUSE_V(1 U)#define FW_PORT_CMD_LPRXPAUSE_S 14 #define FW_PORT_CMD_LPRXPAUSE_V(x) ((x) << FW_PORT_CMD_LPRXPAUSE_S)#define FW_PORT_CMD_LPRXPAUSE_F FW_PORT_CMD_LPRXPAUSE_V(1 U)#define FW_PORT_CMD_PTYPE_S 8 #define FW_PORT_CMD_PTYPE_M 0 x1f#define FW_PORT_CMD_PTYPE_G(x) \#define FW_PORT_CMD_LINKDNRC_S 5 #define FW_PORT_CMD_LINKDNRC_M 0 x7#define FW_PORT_CMD_LINKDNRC_G(x) \#define FW_PORT_CMD_MODTYPE_S 0 #define FW_PORT_CMD_MODTYPE_M 0 x1f#define FW_PORT_CMD_MODTYPE_V(x) ((x) << FW_PORT_CMD_MODTYPE_S)#define FW_PORT_CMD_MODTYPE_G(x) \#define FW_PORT_CMD_DCBXDIS_S 7 #define FW_PORT_CMD_DCBXDIS_V(x) ((x) << FW_PORT_CMD_DCBXDIS_S)#define FW_PORT_CMD_DCBXDIS_F FW_PORT_CMD_DCBXDIS_V(1 U)#define FW_PORT_CMD_APPLY_S 7 #define FW_PORT_CMD_APPLY_V(x) ((x) << FW_PORT_CMD_APPLY_S)#define FW_PORT_CMD_APPLY_F FW_PORT_CMD_APPLY_V(1 U)#define FW_PORT_CMD_ALL_SYNCD_S 7 #define FW_PORT_CMD_ALL_SYNCD_V(x) ((x) << FW_PORT_CMD_ALL_SYNCD_S)#define FW_PORT_CMD_ALL_SYNCD_F FW_PORT_CMD_ALL_SYNCD_V(1 U)#define FW_PORT_CMD_DCB_VERSION_S 12 #define FW_PORT_CMD_DCB_VERSION_M 0 x7#define FW_PORT_CMD_DCB_VERSION_G(x) \#define FW_PORT_CMD_LSTATUS32_S 31 #define FW_PORT_CMD_LSTATUS32_M 0 x1#define FW_PORT_CMD_LSTATUS32_V(x) ((x) << FW_PORT_CMD_LSTATUS32_S)#define FW_PORT_CMD_LSTATUS32_G(x) \#define FW_PORT_CMD_LSTATUS32_F FW_PORT_CMD_LSTATUS32_V(1 U)#define FW_PORT_CMD_LINKDNRC32_S 28 #define FW_PORT_CMD_LINKDNRC32_M 0 x7#define FW_PORT_CMD_LINKDNRC32_V(x) ((x) << FW_PORT_CMD_LINKDNRC32_S)#define FW_PORT_CMD_LINKDNRC32_G(x) \#define FW_PORT_CMD_DCBXDIS32_S 27 #define FW_PORT_CMD_DCBXDIS32_M 0 x1#define FW_PORT_CMD_DCBXDIS32_V(x) ((x) << FW_PORT_CMD_DCBXDIS32_S)#define FW_PORT_CMD_DCBXDIS32_G(x) \#define FW_PORT_CMD_DCBXDIS32_F FW_PORT_CMD_DCBXDIS32_V(1 U)#define FW_PORT_CMD_MDIOCAP32_S 26 #define FW_PORT_CMD_MDIOCAP32_M 0 x1#define FW_PORT_CMD_MDIOCAP32_V(x) ((x) << FW_PORT_CMD_MDIOCAP32_S)#define FW_PORT_CMD_MDIOCAP32_G(x) \#define FW_PORT_CMD_MDIOCAP32_F FW_PORT_CMD_MDIOCAP32_V(1 U)#define FW_PORT_CMD_MDIOADDR32_S 21 #define FW_PORT_CMD_MDIOADDR32_M 0 x1f#define FW_PORT_CMD_MDIOADDR32_V(x) ((x) << FW_PORT_CMD_MDIOADDR32_S)#define FW_PORT_CMD_MDIOADDR32_G(x) \#define FW_PORT_CMD_PORTTYPE32_S 13 #define FW_PORT_CMD_PORTTYPE32_M 0 xff#define FW_PORT_CMD_PORTTYPE32_V(x) ((x) << FW_PORT_CMD_PORTTYPE32_S)#define FW_PORT_CMD_PORTTYPE32_G(x) \#define FW_PORT_CMD_MODTYPE32_S 8 #define FW_PORT_CMD_MODTYPE32_M 0 x1f#define FW_PORT_CMD_MODTYPE32_V(x) ((x) << FW_PORT_CMD_MODTYPE32_S)#define FW_PORT_CMD_MODTYPE32_G(x) \#define FW_PORT_CMD_CBLLEN32_S 0 #define FW_PORT_CMD_CBLLEN32_M 0 xff#define FW_PORT_CMD_CBLLEN32_V(x) ((x) << FW_PORT_CMD_CBLLEN32_S)#define FW_PORT_CMD_CBLLEN32_G(x) \#define FW_PORT_CMD_AUXLINFO32_S 24 #define FW_PORT_CMD_AUXLINFO32_M 0 xff#define FW_PORT_CMD_AUXLINFO32_V(x) ((x) << FW_PORT_CMD_AUXLINFO32_S)#define FW_PORT_CMD_AUXLINFO32_G(x) \#define FW_PORT_AUXLINFO32_KX4_S 2 #define FW_PORT_AUXLINFO32_KX4_M 0 x1#define FW_PORT_AUXLINFO32_KX4_V(x) \#define FW_PORT_AUXLINFO32_KX4_G(x) \#define FW_PORT_AUXLINFO32_KX4_F FW_PORT_AUXLINFO32_KX4_V(1 U)#define FW_PORT_AUXLINFO32_KR_S 1 #define FW_PORT_AUXLINFO32_KR_M 0 x1#define FW_PORT_AUXLINFO32_KR_V(x) \#define FW_PORT_AUXLINFO32_KR_G(x) \#define FW_PORT_AUXLINFO32_KR_F FW_PORT_AUXLINFO32_KR_V(1 U)#define FW_PORT_CMD_MTU32_S 0 #define FW_PORT_CMD_MTU32_M 0 xffff#define FW_PORT_CMD_MTU32_V(x) ((x) << FW_PORT_CMD_MTU32_S)#define FW_PORT_CMD_MTU32_G(x) \enum fw_port_type {enum fw_port_module_type {3 ,2 ,1 ,enum fw_port_mod_sub_type {0 x1,0 x2,0 x3,0 x4,0 x5,0 x8,/* The following will never been in the VPD. They are TWINAX cable * lengths decoded from SFP+ module i2c PROMs. These should * almost certainly go somewhere else ... 0 x9,0 xA,0 xB,0 xC,enum fw_port_stats_tx_index {0 ,enum fw_port_stat_rx_index {0 ,/* port stats */ #define FW_NUM_PORT_STATS (FW_NUM_PORT_TX_STATS + FW_NUM_PORT_RX_STATS)struct fw_port_stats_cmd {union fw_port_stats {struct fw_port_stats_ctl {struct fw_port_stats_all {/* port loopback stats */ #define FW_NUM_LB_STATS 16 enum fw_port_lb_stats_index {struct fw_port_lb_stats_cmd {union fw_port_lb_stats {struct fw_port_lb_stats_ctl {struct fw_port_lb_stats_all {enum fw_ptp_subop {/* none */ 0 x00,0 x01,/* init */ 0 x08,0 x09,/* ts */ 0 x10,0 x11,0 x12,0 x13,0 x14,0 x15,struct fw_ptp_cmd {union fw_ptp {struct fw_ptp_sc {7 ];struct fw_ptp_init {struct fw_ptp_ts {#define FW_PTP_CMD_PORTID_S 0 #define FW_PTP_CMD_PORTID_M 0 xf#define FW_PTP_CMD_PORTID_V(x) ((x) << FW_PTP_CMD_PORTID_S)#define FW_PTP_CMD_PORTID_G(x) \struct fw_rss_ind_tbl_cmd {#define FW_RSS_IND_TBL_CMD_VIID_S 0 #define FW_RSS_IND_TBL_CMD_VIID_V(x) ((x) << FW_RSS_IND_TBL_CMD_VIID_S)#define FW_RSS_IND_TBL_CMD_IQ0_S 20 #define FW_RSS_IND_TBL_CMD_IQ0_V(x) ((x) << FW_RSS_IND_TBL_CMD_IQ0_S)#define FW_RSS_IND_TBL_CMD_IQ1_S 10 #define FW_RSS_IND_TBL_CMD_IQ1_V(x) ((x) << FW_RSS_IND_TBL_CMD_IQ1_S)#define FW_RSS_IND_TBL_CMD_IQ2_S 0 #define FW_RSS_IND_TBL_CMD_IQ2_V(x) ((x) << FW_RSS_IND_TBL_CMD_IQ2_S)struct fw_rss_glb_config_cmd {union fw_rss_glb_config {struct fw_rss_glb_config_manual {struct fw_rss_glb_config_basicvirtual {#define FW_RSS_GLB_CONFIG_CMD_MODE_S 28 #define FW_RSS_GLB_CONFIG_CMD_MODE_M 0 xf#define FW_RSS_GLB_CONFIG_CMD_MODE_V(x) ((x) << FW_RSS_GLB_CONFIG_CMD_MODE_S)#define FW_RSS_GLB_CONFIG_CMD_MODE_G(x) \#define FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL 0 #define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL 1 #define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_S 8 #define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_V(x) \#define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_F \1 U)#define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_S 7 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_V(x) \#define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_F \1 U)#define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_S 6 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_V(x) \#define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_F \1 U)#define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_S 5 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_V(x) \#define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_F \1 U)#define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_S 4 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_V(x) \#define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_F \1 U)#define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_S 3 #define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_V(x) \#define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_F \1 U)#define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_S 2 #define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_V(x) \#define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_F \1 U)#define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_S 1 #define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_V(x) \#define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_F \1 U)#define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_S 0 #define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_V(x) \#define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_F \1 U)struct fw_rss_vi_config_cmd {#define FW_RSS_VI_CONFIG_CMD_VIID(x) ((x) << 0 )union fw_rss_vi_config {struct fw_rss_vi_config_manual {struct fw_rss_vi_config_basicvirtual {#define FW_RSS_VI_CONFIG_CMD_VIID_S 0 #define FW_RSS_VI_CONFIG_CMD_VIID_V(x) ((x) << FW_RSS_VI_CONFIG_CMD_VIID_S)#define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_S 16 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_M 0 x3ff#define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_V(x) \#define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_G(x) \#define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_S 4 #define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_V(x) \#define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_F \1 U)#define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_S 3 #define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_V(x) \#define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_F \1 U)#define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_S 2 #define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_V(x) \#define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_F \1 U)#define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_S 1 #define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_V(x) \#define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_F \1 U)#define FW_RSS_VI_CONFIG_CMD_UDPEN_S 0 #define FW_RSS_VI_CONFIG_CMD_UDPEN_V(x) ((x) << FW_RSS_VI_CONFIG_CMD_UDPEN_S)#define FW_RSS_VI_CONFIG_CMD_UDPEN_F FW_RSS_VI_CONFIG_CMD_UDPEN_V(1 U)enum fw_sched_sc {1 ,struct fw_sched_cmd {union fw_sched {struct fw_sched_config {5 ];4 ];struct fw_sched_params {struct fw_clip_cmd {2 ];#define FW_CLIP_CMD_ALLOC_S 31 #define FW_CLIP_CMD_ALLOC_V(x) ((x) << FW_CLIP_CMD_ALLOC_S)#define FW_CLIP_CMD_ALLOC_F FW_CLIP_CMD_ALLOC_V(1 U)#define FW_CLIP_CMD_FREE_S 30 #define FW_CLIP_CMD_FREE_V(x) ((x) << FW_CLIP_CMD_FREE_S)#define FW_CLIP_CMD_FREE_F FW_CLIP_CMD_FREE_V(1 U)enum fw_error_type {0 x0,0 x1,0 x2,0 x3,struct fw_error_cmd {union fw_error {struct fw_error_exception {6 ];struct fw_error_hwmodule {struct fw_error_wr {16 ];struct fw_error_acl {6 ];struct fw_debug_cmd {union fw_debug {struct fw_debug_assert {8 ];8 ];struct fw_debug_prt {3 ];#define FW_DEBUG_CMD_TYPE_S 0 #define FW_DEBUG_CMD_TYPE_M 0 xff#define FW_DEBUG_CMD_TYPE_G(x) \struct fw_hma_cmd {5 ];#define FW_HMA_CMD_MODE_S 31 #define FW_HMA_CMD_MODE_M 0 x1#define FW_HMA_CMD_MODE_V(x) ((x) << FW_HMA_CMD_MODE_S)#define FW_HMA_CMD_MODE_G(x) \#define FW_HMA_CMD_MODE_F FW_HMA_CMD_MODE_V(1 U)#define FW_HMA_CMD_SOC_S 30 #define FW_HMA_CMD_SOC_M 0 x1#define FW_HMA_CMD_SOC_V(x) ((x) << FW_HMA_CMD_SOC_S)#define FW_HMA_CMD_SOC_G(x) (((x) >> FW_HMA_CMD_SOC_S) & FW_HMA_CMD_SOC_M)#define FW_HMA_CMD_SOC_F FW_HMA_CMD_SOC_V(1 U)#define FW_HMA_CMD_EOC_S 29 #define FW_HMA_CMD_EOC_M 0 x1#define FW_HMA_CMD_EOC_V(x) ((x) << FW_HMA_CMD_EOC_S)#define FW_HMA_CMD_EOC_G(x) (((x) >> FW_HMA_CMD_EOC_S) & FW_HMA_CMD_EOC_M)#define FW_HMA_CMD_EOC_F FW_HMA_CMD_EOC_V(1 U)#define FW_HMA_CMD_PCIE_PARAMS_S 0 #define FW_HMA_CMD_PCIE_PARAMS_M 0 x7ffffff#define FW_HMA_CMD_PCIE_PARAMS_V(x) ((x) << FW_HMA_CMD_PCIE_PARAMS_S)#define FW_HMA_CMD_PCIE_PARAMS_G(x) \#define FW_HMA_CMD_NADDR_S 12 #define FW_HMA_CMD_NADDR_M 0 x3f#define FW_HMA_CMD_NADDR_V(x) ((x) << FW_HMA_CMD_NADDR_S)#define FW_HMA_CMD_NADDR_G(x) \#define FW_HMA_CMD_SIZE_S 0 #define FW_HMA_CMD_SIZE_M 0 xfff#define FW_HMA_CMD_SIZE_V(x) ((x) << FW_HMA_CMD_SIZE_S)#define FW_HMA_CMD_SIZE_G(x) \#define FW_HMA_CMD_ADDR_SIZE_S 11 #define FW_HMA_CMD_ADDR_SIZE_M 0 x1fffff#define FW_HMA_CMD_ADDR_SIZE_V(x) ((x) << FW_HMA_CMD_ADDR_SIZE_S)#define FW_HMA_CMD_ADDR_SIZE_G(x) \enum pcie_fw_eval {0 ,#define PCIE_FW_ERR_S 31 #define PCIE_FW_ERR_V(x) ((x) << PCIE_FW_ERR_S)#define PCIE_FW_ERR_F PCIE_FW_ERR_V(1 U)#define PCIE_FW_INIT_S 30 #define PCIE_FW_INIT_V(x) ((x) << PCIE_FW_INIT_S)#define PCIE_FW_INIT_F PCIE_FW_INIT_V(1 U)#define PCIE_FW_HALT_S 29 #define PCIE_FW_HALT_V(x) ((x) << PCIE_FW_HALT_S)#define PCIE_FW_HALT_F PCIE_FW_HALT_V(1 U)#define PCIE_FW_EVAL_S 24 #define PCIE_FW_EVAL_M 0 x7#define PCIE_FW_EVAL_G(x) (((x) >> PCIE_FW_EVAL_S) & PCIE_FW_EVAL_M)#define PCIE_FW_MASTER_VLD_S 15 #define PCIE_FW_MASTER_VLD_V(x) ((x) << PCIE_FW_MASTER_VLD_S)#define PCIE_FW_MASTER_VLD_F PCIE_FW_MASTER_VLD_V(1 U)#define PCIE_FW_MASTER_S 12 #define PCIE_FW_MASTER_M 0 x7#define PCIE_FW_MASTER_V(x) ((x) << PCIE_FW_MASTER_S)#define PCIE_FW_MASTER_G(x) (((x) >> PCIE_FW_MASTER_S) & PCIE_FW_MASTER_M)struct fw_hdr {/* terminator chip type */ /* bin length in units of 512-bytes */ /* firmware version */ 23 ];enum fw_hdr_chip {#define FW_HDR_FW_VER_MAJOR_S 24 #define FW_HDR_FW_VER_MAJOR_M 0 xff#define FW_HDR_FW_VER_MAJOR_V(x) \#define FW_HDR_FW_VER_MAJOR_G(x) \#define FW_HDR_FW_VER_MINOR_S 16 #define FW_HDR_FW_VER_MINOR_M 0 xff#define FW_HDR_FW_VER_MINOR_V(x) \#define FW_HDR_FW_VER_MINOR_G(x) \#define FW_HDR_FW_VER_MICRO_S 8 #define FW_HDR_FW_VER_MICRO_M 0 xff#define FW_HDR_FW_VER_MICRO_V(x) \#define FW_HDR_FW_VER_MICRO_G(x) \#define FW_HDR_FW_VER_BUILD_S 0 #define FW_HDR_FW_VER_BUILD_M 0 xff#define FW_HDR_FW_VER_BUILD_V(x) \#define FW_HDR_FW_VER_BUILD_G(x) \enum fw_hdr_intfver {0 x00,0 x00,0 x00,0 x00,0 x00,0 x00,0 x00,0 x00,enum fw_hdr_flags {0 x00000001,/* length of the formatting string */ #define FW_DEVLOG_FMT_LEN 192 /* maximum number of the formatting string parameters */ #define FW_DEVLOG_FMT_PARAMS_NUM 8 /* priority levels */ enum fw_devlog_level {0 x0,0 x1,0 x2,0 x3,0 x4,0 x5,0 x5,/* facilities that may send a log message */ enum fw_devlog_facility {0 x00,0 x01,0 x02,0 x04,0 x06,0 x08,0 x10,0 x12,0 x14,0 x16,0 x18,0 x1A,0 x1C,0 x1E,0 x20,0 x22,0 x24,0 x26,0 x28,0 x2A,0 x2C,0 x2E,0 x30,0 x32,0 x34,0 x34,/* log message format */ struct fw_devlog_e {4 ];struct fw_devlog_cmd {7 ];2 ];#define FW_DEVLOG_CMD_MEMTYPE_DEVLOG_S 28 #define FW_DEVLOG_CMD_MEMTYPE_DEVLOG_M 0 xf#define FW_DEVLOG_CMD_MEMTYPE_DEVLOG_G(x) \#define FW_DEVLOG_CMD_MEMADDR16_DEVLOG_S 0 #define FW_DEVLOG_CMD_MEMADDR16_DEVLOG_M 0 xfffffff#define FW_DEVLOG_CMD_MEMADDR16_DEVLOG_G(x) \/* P C I E F W P F 7 R E G I S T E R */ /* PF7 stores the Firmware Device Log parameters which allows Host Drivers to * access the "devlog" which needing to contact firmware. The encoding is * mostly the same as that returned by the DEVLOG command except for the size * which is encoded as the number of entries in multiples-1 of 128 here rather * than the memory size as is done in the DEVLOG command. Thus, 0 means 128 * and 15 means 2048. This of course in turn constrains the allowed values * for the devlog size ... #define PCIE_FW_PF_DEVLOG 7 #define PCIE_FW_PF_DEVLOG_NENTRIES128_S 28 #define PCIE_FW_PF_DEVLOG_NENTRIES128_M 0 xf#define PCIE_FW_PF_DEVLOG_NENTRIES128_V(x) \#define PCIE_FW_PF_DEVLOG_NENTRIES128_G(x) \#define PCIE_FW_PF_DEVLOG_ADDR16_S 4 #define PCIE_FW_PF_DEVLOG_ADDR16_M 0 xffffff#define PCIE_FW_PF_DEVLOG_ADDR16_V(x) ((x) << PCIE_FW_PF_DEVLOG_ADDR16_S)#define PCIE_FW_PF_DEVLOG_ADDR16_G(x) \#define PCIE_FW_PF_DEVLOG_MEMTYPE_S 0 #define PCIE_FW_PF_DEVLOG_MEMTYPE_M 0 xf#define PCIE_FW_PF_DEVLOG_MEMTYPE_V(x) ((x) << PCIE_FW_PF_DEVLOG_MEMTYPE_S)#define PCIE_FW_PF_DEVLOG_MEMTYPE_G(x) \#define MAX_IMM_OFLD_TX_DATA_WR_LEN (0 xff + sizeof (struct fw_ofld_tx_data_wr))struct fw_crypto_lookaside_wr {#define FW_CRYPTO_LOOKASIDE_WR_OPCODE_S 24 #define FW_CRYPTO_LOOKASIDE_WR_OPCODE_M 0 xff#define FW_CRYPTO_LOOKASIDE_WR_OPCODE_V(x) \#define FW_CRYPTO_LOOKASIDE_WR_OPCODE_G(x) \#define FW_CRYPTO_LOOKASIDE_WR_COMPL_S 23 #define FW_CRYPTO_LOOKASIDE_WR_COMPL_M 0 x1#define FW_CRYPTO_LOOKASIDE_WR_COMPL_V(x) \#define FW_CRYPTO_LOOKASIDE_WR_COMPL_G(x) \#define FW_CRYPTO_LOOKASIDE_WR_COMPL_F FW_CRYPTO_LOOKASIDE_WR_COMPL_V(1 U)#define FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_S 15 #define FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_M 0 xff#define FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_V(x) \#define FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_G(x) \#define FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_S 5 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_M 0 x3#define FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_V(x) \#define FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_G(x) \#define FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_S 0 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_M 0 x1f#define FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_V(x) \#define FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_G(x) \#define FW_CRYPTO_LOOKASIDE_WR_LEN16_S 0 #define FW_CRYPTO_LOOKASIDE_WR_LEN16_M 0 xff#define FW_CRYPTO_LOOKASIDE_WR_LEN16_V(x) \#define FW_CRYPTO_LOOKASIDE_WR_LEN16_G(x) \#define FW_CRYPTO_LOOKASIDE_WR_RX_CHID_S 29 #define FW_CRYPTO_LOOKASIDE_WR_RX_CHID_M 0 x3#define FW_CRYPTO_LOOKASIDE_WR_RX_CHID_V(x) \#define FW_CRYPTO_LOOKASIDE_WR_RX_CHID_G(x) \#define FW_CRYPTO_LOOKASIDE_WR_LCB_S 27 #define FW_CRYPTO_LOOKASIDE_WR_LCB_M 0 x3#define FW_CRYPTO_LOOKASIDE_WR_LCB_V(x) \#define FW_CRYPTO_LOOKASIDE_WR_LCB_G(x) \#define FW_CRYPTO_LOOKASIDE_WR_PHASH_S 25 #define FW_CRYPTO_LOOKASIDE_WR_PHASH_M 0 x3#define FW_CRYPTO_LOOKASIDE_WR_PHASH_V(x) \#define FW_CRYPTO_LOOKASIDE_WR_PHASH_G(x) \#define FW_CRYPTO_LOOKASIDE_WR_IV_S 23 #define FW_CRYPTO_LOOKASIDE_WR_IV_M 0 x3#define FW_CRYPTO_LOOKASIDE_WR_IV_V(x) \#define FW_CRYPTO_LOOKASIDE_WR_IV_G(x) \#define FW_CRYPTO_LOOKASIDE_WR_FQIDX_S 15 #define FW_CRYPTO_LOOKASIDE_WR_FQIDX_M 0 xff#define FW_CRYPTO_LOOKASIDE_WR_FQIDX_V(x) \#define FW_CRYPTO_LOOKASIDE_WR_FQIDX_G(x) \#define FW_CRYPTO_LOOKASIDE_WR_TX_CH_S 10 #define FW_CRYPTO_LOOKASIDE_WR_TX_CH_M 0 x3#define FW_CRYPTO_LOOKASIDE_WR_TX_CH_V(x) \#define FW_CRYPTO_LOOKASIDE_WR_TX_CH_G(x) \#define FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_S 0 #define FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_M 0 x3ff#define FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_V(x) \#define FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_G(x) \#define FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_S 24 #define FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_M 0 xff#define FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_V(x) \#define FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_G(x) \#define FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_S 17 #define FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_M 0 x7f#define FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_V(x) \#define FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_G(x) \struct fw_tlstx_data_wr {#define FW_TLSTX_DATA_WR_OPCODE_S 24 #define FW_TLSTX_DATA_WR_OPCODE_M 0 xff#define FW_TLSTX_DATA_WR_OPCODE_V(x) ((x) << FW_TLSTX_DATA_WR_OPCODE_S)#define FW_TLSTX_DATA_WR_OPCODE_G(x) \#define FW_TLSTX_DATA_WR_COMPL_S 21 #define FW_TLSTX_DATA_WR_COMPL_M 0 x1#define FW_TLSTX_DATA_WR_COMPL_V(x) ((x) << FW_TLSTX_DATA_WR_COMPL_S)#define FW_TLSTX_DATA_WR_COMPL_G(x) \#define FW_TLSTX_DATA_WR_COMPL_F FW_TLSTX_DATA_WR_COMPL_V(1 U)#define FW_TLSTX_DATA_WR_IMMDLEN_S 0 #define FW_TLSTX_DATA_WR_IMMDLEN_M 0 xff#define FW_TLSTX_DATA_WR_IMMDLEN_V(x) ((x) << FW_TLSTX_DATA_WR_IMMDLEN_S)#define FW_TLSTX_DATA_WR_IMMDLEN_G(x) \#define FW_TLSTX_DATA_WR_FLOWID_S 8 #define FW_TLSTX_DATA_WR_FLOWID_M 0 xfffff#define FW_TLSTX_DATA_WR_FLOWID_V(x) ((x) << FW_TLSTX_DATA_WR_FLOWID_S)#define FW_TLSTX_DATA_WR_FLOWID_G(x) \#define FW_TLSTX_DATA_WR_LEN16_S 0 #define FW_TLSTX_DATA_WR_LEN16_M 0 xff#define FW_TLSTX_DATA_WR_LEN16_V(x) ((x) << FW_TLSTX_DATA_WR_LEN16_S)#define FW_TLSTX_DATA_WR_LEN16_G(x) \#define FW_TLSTX_DATA_WR_LSODISABLE_S 31 #define FW_TLSTX_DATA_WR_LSODISABLE_M 0 x1#define FW_TLSTX_DATA_WR_LSODISABLE_V(x) \#define FW_TLSTX_DATA_WR_LSODISABLE_G(x) \#define FW_TLSTX_DATA_WR_LSODISABLE_F FW_TLSTX_DATA_WR_LSODISABLE_V(1 U)#define FW_TLSTX_DATA_WR_ALIGNPLD_S 30 #define FW_TLSTX_DATA_WR_ALIGNPLD_M 0 x1#define FW_TLSTX_DATA_WR_ALIGNPLD_V(x) ((x) << FW_TLSTX_DATA_WR_ALIGNPLD_S)#define FW_TLSTX_DATA_WR_ALIGNPLD_G(x) \#define FW_TLSTX_DATA_WR_ALIGNPLD_F FW_TLSTX_DATA_WR_ALIGNPLD_V(1 U)#define FW_TLSTX_DATA_WR_ALIGNPLDSHOVE_S 29 #define FW_TLSTX_DATA_WR_ALIGNPLDSHOVE_M 0 x1#define FW_TLSTX_DATA_WR_ALIGNPLDSHOVE_V(x) \#define FW_TLSTX_DATA_WR_ALIGNPLDSHOVE_G(x) \#define FW_TLSTX_DATA_WR_ALIGNPLDSHOVE_F FW_TLSTX_DATA_WR_ALIGNPLDSHOVE_V(1 U)#define FW_TLSTX_DATA_WR_FLAGS_S 0 #define FW_TLSTX_DATA_WR_FLAGS_M 0 xfffffff#define FW_TLSTX_DATA_WR_FLAGS_V(x) ((x) << FW_TLSTX_DATA_WR_FLAGS_S)#define FW_TLSTX_DATA_WR_FLAGS_G(x) \#define FW_TLSTX_DATA_WR_CTXLOC_S 30 #define FW_TLSTX_DATA_WR_CTXLOC_M 0 x3#define FW_TLSTX_DATA_WR_CTXLOC_V(x) ((x) << FW_TLSTX_DATA_WR_CTXLOC_S)#define FW_TLSTX_DATA_WR_CTXLOC_G(x) \#define FW_TLSTX_DATA_WR_IVDSGL_S 29 #define FW_TLSTX_DATA_WR_IVDSGL_M 0 x1#define FW_TLSTX_DATA_WR_IVDSGL_V(x) ((x) << FW_TLSTX_DATA_WR_IVDSGL_S)#define FW_TLSTX_DATA_WR_IVDSGL_G(x) \#define FW_TLSTX_DATA_WR_IVDSGL_F FW_TLSTX_DATA_WR_IVDSGL_V(1 U)#define FW_TLSTX_DATA_WR_KEYSIZE_S 24 #define FW_TLSTX_DATA_WR_KEYSIZE_M 0 x1f#define FW_TLSTX_DATA_WR_KEYSIZE_V(x) ((x) << FW_TLSTX_DATA_WR_KEYSIZE_S)#define FW_TLSTX_DATA_WR_KEYSIZE_G(x) \#define FW_TLSTX_DATA_WR_NUMIVS_S 14 #define FW_TLSTX_DATA_WR_NUMIVS_M 0 xff#define FW_TLSTX_DATA_WR_NUMIVS_V(x) ((x) << FW_TLSTX_DATA_WR_NUMIVS_S)#define FW_TLSTX_DATA_WR_NUMIVS_G(x) \#define FW_TLSTX_DATA_WR_EXP_S 0 #define FW_TLSTX_DATA_WR_EXP_M 0 x3fff#define FW_TLSTX_DATA_WR_EXP_V(x) ((x) << FW_TLSTX_DATA_WR_EXP_S)#define FW_TLSTX_DATA_WR_EXP_G(x) \#define FW_TLSTX_DATA_WR_ADJUSTEDPLEN_S 1 #define FW_TLSTX_DATA_WR_ADJUSTEDPLEN_V(x) \#define FW_TLSTX_DATA_WR_EXPINPLENMAX_S 4 #define FW_TLSTX_DATA_WR_EXPINPLENMAX_V(x) \#define FW_TLSTX_DATA_WR_PDUSINPLENMAX_S 2 #define FW_TLSTX_DATA_WR_PDUSINPLENMAX_V(x) \#endif /* _T4FW_INTERFACE_H_ */
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