// SPDX-License-Identifier: GPL-2.0-only /* * Contains CPU feature definitions * * Copyright (C) 2015 ARM Ltd. * * A note for the weary kernel hacker: the code here is confusing and hard to * follow! That's partly because it's solving a nasty problem, but also because * there's a little bit of over-abstraction that tends to obscure what's going * on behind a maze of helper functions and macros. * * The basic problem is that hardware folks have started gluing together CPUs * with distinct architectural features; in some cases even creating SoCs where * user-visible instructions are available only on a subset of the available * cores. We try to address this by snapshotting the feature registers of the * boot CPU and comparing these with the feature registers of each secondary * CPU when bringing them up. If there is a mismatch, then we update the * snapshot state to indicate the lowest-common denominator of the feature, * known as the "safe" value. This snapshot state can be queried to view the * "sanitised" value of a feature register. * * The sanitised register values are used to decide which capabilities we * have in the system. These may be in the form of traditional "hwcaps" * advertised to userspace or internal "cpucaps" which are used to configure * things like alternative patching and static keys. While a feature mismatch * may result in a TAINT_CPU_OUT_OF_SPEC kernel taint, a capability mismatch * may prevent a CPU from being onlined at all. * * Some implementation details worth remembering: * * - Mismatched features are *always* sanitised to a "safe" value, which * usually indicates that the feature is not supported. * * - A mismatched feature marked with FTR_STRICT will cause a "SANITY CHECK" * warning when onlining an offending CPU and the kernel will be tainted * with TAINT_CPU_OUT_OF_SPEC. * * - Features marked as FTR_VISIBLE have their sanitised value visible to * userspace. FTR_VISIBLE features in registers that are only visible * to EL0 by trapping *must* have a corresponding HWCAP so that late * onlining of CPUs cannot lead to features disappearing at runtime. * * - A "feature" is typically a 4-bit register field. A "capability" is the * high-level description derived from the sanitised field value. * * - Read the Arm ARM (DDI 0487F.a) section D13.1.3 ("Principles of the ID * scheme for fields in ID registers") to understand when feature fields * may be signed or unsigned (FTR_SIGNED and FTR_UNSIGNED accordingly). * * - KVM exposes its own view of the feature registers to guest operating * systems regardless of FTR_VISIBLE. This is typically driven from the * sanitised register values to allow virtual CPUs to be migrated between * arbitrary physical CPUs, but some features not present on the host are * also advertised and emulated. Look at sys_reg_descs[] for the gory * details. * * - If the arm64_ftr_bits[] for a register has a missing field, then this * field is treated as STRICT RES0, including for read_sanitised_ftr_reg(). * This is stronger than FTR_HIDDEN and can be used to hide features from * KVM guests.
*/
/* * arm64_use_ng_mappings must be placed in the .data section, otherwise it * ends up in the .bss section where it is initialized in early_map_kernel() * after the MMU (with the idmap) was enabled. create_init_idmap() - which * runs before early_map_kernel() and reads the variable via PTE_MAYBE_NG - * may end up generating an incorrect idmap page table attributes.
*/ bool arm64_use_ng_mappings __read_mostly = false;
EXPORT_SYMBOL(arm64_use_ng_mappings);
/* * Permit PER_LINUX32 and execve() of 32-bit binaries even if not all CPUs * support it?
*/ staticbool __read_mostly allow_mismatched_32bit_el0;
/* * Static branch enabled only if allow_mismatched_32bit_el0 is set and we have * seen at least one CPU capable of 32-bit EL0.
*/
DEFINE_STATIC_KEY_FALSE(arm64_mismatched_32bit_el0);
/* * Mask of CPUs supporting 32-bit EL0. * Only valid if arm64_mismatched_32bit_el0 is enabled.
*/ static cpumask_var_t cpu_32bit_el0_mask __cpumask_var_read_mostly;
/* * ARM64_CPUID_FIELDS() encodes a field with a range from min_value to * an implicit maximum that depends on the sign-ess of the field. * * An unsigned field will be capped at all ones, while a signed field * will be limited to the positive half only.
*/ #define ARM64_CPUID_FIELDS(reg, field, min_value) \
__ARM64_CPUID_FIELDS(reg, field, \
SYS_FIELD_VALUE(reg, field, min_value), \
__ARM64_MAX_POSITIVE(reg, field))
/* * ARM64_CPUID_FIELDS_NEG() encodes a field with a range from an * implicit minimal value to max_value. This should be used when * matching a non-implemented property.
*/ #define ARM64_CPUID_FIELDS_NEG(reg, field, max_value) \
__ARM64_CPUID_FIELDS(reg, field, \
__ARM64_MIN_NEGATIVE(reg, field), \
SYS_FIELD_VALUE(reg, field, max_value))
/* Define a feature with a signed value */ #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
__ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
staticconststruct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_ECV_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_FGT_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_EXS_SHIFT, 4, 0), /* * Page size not being supported at Stage-2 is not fatal. You * just give up KVM if PAGE_SIZE isn't supported there. Go fix * your favourite nesting hypervisor. * * There is a small corner case where the hypervisor explicitly * advertises a given granule size at Stage-2 (value 2) on some * vCPUs, and uses the fallback to Stage-1 (value 0) for other * vCPUs. Although this is not forbidden by the architecture, it * indicates that the hypervisor is being silly (or buggy). * * We make no effort to cope with this and pretend that if these * fields are inconsistent across vCPUs, then it isn't worth * trying to bring KVM up.
*/
ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN4_2_SHIFT, 4, 1),
ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN64_2_SHIFT, 4, 1),
ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN16_2_SHIFT, 4, 1), /* * We already refuse to boot CPUs that don't support our configured * page size, so we can only detect mismatches for a page size other * than the one we're currently using. Unfortunately, SoCs like this * exist in the wild so, even though we don't like it, we'll have to go * along with it and treat them as non-strict.
*/
S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN4_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN4_NI),
S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN64_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN64_NI),
ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN16_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN16_NI),
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_BIGENDEL0_SHIFT, 4, 0), /* Linux shouldn't care about secure memory */
ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_SNSMEM_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_BIGEND_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_ASIDBITS_SHIFT, 4, 0), /* * Differing PARange is fine as long as all peripherals and memory are mapped * within the minimum PARange of all CPUs
*/
ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_PARANGE_SHIFT, 4, 0),
ARM64_FTR_END,
};
/* * SpecSEI = 1 indicates that the PE might generate an SError on an * external abort on speculative read. It is safe to assume that an * SError might be generated than it will not be. Hence it has been * classified as FTR_HIGHER_SAFE.
*/
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_MMFR4_EL1_SpecSEI_SHIFT, 4, 0),
ARM64_FTR_END,
};
/* * get_arm64_ftr_reg_nowarn - Looks up a feature register entry using * its sys_reg() encoding. With the array arm64_ftr_regs sorted in the * ascending order of sys_id, we use binary search to find a matching * entry. * * returns - Upon success, matching ftr_reg entry for id. * - NULL on failure. It is upto the caller to decide * the impact of a failure.
*/ staticstruct arm64_ftr_reg *get_arm64_ftr_reg_nowarn(u32 sys_id)
{ conststruct __ftr_reg_entry *ret;
ret = bsearch((constvoid *)(unsignedlong)sys_id,
arm64_ftr_regs,
ARRAY_SIZE(arm64_ftr_regs), sizeof(arm64_ftr_regs[0]),
search_cmp_ftr_reg); if (ret) return ret->reg; return NULL;
}
/* * get_arm64_ftr_reg - Looks up a feature register entry using * its sys_reg() encoding. This calls get_arm64_ftr_reg_nowarn(). * * returns - Upon success, matching ftr_reg entry for id. * - NULL on failure but with an WARN_ON().
*/ struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id)
{ struct arm64_ftr_reg *reg;
reg = get_arm64_ftr_reg_nowarn(sys_id);
/* * Requesting a non-existent register search is an error. Warn * and let the caller handle it.
*/
WARN_ON(!reg); return reg;
}
switch (ftrp->type) { case FTR_EXACT:
ret = ftrp->safe_val; break; case FTR_LOWER_SAFE:
ret = min(new, cur); break; case FTR_HIGHER_OR_ZERO_SAFE: if (!cur || !new) break;
fallthrough; case FTR_HIGHER_SAFE:
ret = max(new, cur); break; default:
BUG();
}
for (i = 0; i < ARRAY_SIZE(arm64_ftr_regs); i++) { conststruct arm64_ftr_reg *ftr_reg = arm64_ftr_regs[i].reg; conststruct arm64_ftr_bits *ftr_bits = ftr_reg->ftr_bits; unsignedint j = 0;
/* * Features here must be sorted in descending order with respect * to their shift values and should not overlap with each other.
*/ for (; ftr_bits->width != 0; ftr_bits++, j++) { unsignedint width = ftr_reg->ftr_bits[j].width; unsignedint shift = ftr_reg->ftr_bits[j].shift; unsignedint prev_shift;
WARN((shift + width) > 64, "%s has invalid feature at shift %d\n",
ftr_reg->name, shift);
/* * Skip the first feature. There is nothing to * compare against for now.
*/ if (j == 0) continue;
prev_shift = ftr_reg->ftr_bits[j - 1].shift;
WARN((shift + width) > prev_shift, "%s has feature overlap at shift %d\n",
ftr_reg->name, shift);
}
/* * Skip the first register. There is nothing to * compare against for now.
*/ if (i == 0) continue; /* * Registers here must be sorted in ascending order with respect * to sys_id for subsequent binary search in get_arm64_ftr_reg() * to work correctly.
*/
BUG_ON(arm64_ftr_regs[i].sys_id <= arm64_ftr_regs[i - 1].sys_id);
}
}
/* * Initialise the CPU feature register from Boot CPU values. * Also initiliases the strict_mask for the register. * Any bits that are not covered by an arm64_ftr_bits entry are considered * RES0 for the system-wide value, and must strictly match.
*/ staticvoid init_cpu_ftr_reg(u32 sys_reg, u64 new)
{
u64 val = 0;
u64 strict_mask = ~0x0ULL;
u64 user_mask = 0;
u64 valid_mask = 0;
/* * If we don't have AArch32 at EL1, then relax the strictness of * EL1-dependent register fields to avoid spurious sanity check fails.
*/ if (!id_aa64pfr0_32bit_el1(pfr0)) {
relax_cpu_ftr_reg(SYS_ID_ISAR4_EL1, ID_ISAR4_EL1_SMC_SHIFT);
relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Virt_frac_SHIFT);
relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Sec_frac_SHIFT);
relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Virtualization_SHIFT);
relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Security_SHIFT);
relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_ProgMod_SHIFT);
}
/* * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and * ACTLR formats could differ across CPUs and therefore would have to * be trapped for virtualization anyway.
*/
taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu,
info->reg_id_mmfr0, boot->reg_id_mmfr0);
taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu,
info->reg_id_mmfr1, boot->reg_id_mmfr1);
taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu,
info->reg_id_mmfr2, boot->reg_id_mmfr2);
taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu,
info->reg_id_mmfr3, boot->reg_id_mmfr3);
taint |= check_update_ftr_reg(SYS_ID_MMFR4_EL1, cpu,
info->reg_id_mmfr4, boot->reg_id_mmfr4);
taint |= check_update_ftr_reg(SYS_ID_MMFR5_EL1, cpu,
info->reg_id_mmfr5, boot->reg_id_mmfr5);
taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu,
info->reg_id_pfr0, boot->reg_id_pfr0);
taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu,
info->reg_id_pfr1, boot->reg_id_pfr1);
taint |= check_update_ftr_reg(SYS_ID_PFR2_EL1, cpu,
info->reg_id_pfr2, boot->reg_id_pfr2);
taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu,
info->reg_mvfr0, boot->reg_mvfr0);
taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu,
info->reg_mvfr1, boot->reg_mvfr1);
taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu,
info->reg_mvfr2, boot->reg_mvfr2);
return taint;
}
/* * Update system wide CPU feature registers with the values from a * non-boot CPU. Also performs SANITY checks to make sure that there * aren't any insane variations from that of the boot CPU.
*/ void update_cpu_features(int cpu, struct cpuinfo_arm64 *info, struct cpuinfo_arm64 *boot)
{ int taint = 0;
/* * The kernel can handle differing I-cache policies, but otherwise * caches should look identical. Userspace JITs will make use of * *minLine.
*/
taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu,
info->reg_ctr, boot->reg_ctr);
/* * Userspace may perform DC ZVA instructions. Mismatched block sizes * could result in too much or too little memory being zeroed if a * process is preempted and migrated between CPUs.
*/
taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu,
info->reg_dczid, boot->reg_dczid);
/* If different, timekeeping will be broken (especially with KVM) */
taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu,
info->reg_cntfrq, boot->reg_cntfrq);
/* * The kernel uses self-hosted debug features and expects CPUs to * support identical debug features. We presently need CTX_CMPs, WRPs, * and BRPs to be identical. * ID_AA64DFR1 is currently RES0.
*/
taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu,
info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0);
taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu,
info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1); /* * Even in big.LITTLE, processors should be identical instruction-set * wise.
*/
taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu,
info->reg_id_aa64isar0, boot->reg_id_aa64isar0);
taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu,
info->reg_id_aa64isar1, boot->reg_id_aa64isar1);
taint |= check_update_ftr_reg(SYS_ID_AA64ISAR2_EL1, cpu,
info->reg_id_aa64isar2, boot->reg_id_aa64isar2);
taint |= check_update_ftr_reg(SYS_ID_AA64ISAR3_EL1, cpu,
info->reg_id_aa64isar3, boot->reg_id_aa64isar3);
/* * Differing PARange support is fine as long as all peripherals and * memory are mapped within the minimum PARange of all CPUs. * Linux should not care about secure memory.
*/
taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu,
info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0);
taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu,
info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1);
taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu,
info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2);
taint |= check_update_ftr_reg(SYS_ID_AA64MMFR3_EL1, cpu,
info->reg_id_aa64mmfr3, boot->reg_id_aa64mmfr3);
taint |= check_update_ftr_reg(SYS_ID_AA64MMFR4_EL1, cpu,
info->reg_id_aa64mmfr4, boot->reg_id_aa64mmfr4);
/* * The kernel uses the LDGM/STGM instructions and the number of tags * they read/write depends on the GMID_EL1.BS field. Check that the * value is the same on all CPUs.
*/ if (IS_ENABLED(CONFIG_ARM64_MTE) &&
id_aa64pfr1_mte(info->reg_id_aa64pfr1)) {
taint |= check_update_ftr_reg(SYS_GMID_EL1, cpu,
info->reg_gmid, boot->reg_gmid);
}
/* * If we don't have AArch32 at all then skip the checks entirely * as the register values may be UNKNOWN and we're not going to be * using them for anything. * * This relies on a sanitised view of the AArch64 ID registers * (e.g. SYS_ID_AA64PFR0_EL1), so we call it last.
*/ if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
lazy_init_32bit_cpu_features(info, boot);
taint |= update_32bit_cpu_features(cpu, &info->aarch32,
&boot->aarch32);
}
/* * Mismatched CPU features are a recipe for disaster. Don't even * pretend to support them.
*/ if (taint) {
pr_warn_once("Unsupported CPU feature variation detected.\n");
add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
}
}
if (!regp) return0; return regp->sys_val;
}
EXPORT_SYMBOL_GPL(read_sanitised_ftr_reg);
#define read_sysreg_case(r) \ case r: val = read_sysreg_s(r); break;
/* * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated. * Read the system register on the current CPU
*/
u64 __read_sysreg_by_encoding(u32 sys_id)
{ struct arm64_ftr_reg *regp;
u64 val;
staticvoid cpu_emulate_effective_ctr(conststruct arm64_cpu_capabilities *__unused)
{ /* * If the CPU exposes raw CTR_EL0.IDC = 0, while effectively * CTR_EL0.IDC = 1 (from CLIDR values), we need to trap accesses * to the CTR_EL0 on this CPU and emulate it with the real/safe * value.
*/ if (!(read_cpuid_cachetype() & BIT(CTR_EL0_IDC_SHIFT)))
sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0);
}
staticbool has_cache_dic(conststruct arm64_cpu_capabilities *entry, int scope)
{
u64 ctr;
staticbool __maybe_unused
has_useable_cnp(conststruct arm64_cpu_capabilities *entry, int scope)
{ /* * Kdump isn't guaranteed to power-off all secondary CPUs, CNP * may share TLB entries with a CPU stuck in the crashed * kernel.
*/ if (is_kdump_kernel()) returnfalse;
if (cpus_have_cap(ARM64_WORKAROUND_NVIDIA_CARMEL_CNP)) returnfalse;
return has_cpuid_feature(entry, scope);
}
staticbool __meltdown_safe = true; staticint __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */
staticbool unmap_kernel_at_el0(conststruct arm64_cpu_capabilities *entry, int scope)
{ /* List of CPUs that are not vulnerable and don't need KPTI */ staticconststruct midr_range kpti_safe_list[] = {
MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53),
MIDR_ALL_VERSIONS(MIDR_CORTEX_A35),
MIDR_ALL_VERSIONS(MIDR_CORTEX_A53),
MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
MIDR_ALL_VERSIONS(MIDR_HISI_TSV110),
MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL),
MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_GOLD),
MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_SILVER),
MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_3XX_SILVER),
MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_SILVER),
{ /* sentinel */ }
}; charconst *str = "kpti command line option"; bool meltdown_safe;
/* Defer to CPU feature registers */ if (has_cpuid_feature(entry, scope))
meltdown_safe = true;
if (!meltdown_safe)
__meltdown_safe = false;
/* * For reasons that aren't entirely clear, enabling KPTI on Cavium * ThunderX leads to apparent I-cache corruption of kernel text, which * ends as well as you might imagine. Don't even try. We cannot rely * on the cpus_have_*cap() helpers here to detect the CPU erratum * because cpucap detection order may change. However, since we know * affected CPUs are always in a homogeneous configuration, it is * safe to rely on this_cpu_has_cap() here.
*/ if (this_cpu_has_cap(ARM64_WORKAROUND_CAVIUM_27456)) {
str = "ARM64_WORKAROUND_CAVIUM_27456";
__kpti_forced = -1;
}
/* Useful for KASLR robustness */ if (kaslr_enabled() && kaslr_requires_kpti()) { if (!__kpti_forced) {
str = "KASLR";
__kpti_forced = 1;
}
}
staticbool has_nv1(conststruct arm64_cpu_capabilities *entry, int scope)
{ /* * Although the Apple M2 family appears to support NV1, the * PTW barfs on the nVHE EL2 S1 page table format. Pretend * that it doesn't support NV1 at all.
*/ staticconststruct midr_range nv1_ni_list[] = {
MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD),
MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE),
MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_PRO),
MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_PRO),
MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_MAX),
MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_MAX),
{}
};
/* * PMUVer follows the standard ID scheme for an unsigned field with the * exception of 0xF (IMP_DEF) which is treated specially and implies * FEAT_PMUv3 is not implemented. * * See DDI0487L.a D24.1.3.2 for more details.
*/
pmuver = cpuid_feature_extract_unsigned_field(dfr0,
ID_AA64DFR0_EL1_PMUVer_SHIFT); if (pmuver == ID_AA64DFR0_EL1_PMUVer_IMP_DEF) returnfalse;
int cpu = smp_processor_id(); int levels = CONFIG_PGTABLE_LEVELS; int order = order_base_2(levels);
u64 kpti_ng_temp_pgd_pa = 0;
pgd_t *kpti_ng_temp_pgd;
u64 alloc = 0;
// // Create a minimal page table hierarchy that permits us to map // the swapper page tables temporarily as we traverse them. // // The physical pages are laid out as follows: // // +--------+-/-------+-/------ +-/------ +-\\\--------+ // : PTE[] : | PMD[] : | PUD[] : | P4D[] : ||| PGD[] : // +--------+-\-------+-\------ +-\------ +-///--------+ // ^ // The first page is mapped into this hierarchy at a PMD_SHIFT // aligned virtual address, so that we can manipulate the PTE // level entries while the mapping is active. The first entry // covers the PTE[] page itself, the remaining entries are free // to be used as a ad-hoc fixmap. //
create_kpti_ng_temp_pgd(kpti_ng_temp_pgd, __pa(alloc),
KPTI_NG_TEMP_VA, PAGE_SIZE, PAGE_KERNEL,
kpti_ng_pgd_alloc, 0);
}
if (!cpu) {
free_pages(alloc, order);
arm64_use_ng_mappings = true;
}
return0;
}
staticvoid __init kpti_install_ng_mappings(void)
{ /* Check whether KPTI is going to be used */ if (!arm64_kernel_unmapped_at_el0()) return;
/* * We don't need to rewrite the page-tables if either we've done * it already or we have KASLR enabled and therefore have not * created any global mappings at all.
*/ if (arm64_use_ng_mappings) return;
staticbool has_hw_dbm(conststruct arm64_cpu_capabilities *cap, int __unused)
{ /* * DBM is a non-conflicting feature. i.e, the kernel can safely * run a mix of CPUs with and without the feature. So, we * unconditionally enable the capability to allow any late CPU * to use the feature. We only enable the control bits on the * CPU, if it is supported.
*/
returntrue;
}
#endif
#ifdef CONFIG_ARM64_AMU_EXTN
/* * The "amu_cpus" cpumask only signals that the CPU implementation for the * flagged CPUs supports the Activity Monitors Unit (AMU) but does not provide * information regarding all the events that it supports. When a CPU bit is * set in the cpumask, the user of this feature can only rely on the presence * of the 4 fixed counters for that CPU. But this does not guarantee that the * counters are enabled or access to these counters is enabled by code * executed at higher exception levels (firmware).
*/ staticstruct cpumask amu_cpus __read_mostly;
/* 0 reference values signal broken/disabled counters */ if (!this_cpu_has_cap(ARM64_WORKAROUND_2457168))
update_freq_counters_refs();
}
}
staticbool has_amu(conststruct arm64_cpu_capabilities *cap, int __unused)
{ /* * The AMU extension is a non-conflicting feature: the kernel can * safely run a mix of CPUs with and without support for the * activity monitors extension. Therefore, unconditionally enable * the capability to allow any late CPU to use the feature. * * With this feature unconditionally enabled, the cpu_enable * function will be called for all CPUs that match the criteria, * including secondary and hotplugged, marking this feature as * present on that respective CPU. The enable function will also * print a detection message.
*/
returntrue;
} #else int get_cpu_with_amu_feat(void)
{ return nr_cpu_ids;
} #endif
staticbool runs_at_el2(conststruct arm64_cpu_capabilities *entry, int __unused)
{ return is_kernel_in_hyp_mode();
}
staticvoid cpu_copy_el2regs(conststruct arm64_cpu_capabilities *__unused)
{ /* * Copy register values that aren't redirected by hardware. * * Before code patching, we only set tpidr_el1, all CPUs need to copy * this value to tpidr_el2 before we patch the code. Once we've done * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to * do anything here.
*/ if (!alternative_is_applied(ARM64_HAS_VIRT_HOST_EXTN))
write_sysreg(read_sysreg(tpidr_el1), tpidr_el2);
}
staticbool has_nested_virt_support(conststruct arm64_cpu_capabilities *cap, int scope)
{ if (kvm_get_mode() != KVM_MODE_NV) returnfalse;
if (!cpucap_multi_entry_cap_matches(cap, scope)) {
pr_warn("unavailable: %s\n", cap->desc); returnfalse;
}
returntrue;
}
staticbool hvhe_possible(conststruct arm64_cpu_capabilities *entry, int __unused)
{ return arm64_test_sw_feature_override(ARM64_SW_FEATURE_OVERRIDE_HVHE);
}
staticbool has_bbml2_noabort(conststruct arm64_cpu_capabilities *caps, int scope)
{ /* * We want to allow usage of BBML2 in as wide a range of kernel contexts * as possible. This list is therefore an allow-list of known-good * implementations that both support BBML2 and additionally, fulfill the * extra constraint of never generating TLB conflict aborts when using * the relaxed BBML2 semantics (such aborts make use of BBML2 in certain * kernel contexts difficult to prove safe against recursive aborts). * * Note that implementations can only be considered "known-good" if their * implementors attest to the fact that the implementation never raises * TLB conflict aborts for BBML2 mapping granularity changes.
*/ staticconststruct midr_range supports_bbml2_noabort_list[] = {
MIDR_REV_RANGE(MIDR_CORTEX_X4, 0, 3, 0xf),
MIDR_REV_RANGE(MIDR_NEOVERSE_V3, 0, 2, 0xf),
{}
};
/* Does our cpu guarantee to never raise TLB conflict aborts? */ if (!is_midr_in_range_list(supports_bbml2_noabort_list)) returnfalse;
/* * We currently ignore the ID_AA64MMFR2_EL1 register, and only care * about whether the MIDR check passes.
*/
returntrue;
}
#ifdef CONFIG_ARM64_PAN staticvoid cpu_enable_pan(conststruct arm64_cpu_capabilities *__unused)
{ /* * We modify PSTATE. This won't work from irq context as the PSTATE * is discarded once we return from the exception.
*/
WARN_ON_ONCE(in_interrupt());
#ifdef CONFIG_ARM64_PTR_AUTH staticbool has_address_auth_cpucap(conststruct arm64_cpu_capabilities *entry, int scope)
{ int boot_val, sec_val;
/* We don't expect to be called with SCOPE_SYSTEM */
WARN_ON(scope == SCOPE_SYSTEM); /* * The ptr-auth feature levels are not intercompatible with lower * levels. Hence we must match ptr-auth feature level of the secondary * CPUs with that of the boot CPU. The level of boot cpu is fetched * from the sanitised register whereas direct register read is done for * the secondary CPUs. * The sanitised feature state is guaranteed to match that of the * boot CPU as a mismatched secondary CPU is parked before it gets * a chance to update the state, with the capability.
*/
boot_val = cpuid_feature_extract_field(read_sanitised_ftr_reg(entry->sys_reg),
entry->field_pos, entry->sign); if (scope & SCOPE_BOOT_CPU) return boot_val >= entry->min_field_value; /* Now check for the secondary CPUs with SCOPE_LOCAL_CPU scope */
sec_val = cpuid_feature_extract_field(__read_sysreg_by_encoding(entry->sys_reg),
entry->field_pos, entry->sign); return (sec_val >= entry->min_field_value) && (sec_val == boot_val);
}
staticbool has_address_auth_metacap(conststruct arm64_cpu_capabilities *entry, int scope)
{ bool api = has_address_auth_cpucap(cpucap_ptrs[ARM64_HAS_ADDRESS_AUTH_IMP_DEF], scope); bool apa = has_address_auth_cpucap(cpucap_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA5], scope); bool apa3 = has_address_auth_cpucap(cpucap_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA3], scope);
#ifdef CONFIG_ARM64_PSEUDO_NMI staticbool can_use_gic_priorities(conststruct arm64_cpu_capabilities *entry, int scope)
{ /* * ARM64_HAS_GICV3_CPUIF has a lower index, and is a boot CPU * feature, so will be detected earlier.
*/
BUILD_BUG_ON(ARM64_HAS_GIC_PRIO_MASKING <= ARM64_HAS_GICV3_CPUIF); if (!cpus_have_cap(ARM64_HAS_GICV3_CPUIF)) returnfalse;
return enable_pseudo_nmi;
}
staticbool has_gic_prio_relaxed_sync(conststruct arm64_cpu_capabilities *entry, int scope)
{ /* * If we're not using priority masking then we won't be poking PMR_EL1, * and there's no need to relax synchronization of writes to it, and * ICC_CTLR_EL1 might not be accessible and we must avoid reads from * that. * * ARM64_HAS_GIC_PRIO_MASKING has a lower index, and is a boot CPU * feature, so will be detected earlier.
*/
BUILD_BUG_ON(ARM64_HAS_GIC_PRIO_RELAXED_SYNC <= ARM64_HAS_GIC_PRIO_MASKING); if (!cpus_have_cap(ARM64_HAS_GIC_PRIO_MASKING)) returnfalse;
/* * When Priority Mask Hint Enable (PMHE) == 0b0, PMR is not used as a * hint for interrupt distribution, a DSB is not necessary when * unmasking IRQs via PMR, and we can relax the barrier to a NOP. * * Linux itself doesn't use 1:N distribution, so has no need to * set PMHE. The only reason to have it set is if EL3 requires it * (and we can't change it).
*/ return (gic_read_ctlr() & ICC_CTLR_EL1_PMHE_MASK) == 0;
} #endif
#ifdef CONFIG_ARM64_BTI staticvoid bti_enable(conststruct arm64_cpu_capabilities *__unused)
{ /* * Use of X16/X17 for tail-calls and trampolines that jump to * function entry points using BR is a requirement for * marking binaries with GNU_PROPERTY_AARCH64_FEATURE_1_BTI. * So, be strict and forbid other BRs using other registers to * jump onto a PACIxSP instruction:
*/
sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_BT0 | SCTLR_EL1_BT1);
isb();
} #endif/* CONFIG_ARM64_BTI */
/* * Clear the tags in the zero page. This needs to be done via the * linear map which has the Tagged attribute. Since this page is * always mapped as pte_special(), set_pte_at() will not attempt to * clear the tags or set PG_mte_tagged.
*/ if (!cleared_zero_page) {
cleared_zero_page = true;
mte_clear_page_tags(lm_alias(empty_zero_page));
}
/* Internal helper functions to match cpu capability type */ staticbool
cpucap_late_cpu_optional(conststruct arm64_cpu_capabilities *cap)
{ return !!(cap->type & ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU);
}
staticbool
test_has_mpam(conststruct arm64_cpu_capabilities *entry, int scope)
{ if (!has_cpuid_feature(entry, scope)) returnfalse;
/* Check firmware actually enabled MPAM on this cpu. */ return (read_sysreg_s(SYS_MPAM1_EL1) & MPAM1_EL1_MPAMEN);
}
staticvoid
cpu_enable_mpam(conststruct arm64_cpu_capabilities *entry)
{ /* * Access by the kernel (at EL1) should use the reserved PARTID * which is configured unrestricted. This avoids priority-inversion * where latency sensitive tasks have to wait for a task that has * been throttled to release the lock.
*/
write_sysreg_s(0, SYS_MPAM1_EL1);
}
#ifdef CONFIG_COMPAT staticbool compat_has_neon(conststruct arm64_cpu_capabilities *cap, int scope)
{ /* * Check that all of MVFR1_EL1.{SIMDSP, SIMDInt, SIMDLS} are available, * in line with that of arm32 as in vfp_init(). We make sure that the * check is future proof, by making sure value is non-zero.
*/
u32 mvfr1;
staticvoid setup_elf_hwcaps(conststruct arm64_cpu_capabilities *hwcaps)
{ /* We support emulation of accesses to CPU ID feature registers */
cpu_set_named_feature(CPUID); for (; hwcaps->matches; hwcaps++) if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps)))
cap_set_elf_hwcap(hwcaps);
}
staticvoid update_cpu_capabilities(u16 scope_mask)
{ int i; conststruct arm64_cpu_capabilities *caps;
scope_mask &= ARM64_CPUCAP_SCOPE_MASK; for (i = 0; i < ARM64_NCAPS; i++) { bool match_all = false; bool caps_set = false; bool boot_cpu = false;
caps = cpucap_ptrs[i]; if (!caps || !(caps->type & scope_mask)) continue;
/* * Unless it's a match-all CPUs feature, avoid probing if * already detected.
*/ if (!match_all && caps_set) continue;
/* * A match-all CPUs capability is only set when probing the * boot CPU. It may be cleared subsequently if not detected on * secondary ones.
*/ if (match_all && !caps_set && !boot_cpu) continue;
if (!caps->matches(caps, cpucap_default_scope(caps))) { if (match_all)
__clear_bit(caps->capability, system_cpucaps); continue;
}
/* * Match-all CPUs capabilities are logged later when the * system capabilities are finalised.
*/ if (!match_all && caps->desc && !caps->cpus)
pr_info("detected: %s\n", caps->desc);
__set_bit(caps->capability, system_cpucaps);
if (boot_cpu && (caps->type & SCOPE_BOOT_CPU))
set_bit(caps->capability, boot_cpucaps);
}
}
/* * Enable all the available capabilities on this CPU. The capabilities * with BOOT_CPU scope are handled separately and hence skipped here.
*/ staticint cpu_enable_non_boot_scope_capabilities(void *__unused)
{ int i;
u16 non_boot_scope = SCOPE_ALL & ~SCOPE_BOOT_CPU;
if (cap->cpu_enable)
cap->cpu_enable(cap);
} return0;
}
/* * Run through the enabled capabilities and enable() it on all active * CPUs
*/ staticvoid __init enable_cpu_capabilities(u16 scope_mask)
{ int i; conststruct arm64_cpu_capabilities *caps; bool boot_scope;
for (i = 0; i < ARM64_NCAPS; i++) {
caps = cpucap_ptrs[i]; if (!caps || !(caps->type & scope_mask) ||
!cpus_have_cap(caps->capability)) continue;
if (boot_scope && caps->cpu_enable) /* * Capabilities with SCOPE_BOOT_CPU scope are finalised * before any secondary CPU boots. Thus, each secondary * will enable the capability as appropriate via * check_local_cpu_capabilities(). The only exception is * the boot CPU, for which the capability must be * enabled here. This approach avoids costly * stop_machine() calls for this case.
*/
caps->cpu_enable(caps);
}
/* * For all non-boot scope capabilities, use stop_machine() * as it schedules the work allowing us to modify PSTATE, * instead of on_each_cpu() which uses an IPI, giving us a * PSTATE that disappears when we return.
*/ if (!boot_scope)
stop_machine(cpu_enable_non_boot_scope_capabilities,
NULL, cpu_online_mask);
}
/* * Run through the list of capabilities to check for conflicts. * If the system has already detected a capability, take necessary * action on this CPU.
*/ staticvoid verify_local_cpu_caps(u16 scope_mask)
{ int i; bool cpu_has_cap, system_has_cap; conststruct arm64_cpu_capabilities *caps;
scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
for (i = 0; i < ARM64_NCAPS; i++) {
caps = cpucap_ptrs[i]; if (!caps || !(caps->type & scope_mask)) continue;
if (system_has_cap) { /* * Check if the new CPU misses an advertised feature, * which is not safe to miss.
*/ if (!cpu_has_cap && !cpucap_late_cpu_optional(caps)) break; /* * We have to issue cpu_enable() irrespective of * whether the CPU has it or not, as it is enabeld * system wide. It is upto the call back to take * appropriate action on this CPU.
*/ if (caps->cpu_enable)
caps->cpu_enable(caps);
} else { /* * Check if the CPU has this capability if it isn't * safe to have when the system doesn't.
*/ if (cpu_has_cap && !cpucap_late_cpu_permitted(caps)) break;
}
}
if (i < ARM64_NCAPS) {
pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n",
smp_processor_id(), caps->capability,
caps->desc, system_has_cap, cpu_has_cap);
if (cpucap_panic_on_conflict(caps))
cpu_panic_kernel(); else
cpu_die_early();
}
}
/* * Check for CPU features that are used in early boot * based on the Boot CPU value.
*/ staticvoid check_early_cpu_features(void)
{
verify_cpu_asid_bits();
/* * Run through the enabled system capabilities and enable() it on this CPU. * The capabilities were decided based on the available CPUs at the boot time. * Any new CPU should match the system wide status of the capability. If the * new CPU doesn't have a capability which the system now has enabled, we * cannot do anything to fix it up and could cause unexpected failures. So * we park the CPU.
*/ staticvoid verify_local_cpu_capabilities(void)
{ /* * The capabilities with SCOPE_BOOT_CPU are checked from * check_early_cpu_features(), as they need to be verified * on all secondary CPUs.
*/
verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU);
verify_local_elf_hwcaps();
if (system_supports_sve())
verify_sve_features();
if (system_supports_sme())
verify_sme_features();
if (is_hyp_mode_available())
verify_hyp_capabilities();
if (system_supports_mpam())
verify_mpam_capabilities();
}
void check_local_cpu_capabilities(void)
{ /* * All secondary CPUs should conform to the early CPU features * in use by the kernel based on boot CPU.
*/
check_early_cpu_features();
/* * If we haven't finalised the system capabilities, this CPU gets * a chance to update the errata work arounds and local features. * Otherwise, this CPU should verify that it has all the system * advertised capabilities.
*/ if (!system_capabilities_finalized())
update_cpu_capabilities(SCOPE_LOCAL_CPU); else
verify_local_cpu_capabilities();
}
bool this_cpu_has_cap(unsignedint n)
{ if (!WARN_ON(preemptible()) && n < ARM64_NCAPS) { conststruct arm64_cpu_capabilities *cap = cpucap_ptrs[n];
if (cap) return cap->matches(cap, SCOPE_LOCAL_CPU);
}
/* * This helper function is used in a narrow window when, * - The system wide safe registers are set with all the SMP CPUs and, * - The SYSTEM_FEATURE system_cpucaps may not have been set.
*/ staticbool __maybe_unused __system_matches_cap(unsignedint n)
{ if (n < ARM64_NCAPS) { conststruct arm64_cpu_capabilities *cap = cpucap_ptrs[n];
if (cap) return cap->matches(cap, SCOPE_SYSTEM);
} returnfalse;
}
unsignedlong cpu_get_elf_hwcap(void)
{ /* * We currently only populate the first 32 bits of AT_HWCAP. Please * note that for userspace compatibility we guarantee that bits 62 * and 63 will always be returned as 0.
*/ return elf_hwcap[0];
}
staticvoid __init setup_boot_cpu_capabilities(void)
{
kvm_arm_target_impl_cpu_init(); /* * The boot CPU's feature register values have been recorded. Detect * boot cpucaps and local cpucaps for the boot CPU, then enable and * patch alternatives for the available boot cpucaps.
*/
update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU);
enable_cpu_capabilities(SCOPE_BOOT_CPU);
apply_boot_alternatives();
}
void __init setup_boot_cpu_features(void)
{ /* * Initialize the indirect array of CPU capabilities pointers before we * handle the boot CPU.
*/
init_cpucap_indirect_list();
/* * Detect broken pseudo-NMI. Must be called _before_ the call to * setup_boot_cpu_capabilities() since it interacts with * can_use_gic_priorities().
*/
detect_system_supports_pseudo_nmi();
setup_boot_cpu_capabilities();
}
staticvoid __init setup_system_capabilities(void)
{ /* * The system-wide safe feature register values have been finalized. * Detect, enable, and patch alternatives for the available system * cpucaps.
*/
update_cpu_capabilities(SCOPE_SYSTEM);
enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU);
apply_alternatives_all();
for (int i = 0; i < ARM64_NCAPS; i++) { conststruct arm64_cpu_capabilities *caps = cpucap_ptrs[i];
if (!caps || !caps->desc) continue;
/* * Log any cpucaps with a cpumask as these aren't logged by * update_cpu_capabilities().
*/ if (caps->cpus && cpumask_any(caps->cpus) < nr_cpu_ids)
pr_info("detected: %s on CPU%*pbl\n",
caps->desc, cpumask_pr_args(caps->cpus));
/* * TTBR0 PAN doesn't have its own cpucap, so log it manually.
*/ if (system_uses_ttbr0_pan())
pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n");
}
if (system_supports_32bit_el0()) {
setup_elf_hwcaps(compat_elf_hwcaps);
elf_hwcap_fixup();
}
minsigstksz_setup();
}
staticint enable_mismatched_32bit_el0(unsignedint cpu)
{ /* * The first 32-bit-capable CPU we detected and so can no longer * be offlined by userspace. -1 indicates we haven't yet onlined * a 32-bit-capable CPU.
*/ staticint lucky_winner = -1;
if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) { if (!housekeeping_cpu(cpu, HK_TYPE_TICK))
pr_info("Treating adaptive-ticks CPU %u as 64-bit only\n", cpu); else
cpu_32bit = true;
}
if (cpu_32bit) {
cpumask_set_cpu(cpu, cpu_32bit_el0_mask);
static_branch_enable_cpuslocked(&arm64_mismatched_32bit_el0);
}
if (cpumask_test_cpu(0, cpu_32bit_el0_mask) == cpu_32bit) return0;
if (lucky_winner >= 0) return0;
/* * We've detected a mismatch. We need to keep one of our CPUs with * 32-bit EL0 online so that is_cpu_allowed() doesn't end up rejecting * every CPU in the system for a 32-bit task.
*/
lucky_winner = cpu_32bit ? cpu : cpumask_any_and(cpu_32bit_el0_mask,
cpu_active_mask);
get_cpu_device(lucky_winner)->offline_disabled = true;
setup_elf_hwcaps(compat_elf_hwcaps);
elf_hwcap_fixup();
pr_info("Asymmetric 32-bit EL0 support detected on CPU %u; CPU hot-unplug disabled on CPU %u\n",
cpu, lucky_winner); return0;
}
staticint __init init_32bit_el0_mask(void)
{ if (!allow_mismatched_32bit_el0) return0;
if (!zalloc_cpumask_var(&cpu_32bit_el0_mask, GFP_KERNEL)) return -ENOMEM;
/* * We emulate only the following system register space. * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 2 - 7] * See Table C5-6 System instruction encodings for System register accesses, * ARMv8 ARM(ARM DDI 0487A.f) for more details.
*/ staticinlinebool __attribute_const__ is_emulated(u32 id)
{ return (sys_reg_Op0(id) == 0x3 &&
sys_reg_CRn(id) == 0x0 &&
sys_reg_Op1(id) == 0x0 &&
(sys_reg_CRm(id) == 0 ||
((sys_reg_CRm(id) >= 2) && (sys_reg_CRm(id) <= 7))));
}
/* * With CRm == 0, reg should be one of : * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1.
*/ staticinlineint emulate_id_reg(u32 id, u64 *valp)
{ switch (id) { case SYS_MIDR_EL1:
*valp = read_cpuid_id(); break; case SYS_MPIDR_EL1:
*valp = SYS_MPIDR_SAFE_VAL; break; case SYS_REVIDR_EL1: /* IMPLEMENTATION DEFINED values are emulated with 0 */
*valp = 0; break; default: return -EINVAL;
}
if (sys_reg_CRm(id) == 0) return emulate_id_reg(id, valp);
regp = get_arm64_ftr_reg_nowarn(id); if (regp)
*valp = arm64_ftr_reg_user_value(regp); else /* * The untracked registers are either IMPLEMENTATION DEFINED * (e.g, ID_AFR0_EL1) or reserved RAZ.
*/
*valp = 0; return0;
}
int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt)
{ int rc;
u64 val;
if (compat_user_mode(regs) || !aarch64_insn_is_mrs(insn)) returnfalse;
/* * sys_reg values are defined as used in mrs/msr instruction. * shift the imm value to get the encoding.
*/
sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5;
rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn); return do_emulate_mrs(regs, sys_reg, rt) == 0;
}
enum mitigation_state arm64_get_meltdown_state(void)
{ if (__meltdown_safe) return SPECTRE_UNAFFECTED;
if (arm64_kernel_unmapped_at_el0()) return SPECTRE_MITIGATED;
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