SSL sc8180x.dtsi   Sprache: unbekannt

// SPDX-License-Identifier: BSD-3-Clause
/*
 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
 * Copyright (c) 2020-2023, Linaro Limited
 */

#include <dt-bindings/clock/qcom,dispcc-sm8250.h>
#include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
#include <dt-bindings/clock/qcom,gcc-sc8180x.h>
#include <dt-bindings/clock/qcom,gpucc-sm8150.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,sc8180x-camcc.h>
#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interconnect/qcom,osm-l3.h>
#include <dt-bindings/interconnect/qcom,sc8180x.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/phy/phy-qcom-qmp.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
#include <dt-bindings/thermal/thermal.h>

/ {
 interrupt-parent = <&intc>;

 #address-cells = <2>;
 #size-cells = <2>;

 clocks {
  xo_board_clk: xo-board {
   compatible = "fixed-clock";
   #clock-cells = <0>;
   clock-frequency = <38400000>;
  };

  sleep_clk: sleep-clk {
   compatible = "fixed-clock";
   #clock-cells = <0>;
   clock-frequency = <32764>;
   clock-output-names = "sleep_clk";
  };
 };

 cpus {
  #address-cells = <2>;
  #size-cells = <0>;

  cpu0: cpu@0 {
   device_type = "cpu";
   compatible = "qcom,kryo485";
   reg = <0x0 0x0>;
   enable-method = "psci";
   capacity-dmips-mhz = <602>;
   next-level-cache = <&l2_0>;
   qcom,freq-domain = <&cpufreq_hw 0>;
   operating-points-v2 = <&cpu0_opp_table>;
   interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>,
     <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
   power-domains = <&cpu_pd0>;
   power-domain-names = "psci";
   #cooling-cells = <2>;
   clocks = <&cpufreq_hw 0>;

   l2_0: l2-cache {
    compatible = "cache";
    cache-level = <2>;
    cache-unified;
    next-level-cache = <&l3_0>;
    l3_0: l3-cache {
     compatible = "cache";
     cache-level = <3>;
     cache-unified;
    };
   };
  };

  cpu1: cpu@100 {
   device_type = "cpu";
   compatible = "qcom,kryo485";
   reg = <0x0 0x100>;
   enable-method = "psci";
   capacity-dmips-mhz = <602>;
   next-level-cache = <&l2_100>;
   qcom,freq-domain = <&cpufreq_hw 0>;
   operating-points-v2 = <&cpu0_opp_table>;
   interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>,
     <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
   power-domains = <&cpu_pd1>;
   power-domain-names = "psci";
   #cooling-cells = <2>;
   clocks = <&cpufreq_hw 0>;

   l2_100: l2-cache {
    compatible = "cache";
    cache-level = <2>;
    cache-unified;
    next-level-cache = <&l3_0>;
   };

  };

  cpu2: cpu@200 {
   device_type = "cpu";
   compatible = "qcom,kryo485";
   reg = <0x0 0x200>;
   enable-method = "psci";
   capacity-dmips-mhz = <602>;
   next-level-cache = <&l2_200>;
   qcom,freq-domain = <&cpufreq_hw 0>;
   operating-points-v2 = <&cpu0_opp_table>;
   interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>,
     <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
   power-domains = <&cpu_pd2>;
   power-domain-names = "psci";
   #cooling-cells = <2>;
   clocks = <&cpufreq_hw 0>;

   l2_200: l2-cache {
    compatible = "cache";
    cache-level = <2>;
    cache-unified;
    next-level-cache = <&l3_0>;
   };
  };

  cpu3: cpu@300 {
   device_type = "cpu";
   compatible = "qcom,kryo485";
   reg = <0x0 0x300>;
   enable-method = "psci";
   capacity-dmips-mhz = <602>;
   next-level-cache = <&l2_300>;
   qcom,freq-domain = <&cpufreq_hw 0>;
   operating-points-v2 = <&cpu0_opp_table>;
   interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>,
     <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
   power-domains = <&cpu_pd3>;
   power-domain-names = "psci";
   #cooling-cells = <2>;
   clocks = <&cpufreq_hw 0>;

   l2_300: l2-cache {
    compatible = "cache";
    cache-unified;
    cache-level = <2>;
    next-level-cache = <&l3_0>;
   };
  };

  cpu4: cpu@400 {
   device_type = "cpu";
   compatible = "qcom,kryo485";
   reg = <0x0 0x400>;
   enable-method = "psci";
   capacity-dmips-mhz = <1024>;
   next-level-cache = <&l2_400>;
   qcom,freq-domain = <&cpufreq_hw 1>;
   operating-points-v2 = <&cpu4_opp_table>;
   interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>,
     <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
   power-domains = <&cpu_pd4>;
   power-domain-names = "psci";
   #cooling-cells = <2>;
   clocks = <&cpufreq_hw 1>;

   l2_400: l2-cache {
    compatible = "cache";
    cache-unified;
    cache-level = <2>;
    next-level-cache = <&l3_0>;
   };
  };

  cpu5: cpu@500 {
   device_type = "cpu";
   compatible = "qcom,kryo485";
   reg = <0x0 0x500>;
   enable-method = "psci";
   capacity-dmips-mhz = <1024>;
   next-level-cache = <&l2_500>;
   qcom,freq-domain = <&cpufreq_hw 1>;
   operating-points-v2 = <&cpu4_opp_table>;
   interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>,
     <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
   power-domains = <&cpu_pd5>;
   power-domain-names = "psci";
   #cooling-cells = <2>;
   clocks = <&cpufreq_hw 1>;

   l2_500: l2-cache {
    compatible = "cache";
    cache-unified;
    cache-level = <2>;
    next-level-cache = <&l3_0>;
   };
  };

  cpu6: cpu@600 {
   device_type = "cpu";
   compatible = "qcom,kryo485";
   reg = <0x0 0x600>;
   enable-method = "psci";
   capacity-dmips-mhz = <1024>;
   next-level-cache = <&l2_600>;
   qcom,freq-domain = <&cpufreq_hw 1>;
   operating-points-v2 = <&cpu4_opp_table>;
   interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>,
     <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
   power-domains = <&cpu_pd6>;
   power-domain-names = "psci";
   #cooling-cells = <2>;
   clocks = <&cpufreq_hw 1>;

   l2_600: l2-cache {
    compatible = "cache";
    cache-unified;
    cache-level = <2>;
    next-level-cache = <&l3_0>;
   };
  };

  cpu7: cpu@700 {
   device_type = "cpu";
   compatible = "qcom,kryo485";
   reg = <0x0 0x700>;
   enable-method = "psci";
   capacity-dmips-mhz = <1024>;
   next-level-cache = <&l2_700>;
   qcom,freq-domain = <&cpufreq_hw 1>;
   operating-points-v2 = <&cpu4_opp_table>;
   interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>,
     <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
   power-domains = <&cpu_pd7>;
   power-domain-names = "psci";
   #cooling-cells = <2>;
   clocks = <&cpufreq_hw 1>;

   l2_700: l2-cache {
    compatible = "cache";
    cache-unified;
    cache-level = <2>;
    next-level-cache = <&l3_0>;
   };
  };

  cpu-map {
   cluster0 {
    core0 {
     cpu = <&cpu0>;
    };

    core1 {
     cpu = <&cpu1>;
    };

    core2 {
     cpu = <&cpu2>;
    };

    core3 {
     cpu = <&cpu3>;
    };

    core4 {
     cpu = <&cpu4>;
    };

    core5 {
     cpu = <&cpu5>;
    };

    core6 {
     cpu = <&cpu6>;
    };

    core7 {
     cpu = <&cpu7>;
    };
   };
  };

  idle-states {
   entry-method = "psci";

   little_cpu_sleep_0: cpu-sleep-0-0 {
    compatible = "arm,idle-state";
    arm,psci-suspend-param = <0x40000004>;
    entry-latency-us = <355>;
    exit-latency-us = <909>;
    min-residency-us = <3934>;
    local-timer-stop;
   };

   big_cpu_sleep_0: cpu-sleep-1-0 {
    compatible = "arm,idle-state";
    arm,psci-suspend-param = <0x40000004>;
    entry-latency-us = <2411>;
    exit-latency-us = <1461>;
    min-residency-us = <4488>;
    local-timer-stop;
   };
  };

  domain-idle-states {
   cluster_sleep_apss_off: cluster-sleep-0 {
    compatible = "domain-idle-state";
    arm,psci-suspend-param = <0x41000044>;
    entry-latency-us = <3300>;
    exit-latency-us = <3300>;
    min-residency-us = <6000>;
   };

   cluster_sleep_aoss_sleep: cluster-sleep-1 {
    compatible = "domain-idle-state";
    arm,psci-suspend-param = <0x4100a344>;
    entry-latency-us = <3263>;
    exit-latency-us = <6562>;
    min-residency-us = <9987>;
   };
  };
 };

 cpu0_opp_table: opp-table-cpu0 {
  compatible = "operating-points-v2";
  opp-shared;

  opp-300000000 {
   opp-hz = /bits/ 64 <300000000>;
   opp-peak-kBps = <800000 9600000>;
  };

  opp-422400000 {
   opp-hz = /bits/ 64 <422400000>;
   opp-peak-kBps = <800000 9600000>;
  };

  opp-537600000 {
   opp-hz = /bits/ 64 <537600000>;
   opp-peak-kBps = <800000 12902400>;
  };

  opp-652800000 {
   opp-hz = /bits/ 64 <652800000>;
   opp-peak-kBps = <800000 12902400>;
  };

  opp-768000000 {
   opp-hz = /bits/ 64 <768000000>;
   opp-peak-kBps = <800000 15974400>;
  };

  opp-883200000 {
   opp-hz = /bits/ 64 <883200000>;
   opp-peak-kBps = <1804000 19660800>;
  };

  opp-998400000 {
   opp-hz = /bits/ 64 <998400000>;
   opp-peak-kBps = <1804000 19660800>;
  };

  opp-1113600000 {
   opp-hz = /bits/ 64 <1113600000>;
   opp-peak-kBps = <1804000 22732800>;
  };

  opp-1228800000 {
   opp-hz = /bits/ 64 <1228800000>;
   opp-peak-kBps = <1804000 22732800>;
  };

  opp-1363200000 {
   opp-hz = /bits/ 64 <1363200000>;
   opp-peak-kBps = <2188000 25804800>;
  };

  opp-1478400000 {
   opp-hz = /bits/ 64 <1478400000>;
   opp-peak-kBps = <2188000 31948800>;
  };

  opp-1574400000 {
   opp-hz = /bits/ 64 <1574400000>;
   opp-peak-kBps = <3072000 31948800>;
  };

  opp-1670400000 {
   opp-hz = /bits/ 64 <1670400000>;
   opp-peak-kBps = <3072000 31948800>;
  };

  opp-1766400000 {
   opp-hz = /bits/ 64 <1766400000>;
   opp-peak-kBps = <3072000 31948800>;
  };
 };

 cpu4_opp_table: opp-table-cpu4 {
  compatible = "operating-points-v2";
  opp-shared;

  opp-825600000 {
   opp-hz = /bits/ 64 <825600000>;
   opp-peak-kBps = <1804000 15974400>;
  };

  opp-940800000 {
   opp-hz = /bits/ 64 <940800000>;
   opp-peak-kBps = <2188000 19660800>;
  };

  opp-1056000000 {
   opp-hz = /bits/ 64 <1056000000>;
   opp-peak-kBps = <2188000 22732800>;
  };

  opp-1171200000 {
   opp-hz = /bits/ 64 <1171200000>;
   opp-peak-kBps = <3072000 25804800>;
  };

  opp-1286400000 {
   opp-hz = /bits/ 64 <1286400000>;
   opp-peak-kBps = <3072000 31948800>;
  };

  opp-1420800000 {
   opp-hz = /bits/ 64 <1420800000>;
   opp-peak-kBps = <4068000 31948800>;
  };

  opp-1536000000 {
   opp-hz = /bits/ 64 <1536000000>;
   opp-peak-kBps = <4068000 31948800>;
  };

  opp-1651200000 {
   opp-hz = /bits/ 64 <1651200000>;
   opp-peak-kBps = <4068000 40550400>;
  };

  opp-1766400000 {
   opp-hz = /bits/ 64 <1766400000>;
   opp-peak-kBps = <4068000 40550400>;
  };

  opp-1881600000 {
   opp-hz = /bits/ 64 <1881600000>;
   opp-peak-kBps = <4068000 43008000>;
  };

  opp-1996800000 {
   opp-hz = /bits/ 64 <1996800000>;
   opp-peak-kBps = <6220000 43008000>;
  };

  opp-2131200000 {
   opp-hz = /bits/ 64 <2131200000>;
   opp-peak-kBps = <6220000 49152000>;
  };

  opp-2246400000 {
   opp-hz = /bits/ 64 <2246400000>;
   opp-peak-kBps = <7216000 49152000>;
  };

  opp-2361600000 {
   opp-hz = /bits/ 64 <2361600000>;
   opp-peak-kBps = <8368000 49152000>;
  };

  opp-2457600000 {
   opp-hz = /bits/ 64 <2457600000>;
   opp-peak-kBps = <8368000 51609600>;
  };

  opp-2553600000 {
   opp-hz = /bits/ 64 <2553600000>;
   opp-peak-kBps = <8368000 51609600>;
  };

  opp-2649600000 {
   opp-hz = /bits/ 64 <2649600000>;
   opp-peak-kBps = <8368000 51609600>;
  };

  opp-2745600000 {
   opp-hz = /bits/ 64 <2745600000>;
   opp-peak-kBps = <8368000 51609600>;
  };

  opp-2841600000 {
   opp-hz = /bits/ 64 <2841600000>;
   opp-peak-kBps = <8368000 51609600>;
  };

  opp-2918400000 {
   opp-hz = /bits/ 64 <2918400000>;
   opp-peak-kBps = <8368000 51609600>;
  };

  opp-2995200000 {
   opp-hz = /bits/ 64 <2995200000>;
   opp-peak-kBps = <8368000 51609600>;
  };
 };

 firmware {
  scm: scm {
   compatible = "qcom,scm-sc8180x", "qcom,scm";
  };
 };

 camnoc_virt: interconnect-camnoc-virt {
  compatible = "qcom,sc8180x-camnoc-virt";
  #interconnect-cells = <2>;
  qcom,bcm-voters = <&apps_bcm_voter>;
 };

 mc_virt: interconnect-mc-virt {
  compatible = "qcom,sc8180x-mc-virt";
  #interconnect-cells = <2>;
  qcom,bcm-voters = <&apps_bcm_voter>;
 };

 qup_virt: interconnect-qup-virt {
  compatible = "qcom,sc8180x-qup-virt";
  #interconnect-cells = <2>;
  qcom,bcm-voters = <&apps_bcm_voter>;
 };

 memory@80000000 {
  device_type = "memory";
  /* We expect the bootloader to fill in the size */
  reg = <0x0 0x80000000 0x0 0x0>;
 };

 pmu {
  compatible = "arm,armv8-pmuv3";
  interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
 };

 psci {
  compatible = "arm,psci-1.0";
  method = "smc";

  cpu_pd0: power-domain-cpu0 {
   #power-domain-cells = <0>;
   power-domains = <&cluster_pd>;
   domain-idle-states = <&little_cpu_sleep_0>;
  };

  cpu_pd1: power-domain-cpu1 {
   #power-domain-cells = <0>;
   power-domains = <&cluster_pd>;
   domain-idle-states = <&little_cpu_sleep_0>;
  };

  cpu_pd2: power-domain-cpu2 {
   #power-domain-cells = <0>;
   power-domains = <&cluster_pd>;
   domain-idle-states = <&little_cpu_sleep_0>;
  };

  cpu_pd3: power-domain-cpu3 {
   #power-domain-cells = <0>;
   power-domains = <&cluster_pd>;
   domain-idle-states = <&little_cpu_sleep_0>;
  };

  cpu_pd4: power-domain-cpu4 {
   #power-domain-cells = <0>;
   power-domains = <&cluster_pd>;
   domain-idle-states = <&big_cpu_sleep_0>;
  };

  cpu_pd5: power-domain-cpu5 {
   #power-domain-cells = <0>;
   power-domains = <&cluster_pd>;
   domain-idle-states = <&big_cpu_sleep_0>;
  };

  cpu_pd6: power-domain-cpu6 {
   #power-domain-cells = <0>;
   power-domains = <&cluster_pd>;
   domain-idle-states = <&big_cpu_sleep_0>;
  };

  cpu_pd7: power-domain-cpu7 {
   #power-domain-cells = <0>;
   power-domains = <&cluster_pd>;
   domain-idle-states = <&big_cpu_sleep_0>;
  };

  cluster_pd: power-domain-cpu-cluster0 {
   #power-domain-cells = <0>;
   domain-idle-states = <&cluster_sleep_apss_off &cluster_sleep_aoss_sleep>;
  };
 };

 reserved-memory {
  #address-cells = <2>;
  #size-cells = <2>;
  ranges;

  hyp_mem: hyp@85700000 {
   reg = <0x0 0x85700000 0x0 0x600000>;
   no-map;
  };

  xbl_mem: xbl@85d00000 {
   reg = <0x0 0x85d00000 0x0 0x140000>;
   no-map;
  };

  aop_mem: aop@85f00000 {
   reg = <0x0 0x85f00000 0x0 0x20000>;
   no-map;
  };

  aop_cmd_db: cmd-db@85f20000 {
   compatible = "qcom,cmd-db";
   reg = <0x0 0x85f20000 0x0 0x20000>;
   no-map;
  };

  reserved@85f40000 {
   reg = <0x0 0x85f40000 0x0 0x10000>;
   no-map;
  };

  smem_mem: smem@86000000 {
   compatible = "qcom,smem";
   reg = <0x0 0x86000000 0x0 0x200000>;
   no-map;
   hwlocks = <&tcsr_mutex 3>;
  };

  reserved@86200000 {
   reg = <0x0 0x86200000 0x0 0x3900000>;
   no-map;
  };

  reserved@89b00000 {
   reg = <0x0 0x89b00000 0x0 0x1c00000>;
   no-map;
  };

  reserved@9d400000 {
   reg = <0x0 0x9d400000 0x0 0x1000000>;
   no-map;
  };

  reserved@9e400000 {
   reg = <0x0 0x9e400000 0x0 0x1400000>;
   no-map;
  };

  reserved@9f800000 {
   reg = <0x0 0x9f800000 0x0 0x800000>;
   no-map;
  };
 };

 smp2p-cdsp {
  compatible = "qcom,smp2p";
  qcom,smem = <94>, <432>;

  interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;

  mboxes = <&apss_shared 6>;

  qcom,local-pid = <0>;
  qcom,remote-pid = <5>;

  cdsp_smp2p_out: master-kernel {
   qcom,entry-name = "master-kernel";
   #qcom,smem-state-cells = <1>;
  };

  cdsp_smp2p_in: slave-kernel {
   qcom,entry-name = "slave-kernel";

   interrupt-controller;
   #interrupt-cells = <2>;
  };
 };

 smp2p-lpass {
  compatible = "qcom,smp2p";
  qcom,smem = <443>, <429>;

  interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;

  mboxes = <&apss_shared 10>;

  qcom,local-pid = <0>;
  qcom,remote-pid = <2>;

  adsp_smp2p_out: master-kernel {
   qcom,entry-name = "master-kernel";
   #qcom,smem-state-cells = <1>;
  };

  adsp_smp2p_in: slave-kernel {
   qcom,entry-name = "slave-kernel";

   interrupt-controller;
   #interrupt-cells = <2>;
  };
 };

 smp2p-mpss {
  compatible = "qcom,smp2p";
  qcom,smem = <435>, <428>;

  interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;

  mboxes = <&apss_shared 14>;

  qcom,local-pid = <0>;
  qcom,remote-pid = <1>;

  modem_smp2p_out: master-kernel {
   qcom,entry-name = "master-kernel";
   #qcom,smem-state-cells = <1>;
  };

  modem_smp2p_in: slave-kernel {
   qcom,entry-name = "slave-kernel";

   interrupt-controller;
   #interrupt-cells = <2>;
  };

  modem_smp2p_ipa_out: ipa-ap-to-modem {
   qcom,entry-name = "ipa";
   #qcom,smem-state-cells = <1>;
  };

  modem_smp2p_ipa_in: ipa-modem-to-ap {
   qcom,entry-name = "ipa";
   interrupt-controller;
   #interrupt-cells = <2>;
  };

  modem_smp2p_wlan_in: wlan-wpss-to-ap {
   qcom,entry-name = "wlan";
   interrupt-controller;
   #interrupt-cells = <2>;
  };
 };

 smp2p-slpi {
  compatible = "qcom,smp2p";
  qcom,smem = <481>, <430>;

  interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>;

  mboxes = <&apss_shared 26>;

  qcom,local-pid = <0>;
  qcom,remote-pid = <3>;

  slpi_smp2p_out: master-kernel {
   qcom,entry-name = "master-kernel";
   #qcom,smem-state-cells = <1>;
  };

  slpi_smp2p_in: slave-kernel {
   qcom,entry-name = "slave-kernel";

   interrupt-controller;
   #interrupt-cells = <2>;
  };
 };

 soc: soc@0 {
  compatible = "simple-bus";
  #address-cells = <2>;
  #size-cells = <2>;
  ranges = <0 0 0 0 0x10 0>;
  dma-ranges = <0 0 0 0 0x10 0>;

  gcc: clock-controller@100000 {
   compatible = "qcom,gcc-sc8180x";
   reg = <0x0 0x00100000 0x0 0x1f0000>;
   #clock-cells = <1>;
   #reset-cells = <1>;
   #power-domain-cells = <1>;
   clocks = <&rpmhcc RPMH_CXO_CLK>,
     <&rpmhcc RPMH_CXO_CLK_A>,
     <&sleep_clk>;
   clock-names = "bi_tcxo",
          "bi_tcxo_ao",
          "sleep_clk";
   power-domains = <&rpmhpd SC8180X_CX>;
  };

  qupv3_id_0: geniqup@8c0000 {
   compatible = "qcom,geni-se-qup";
   reg = <0 0x008c0000 0 0x6000>;
   clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
     <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
   clock-names = "m-ahb", "s-ahb";
   #address-cells = <2>;
   #size-cells = <2>;
   ranges;
   iommus = <&apps_smmu 0x4c3 0>;
   status = "disabled";

   i2c0: i2c@880000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x00880000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
    interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
      <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
      <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };

   spi0: spi@880000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x00880000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
    interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
      <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
    interconnect-names = "qup-core", "qup-config";
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };

   uart0: serial@880000 {
    compatible = "qcom,geni-uart";
    reg = <0 0x00880000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
    interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
      <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
    interconnect-names = "qup-core", "qup-config";
    status = "disabled";
   };

   i2c1: i2c@884000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x00884000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
    interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
      <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
      <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };

   spi1: spi@884000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x00884000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
    interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
      <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
    interconnect-names = "qup-core", "qup-config";
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };

   uart1: serial@884000 {
    compatible = "qcom,geni-uart";
    reg = <0 0x00884000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
    interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
      <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
    interconnect-names = "qup-core", "qup-config";
    status = "disabled";
   };

   i2c2: i2c@888000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x00888000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
    interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
      <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
      <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };

   spi2: spi@888000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x00888000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
    interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
      <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
    interconnect-names = "qup-core", "qup-config";
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };

   uart2: serial@888000 {
    compatible = "qcom,geni-uart";
    reg = <0 0x00888000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
    interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
      <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
    interconnect-names = "qup-core", "qup-config";
    status = "disabled";
   };

   i2c3: i2c@88c000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x0088c000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
    interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
      <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
      <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };

   spi3: spi@88c000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x0088c000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
    interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
      <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
    interconnect-names = "qup-core", "qup-config";
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };

   uart3: serial@88c000 {
    compatible = "qcom,geni-uart";
    reg = <0 0x0088c000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
    interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
      <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
    interconnect-names = "qup-core", "qup-config";
    status = "disabled";
   };

   i2c4: i2c@890000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x00890000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
    interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
      <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
      <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };

   spi4: spi@890000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x00890000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
    interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
      <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
    interconnect-names = "qup-core", "qup-config";
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };

   uart4: serial@890000 {
    compatible = "qcom,geni-uart";
    reg = <0 0x00890000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
    interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
      <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
    interconnect-names = "qup-core", "qup-config";
    status = "disabled";
   };

   i2c5: i2c@894000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x00894000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
    interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
      <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
      <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };

   spi5: spi@894000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x00894000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
    interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
      <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
    interconnect-names = "qup-core", "qup-config";
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };

   uart5: serial@894000 {
    compatible = "qcom,geni-uart";
    reg = <0 0x00894000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
    interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
      <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
    interconnect-names = "qup-core", "qup-config";
    status = "disabled";
   };

   i2c6: i2c@898000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x00898000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
    interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
      <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
      <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };

   spi6: spi@898000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x00898000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
    interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
      <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
    interconnect-names = "qup-core", "qup-config";
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };

   uart6: serial@898000 {
    compatible = "qcom,geni-uart";
    reg = <0 0x00898000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
    interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
      <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
    interconnect-names = "qup-core", "qup-config";
    status = "disabled";
   };

   i2c7: i2c@89c000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x0089c000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
    interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
      <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
      <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };

   spi7: spi@89c000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x0089c000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
    interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
      <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
    interconnect-names = "qup-core", "qup-config";
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };

   uart7: serial@89c000 {
    compatible = "qcom,geni-uart";
    reg = <0 0x0089c000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
    interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
      <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
    interconnect-names = "qup-core", "qup-config";
    status = "disabled";
   };
  };

  qupv3_id_1: geniqup@ac0000 {
   compatible = "qcom,geni-se-qup";
   reg = <0x0 0x00ac0000 0x0 0x6000>;
   clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
     <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
   clock-names = "m-ahb", "s-ahb";
   #address-cells = <2>;
   #size-cells = <2>;
   ranges;
   iommus = <&apps_smmu 0x603 0>;
   status = "disabled";

   i2c8: i2c@a80000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x00a80000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
    interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
      <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
      <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };

   spi8: spi@a80000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x00a80000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
    interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
      <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
    interconnect-names = "qup-core", "qup-config";
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };

   uart8: serial@a80000 {
    compatible = "qcom,geni-uart";
    reg = <0 0x00a80000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
    interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
      <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
    interconnect-names = "qup-core", "qup-config";
    status = "disabled";
   };

   i2c9: i2c@a84000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x00a84000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
    interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
      <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
      <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };

   spi9: spi@a84000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x00a84000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
    interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
      <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
    interconnect-names = "qup-core", "qup-config";
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };

   uart9: serial@a84000 {
    compatible = "qcom,geni-debug-uart";
    reg = <0 0x00a84000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
    interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
      <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
    interconnect-names = "qup-core", "qup-config";
    status = "disabled";
   };

   i2c10: i2c@a88000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x00a88000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
    interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
      <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
      <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };

   spi10: spi@a88000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x00a88000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
    interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
      <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
    interconnect-names = "qup-core", "qup-config";
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };

   uart10: serial@a88000 {
    compatible = "qcom,geni-uart";
    reg = <0 0x00a88000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
    interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
      <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
    interconnect-names = "qup-core", "qup-config";
    status = "disabled";
   };

   i2c11: i2c@a8c000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x00a8c000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
    interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
      <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
      <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };

   spi11: spi@a8c000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x00a8c000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
    interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
      <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
    interconnect-names = "qup-core", "qup-config";
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };

   uart11: serial@a8c000 {
    compatible = "qcom,geni-uart";
    reg = <0 0x00a8c000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
    interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
      <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
    interconnect-names = "qup-core", "qup-config";
    status = "disabled";
   };

   i2c12: i2c@a90000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x00a90000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
    interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
      <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
      <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };

   spi12: spi@a90000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x00a90000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
    interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
      <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
    interconnect-names = "qup-core", "qup-config";
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };

   uart12: serial@a90000 {
    compatible = "qcom,geni-uart";
    reg = <0 0x00a90000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
    interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
      <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
    interconnect-names = "qup-core", "qup-config";
    status = "disabled";
   };

   i2c16: i2c@a94000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x00a94000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
    interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
      <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
      <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };

   spi16: spi@a94000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x00a94000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
    interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
      <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
    interconnect-names = "qup-core", "qup-config";
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };

   uart16: serial@a94000 {
    compatible = "qcom,geni-uart";
    reg = <0 0x00a94000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
    interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
      <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
    interconnect-names = "qup-core", "qup-config";
    status = "disabled";
   };
  };

  qupv3_id_2: geniqup@cc0000 {
   compatible = "qcom,geni-se-qup";
   reg = <0x0 0x00cc0000 0x0 0x6000>;
   clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
     <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
   clock-names = "m-ahb", "s-ahb";
   #address-cells = <2>;
   #size-cells = <2>;
   ranges;
   iommus = <&apps_smmu 0x7a3 0>;
   status = "disabled";

   i2c17: i2c@c80000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x00c80000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
    interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
      <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
      <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };

   spi17: spi@c80000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x00c80000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
    interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
      <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
    interconnect-names = "qup-core", "qup-config";
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };

   uart17: serial@c80000 {
    compatible = "qcom,geni-uart";
    reg = <0 0x00c80000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
    interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
      <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
    interconnect-names = "qup-core", "qup-config";
    status = "disabled";
   };

   i2c18: i2c@c84000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x00c84000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
    interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
      <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
      <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };

   spi18: spi@c84000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x00c84000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
    interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
      <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
    interconnect-names = "qup-core", "qup-config";
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };

   uart18: serial@c84000 {
    compatible = "qcom,geni-uart";
    reg = <0 0x00c84000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
    interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
      <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
    interconnect-names = "qup-core", "qup-config";
    status = "disabled";
   };

   i2c19: i2c@c88000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x00c88000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
    interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
      <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
      <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };

   spi19: spi@c88000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x00c88000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
    interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
      <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
    interconnect-names = "qup-core", "qup-config";
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };

   uart19: serial@c88000 {
    compatible = "qcom,geni-uart";
    reg = <0 0x00c88000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
    interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
      <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
    interconnect-names = "qup-core", "qup-config";
    status = "disabled";
   };

   i2c13: i2c@c8c000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x00c8c000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
    interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
      <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
      <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };

   spi13: spi@c8c000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x00c8c000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
    interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
      <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
    interconnect-names = "qup-core", "qup-config";
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };

   uart13: serial@c8c000 {
    compatible = "qcom,geni-uart";
    reg = <0 0x00c8c000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
    interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
      <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
    interconnect-names = "qup-core", "qup-config";
    status = "disabled";
   };

   i2c14: i2c@c90000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x00c90000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
    interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
      <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
      <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };

   spi14: spi@c90000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x00c90000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
    interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
      <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
    interconnect-names = "qup-core", "qup-config";
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };

   uart14: serial@c90000 {
    compatible = "qcom,geni-uart";
    reg = <0 0x00c90000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
    interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
      <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
    interconnect-names = "qup-core", "qup-config";
    status = "disabled";
   };

   i2c15: i2c@c94000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x00c94000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
    interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
      <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
      <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };

   spi15: spi@c94000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x00c94000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
    interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
      <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
    interconnect-names = "qup-core", "qup-config";
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };

   uart15: serial@c94000 {
    compatible = "qcom,geni-uart";
    reg = <0 0x00c94000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
    interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
      <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
    interconnect-names = "qup-core", "qup-config";
    status = "disabled";
   };
  };

  config_noc: interconnect@1500000 {
   compatible = "qcom,sc8180x-config-noc";
   reg = <0 0x01500000 0 0x7400>;
   #interconnect-cells = <2>;
   qcom,bcm-voters = <&apps_bcm_voter>;
  };

  system_noc: interconnect@1620000 {
   compatible = "qcom,sc8180x-system-noc";
   reg = <0 0x01620000 0 0x19400>;
   #interconnect-cells = <2>;
   qcom,bcm-voters = <&apps_bcm_voter>;
  };

  aggre1_noc: interconnect@16e0000 {
   compatible = "qcom,sc8180x-aggre1-noc";
   reg = <0 0x016e0000 0 0xd080>;
   #interconnect-cells = <2>;
   qcom,bcm-voters = <&apps_bcm_voter>;
  };

  aggre2_noc: interconnect@1700000 {
   compatible = "qcom,sc8180x-aggre2-noc";
   reg = <0 0x01700000 0 0x20000>;
   #interconnect-cells = <2>;
   qcom,bcm-voters = <&apps_bcm_voter>;
  };

  compute_noc: interconnect@1720000 {
   compatible = "qcom,sc8180x-compute-noc";
   reg = <0 0x01720000 0 0x7000>;
   #interconnect-cells = <2>;
   qcom,bcm-voters = <&apps_bcm_voter>;
  };

  mmss_noc: interconnect@1740000 {
   compatible = "qcom,sc8180x-mmss-noc";
   reg = <0 0x01740000 0 0x1c100>;
   #interconnect-cells = <2>;
   qcom,bcm-voters = <&apps_bcm_voter>;
  };

  pcie0: pcie@1c00000 {
   compatible = "qcom,pcie-sc8180x";
   reg = <0 0x01c00000 0 0x3000>,
         <0 0x60000000 0 0xf1d>,
         <0 0x60000f20 0 0xa8>,
         <0 0x60001000 0 0x1000>,
         <0 0x60100000 0 0x100000>;
   reg-names = "parf",
        "dbi",
        "elbi",
        "atu",
        "config";
   device_type = "pci";
   linux,pci-domain = <0>;
   bus-range = <0x00 0xff>;
   num-lanes = <2>;

   #address-cells = <3>;
   #size-cells = <2>;

   ranges = <0x01000000 0x0 0x60200000 0x0 0x60200000 0x0 0x100000>,
     <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;

   interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
   interrupt-names = "msi0",
       "msi1",
       "msi2",
       "msi3",
       "msi4",
       "msi5",
       "msi6",
       "msi7",
       "global";
   #interrupt-cells = <1>;
   interrupt-map-mask = <0 0 0 0x7>;
   interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
     <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
     <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
     <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */

   clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
     <&gcc GCC_PCIE_0_AUX_CLK>,
     <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
     <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
     <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
     <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>;
   clock-names = "pipe",
          "aux",
          "cfg",
          "bus_master",
          "bus_slave",
          "slave_q2a";

   assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>;
   assigned-clock-rates = <19200000>;

   iommu-map = <0x0   &apps_smmu 0x1d80 0x1>,
        <0x100 &apps_smmu 0x1d81 0x1>;

   resets = <&gcc GCC_PCIE_0_BCR>;
   reset-names = "pci";

   power-domains = <&gcc PCIE_0_GDSC>;

   interconnects = <&aggre2_noc MASTER_PCIE 0 &mc_virt SLAVE_EBI_CH0 0>,
     <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>;
   interconnect-names = "pcie-mem", "cpu-pcie";

   phys = <&pcie0_phy>;
   phy-names = "pciephy";
   dma-coherent;

   status = "disabled";

   pcie@0 {
    device_type = "pci";
    reg = <0x0 0x0 0x0 0x0 0x0>;
    bus-range = <0x01 0xff>;

    #address-cells = <3>;
    #size-cells = <2>;
    ranges;
   };
  };

  pcie0_phy: phy@1c06000 {
   compatible = "qcom,sc8180x-qmp-pcie-phy";
   reg = <0 0x01c06000 0 0x1000>;
   clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
     <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
     <&gcc GCC_PCIE_0_CLKREF_CLK>,
     <&gcc GCC_PCIE0_PHY_REFGEN_CLK>,
     <&gcc GCC_PCIE_0_PIPE_CLK>;
   clock-names = "aux",
          "cfg_ahb",
          "ref",
          "refgen",
          "pipe";
   #clock-cells = <0>;
   clock-output-names = "pcie_0_pipe_clk";
   #phy-cells = <0>;

   resets = <&gcc GCC_PCIE_0_PHY_BCR>;
   reset-names = "phy";

   assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
   assigned-clock-rates = <100000000>;

   status = "disabled";
  };

  pcie3: pcie@1c08000 {
   compatible = "qcom,pcie-sc8180x";
   reg = <0 0x01c08000 0 0x3000>,
         <0 0x40000000 0 0xf1d>,
         <0 0x40000f20 0 0xa8>,
         <0 0x40001000 0 0x1000>,
         <0 0x40100000 0 0x100000>;
   reg-names = "parf",
        "dbi",
        "elbi",
        "atu",
        "config";
   device_type = "pci";
   linux,pci-domain = <3>;
   bus-range = <0x00 0xff>;
   num-lanes = <2>;

   #address-cells = <3>;
   #size-cells = <2>;

   ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
     <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;

   interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
   interrupt-names = "msi0",
       "msi1",
       "msi2",
       "msi3",
       "msi4",
       "msi5",
       "msi6",
       "msi7",
       "global";
   #interrupt-cells = <1>;
   interrupt-map-mask = <0 0 0 0x7>;
   interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
     <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
     <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
     <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */

   clocks = <&gcc GCC_PCIE_3_PIPE_CLK>,
     <&gcc GCC_PCIE_3_AUX_CLK>,
     <&gcc GCC_PCIE_3_CFG_AHB_CLK>,
     <&gcc GCC_PCIE_3_MSTR_AXI_CLK>,
     <&gcc GCC_PCIE_3_SLV_AXI_CLK>,
     <&gcc GCC_PCIE_3_SLV_Q2A_AXI_CLK>;
   clock-names = "pipe",
          "aux",
          "cfg",
          "bus_master",
          "bus_slave",
          "slave_q2a";

   assigned-clocks = <&gcc GCC_PCIE_3_AUX_CLK>;
   assigned-clock-rates = <19200000>;

   iommu-map = <0x0   &apps_smmu 0x1e00 0x1>,
        <0x100 &apps_smmu 0x1e01 0x1>;

   resets = <&gcc GCC_PCIE_3_BCR>;
   reset-names = "pci";

   power-domains = <&gcc PCIE_3_GDSC>;

   interconnects = <&aggre2_noc MASTER_PCIE_3 0 &mc_virt SLAVE_EBI_CH0 0>,
     <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_3 0>;
   interconnect-names = "pcie-mem", "cpu-pcie";

   phys = <&pcie3_phy>;
   phy-names = "pciephy";
   dma-coherent;

   status = "disabled";

   pcie@0 {
    device_type = "pci";
    reg = <0x0 0x0 0x0 0x0 0x0>;
    bus-range = <0x01 0xff>;

    #address-cells = <3>;
    #size-cells = <2>;
    ranges;
   };
  };

  pcie3_phy: phy@1c0c000 {
   compatible = "qcom,sc8180x-qmp-pcie-phy";
   reg = <0 0x01c0c000 0 0x1000>;
   clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
     <&gcc GCC_PCIE_3_CFG_AHB_CLK>,
     <&gcc GCC_PCIE_3_CLKREF_CLK>,
     <&gcc GCC_PCIE3_PHY_REFGEN_CLK>,
     <&gcc GCC_PCIE_3_PIPE_CLK>;
   clock-names = "aux",
          "cfg_ahb",
          "ref",
          "refgen",
          "pipe";
   #clock-cells = <0>;
   clock-output-names = "pcie_3_pipe_clk";

   #phy-cells = <0>;

   resets = <&gcc GCC_PCIE_3_PHY_BCR>;
   reset-names = "phy";

   assigned-clocks = <&gcc GCC_PCIE3_PHY_REFGEN_CLK>;
   assigned-clock-rates = <100000000>;

   status = "disabled";
  };

  pcie1: pcie@1c10000 {
   compatible = "qcom,pcie-sc8180x";
   reg = <0 0x01c10000 0 0x3000>,
         <0 0x68000000 0 0xf1d>,
         <0 0x68000f20 0 0xa8>,
         <0 0x68001000 0 0x1000>,
         <0 0x68100000 0 0x100000>;
   reg-names = "parf",
        "dbi",
        "elbi",
        "atu",
        "config";
   device_type = "pci";
   linux,pci-domain = <1>;
   bus-range = <0x00 0xff>;
   num-lanes = <2>;

   #address-cells = <3>;
   #size-cells = <2>;

   ranges = <0x01000000 0x0 0x68200000 0x0 0x68200000 0x0 0x100000>,
     <0x02000000 0x0 0x68300000 0x0 0x68300000 0x0 0x3d00000>;

   interrupts = <GIC_SPI 756 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 755 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 754 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 753 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 752 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 751 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 750 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 749 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 758 IRQ_TYPE_LEVEL_HIGH>;
   interrupt-names = "msi0",
       "msi1",
       "msi2",
       "msi3",
       "msi4",
       "msi5",
       "msi6",
       "msi7",
       "global";
   #interrupt-cells = <1>;
   interrupt-map-mask = <0 0 0 0x7>;
   interrupt-map = <0 0 0 1 &intc 0 747 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
     <0 0 0 2 &intc 0 746 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
     <0 0 0 3 &intc 0 745 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
     <0 0 0 4 &intc 0 744 IRQ_TYPE_LEVEL_HIGH>; /* int_d */

   clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
     <&gcc GCC_PCIE_1_AUX_CLK>,
     <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
     <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
     <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
     <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>;
   clock-names = "pipe",
          "aux",
          "cfg",
          "bus_master",
          "bus_slave",
          "slave_q2a";

   assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
   assigned-clock-rates = <19200000>;

   iommu-map = <0x0   &apps_smmu 0x1c80 0x1>,
        <0x100 &apps_smmu 0x1c81 0x1>;

   resets = <&gcc GCC_PCIE_1_BCR>;
   reset-names = "pci";

   power-domains = <&gcc PCIE_1_GDSC>;

   interconnects = <&aggre2_noc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI_CH0 0>,
     <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_1 0>;
   interconnect-names = "pcie-mem", "cpu-pcie";

   phys = <&pcie1_phy>;
   phy-names = "pciephy";
   dma-coherent;

   status = "disabled";

   pcie@0 {
    device_type = "pci";
    reg = <0x0 0x0 0x0 0x0 0x0>;
    bus-range = <0x01 0xff>;

    #address-cells = <3>;
    #size-cells = <2>;
    ranges;
   };
  };

  pcie1_phy: phy@1c16000 {
   compatible = "qcom,sc8180x-qmp-pcie-phy";
   reg = <0 0x01c16000 0 0x1000>;
   clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
     <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
     <&gcc GCC_PCIE_1_CLKREF_CLK>,
     <&gcc GCC_PCIE1_PHY_REFGEN_CLK>,
     <&gcc GCC_PCIE_1_PIPE_CLK>;
   clock-names = "aux",
          "cfg_ahb",
          "ref",
          "refgen",
          "pipe";
   #clock-cells = <0>;
   clock-output-names = "pcie_1_pipe_clk";

   #phy-cells = <0>;

   resets = <&gcc GCC_PCIE_1_PHY_BCR>;
   reset-names = "phy";

   assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
   assigned-clock-rates = <100000000>;

   status = "disabled";
  };

  pcie2: pcie@1c18000 {
   compatible = "qcom,pcie-sc8180x";
   reg = <0 0x01c18000 0 0x3000>,
         <0 0x70000000 0 0xf1d>,
         <0 0x70000f20 0 0xa8>,
         <0 0x70001000 0 0x1000>,
         <0 0x70100000 0 0x100000>;
   reg-names = "parf",
        "dbi",
        "elbi",
        "atu",
        "config";
   device_type = "pci";
   linux,pci-domain = <2>;
   bus-range = <0x00 0xff>;
   num-lanes = <4>;

   #address-cells = <3>;
   #size-cells = <2>;

   ranges = <0x01000000 0x0 0x70200000 0x0 0x70200000 0x0 0x100000>,
     <0x02000000 0x0 0x70300000 0x0 0x70300000 0x0 0x3d00000>;

   interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 671 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 670 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 668 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 667 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 744 IRQ_TYPE_LEVEL_HIGH>;
   interrupt-names = "msi0",
       "msi1",
       "msi2",
       "msi3",
       "msi4",
       "msi5",
       "msi6",
       "msi7",
       "global";
   #interrupt-cells = <1>;
   interrupt-map-mask = <0 0 0 0x7>;
   interrupt-map = <0 0 0 1 &intc 0 663 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
     <0 0 0 2 &intc 0 662 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
     <0 0 0 3 &intc 0 661 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
     <0 0 0 4 &intc 0 660 IRQ_TYPE_LEVEL_HIGH>; /* int_d */

   clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
     <&gcc GCC_PCIE_2_AUX_CLK>,
     <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
     <&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
     <&gcc GCC_PCIE_2_SLV_AXI_CLK>,
     <&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>;
   clock-names = "pipe",
          "aux",
          "cfg",
          "bus_master",
          "bus_slave",
          "slave_q2a";

   assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>;
   assigned-clock-rates = <19200000>;

   iommu-map = <0x0   &apps_smmu 0x1d00 0x1>,
        <0x100 &apps_smmu 0x1d01 0x1>;

   resets = <&gcc GCC_PCIE_2_BCR>;
   reset-names = "pci";

   power-domains = <&gcc PCIE_2_GDSC>;

   interconnects = <&aggre2_noc MASTER_PCIE_2 0 &mc_virt SLAVE_EBI_CH0 0>,
     <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_2 0>;
   interconnect-names = "pcie-mem", "cpu-pcie";

   phys = <&pcie2_phy>;
   phy-names = "pciephy";
   dma-coherent;

   status = "disabled";

   pcie@0 {
    device_type = "pci";
    reg = <0x0 0x0 0x0 0x0 0x0>;
    bus-range = <0x01 0xff>;

    #address-cells = <3>;
    #size-cells = <2>;
    ranges;
   };
  };

  pcie2_phy: phy@1c1c000 {
   compatible = "qcom,sc8180x-qmp-pcie-phy";
   reg = <0 0x01c1c000 0 0x1000>;
   clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
     <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
     <&gcc GCC_PCIE_2_CLKREF_CLK>,
     <&gcc GCC_PCIE2_PHY_REFGEN_CLK>,
     <&gcc GCC_PCIE_2_PIPE_CLK>;
   clock-names = "aux",
          "cfg_ahb",
          "ref",
          "refgen",
          "pipe";
   #clock-cells = <0>;
   clock-output-names = "pcie_2_pipe_clk";

   #phy-cells = <0>;

   resets = <&gcc GCC_PCIE_2_PHY_BCR>;
   reset-names = "phy";

   assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
   assigned-clock-rates = <100000000>;

   status = "disabled";
  };

  ufs_mem_hc: ufshc@1d84000 {
   compatible = "qcom,sc8180x-ufshc", "qcom,ufshc",
         "jedec,ufs-2.0";
   reg = <0 0x01d84000 0 0x2500>;
   interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
   phys = <&ufs_mem_phy>;
   phy-names = "ufsphy";
   lanes-per-direction = <2>;
   #reset-cells = <1>;
   resets = <&gcc GCC_UFS_PHY_BCR>;
   reset-names = "rst";

   iommus = <&apps_smmu 0x300 0>;

   clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
     <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
     <&gcc GCC_UFS_PHY_AHB_CLK>,
     <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
     <&rpmhcc RPMH_CXO_CLK>,
     <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
     <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
     <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
   clock-names = "core_clk",
          "bus_aggr_clk",
          "iface_clk",
          "core_clk_unipro",
          "ref_clk",
          "tx_lane0_sync_clk",
          "rx_lane0_sync_clk",
          "rx_lane1_sync_clk";
   freq-table-hz = <37500000 300000000>,
     <0 0>,
     <0 0>,
     <37500000 300000000>,
     <0 0>,
     <0 0>,
     <0 0>,
     <0 0>;

   power-domains = <&gcc UFS_PHY_GDSC>;

   interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS
      &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>,
     <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ALWAYS
      &config_noc SLAVE_UFS_MEM_0_CFG QCOM_ICC_TAG_ALWAYS>;
   interconnect-names = "ufs-ddr", "cpu-ufs";

   status = "disabled";
  };

  ufs_mem_phy: phy-wrapper@1d87000 {
   compatible = "qcom,sc8180x-qmp-ufs-phy";
   reg = <0 0x01d87000 0 0x1000>;

   clocks = <&rpmhcc RPMH_CXO_CLK>,
     <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
     <&gcc GCC_UFS_MEM_CLKREF_EN>;
   clock-names = "ref",
          "ref_aux",
          "qref";

   resets = <&ufs_mem_hc 0>;
   reset-names = "ufsphy";

   power-domains = <&gcc UFS_PHY_GDSC>;

   #phy-cells = <0>;

   status = "disabled";
  };

  tcsr_mutex: hwlock@1f40000 {
   compatible = "qcom,tcsr-mutex";
   reg = <0x0 0x01f40000 0x0 0x40000>;
   #hwlock-cells = <1>;
  };

  gpu: gpu@2c00000 {
   compatible = "qcom,adreno-680.1", "qcom,adreno";

   reg = <0 0x02c00000 0 0x40000>;
   reg-names = "kgsl_3d0_reg_memory";

   interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;

   iommus = <&adreno_smmu 0 0xc01>;

   operating-points-v2 = <&gpu_opp_table>;

   interconnects = <&gem_noc MASTER_GRAPHICS_3D 0 &mc_virt SLAVE_EBI_CH0 0>;
   interconnect-names = "gfx-mem";

   qcom,gmu = <&gmu>;
   #cooling-cells = <2>;

   status = "disabled";

   gpu_opp_table: opp-table {
    compatible = "operating-points-v2";

    opp-514000000 {
     opp-hz = /bits/ 64 <514000000>;
     opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
    };

    opp-500000000 {
     opp-hz = /bits/ 64 <500000000>;
     opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
    };

    opp-461000000 {
     opp-hz = /bits/ 64 <461000000>;
     opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
    };

    opp-405000000 {
     opp-hz = /bits/ 64 <405000000>;
     opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
    };

    opp-315000000 {
     opp-hz = /bits/ 64 <315000000>;
     opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
    };

    opp-256000000 {
     opp-hz = /bits/ 64 <256000000>;
     opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
    };

    opp-177000000 {
     opp-hz = /bits/ 64 <177000000>;
     opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
    };
   };
  };

  gmu: gmu@2c6a000 {
   compatible = "qcom,adreno-gmu-680.1", "qcom,adreno-gmu";

   reg = <0 0x02c6a000 0 0x30000>,
         <0 0x0b290000 0 0x10000>,
         <0 0x0b490000 0 0x10000>;
   reg-names = "gmu",
        "gmu_pdc",
        "gmu_pdc_seq";

   interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
   interrupt-names = "hfi", "gmu";

   clocks = <&gpucc GPU_CC_AHB_CLK>,
     <&gpucc GPU_CC_CX_GMU_CLK>,
     <&gpucc GPU_CC_CXO_CLK>,
     <&gcc GCC_DDRSS_GPU_AXI_CLK>,
     <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
   clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";

   power-domains = <&gpucc GPU_CX_GDSC>,
     <&gpucc GPU_GX_GDSC>;
   power-domain-names = "cx", "gx";

   iommus = <&adreno_smmu 5 0xc00>;

   operating-points-v2 = <&gmu_opp_table>;

   gmu_opp_table: opp-table {
    compatible = "operating-points-v2";

    opp-200000000 {
     opp-hz = /bits/ 64 <200000000>;
     opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
    };

    opp-500000000 {
     opp-hz = /bits/ 64 <500000000>;
     opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
    };
   };
  };

  gpucc: clock-controller@2c90000 {
   compatible = "qcom,sc8180x-gpucc";
   reg = <0 0x02c90000 0 0x9000>;
   clocks = <&rpmhcc RPMH_CXO_CLK>,
     <&gcc GCC_GPU_GPLL0_CLK_SRC>,
     <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
   clock-names = "bi_tcxo",
          "gcc_gpu_gpll0_clk_src",
          "gcc_gpu_gpll0_div_clk_src";
   #clock-cells = <1>;
   #reset-cells = <1>;
   #power-domain-cells = <1>;
  };

  adreno_smmu: iommu@2ca0000 {
   compatible = "qcom,sc8180x-smmu-500", "qcom,adreno-smmu",
         "qcom,smmu-500", "arm,mmu-500";
   reg = <0 0x02ca0000 0 0x10000>;
   #iommu-cells = <2>;
   #global-interrupts = <1>;
   interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>;
   clocks = <&gpucc GPU_CC_AHB_CLK>,
     <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
     <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
   clock-names = "ahb", "bus", "iface";

   power-domains = <&gpucc GPU_CX_GDSC>;
  };

  tlmm: pinctrl@3100000 {
   compatible = "qcom,sc8180x-tlmm";
   reg = <0 0x03100000 0 0x300000>,
         <0 0x03500000 0 0x700000>,
         <0 0x03d00000 0 0x300000>;
   reg-names = "west", "east", "south";
   interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
   gpio-controller;
   #gpio-cells = <2>;
   interrupt-controller;
   #interrupt-cells = <2>;
   gpio-ranges = <&tlmm 0 0 191>;
   wakeup-parent = <&pdc>;
  };

  remoteproc_mpss: remoteproc@4080000 {
   compatible = "qcom,sc8180x-mpss-pas";
   reg = <0x0 0x04080000 0x0 0x4040>;

   interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
           <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
           <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
           <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
           <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
           <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
   interrupt-names = "wdog", "fatal", "ready", "handover",
       "stop-ack", "shutdown-ack";

   clocks = <&rpmhcc RPMH_CXO_CLK>;
   clock-names = "xo";

   power-domains = <&rpmhpd SC8180X_CX>,
     <&rpmhpd SC8180X_MSS>;
   power-domain-names = "cx", "mss";

   qcom,qmp = <&aoss_qmp>;

   qcom,smem-states = <&modem_smp2p_out 0>;
   qcom,smem-state-names = "stop";

   glink-edge {
    interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
    label = "modem";
    qcom,remote-pid = <1>;
    mboxes = <&apss_shared 12>;
   };
  };

  remoteproc_cdsp: remoteproc@8300000 {
   compatible = "qcom,sc8180x-cdsp-pas";
   reg = <0x0 0x08300000 0x0 0x4040>;

   interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
           <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
           <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
           <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
           <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
   interrupt-names = "wdog", "fatal", "ready",
       "handover", "stop-ack";

   clocks = <&rpmhcc RPMH_CXO_CLK>;
   clock-names = "xo";

   power-domains = <&rpmhpd SC8180X_CX>;
   power-domain-names = "cx";

   qcom,qmp = <&aoss_qmp>;

   qcom,smem-states = <&cdsp_smp2p_out 0>;
   qcom,smem-state-names = "stop";

   status = "disabled";

   glink-edge {
    interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>;
    label = "cdsp";
    qcom,remote-pid = <5>;
    mboxes = <&apss_shared 4>;
   };
  };

  usb_prim_hsphy: phy@88e2000 {
   compatible = "qcom,sc8180x-usb-hs-phy",
         "qcom,usb-snps-hs-7nm-phy";
   reg = <0 0x088e2000 0 0x400>;
   clocks = <&rpmhcc RPMH_CXO_CLK>;
   clock-names = "ref";
   resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;

   #phy-cells = <0>;

   status = "disabled";
  };

  usb_sec_hsphy: phy@88e3000 {
   compatible = "qcom,sc8180x-usb-hs-phy",
         "qcom,usb-snps-hs-7nm-phy";
   reg = <0 0x088e3000 0 0x400>;
   clocks = <&rpmhcc RPMH_CXO_CLK>;
   clock-names = "ref";
   resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;

   #phy-cells = <0>;

   status = "disabled";
  };

  usb_mp_hsphy0: phy@88e4000 {
   compatible = "qcom,sc8180x-usb-hs-phy",
         "qcom,usb-snps-hs-7nm-phy";
   reg = <0 0x088e4000 0 0x400>;
   #phy-cells = <0>;

   clocks = <&rpmhcc RPMH_CXO_CLK>;
   clock-names = "ref";

   resets = <&gcc GCC_QUSB2PHY_MP0_BCR>;

   status = "disabled";
  };

  usb_mp_hsphy1: phy@88e5000 {
   compatible = "qcom,sc8180x-usb-hs-phy",
         "qcom,usb-snps-hs-7nm-phy";
   reg = <0 0x088e5000 0 0x400>;
   #phy-cells = <0>;

   clocks = <&rpmhcc RPMH_CXO_CLK>;
   clock-names = "ref";

   resets = <&gcc GCC_QUSB2PHY_MP1_BCR>;

   status = "disabled";
  };

  usb_prim_qmpphy: phy@88e8000 {
   compatible = "qcom,sc8180x-qmp-usb3-dp-phy";
   reg = <0 0x088e8000 0 0x3000>;

   clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
     <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
     <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
     <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
   clock-names = "aux",
          "ref",
          "com_aux",
          "usb3_pipe";

   resets = <&gcc GCC_USB3_DP_PHY_PRIM_SP0_BCR>,
     <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>;
   reset-names = "phy", "common";

   #clock-cells = <1>;
   #phy-cells = <1>;

   status = "disabled";

   ports {
    #address-cells = <1>;
    #size-cells = <0>;

    port@0 {
     reg = <0>;

     usb_prim_qmpphy_out: endpoint {};
    };

    port@1 {
     reg = <1>;

     usb_prim_qmpphy_usb_ss_in: endpoint {
      remote-endpoint = <&usb_prim_dwc3_ss>;
     };
    };

    port@2 {
     reg = <2>;

     usb_prim_qmpphy_dp_in: endpoint {};
    };
   };
  };

  usb_mp_qmpphy0: phy@88eb000 {
   compatible = "qcom,sc8180x-qmp-usb3-uni-phy";
   reg = <0 0x088eb000 0 0x1000>;

   clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,
     <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
     <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>,
     <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>;
   clock-names = "aux",
          "ref",
          "com_aux",
          "pipe";

   resets = <&gcc GCC_USB3_UNIPHY_MP0_BCR>,
     <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>;
   reset-names = "phy", "phy_phy";

   power-domains = <&gcc USB30_MP_GDSC>;

   #clock-cells = <0>;
   clock-output-names = "usb2_phy0_pipe_clk";

   #phy-cells = <0>;

   status = "disabled";
  };

  usb_mp_qmpphy1: phy@88ec000 {
   compatible = "qcom,sc8180x-qmp-usb3-uni-phy";
   reg = <0 0x088ec000 0 0x1000>;

   clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,
     <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
     <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>,
     <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>;
   clock-names = "aux",
          "ref",
          "com_aux",
          "pipe";

   resets = <&gcc GCC_USB3_UNIPHY_MP1_BCR>,
     <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>;
   reset-names = "phy", "phy_phy";

   power-domains = <&gcc USB30_MP_GDSC>;

   #clock-cells = <0>;
   clock-output-names = "usb2_phy1_pipe_clk";

   #phy-cells = <0>;

   status = "disabled";
  };

  usb_sec_qmpphy: phy@88ee000 {
   compatible = "qcom,sc8180x-qmp-usb3-dp-phy";
   reg = <0 0x088ed000 0 0x3000>;

   clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
     <&gcc GCC_USB3_SEC_CLKREF_CLK>,
     <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>,
     <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
   clock-names = "aux",
          "ref",
          "com_aux",
          "usb3_pipe";
   resets = <&gcc GCC_USB3_DP_PHY_SEC_BCR>,
     <&gcc GCC_USB3_PHY_SEC_BCR>;
   reset-names = "phy", "common";

   #clock-cells = <1>;
   #phy-cells = <1>;

   status = "disabled";

   ports {
    #address-cells = <1>;
    #size-cells = <0>;

    port@0 {
     reg = <0>;

     usb_sec_qmpphy_out: endpoint {};
    };

    port@1 {
     reg = <1>;

     usb_sec_qmpphy_usb_ss_in: endpoint {
      remote-endpoint = <&usb_sec_dwc3_ss>;
     };
    };

    port@2 {
     reg = <2>;

     usb_sec_qmpphy_dp_in: endpoint {};
    };
   };
  };

  system-cache-controller@9200000 {
   compatible = "qcom,sc8180x-llcc";
   reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>,
         <0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>,
         <0 0x09400000 0 0x58000>, <0 0x09480000 0 0x58000>,
         <0 0x09500000 0 0x58000>, <0 0x09580000 0 0x58000>,
         <0 0x09600000 0 0x58000>;
   reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
        "llcc3_base", "llcc4_base", "llcc5_base",
        "llcc6_base", "llcc7_base",  "llcc_broadcast_base";
   interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
  };

  gem_noc: interconnect@9680000 {
   compatible = "qcom,sc8180x-gem-noc";
   reg = <0 0x09680000 0 0x58200>;
   #interconnect-cells = <2>;
   qcom,bcm-voters = <&apps_bcm_voter>;
  };

  usb_mp: usb@a4f8800 {
   compatible = "qcom,sc8180x-dwc3-mp", "qcom,dwc3";
   reg = <0 0x0a4f8800 0 0x400>;
   #address-cells = <2>;
   #size-cells = <2>;
   ranges;
   dma-ranges;

   clocks = <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>,
     <&gcc GCC_USB30_MP_MASTER_CLK>,
     <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>,
     <&gcc GCC_USB30_MP_SLEEP_CLK>,
     <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
     <&gcc GCC_USB3_SEC_CLKREF_CLK>;
   clock-names = "cfg_noc",
          "core",
          "iface",
          "sleep",
          "mock_utmi",
          "xo";

   interconnects = <&aggre1_noc MASTER_USB3_2 0 &mc_virt SLAVE_EBI_CH0 0>,
     <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3_2 0>;
   interconnect-names = "usb-ddr", "apps-usb";

   assigned-clocks = <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
       <&gcc GCC_USB30_MP_MASTER_CLK>;
   assigned-clock-rates = <19200000>, <200000000>;

   interrupts-extended = <&intc GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>,
           <&intc GIC_SPI 655 IRQ_TYPE_LEVEL_HIGH>,
           <&intc GIC_SPI 658 IRQ_TYPE_LEVEL_HIGH>,
           <&intc GIC_SPI 657 IRQ_TYPE_LEVEL_HIGH>,
           <&pdc 59 IRQ_TYPE_EDGE_BOTH>,
           <&pdc 46 IRQ_TYPE_EDGE_BOTH>,
           <&pdc 71 IRQ_TYPE_EDGE_BOTH>,
           <&pdc 68 IRQ_TYPE_EDGE_BOTH>,
           <&pdc 7 IRQ_TYPE_LEVEL_HIGH>,
           <&pdc 30 IRQ_TYPE_LEVEL_HIGH>;
   interrupt-names = "pwr_event_1", "pwr_event_2",
       "hs_phy_1",  "hs_phy_2",
       "dp_hs_phy_1", "dm_hs_phy_1",
       "dp_hs_phy_2", "dm_hs_phy_2",
       "ss_phy_1",  "ss_phy_2";

   power-domains = <&gcc USB30_MP_GDSC>;

   resets = <&gcc GCC_USB30_MP_BCR>;

   status = "disabled";

   usb_mp_dwc3: usb@a400000 {
    compatible = "snps,dwc3";
    reg = <0 0x0a400000 0 0xcd00>;
    interrupts = <GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH>;
    iommus = <&apps_smmu 0x60 0>;
    snps,dis_u2_susphy_quirk;
    snps,dis_enblslpm_quirk;
    snps,dis-u1-entry-quirk;
    snps,dis-u2-entry-quirk;
    phys = <&usb_mp_hsphy0>,
           <&usb_mp_qmpphy0>,
           <&usb_mp_hsphy1>,
           <&usb_mp_qmpphy1>;
    phy-names = "usb2-0",
         "usb3-0",
         "usb2-1",
         "usb3-1";
    dr_mode = "host";
   };
  };

  usb_prim: usb@a6f8800 {
   compatible = "qcom,sc8180x-dwc3", "qcom,dwc3";
   reg = <0 0x0a6f8800 0 0x400>;
   interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
           <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
           <&pdc 9 IRQ_TYPE_EDGE_BOTH>,
           <&pdc 8 IRQ_TYPE_EDGE_BOTH>,
           <&pdc 6 IRQ_TYPE_LEVEL_HIGH>;
   interrupt-names = "pwr_event",
       "hs_phy_irq",
       "dp_hs_phy_irq",
       "dm_hs_phy_irq",
       "ss_phy_irq";

   clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
     <&gcc GCC_USB30_PRIM_MASTER_CLK>,
     <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
     <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
     <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
     <&gcc GCC_USB3_SEC_CLKREF_CLK>;
   clock-names = "cfg_noc",
          "core",
          "iface",
          "sleep",
          "mock_utmi",
          "xo";
   resets = <&gcc GCC_USB30_PRIM_BCR>;
   power-domains = <&gcc USB30_PRIM_GDSC>;

   interconnects = <&aggre1_noc MASTER_USB3 0 &mc_virt SLAVE_EBI_CH0 0>,
     <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>;
   interconnect-names = "usb-ddr", "apps-usb";

   assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
       <&gcc GCC_USB30_PRIM_MASTER_CLK>;
   assigned-clock-rates = <19200000>, <200000000>;

   #address-cells = <2>;
   #size-cells = <2>;
   ranges;
   dma-ranges;

   status = "disabled";

   usb_prim_dwc3: usb@a600000 {
    compatible = "snps,dwc3";
    reg = <0 0x0a600000 0 0xcd00>;
    interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
    iommus = <&apps_smmu 0x140 0>;
    snps,dis_u2_susphy_quirk;
    snps,dis_enblslpm_quirk;
    snps,dis-u1-entry-quirk;
    snps,dis-u2-entry-quirk;
    phys = <&usb_prim_hsphy>, <&usb_prim_qmpphy QMP_USB43DP_USB3_PHY>;
    phy-names = "usb2-phy", "usb3-phy";

    ports {
     #address-cells = <1>;
     #size-cells = <0>;

     port@0 {
      reg = <0>;

      usb_prim_dwc3_hs: endpoint {
      };
     };

     port@1 {
      reg = <1>;

      usb_prim_dwc3_ss: endpoint {
       remote-endpoint = <&usb_prim_qmpphy_usb_ss_in>;
      };
     };
    };
   };
  };

  usb_sec: usb@a8f8800 {
   compatible = "qcom,sc8180x-dwc3", "qcom,dwc3";
   reg = <0 0x0a8f8800 0 0x400>;

   clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
     <&gcc GCC_USB30_SEC_MASTER_CLK>,
     <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
     <&gcc GCC_USB30_SEC_SLEEP_CLK>,
     <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
     <&gcc GCC_USB3_SEC_CLKREF_CLK>;
   clock-names = "cfg_noc",
          "core",
          "iface",
          "sleep",
          "mock_utmi",
          "xo";
   resets = <&gcc GCC_USB30_SEC_BCR>;
   power-domains = <&gcc USB30_SEC_GDSC>;

   interrupts-extended = <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
           <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
           <&pdc 11 IRQ_TYPE_EDGE_BOTH>,
           <&pdc 10 IRQ_TYPE_EDGE_BOTH>,
           <&pdc 40 IRQ_TYPE_LEVEL_HIGH>;
   interrupt-names = "pwr_event",
       "hs_phy_irq",
       "dp_hs_phy_irq",
       "dm_hs_phy_irq",
       "ss_phy_irq";

   assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
       <&gcc GCC_USB30_SEC_MASTER_CLK>;
   assigned-clock-rates = <19200000>, <200000000>;

   interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI_CH0 0>,
     <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3_1 0>;
   interconnect-names = "usb-ddr", "apps-usb";

   #address-cells = <2>;
   #size-cells = <2>;
   ranges;
   dma-ranges;

   status = "disabled";

   usb_sec_dwc3: usb@a800000 {
    compatible = "snps,dwc3";
    reg = <0 0x0a800000 0 0xcd00>;
    interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
    iommus = <&apps_smmu 0x160 0>;
    snps,dis_u2_susphy_quirk;
    snps,dis_enblslpm_quirk;
    snps,dis-u1-entry-quirk;
    snps,dis-u2-entry-quirk;
    phys = <&usb_sec_hsphy>, <&usb_sec_qmpphy QMP_USB43DP_USB3_PHY>;
    phy-names = "usb2-phy", "usb3-phy";

    ports {
     #address-cells = <1>;
     #size-cells = <0>;

     port@0 {
      reg = <0>;

      usb_sec_dwc3_hs: endpoint {
      };
     };

     port@1 {
      reg = <1>;

      usb_sec_dwc3_ss: endpoint {
       remote-endpoint = <&usb_sec_qmpphy_usb_ss_in>;
      };
     };
    };
   };
  };

  camcc: clock-controller@ad00000 {
   compatible = "qcom,sc8180x-camcc";
   reg = <0 0x0ad00000 0 0x20000>;
   clocks = <&gcc GCC_CAMERA_AHB_CLK>,
     <&rpmhcc RPMH_CXO_CLK>,
     <&sleep_clk>;
   power-domains = <&rpmhpd SC8180X_MMCX>;
   required-opps = <&rpmhpd_opp_low_svs>;
   #clock-cells = <1>;
   #reset-cells = <1>;
   #power-domain-cells = <1>;
  };

  mdss: mdss@ae00000 {
   compatible = "qcom,sc8180x-mdss";
   reg = <0 0x0ae00000 0 0x1000>;
   reg-names = "mdss";

   power-domains = <&dispcc MDSS_GDSC>;

   clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
     <&gcc GCC_DISP_HF_AXI_CLK>,
     <&gcc GCC_DISP_SF_AXI_CLK>,
     <&dispcc DISP_CC_MDSS_MDP_CLK>;
   clock-names = "iface",
          "bus",
          "nrt_bus",
          "core";

   resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;

   interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
   interrupt-controller;
   #interrupt-cells = <1>;

   interconnects = <&mmss_noc MASTER_MDP_PORT0 QCOM_ICC_TAG_ALWAYS
      &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>,
     <&mmss_noc MASTER_MDP_PORT1 QCOM_ICC_TAG_ALWAYS
      &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>,
     <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ALWAYS
      &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ALWAYS>;
   interconnect-names = "mdp0-mem",
          "mdp1-mem",
          "cpu-cfg";

   iommus = <&apps_smmu 0x800 0x420>;

   #address-cells = <2>;
   #size-cells = <2>;
   ranges;

   status = "disabled";

   mdss_mdp: mdp@ae01000 {
    compatible = "qcom,sc8180x-dpu";
    reg = <0 0x0ae01000 0 0x8f000>,
          <0 0x0aeb0000 0 0x3000>;
    reg-names = "mdp", "vbif";

    clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
      <&gcc GCC_DISP_HF_AXI_CLK>,
      <&dispcc DISP_CC_MDSS_MDP_CLK>,
      <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
      <&dispcc DISP_CC_MDSS_ROT_CLK>,
      <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>;
    clock-names = "iface",
           "bus",
           "core",
           "vsync",
           "rot",
           "lut";

    assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
    assigned-clock-rates = <19200000>;

    operating-points-v2 = <&mdp_opp_table>;
    power-domains = <&rpmhpd SC8180X_MMCX>;

    interrupt-parent = <&mdss>;
    interrupts = <0>;

    ports {
     #address-cells = <1>;
     #size-cells = <0>;

     port@0 {
      reg = <0>;
      dpu_intf0_out: endpoint {
       remote-endpoint = <&dp0_in>;
      };
     };

     port@1 {
      reg = <1>;
      dpu_intf1_out: endpoint {
       remote-endpoint = <&mdss_dsi0_in>;
      };
     };

     port@2 {
      reg = <2>;
      dpu_intf2_out: endpoint {
       remote-endpoint = <&mdss_dsi1_in>;
      };
     };

     port@4 {
      reg = <4>;
      dpu_intf4_out: endpoint {
       remote-endpoint = <&dp1_in>;
      };
     };

     port@5 {
      reg = <5>;
      dpu_intf5_out: endpoint {
       remote-endpoint = <&edp_in>;
      };
     };
    };

    mdp_opp_table: opp-table {
     compatible = "operating-points-v2";

     opp-200000000 {
      opp-hz = /bits/ 64 <200000000>;
      required-opps = <&rpmhpd_opp_low_svs>;
     };

     opp-300000000 {
      opp-hz = /bits/ 64 <300000000>;
      required-opps = <&rpmhpd_opp_svs>;
     };

     opp-345000000 {
      opp-hz = /bits/ 64 <345000000>;
      required-opps = <&rpmhpd_opp_svs_l1>;
     };

     opp-460000000 {
      opp-hz = /bits/ 64 <460000000>;
      required-opps = <&rpmhpd_opp_nom>;
     };
    };
   };

   mdss_dsi0: dsi@ae94000 {
    compatible = "qcom,mdss-dsi-ctrl";
    reg = <0 0x0ae94000 0 0x400>;
    reg-names = "dsi_ctrl";

    interrupt-parent = <&mdss>;
    interrupts = <4>;

    clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
      <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
      <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
      <&dispcc DISP_CC_MDSS_ESC0_CLK>,
      <&dispcc DISP_CC_MDSS_AHB_CLK>,
      <&gcc GCC_DISP_HF_AXI_CLK>;
    clock-names = "byte",
           "byte_intf",
           "pixel",
           "core",
           "iface",
           "bus";

    operating-points-v2 = <&dsi_opp_table>;
    power-domains = <&rpmhpd SC8180X_MMCX>;

    phys = <&mdss_dsi0_phy>;
    phy-names = "dsi";

    status = "disabled";

    ports {
     #address-cells = <1>;
     #size-cells = <0>;

     port@0 {
      reg = <0>;
      mdss_dsi0_in: endpoint {
       remote-endpoint = <&dpu_intf1_out>;
      };
     };

     port@1 {
      reg = <1>;
      mdss_dsi0_out: endpoint {
      };
     };
    };

    dsi_opp_table: opp-table {
     compatible = "operating-points-v2";

     opp-187500000 {
      opp-hz = /bits/ 64 <187500000>;
      required-opps = <&rpmhpd_opp_low_svs>;
     };

     opp-300000000 {
      opp-hz = /bits/ 64 <300000000>;
      required-opps = <&rpmhpd_opp_svs>;
     };

     opp-358000000 {
      opp-hz = /bits/ 64 <358000000>;
      required-opps = <&rpmhpd_opp_svs_l1>;
     };
    };
   };

   mdss_dsi0_phy: dsi-phy@ae94400 {
    compatible = "qcom,dsi-phy-7nm";
    reg = <0 0x0ae94400 0 0x200>,
          <0 0x0ae94600 0 0x280>,
          <0 0x0ae94900 0 0x260>;
    reg-names = "dsi_phy",
         "dsi_phy_lane",
         "dsi_pll";

    #clock-cells = <1>;
    #phy-cells = <0>;

    clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
      <&rpmhcc RPMH_CXO_CLK>;
    clock-names = "iface", "ref";

    status = "disabled";
   };

   mdss_dsi1: dsi@ae96000 {
    compatible = "qcom,mdss-dsi-ctrl";
    reg = <0 0x0ae96000 0 0x400>;
    reg-names = "dsi_ctrl";

    interrupt-parent = <&mdss>;
    interrupts = <5>;

    clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
      <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
      <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
      <&dispcc DISP_CC_MDSS_ESC1_CLK>,
      <&dispcc DISP_CC_MDSS_AHB_CLK>,
      <&gcc GCC_DISP_HF_AXI_CLK>;
    clock-names = "byte",
           "byte_intf",
           "pixel",
           "core",
           "iface",
           "bus";

    operating-points-v2 = <&dsi_opp_table>;
    power-domains = <&rpmhpd SC8180X_MMCX>;

    phys = <&mdss_dsi1_phy>;
    phy-names = "dsi";

    status = "disabled";

    ports {
     #address-cells = <1>;
     #size-cells = <0>;

     port@0 {
      reg = <0>;
      mdss_dsi1_in: endpoint {
       remote-endpoint = <&dpu_intf2_out>;
      };
     };

     port@1 {
      reg = <1>;
      mdss_dsi1_out: endpoint {
      };
     };
    };
   };

   mdss_dsi1_phy: dsi-phy@ae96400 {
    compatible = "qcom,dsi-phy-7nm";
    reg = <0 0x0ae96400 0 0x200>,
          <0 0x0ae96600 0 0x280>,
          <0 0x0ae96900 0 0x260>;
    reg-names = "dsi_phy",
         "dsi_phy_lane",
         "dsi_pll";

    #clock-cells = <1>;
    #phy-cells = <0>;

    clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
      <&rpmhcc RPMH_CXO_CLK>;
    clock-names = "iface", "ref";

    status = "disabled";
   };

   mdss_dp0: displayport-controller@ae90000 {
    compatible = "qcom,sc8180x-dp";
    reg = <0 0xae90000 0 0x200>,
          <0 0xae90200 0 0x200>,
          <0 0xae90400 0 0x600>,
          <0 0xae90a00 0 0x400>,
          <0 0xae91000 0 0x400>;
    interrupt-parent = <&mdss>;
    interrupts = <12>;
    clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
      <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
      <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
      <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
      <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
    clock-names = "core_iface",
           "core_aux",
           "ctrl_link",
           "ctrl_link_iface",
           "stream_pixel";

    assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
        <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
    assigned-clock-parents = <&usb_prim_qmpphy QMP_USB43DP_DP_LINK_CLK>,
        <&usb_prim_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;

    phys = <&usb_prim_qmpphy QMP_USB43DP_DP_PHY>;
    phy-names = "dp";

    #sound-dai-cells = <0>;

    operating-points-v2 = <&dp0_opp_table>;
    power-domains = <&rpmhpd SC8180X_MMCX>;

    status = "disabled";

    ports {
     #address-cells = <1>;
     #size-cells = <0>;

     port@0 {
      reg = <0>;
      dp0_in: endpoint {
       remote-endpoint = <&dpu_intf0_out>;
      };
     };

     port@1 {
      reg = <1>;
      mdss_dp0_out: endpoint {
      };
     };
    };

    dp0_opp_table: opp-table {
     compatible = "operating-points-v2";

     opp-160000000 {
      opp-hz = /bits/ 64 <160000000>;
      required-opps = <&rpmhpd_opp_low_svs>;
     };

     opp-270000000 {
      opp-hz = /bits/ 64 <270000000>;
      required-opps = <&rpmhpd_opp_svs>;
     };

     opp-540000000 {
      opp-hz = /bits/ 64 <540000000>;
      required-opps = <&rpmhpd_opp_svs_l1>;
     };

     opp-810000000 {
      opp-hz = /bits/ 64 <810000000>;
      required-opps = <&rpmhpd_opp_nom>;
     };
    };
   };

   mdss_dp1: displayport-controller@ae98000 {
    compatible = "qcom,sc8180x-dp";
    reg = <0 0xae98000 0 0x200>,
          <0 0xae98200 0 0x200>,
          <0 0xae98400 0 0x600>,
          <0 0xae98a00 0 0x400>,
          <0 0xae99000 0 0x400>;
    interrupt-parent = <&mdss>;
    interrupts = <13>;
    clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
      <&dispcc DISP_CC_MDSS_DP_AUX1_CLK>,
      <&dispcc DISP_CC_MDSS_DP_LINK1_CLK>,
      <&dispcc DISP_CC_MDSS_DP_LINK1_INTF_CLK>,
      <&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK>;
    clock-names = "core_iface",
           "core_aux",
           "ctrl_link",
           "ctrl_link_iface",
           "stream_pixel";

    assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK1_CLK_SRC>,
        <&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK_SRC>;
    assigned-clock-parents = <&usb_sec_qmpphy QMP_USB43DP_DP_LINK_CLK>,
        <&usb_sec_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;

    phys = <&usb_sec_qmpphy QMP_USB43DP_DP_PHY>;
    phy-names = "dp";

    #sound-dai-cells = <0>;

    operating-points-v2 = <&dp0_opp_table>;
    power-domains = <&rpmhpd SC8180X_MMCX>;

    status = "disabled";

    ports {
     #address-cells = <1>;
     #size-cells = <0>;

     port@0 {
      reg = <0>;
      dp1_in: endpoint {
       remote-endpoint = <&dpu_intf4_out>;
      };
     };

     port@1 {
      reg = <1>;
      mdss_dp1_out: endpoint {
      };
     };
    };

    dp1_opp_table: opp-table {
     compatible = "operating-points-v2";

     opp-160000000 {
      opp-hz = /bits/ 64 <160000000>;
      required-opps = <&rpmhpd_opp_low_svs>;
     };

     opp-270000000 {
      opp-hz = /bits/ 64 <270000000>;
      required-opps = <&rpmhpd_opp_svs>;
     };

     opp-540000000 {
      opp-hz = /bits/ 64 <540000000>;
      required-opps = <&rpmhpd_opp_svs_l1>;
     };

     opp-810000000 {
      opp-hz = /bits/ 64 <810000000>;
      required-opps = <&rpmhpd_opp_nom>;
     };
    };
   };

   mdss_edp: displayport-controller@ae9a000 {
    compatible = "qcom,sc8180x-edp";
    reg = <0 0xae9a000 0 0x200>,
          <0 0xae9a200 0 0x200>,
          <0 0xae9a400 0 0x600>,
          <0 0xae9aa00 0 0x400>;
    interrupt-parent = <&mdss>;
    interrupts = <14>;
    clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
      <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>,
      <&dispcc DISP_CC_MDSS_EDP_LINK_CLK>,
      <&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>,
      <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>;
    clock-names = "core_iface",
           "core_aux",
           "ctrl_link",
            "ctrl_link_iface",
           "stream_pixel";

    assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>,
        <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>;
    assigned-clock-parents = <&edp_phy 0>, <&edp_phy 1>;

    phys = <&edp_phy>;
    phy-names = "dp";

    operating-points-v2 = <&edp_opp_table>;
    power-domains = <&rpmhpd SC8180X_MMCX>;

    status = "disabled";

    ports {
     #address-cells = <1>;
     #size-cells = <0>;

     port@0 {
      reg = <0>;
      edp_in: endpoint {
       remote-endpoint = <&dpu_intf5_out>;
      };
     };
    };

    edp_opp_table: opp-table {
     compatible = "operating-points-v2";

     opp-160000000 {
      opp-hz = /bits/ 64 <160000000>;
      required-opps = <&rpmhpd_opp_low_svs>;
     };

     opp-270000000 {
      opp-hz = /bits/ 64 <270000000>;
      required-opps = <&rpmhpd_opp_svs>;
     };

     opp-540000000 {
      opp-hz = /bits/ 64 <540000000>;
      required-opps = <&rpmhpd_opp_svs_l1>;
     };

     opp-810000000 {
      opp-hz = /bits/ 64 <810000000>;
      required-opps = <&rpmhpd_opp_nom>;
     };
    };
   };
  };

  edp_phy: phy@aec2a00 {
   compatible = "qcom,sc8180x-edp-phy";
   reg = <0 0x0aec2a00 0 0x1c0>,
         <0 0x0aec2200 0 0xa0>,
         <0 0x0aec2600 0 0xa0>,
         <0 0x0aec2000 0 0x19c>;

   clocks = <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>,
     <&dispcc DISP_CC_MDSS_AHB_CLK>;
   clock-names = "aux", "cfg_ahb";

   power-domains = <&rpmhpd SC8180X_MX>;

   #clock-cells = <1>;
   #phy-cells = <0>;
  };

  dispcc: clock-controller@af00000 {
   compatible = "qcom,sc8180x-dispcc";
   reg = <0 0x0af00000 0 0x20000>;
   clocks = <&rpmhcc RPMH_CXO_CLK>,
     <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
     <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>,
     <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>,
     <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>,
     <&usb_prim_qmpphy QMP_USB43DP_DP_LINK_CLK>,
     <&usb_prim_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
     <&edp_phy 0>,
     <&edp_phy 1>,
     <&usb_sec_qmpphy QMP_USB43DP_DP_LINK_CLK>,
     <&usb_sec_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
   clock-names = "bi_tcxo",
          "dsi0_phy_pll_out_byteclk",
          "dsi0_phy_pll_out_dsiclk",
          "dsi1_phy_pll_out_byteclk",
          "dsi1_phy_pll_out_dsiclk",
          "dp_phy_pll_link_clk",
          "dp_phy_pll_vco_div_clk",
          "edp_phy_pll_link_clk",
          "edp_phy_pll_vco_div_clk",
          "dptx1_phy_pll_link_clk",
          "dptx1_phy_pll_vco_div_clk";
   power-domains = <&rpmhpd SC8180X_MMCX>;
   required-opps = <&rpmhpd_opp_low_svs>;
   #clock-cells = <1>;
   #reset-cells = <1>;
   #power-domain-cells = <1>;
  };

  pdc: interrupt-controller@b220000 {
   compatible = "qcom,sc8180x-pdc", "qcom,pdc";
   reg = <0 0x0b220000 0 0x30000>;
   qcom,pdc-ranges = <0 480 94>, <94 609 31>;
   #interrupt-cells = <2>;
   interrupt-parent = <&intc>;
   interrupt-controller;
  };

  tsens0: thermal-sensor@c263000 {
   compatible = "qcom,sc8180x-tsens", "qcom,tsens-v2";
   reg = <0 0x0c263000 0 0x1ff>, /* TM */
         <0 0x0c222000 0 0x1ff>; /* SROT */
   #qcom,sensors = <16>;
   interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
   interrupt-names = "uplow", "critical";
   #thermal-sensor-cells = <1>;
  };

  tsens1: thermal-sensor@c265000 {
   compatible = "qcom,sc8180x-tsens", "qcom,tsens-v2";
   reg = <0 0x0c265000 0 0x1ff>, /* TM */
         <0 0x0c223000 0 0x1ff>; /* SROT */
   #qcom,sensors = <9>;
   interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
   interrupt-names = "uplow", "critical";
   #thermal-sensor-cells = <1>;
  };

  aoss_qmp: power-management@c300000 {
   compatible = "qcom,sc8180x-aoss-qmp", "qcom,aoss-qmp";
   reg = <0x0 0x0c300000 0x0 0x400>;
   interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
   mboxes = <&apss_shared 0>;

   #clock-cells = <0>;
  };

  sram@c3f0000 {
   compatible = "qcom,rpmh-stats";
   reg = <0x0 0x0c3f0000 0x0 0x400>;
  };

  spmi_bus: spmi@c440000 {
   compatible = "qcom,spmi-pmic-arb";
   reg = <0x0 0x0c440000 0x0 0x0001100>,
         <0x0 0x0c600000 0x0 0x2000000>,
         <0x0 0x0e600000 0x0 0x0100000>,
         <0x0 0x0e700000 0x0 0x00a0000>,
         <0x0 0x0c40a000 0x0 0x0026000>;
   reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
   interrupt-names = "periph_irq";
   interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
   qcom,ee = <0>;
   qcom,channel = <0>;
   #address-cells = <2>;
   #size-cells = <0>;
   interrupt-controller;
   #interrupt-cells = <4>;
  };

  apps_smmu: iommu@15000000 {
   compatible = "qcom,sc8180x-smmu-500", "arm,mmu-500";
   reg = <0 0x15000000 0 0x100000>;
   #iommu-cells = <2>;
   #global-interrupts = <1>;
   interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 768 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 771 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 775 IRQ_TYPE_LEVEL_HIGH>;
   dma-coherent;
  };

  remoteproc_adsp: remoteproc@17300000 {
   compatible = "qcom,sc8180x-adsp-pas";
   reg = <0x0 0x17300000 0x0 0x4040>;

   interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
           <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
           <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
           <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
           <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
   interrupt-names = "wdog", "fatal", "ready",
       "handover", "stop-ack";

   clocks = <&rpmhcc RPMH_CXO_CLK>;
   clock-names = "xo";

   power-domains = <&rpmhpd SC8180X_CX>;
   power-domain-names = "cx";

   qcom,qmp = <&aoss_qmp>;

   qcom,smem-states = <&adsp_smp2p_out 0>;
   qcom,smem-state-names = "stop";

   status = "disabled";

   remoteproc_adsp_glink: glink-edge {
    interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
    label = "lpass";
    qcom,remote-pid = <2>;
    mboxes = <&apss_shared 8>;
   };
  };

  intc: interrupt-controller@17a00000 {
   compatible = "arm,gic-v3";
   interrupt-controller;
   #interrupt-cells = <3>;
   reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
         <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
   interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
   #redistributor-regions = <1>;
   redistributor-stride = <0 0x20000>;
  };

  apss_shared: mailbox@17c00000 {
   compatible = "qcom,sc8180x-apss-shared", "qcom,sdm845-apss-shared";
   reg = <0x0 0x17c00000 0x0 0x1000>;
   #mbox-cells = <1>;
  };

  timer@17c20000 {
   compatible = "arm,armv7-timer-mem";
   reg = <0x0 0x17c20000 0x0 0x1000>;

   #address-cells = <1>;
   #size-cells = <1>;
   ranges = <0 0 0 0x20000000>;

   frame@17c21000 {
    reg = <0x17c21000 0x1000>,
          <0x17c22000 0x1000>;
    frame-number = <0>;
    interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
          <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
   };

   frame@17c23000 {
    reg = <0x17c23000 0x1000>;
    frame-number = <1>;
    interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
    status = "disabled";
   };

   frame@17c25000 {
    reg = <0x17c25000 0x1000>;
    frame-number = <2>;
    interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
    status = "disabled";
   };

   frame@17c27000 {
    reg = <0x17c26000 0x1000>;
    frame-number = <3>;
    interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
    status = "disabled";
   };

   frame@17c29000 {
    reg = <0x17c29000 0x1000>;
    frame-number = <4>;
    interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
    status = "disabled";
   };

   frame@17c2b000 {
    reg = <0x17c2b000 0x1000>;
    frame-number = <5>;
    interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
    status = "disabled";
   };

   frame@17c2d000 {
    reg = <0x17c2d000 0x1000>;
    frame-number = <6>;
    interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
    status = "disabled";
   };
  };

  apps_rsc: rsc@18200000 {
   compatible = "qcom,rpmh-rsc";
   reg = <0x0 0x18200000 0x0 0x10000>,
         <0x0 0x18210000 0x0 0x10000>,
         <0x0 0x18220000 0x0 0x10000>;
   reg-names = "drv-0", "drv-1", "drv-2";
   interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
   qcom,tcs-offset = <0xd00>;
   qcom,drv-id = <2>;
   qcom,tcs-config = <ACTIVE_TCS  2>,
       <SLEEP_TCS   1>,
       <WAKE_TCS    1>,
       <CONTROL_TCS 0>;
   label = "apps_rsc";
   power-domains = <&cluster_pd>;

   apps_bcm_voter: bcm-voter {
    compatible = "qcom,bcm-voter";
   };

   rpmhcc: clock-controller {
    compatible = "qcom,sc8180x-rpmh-clk";
    #clock-cells = <1>;
    clock-names = "xo";
    clocks = <&xo_board_clk>;
   };

   rpmhpd: power-controller {
    compatible = "qcom,sc8180x-rpmhpd";
    #power-domain-cells = <1>;
    operating-points-v2 = <&rpmhpd_opp_table>;

    rpmhpd_opp_table: opp-table {
     compatible = "operating-points-v2";

     rpmhpd_opp_ret: opp1 {
      opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
     };

     rpmhpd_opp_min_svs: opp2 {
      opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
     };

     rpmhpd_opp_low_svs: opp3 {
      opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
     };

     rpmhpd_opp_svs: opp4 {
      opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
     };

     rpmhpd_opp_svs_l1: opp5 {
      opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
     };

     rpmhpd_opp_nom: opp6 {
      opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
     };

     rpmhpd_opp_nom_l1: opp7 {
      opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
     };

     rpmhpd_opp_nom_l2: opp8 {
      opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
     };

     rpmhpd_opp_turbo: opp9 {
      opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
     };

     rpmhpd_opp_turbo_l1: opp10 {
      opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
     };
    };
   };
  };

  osm_l3: interconnect@18321000 {
   compatible = "qcom,sc8180x-osm-l3", "qcom,osm-l3";
   reg = <0 0x18321000 0 0x1400>;

   clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
   clock-names = "xo", "alternate";

   #interconnect-cells = <1>;
  };

  lmh@18350800 {
   compatible = "qcom,sc8180x-lmh";
   reg = <0 0x18350800 0 0x400>;
   interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
   cpus = <&cpu4>;
   qcom,lmh-temp-arm-millicelsius = <65000>;
   qcom,lmh-temp-low-millicelsius = <94500>;
   qcom,lmh-temp-high-millicelsius = <95000>;
   interrupt-controller;
   #interrupt-cells = <1>;
  };

  lmh@18358800 {
   compatible = "qcom,sc8180x-lmh";
   reg = <0 0x18358800 0 0x400>;
   interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
   cpus = <&cpu0>;
   qcom,lmh-temp-arm-millicelsius = <65000>;
   qcom,lmh-temp-low-millicelsius = <94500>;
   qcom,lmh-temp-high-millicelsius = <95000>;
   interrupt-controller;
   #interrupt-cells = <1>;
  };

  cpufreq_hw: cpufreq@18323000 {
   compatible = "qcom,sc8180x-cpufreq-hw", "qcom,cpufreq-hw";
   reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>;
   reg-names = "freq-domain0", "freq-domain1";

   clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
   clock-names = "xo", "alternate";

   #freq-domain-cells = <1>;
   #clock-cells = <1>;
  };

  wifi: wifi@18800000 {
   compatible = "qcom,wcn3990-wifi";
   reg = <0 0x18800000 0 0x800000>;
   reg-names = "membase";
   clock-names = "cxo_ref_clk_pin";
   clocks = <&rpmhcc RPMH_RF_CLK2>;
   interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
   iommus = <&apps_smmu 0x0640 0x1>;
   qcom,msa-fixed-perm;
   status = "disabled";
  };
 };

 thermal-zones {
  cpu0-thermal {
   polling-delay-passive = <250>;

   thermal-sensors = <&tsens0 1>;

   trips {
    cpu-crit {
     temperature = <110000>;
     hysteresis = <1000>;
     type = "critical";
    };
   };
  };

  cpu1-thermal {
   polling-delay-passive = <250>;

   thermal-sensors = <&tsens0 2>;

   trips {
    cpu-crit {
     temperature = <110000>;
     hysteresis = <1000>;
     type = "critical";
    };
   };
  };

  cpu2-thermal {
   polling-delay-passive = <250>;

   thermal-sensors = <&tsens0 3>;

   trips {
    cpu-crit {
     temperature = <110000>;
     hysteresis = <1000>;
     type = "critical";
    };
   };
  };

  cpu3-thermal {
   polling-delay-passive = <250>;

   thermal-sensors = <&tsens0 4>;

   trips {
    cpu-crit {
     temperature = <110000>;
     hysteresis = <1000>;
     type = "critical";
    };
   };
  };

  cpu4-top-thermal {
   polling-delay-passive = <250>;

   thermal-sensors = <&tsens0 7>;

   trips {
    cpu-crit {
     temperature = <110000>;
     hysteresis = <1000>;
     type = "critical";
    };
   };
  };

  cpu5-top-thermal {
   polling-delay-passive = <250>;

   thermal-sensors = <&tsens0 8>;

   trips {
    cpu-crit {
     temperature = <110000>;
     hysteresis = <1000>;
     type = "critical";
    };
   };
  };

  cpu6-top-thermal {
   polling-delay-passive = <250>;

   thermal-sensors = <&tsens0 9>;

   trips {
    cpu-crit {
     temperature = <110000>;
     hysteresis = <1000>;
     type = "critical";
    };
   };
  };

  cpu7-top-thermal {
   polling-delay-passive = <250>;

   thermal-sensors = <&tsens0 10>;

   trips {
    cpu-crit {
     temperature = <110000>;
     hysteresis = <1000>;
     type = "critical";
    };
   };
  };

  cpu4-bottom-thermal {
   polling-delay-passive = <250>;

   thermal-sensors = <&tsens0 11>;

   trips {
    cpu-crit {
     temperature = <110000>;
     hysteresis = <1000>;
     type = "critical";
    };
   };
  };

  cpu5-bottom-thermal {
   polling-delay-passive = <250>;

   thermal-sensors = <&tsens0 12>;

   trips {
    cpu-crit {
     temperature = <110000>;
     hysteresis = <1000>;
     type = "critical";
    };
   };
  };

  cpu6-bottom-thermal {
   polling-delay-passive = <250>;

   thermal-sensors = <&tsens0 13>;

   trips {
    cpu-crit {
     temperature = <110000>;
     hysteresis = <1000>;
     type = "critical";
    };
   };
  };

  cpu7-bottom-thermal {
   polling-delay-passive = <250>;

   thermal-sensors = <&tsens0 14>;

   trips {
    cpu-crit {
     temperature = <110000>;
     hysteresis = <1000>;
     type = "critical";
    };
   };
  };

  aoss0-thermal {
   polling-delay-passive = <250>;

   thermal-sensors = <&tsens0 0>;

   trips {
    trip-point0 {
     temperature = <90000>;
     hysteresis = <2000>;
     type = "hot";
    };
   };
  };

  cluster0-thermal {
   polling-delay-passive = <250>;

   thermal-sensors = <&tsens0 5>;

   trips {
    cluster-crit {
     temperature = <110000>;
     hysteresis = <2000>;
     type = "critical";
    };
   };
  };

  cluster1-thermal {
   polling-delay-passive = <250>;

   thermal-sensors = <&tsens0 6>;

   trips {
    cluster-crit {
     temperature = <110000>;
     hysteresis = <2000>;
     type = "critical";
    };
   };
  };

  gpu-top-thermal {
   polling-delay-passive = <250>;

   thermal-sensors = <&tsens0 15>;

   cooling-maps {
    map0 {
     trip = <&gpu_top_alert0>;
     cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
    };
   };

   trips {
    gpu_top_alert0: trip-point0 {
     temperature = <85000>;
     hysteresis = <1000>;
     type = "passive";
    };

    trip-point1 {
     temperature = <90000>;
     hysteresis = <1000>;
     type = "hot";
    };

    trip-point2 {
     temperature = <110000>;
     hysteresis = <1000>;
     type = "critical";
    };
   };
  };

  aoss1-thermal {
   polling-delay-passive = <250>;

   thermal-sensors = <&tsens1 0>;

   trips {
    trip-point0 {
     temperature = <90000>;
     hysteresis = <2000>;
     type = "hot";
    };
   };
  };

  wlan-thermal {
   polling-delay-passive = <250>;

   thermal-sensors = <&tsens1 1>;

   trips {
    trip-point0 {
     temperature = <90000>;
     hysteresis = <2000>;
     type = "hot";
    };
   };
  };

  video-thermal {
   polling-delay-passive = <250>;

   thermal-sensors = <&tsens1 2>;

   trips {
    trip-point0 {
     temperature = <90000>;
     hysteresis = <2000>;
     type = "hot";
    };
   };
  };

  mem-thermal {
   polling-delay-passive = <250>;

   thermal-sensors = <&tsens1 3>;

   trips {
    trip-point0 {
     temperature = <90000>;
     hysteresis = <2000>;
     type = "hot";
    };
   };
  };

  q6-hvx-thermal {
   polling-delay-passive = <250>;

   thermal-sensors = <&tsens1 4>;

   trips {
    trip-point0 {
     temperature = <90000>;
     hysteresis = <2000>;
     type = "hot";
    };
   };
  };

  camera-thermal {
   polling-delay-passive = <250>;

   thermal-sensors = <&tsens1 5>;

   trips {
    trip-point0 {
     temperature = <90000>;
     hysteresis = <2000>;
     type = "hot";
    };
   };
  };

  compute-thermal {
   polling-delay-passive = <250>;

   thermal-sensors = <&tsens1 6>;

   trips {
    trip-point0 {
     temperature = <90000>;
     hysteresis = <2000>;
     type = "hot";
    };
   };
  };

  mdm-dsp-thermal {
   polling-delay-passive = <250>;

   thermal-sensors = <&tsens1 7>;

   trips {
    trip-point0 {
     temperature = <90000>;
     hysteresis = <2000>;
     type = "hot";
    };
   };
  };

  npu-thermal {
   polling-delay-passive = <250>;

   thermal-sensors = <&tsens1 8>;

   trips {
    trip-point0 {
     temperature = <90000>;
     hysteresis = <2000>;
     type = "hot";
    };
   };
  };

  gpu-bottom-thermal {
   polling-delay-passive = <250>;

   thermal-sensors = <&tsens1 11>;

   cooling-maps {
    map0 {
     trip = <&gpu_bottom_alert0>;
     cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
    };
   };

   trips {
    gpu_bottom_alert0: trip-point0 {
     temperature = <85000>;
     hysteresis = <1000>;
     type = "passive";
    };

    trip-point1 {
     temperature = <90000>;
     hysteresis = <1000>;
     type = "hot";
    };

    trip-point2 {
     temperature = <110000>;
     hysteresis = <1000>;
     type = "critical";
    };
   };
  };
 };

 timer {
  compatible = "arm,armv8-timer";
  interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
        <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
        <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
        <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
 };
};