// SPDX-License-Identifier: (GPL-2.0 OR MIT)
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
compatible = "brcm,bcm2712";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&gicv2>;
clocks {
/* The oscillator is the root of the clock tree. */
clk_osc: clk-osc {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-output-names = "osc";
clock-frequency = <54000000>;
};
clk_vpu: clk-vpu {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <750000000>;
clock-output-names = "vpu-clock";
};
clk_uart: clk-uart {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <9216000>;
clock-output-names = "uart-clock";
};
clk_emmc2: clk-emmc2 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
clock-output-names = "emmc2-clock";
};
};
cpus: cpus {
#address-cells = <1>;
#size-cells = <0>;
/* Source for L1 d/i cache-line-size, cache-sets, cache-size
*
https://developer.arm.com/documentation/100798/0401/L1-memory-system/About-the-L1-memory-system?lang=en
* Source for L2 cache-line-size and cache-sets:
*
https://developer.arm.com/documentation/100798/0401/L2-memory-system/About-the-L2-memory-system?lang=en
* and for cache-size:
*
https://www.raspberrypi.com/documentation/computers/processors.html#bcm2712
*/
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a76";
reg = <0x000>;
enable-method = "psci";
d-cache-size = <0x10000>;
d-cache-line-size = <64>;
d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
i-cache-size = <0x10000>;
i-cache-line-size = <64>;
i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
next-level-cache = <&l2_cache_l0>;
l2_cache_l0: l2-cache {
compatible = "cache";
cache-size = <0x80000>;
cache-line-size = <64>;
cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set
cache-level = <2>;
cache-unified;
next-level-cache = <&l3_cache>;
};
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a76";
reg = <0x100>;
enable-method = "psci";
d-cache-size = <0x10000>;
d-cache-line-size = <64>;
d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
i-cache-size = <0x10000>;
i-cache-line-size = <64>;
i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
next-level-cache = <&l2_cache_l1>;
l2_cache_l1: l2-cache {
compatible = "cache";
cache-size = <0x80000>;
cache-line-size = <64>;
cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set
cache-level = <2>;
cache-unified;
next-level-cache = <&l3_cache>;
};
};
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a76";
reg = <0x200>;
enable-method = "psci";
d-cache-size = <0x10000>;
d-cache-line-size = <64>;
d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
i-cache-size = <0x10000>;
i-cache-line-size = <64>;
i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
next-level-cache = <&l2_cache_l2>;
l2_cache_l2: l2-cache {
compatible = "cache";
cache-size = <0x80000>;
cache-line-size = <64>;
cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set
cache-level = <2>;
cache-unified;
next-level-cache = <&l3_cache>;
};
};
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a76";
reg = <0x300>;
enable-method = "psci";
d-cache-size = <0x10000>;
d-cache-line-size = <64>;
d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
i-cache-size = <0x10000>;
i-cache-line-size = <64>;
i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
next-level-cache = <&l2_cache_l3>;
l2_cache_l3: l2-cache {
compatible = "cache";
cache-size = <0x80000>;
cache-line-size = <64>;
cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set
cache-level = <2>;
cache-unified;
next-level-cache = <&l3_cache>;
};
};
/* Source for cache-line-size and cache-sets:
*
https://developer.arm.com/documentation/100453/0401/L3-cache?lang=en
* Source for cache-size:
*
https://www.raspberrypi.com/documentation/computers/processors.html#bcm2712
*/
l3_cache: l3-cache {
compatible = "cache";
cache-size = <0x200000>;
cache-line-size = <64>;
cache-sets = <2048>; // 2MiB(size)/64(line-size)=32768ways/16-way set
cache-level = <3>;
cache-unified;
};
};
psci {
method = "smc";
compatible = "arm,psci-1.0", "arm,psci-0.2";
};
rmem: reserved-memory {
ranges;
#address-cells = <2>;
#size-cells = <2>;
atf@0 {
reg = <0x0 0x0 0x0 0x80000>;
no-map;
};
cma: linux,cma {
compatible = "shared-dma-pool";
size = <0x0 0x4000000>; /* 64MB */
reusable;
linux,cma-default;
alloc-ranges = <0x0 0x00000000 0x0 0x40000000>;
};
};
soc: soc@107c000000 {
compatible = "simple-bus";
ranges = <0x00000000 0x10 0x00000000 0x80000000>;
#address-cells = <1>;
#size-cells = <1>;
pcie_rescal: reset-controller@119500 {
compatible = "brcm,bcm7216-pcie-sata-rescal";
reg = <0x00119500 0x10>;
#reset-cells = <0>;
};
sdio1: mmc@fff000 {
compatible = "brcm,bcm2712-sdhci",
"brcm,sdhci-brcmstb";
reg = <0x00fff000 0x260>,
<0x00fff400 0x200>;
reg-names = "host", "cfg";
interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_emmc2>;
clock-names = "sw_sdio";
mmc-ddr-3_3v;
};
bcm_reset: reset-controller@1504318 {
compatible = "brcm,brcmstb-reset";
reg = <0x01504318 0x30>;
#reset-cells = <1>;
};
system_timer: timer@7c003000 {
compatible = "brcm,bcm2835-system-timer";
reg = <0x7c003000 0x1000>;
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <1000000>;
};
mailbox: mailbox@7c013880 {
compatible = "brcm,bcm2835-mbox";
reg = <0x7c013880 0x40>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <0>;
};
uart10: serial@7d001000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x7d001000 0x200>;
interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_uart>, <&clk_vpu>;
clock-names = "uartclk", "apb_pclk";
arm,primecell-periphid = <0x00341011>;
status = "disabled";
};
interrupt-controller@7d517000 {
compatible = "brcm,bcm7271-l2-intc";
reg = <0x7d517000 0x10>;
interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <1>;
};
gio_aon: gpio@7d517c00 {
compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio";
reg = <0x7d517c00 0x40>;
gpio-controller;
#gpio-cells = <2>;
brcm,gpio-bank-widths = <17 6>;
/* The lack of 'interrupt-controller' property here is intended:
* don't use GIO_AON as an interrupt controller because it will
* clash with the firmware monitoring the PMIC interrupt via the VPU.
*/
};
gicv2: interrupt-controller@7fff9000 {
compatible = "arm,gic-400";
reg = <0x7fff9000 0x1000>,
<0x7fffa000 0x2000>,
<0x7fffc000 0x2000>,
<0x7fffe000 0x2000>;
interrupt-controller;
#address-cells = <0>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_HIGH)>;
#interrupt-cells = <3>;
};
aon_intr: interrupt-controller@7d510600 {
compatible = "brcm,bcm2711-l2-intc", "brcm,l2-intc";
reg = <0x7d510600 0x30>;
interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <1>;
};
pixelvalve0: pixelvalve@7c410000 {
compatible = "brcm,bcm2712-pixelvalve0";
reg = <0x7c410000 0x100>;
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
};
pixelvalve1: pixelvalve@7c411000 {
compatible = "brcm,bcm2712-pixelvalve1";
reg = <0x7c411000 0x100>;
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
};
mop: mop@7c500000 {
compatible = "brcm,bcm2712-mop";
reg = <0x7c500000 0x28>;
interrupt-parent = <&disp_intr>;
interrupts = <1>;
};
moplet: moplet@7c501000 {
compatible = "brcm,bcm2712-moplet";
reg = <0x7c501000 0x20>;
interrupt-parent = <&disp_intr>;
interrupts = <0>;
};
disp_intr: interrupt-controller@7c502000 {
compatible = "brcm,bcm2711-l2-intc", "brcm,l2-intc";
reg = <0x7c502000 0x30>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <1>;
};
dvp: clock@7c700000 {
compatible = "brcm,brcm2711-dvp";
reg = <0x7c700000 0x10>;
clocks = <&clk_108MHz>;
#clock-cells = <1>;
#reset-cells = <1>;
};
ddc0: i2c@7d508200 {
compatible = "brcm,brcmstb-i2c";
reg = <0x7d508200 0x58>;
interrupt-parent = <&bsc_irq>;
interrupts = <1>;
clock-frequency = <97500>;
#address-cells = <1>;
#size-cells = <0>;
};
ddc1: i2c@7d508280 {
compatible = "brcm,brcmstb-i2c";
reg = <0x7d508280 0x58>;
interrupt-parent = <&bsc_irq>;
interrupts = <2>;
clock-frequency = <97500>;
#address-cells = <1>;
#size-cells = <0>;
};
bsc_irq: interrupt-controller@7d508380 {
compatible = "brcm,bcm7271-l2-intc";
reg = <0x7d508380 0x10>;
interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <1>;
};
main_irq: interrupt-controller@7d508400 {
compatible = "brcm,bcm7271-l2-intc";
reg = <0x7d508400 0x10>;
interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <1>;
};
hdmi0: hdmi@7c701400 {
compatible = "brcm,bcm2712-hdmi0";
reg = <0x7c701400 0x300>,
<0x7c701000 0x200>,
<0x7c701d00 0x300>,
<0x7c702000 0x80>,
<0x7c703800 0x200>,
<0x7c704000 0x800>,
<0x7c700100 0x80>,
<0x7d510800 0x100>,
<0x7c720000 0x100>;
reg-names = "hdmi",
"dvp",
"phy",
"rm",
"packet",
"metadata",
"csc",
"cec",
"hd";
resets = <&dvp 1>;
interrupt-parent = <&aon_intr>;
interrupts = <1>, <2>, <3>,
<7>, <8>;
interrupt-names = "cec-tx", "cec-rx", "cec-low",
"hpd-connected", "hpd-removed";
ddc = <&ddc0>;
};
hdmi1: hdmi@7c706400 {
compatible = "brcm,bcm2712-hdmi1";
reg = <0x7c706400 0x300>,
<0x7c706000 0x200>,
<0x7c706d00 0x300>,
<0x7c707000 0x80>,
<0x7c708800 0x200>,
<0x7c709000 0x800>,
<0x7c700180 0x80>,
<0x7d511000 0x100>,
<0x7c720000 0x100>;
reg-names = "hdmi",
"dvp",
"phy",
"rm",
"packet",
"metadata",
"csc",
"cec",
"hd";
resets = <&dvp 2>;
interrupt-parent = <&aon_intr>;
interrupts = <11>, <12>, <13>,
<14>, <15>;
interrupt-names = "cec-tx", "cec-rx", "cec-low",
"hpd-connected", "hpd-removed";
ddc = <&ddc1>;
};
};
axi: axi {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x00 0x00000000 0x00 0x00000000 0x10 0x00000000>,
<0x10 0x00000000 0x10 0x00000000 0x01 0x00000000>,
<0x14 0x00000000 0x14 0x00000000 0x04 0x00000000>,
<0x18 0x00000000 0x18 0x00000000 0x04 0x00000000>,
<0x1c 0x00000000 0x1c 0x00000000 0x04 0x00000000>;
dma-ranges = <0x00 0x00000000 0x00 0x00000000 0x10 0x00000000>,
<0x10 0x00000000 0x10 0x00000000 0x01 0x00000000>,
<0x14 0x00000000 0x14 0x00000000 0x04 0x00000000>,
<0x18 0x00000000 0x18 0x00000000 0x04 0x00000000>,
<0x1c 0x00000000 0x1c 0x00000000 0x04 0x00000000>;
vc4: gpu {
compatible = "brcm,bcm2712-vc6";
};
pcie0: pcie@1000100000 {
compatible = "brcm,bcm2712-pcie";
reg = <0x10 0x00100000 0x00 0x9310>;
device_type = "pci";
linux,pci-domain = <0>;
max-link-speed = <2>;
num-lanes = <1>;
#address-cells = <3>;
#interrupt-cells = <1>;
#size-cells = <2>;
interrupt-parent = <&gicv2>;
interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "pcie", "msi";
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2 &gicv2 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &gicv2 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &gicv2 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
resets = <&pcie_rescal>, <&bcm_reset 42>;
reset-names = "rescal", "bridge";
msi-controller;
msi-parent = <&pcie0>;
ranges =
/* ~4GiB, 32-bit, non-prefetchable at PCIe 00_0000_0000 */
<0x02000000 0x00 0x00000000 0x17 0x00000000 0x00 0xfffffffc>,
/* 12GiB, 64-bit, prefetchable at PCIe 04_0000_0000 */
<0x43000000 0x04 0x00000000 0x14 0x00000000 0x03 0x00000000>;
dma-ranges =
/* 64GiB, 64-bit, prefetchable at PCIe 10_0000_0000 */
<0x43000000 0x10 0x00000000 0x00 0x00000000 0x10 0x00000000>;
status = "disabled";
};
pcie1: pcie@1000110000 {
compatible = "brcm,bcm2712-pcie";
reg = <0x10 0x00110000 0x00 0x9310>;
device_type = "pci";
linux,pci-domain = <1>;
max-link-speed = <2>;
num-lanes = <1>;
#address-cells = <3>;
#interrupt-cells = <1>;
#size-cells = <2>;
interrupt-parent = <&gicv2>;
interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "pcie", "msi";
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2 &gicv2 GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &gicv2 GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &gicv2 GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
resets = <&pcie_rescal>, <&bcm_reset 43>;
reset-names = "rescal", "bridge";
msi-controller;
msi-parent = <&mip1>;
ranges =
/* ~4GiB, 32-bit, non-prefetchable at PCIe 00_0000_0000 */
<0x02000000 0x00 0x00000000 0x1b 0x00000000 0x00 0xfffffffc>,
/* 12GiB, 64-bit, prefetchable at PCIe 04_0000_0000 */
<0x43000000 0x04 0x00000000 0x18 0x00000000 0x03 0x00000000>;
dma-ranges =
/* 64GiB, 64-bit, non-prefetchable at PCIe 10_0000_0000 */
<0x03000000 0x10 0x00000000 0x00 0x00000000 0x10 0x00000000>,
/* 4KiB, 64-bit, non-prefetchable at PCIe ff_ffff_f000 MIP1 */
<0x03000000 0xff 0xfffff000 0x10 0x00131000 0x00 0x00001000>;
status = "disabled";
};
pcie2: pcie@1000120000 {
compatible = "brcm,bcm2712-pcie";
reg = <0x10 0x00120000 0x00 0x9310>;
device_type = "pci";
linux,pci-domain = <2>;
max-link-speed = <2>;
num-lanes = <4>;
#address-cells = <3>;
#interrupt-cells = <1>;
#size-cells = <2>;
interrupt-parent = <&gicv2>;
interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "pcie", "msi";
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2 &gicv2 GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &gicv2 GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &gicv2 GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
resets = <&pcie_rescal>, <&bcm_reset 44>;
reset-names = "rescal", "bridge";
msi-controller;
msi-parent = <&mip0>;
ranges =
/* ~4GiB, 32-bit, non-prefetchable at PCIe 00_0000_0000 */
<0x02000000 0x00 0x00000000 0x1f 0x00000000 0x00 0xfffffffc>,
/* 12GiB, 64-bit, prefetchable at PCIe 04_0000_0000 */
<0x43000000 0x04 0x00000000 0x1c 0x00000000 0x03 0x00000000>;
dma-ranges =
/* 4MiB, 32-bit, non-prefetchable at PCIe 00_0000_0000 */
<0x02000000 0x00 0x00000000 0x1f 0x00000000 0x00 0x00400000>,
/* 64GiB, 64-bit, prefetchable at PCIe 10_0000_0000 */
<0x43000000 0x10 0x00000000 0x00 0x00000000 0x10 0x00000000>,
/* 4KiB, 64-bit, non-prefetchable at PCIe ff_ffff_f000 MIP0 */
<0x03000000 0xff 0xfffff000 0x10 0x00130000 0x00 0x00001000>;
status = "disabled";
};
mip0: msi-controller@1000130000 {
compatible = "brcm,bcm2712-mip";
reg = <0x10 0x00130000 0x00 0xc0>,
<0xff 0xfffff000 0x00 0x1000>;
msi-controller;
msi-ranges = <&gicv2 GIC_SPI 128 IRQ_TYPE_EDGE_RISING 64>;
brcm,msi-offset = <0>;
};
mip1: msi-controller@1000131000 {
compatible = "brcm,bcm2712-mip";
reg = <0x10 0x00131000 0x00 0xc0>,
<0xff 0xfffff000 0x00 0x1000>;
msi-controller;
msi-ranges = <&gicv2 GIC_SPI 247 IRQ_TYPE_EDGE_RISING 8>;
brcm,msi-offset = <8>;
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_LOW)>;
};
clk_27MHz: clk-27M {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <27000000>;
clock-output-names = "27MHz-clock";
};
clk_108MHz: clk-108M {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <108000000>;
clock-output-names = "108MHz-clock";
};
hvs: hvs@107c580000 {
compatible = "brcm,bcm2712-hvs";
reg = <0x10 0x7c580000 0x0 0x1a000>;
interrupt-parent = <&disp_intr>;
interrupts = <2>, <9>, <16>;
interrupt-names = "ch0-eof", "ch1-eof", "ch2-eof";
};
};
