// SPDX-License-Identifier: GPL-2.0-only /* * arch/arm/kernel/kprobes-test-arm.c * * Copyright (C) 2011 Jon Medhurst <tixy@yxit.co.uk>. #include <linux/kernel.h>#include <linux/module.h>#include <asm /system_info.h>#include <asm /opcodes.h>#include <asm /probes.h>#include "test-core.h" #define TEST_ISA "32" #define TEST_ARM_TO_THUMB_INTERWORK_R(code1, reg, val, code2) \#reg code2) \"" ) \"50: nop \n\t" \"1: " code1 #reg code2" \n\t" \" bx lr \n\t" \".thumb \n\t" \"3: adr lr, 2f \n\t" \" bx lr \n\t" \".arm \n\t" \"2: nop \n\t" \#define TEST_ARM_TO_THUMB_INTERWORK_P(code1, reg, val, code2) \#reg code2) \"" ) \"50: nop \n\t" \"1: " code1 #reg code2" \n\t" \" bx lr \n\t" \".thumb \n\t" \"3: adr lr, 2f \n\t" \" bx lr \n\t" \".arm \n\t" \"2: nop \n\t" \void kprobe_arm_test_cases(void )"Data-processing (register), (register-shifted register), (immediate)" )#define _DATA_PROCESSING_DNM(op,s,val) \"eq r0, r" ,1, VAL1,", r" ,2, val, "" ) \"ne r1, r" ,1, VAL1,", r" ,2, val, ", lsl #3" ) \"cs r2, r" ,3, VAL1,", r" ,2, val, ", lsr #4" ) \"cc r3, r" ,3, VAL1,", r" ,2, val, ", asr #5" ) \"mi r4, r" ,5, VAL1,", r" ,2, N(val),", asr #6" ) \"pl r5, r" ,5, VAL1,", r" ,2, val, ", ror #7" ) \"vs r6, r" ,7, VAL1,", r" ,2, val, ", rrx" ) \"vc r6, r" ,7, VAL1,", pc, lsl #3" ) \"vc r6, r" ,7, VAL1,", sp, lsr #4" ) \"vc r6, pc, r" ,7, VAL1,", asr #5" ) \"vc r6, sp, r" ,7, VAL1,", ror #6" ) \"hi r8, r" ,9, VAL1,", r" ,14,val, ", lsl r" ,0, 3,"" )\"ls r9, r" ,9, VAL1,", r" ,14,val, ", lsr r" ,7, 4,"" )\"ge r10, r" ,11,VAL1,", r" ,14,val, ", asr r" ,7, 5,"" )\"lt r11, r" ,11,VAL1,", r" ,14,N(val),", asr r" ,7, 6,"" )\"gt r12, r13" ", r" ,14,val, ", ror r" ,14,7,"" )\"le r14, r" ,0, val, ", r13" ", lsl r" ,14,8,"" )\"eq r0, r" ,11,VAL1,", #0xf5" ) \"ne r11, r" ,0, VAL1,", #0xf5000000" ) \" r7, r" ,8, VAL2,", #0x000af000" ) \" r4, pc" ", #0x00005a00" )#define DATA_PROCESSING_DNM(op,val) \"" ,val) \"s" ,val)#define DATA_PROCESSING_NM(op,val) \"ne r" ,1, VAL1,", r" ,2, val, "" ) \"eq r" ,1, VAL1,", r" ,2, val, ", lsl #3" ) \"cc r" ,3, VAL1,", r" ,2, val, ", lsr #4" ) \"cs r" ,3, VAL1,", r" ,2, val, ", asr #5" ) \"pl r" ,5, VAL1,", r" ,2, N(val),", asr #6" ) \"mi r" ,5, VAL1,", r" ,2, val, ", ror #7" ) \"vc r" ,7, VAL1,", r" ,2, val, ", rrx" ) \"vs r" ,7, VAL1,", pc, lsl #3" ) \"vs r" ,7, VAL1,", sp, lsr #4" ) \"vs pc, r" ,7, VAL1,", asr #5" ) \"vs sp, r" ,7, VAL1,", ror #6" ) \"ls r" ,9, VAL1,", r" ,14,val, ", lsl r" ,0, 3,"" ) \"hi r" ,9, VAL1,", r" ,14,val, ", lsr r" ,7, 4,"" ) \"lt r" ,11,VAL1,", r" ,14,val, ", asr r" ,7, 5,"" ) \"ge r" ,11,VAL1,", r" ,14,N(val),", asr r" ,7, 6,"" ) \"le r13" ", r" ,14,val, ", ror r" ,14,7,"" ) \"gt r" ,0, val, ", r13" ", lsl r" ,14,8,"" ) \"eq r" ,11,VAL1,", #0xf5" ) \"ne r" ,0, VAL1,", #0xf5000000" ) \" r" ,8, VAL2,", #0x000af000" )#define _DATA_PROCESSING_DM(op,s,val) \"eq r0, r" ,1, val, "" ) \"ne r1, r" ,1, val, ", lsl #3" ) \"cs r2, r" ,3, val, ", lsr #4" ) \"cc r3, r" ,3, val, ", asr #5" ) \"mi r4, r" ,5, N(val),", asr #6" ) \"pl r5, r" ,5, val, ", ror #7" ) \"vs r6, r" ,10,val, ", rrx" ) \"vs r7, pc, lsl #3" ) \"vs r7, sp, lsr #4" ) \"vc r8, r" ,7, val, ", lsl r" ,0, 3,"" ) \"hi r9, r" ,9, val, ", lsr r" ,7, 4,"" ) \"ls r10, r" ,9, val, ", asr r" ,7, 5,"" ) \"ge r11, r" ,11,N(val),", asr r" ,7, 6,"" ) \"lt r12, r" ,11,val, ", ror r" ,14,7,"" ) \"gt r14, r13" ", lsl r" ,14,8,"" ) \"eq r0, #0xf5" ) \"ne r11, #0xf5000000" ) \" r7, #0x000af000" ) \" r4, #0x00005a00" )#define DATA_PROCESSING_DM(op,val) \"" ,val) \"s" ,val)"and" ,0xf00f00ff)"eor" ,0xf00f00ff)"sub" ,VAL2)"rsb" ,VAL2)"add" ,VAL2)"adc" ,VAL2)"sbc" ,VAL2)"rsc" ,VAL2)"tst" ,0xf00f00ff)"teq" ,0xf00f00ff)"cmp" ,VAL2)"cmn" ,VAL2)"orr" ,0xf00f00ff)"mov" ,VAL2)"bic" ,0xf00f00ff)"mvn" ,VAL2)"mov ip, sp" ) /* This has special case emulation code */ "mov pc, #0x1000" );"mov sp, #0x1000" );"cmp pc, #0x1000" );"cmp sp, #0x1000" );/* Data-processing with PC and a shift count in a register */ " @ cmp r12, r14, asl pc" )" @ mov r12, r14, asl pc" )" @ add r10, r12, r14, asl pc" )" @ cmp r1, pc, lsl r2" )" @ cmn pc, r1, lsl r2" )" @ mov r1, pc, lsl r2" )" @ mov pc, r1, lsl r2" )" @ sub r1, r2, pc, lsl r3" )" @ bic r1, pc, r2, lsl r3" )" @ add pc, r1, r2, lsl r3" )/* Data-processing with PC as a target and status registers updated */ "movs pc, r1" )" @movs pc, r1, lsl r2" )"movs pc, #0x10000" )"adds pc, lr, r1" )" @adds pc, lr, r1, lsl r2" )"adds pc, lr, #4" )/* Data-processing with SP as target */ "add sp, sp, #16" )"sub sp, sp, #8" )"bic sp, sp, #0x20" )"orr sp, sp, #0x20" )"add sp, r" ,10,0,", r" ,11,4,"" )"add sp, r" ,10,0,", r" ,11,4,", asl r" ,12,1,"" )"mov sp, r" ,10,0,"" )"mov sp, r" ,10,0,", asl r" ,12,0,"" )/* Data-processing with PC as target */ "add pc, pc, #2f-1b-8" )"add pc, pc, r" ,14,2f-1f-8,"" )"add pc, r" ,14,2f-1f-8,", pc" )"mov pc, r" ,0,2f,"" )"add pc, pc, r" ,14,(2f-1f-8)*2,", asr #1" )"sub pc, pc, #1b-2b+8" )#if __LINUX_ARM_ARCH__ == 6 && !defined (CONFIG_CPU_V7)"sub pc, pc, #1b-2b+8-2" ) /* UNPREDICTABLE before and after ARMv6 */ #endif "sub pc, pc, r" ,14, 1f-2f+8,"" )"rsb pc, r" ,14,1f-2f+8,", pc" )"add pc, pc, r" ,10,-2,", asl #1" )#ifdef CONFIG_THUMB2_KERNEL"add pc, pc, r" ,0,3f-1f-8+1,"" )"sub pc, r" ,0,3f+8+1,", #8" )#endif "Miscellaneous instructions" )"mrs r" ,0,~PSR_IGNORE_BITS,", cpsr" )"mrspl r" ,7,~PSR_IGNORE_BITS,", cpsr" )"mrs r" ,14,~PSR_IGNORE_BITS,", cpsr" )" @ mrs r15, cpsr" )"mrs r0, spsr" )"mrs lr, spsr" )"msr cpsr, r0" )"msr cpsr_f, lr" )"msr spsr, r0" )#if __LINUX_ARM_ARCH__ >= 5 || \defined (CONFIG_CPU_32v4))"bx r" ,0,2f,"" )"bx r" ,7,2f,"" )"bxeq r" ,14,2f,"" )#endif #if __LINUX_ARM_ARCH__ >= 5"clz r0, r" ,0, 0x0,"" )"clzeq r7, r" ,14,0x1,"" )"clz lr, r" ,7, 0xffffffff,"" )"clz r4, sp" )" @ clz pc, r0" )" @ clz r0, pc" )#if __LINUX_ARM_ARCH__ >= 6"bxj r0" )#endif "blx r" ,0,2f,"" )"blx r" ,7,2f,"" )"blxeq r" ,14,2f,"" )" @ blx pc" )"qadd r0, r" ,1, VAL1,", r" ,2, VAL2,"" )"qaddvs lr, r" ,9, VAL2,", r" ,8, VAL1,"" )"qadd lr, r" ,9, VAL2,", r13" )"qsub r0, r" ,1, VAL1,", r" ,2, VAL2,"" )"qsubvs lr, r" ,9, VAL2,", r" ,8, VAL1,"" )"qsub lr, r" ,9, VAL2,", r13" )"qdadd r0, r" ,1, VAL1,", r" ,2, VAL2,"" )"qdaddvs lr, r" ,9, VAL2,", r" ,8, VAL1,"" )"qdadd lr, r" ,9, VAL2,", r13" )"qdsub r0, r" ,1, VAL1,", r" ,2, VAL2,"" )"qdsubvs lr, r" ,9, VAL2,", r" ,8, VAL1,"" )"qdsub lr, r" ,9, VAL2,", r13" )" @ qadd pc, r0, r1" )" @ qsub pc, r0, r1" )" @ qdadd pc, r0, r1" )" @ qdsub pc, r0, r1" )" @ qdsub r2, r0, pc" )" @ qdsub r2, pc, r1" )"bkpt 0xffff" )"bkpt 0x0000" )" @ smc #0" )"Halfword multiply and multiply-accumulate" )"smlabb r0, r" ,1, VAL1,", r" ,2, VAL2,", r" ,3, VAL3,"" )"smlabbge r7, r" ,8, VAL3,", r" ,9, VAL1,", r" ,10, VAL2,"" )"smlabb lr, r" ,1, VAL2,", r" ,2, VAL3,", r13" )" @ smlabb pc, r1, r2, r3" )"smlatb r0, r" ,1, VAL1,", r" ,2, VAL2,", r" ,3, VAL3,"" )"smlatbge r7, r" ,8, VAL3,", r" ,9, VAL1,", r" ,10, VAL2,"" )"smlatb lr, r" ,1, VAL2,", r" ,2, VAL3,", r13" )" @ smlatb pc, r1, r2, r3" )"smlabt r0, r" ,1, VAL1,", r" ,2, VAL2,", r" ,3, VAL3,"" )"smlabtge r7, r" ,8, VAL3,", r" ,9, VAL1,", r" ,10, VAL2,"" )"smlabt lr, r" ,1, VAL2,", r" ,2, VAL3,", r13" )" @ smlabt pc, r1, r2, r3" )"smlatt r0, r" ,1, VAL1,", r" ,2, VAL2,", r" ,3, VAL3,"" )"smlattge r7, r" ,8, VAL3,", r" ,9, VAL1,", r" ,10, VAL2,"" )"smlatt lr, r" ,1, VAL2,", r" ,2, VAL3,", r13" )" @ smlatt pc, r1, r2, r3" )"smlawb r0, r" ,1, VAL1,", r" ,2, VAL2,", r" ,3, VAL3,"" )"smlawbge r7, r" ,8, VAL3,", r" ,9, VAL1,", r" ,10, VAL2,"" )"smlawb lr, r" ,1, VAL2,", r" ,2, VAL3,", r13" )" @ smlawb pc, r1, r2, r3" )"smlawt r0, r" ,1, VAL1,", r" ,2, VAL2,", r" ,3, VAL3,"" )"smlawtge r7, r" ,8, VAL3,", r" ,9, VAL1,", r" ,10, VAL2,"" )"smlawt lr, r" ,1, VAL2,", r" ,2, VAL3,", r13" )" @ smlawt pc, r1, r2, r3" )" @ smlawt r0, pc, r2, r3" )" @ smlawt r0, r1, pc, r3" )" @ smlawt r0, r1, r2, pc" )"smulwb r0, r" ,1, VAL1,", r" ,2, VAL2,"" )"smulwbge r7, r" ,8, VAL3,", r" ,9, VAL1,"" )"smulwb lr, r" ,1, VAL2,", r13" )" @ smulwb pc, r1, r2" )"smulwt r0, r" ,1, VAL1,", r" ,2, VAL2,"" )"smulwtge r7, r" ,8, VAL3,", r" ,9, VAL1,"" )"smulwt lr, r" ,1, VAL2,", r13" )" @ smulwt pc, r1, r2" )"smlalbb r" ,0, VAL1,", r" ,1, VAL2,", r" ,2, VAL3,", r" ,3, VAL4)"smlalbble r" ,8, VAL4,", r" ,9, VAL1,", r" ,10,VAL2,", r" ,11,VAL3)"smlalbb r" ,14,VAL3,", r" ,7, VAL4,", r" ,5, VAL1,", r13" )" @ smlalbb pc, r1, r2, r3" )" @ smlalbb r1, pc, r2, r3" )"smlaltb r" ,0, VAL1,", r" ,1, VAL2,", r" ,2, VAL3,", r" ,3, VAL4)"smlaltble r" ,8, VAL4,", r" ,9, VAL1,", r" ,10,VAL2,", r" ,11,VAL3)"smlaltb r" ,14,VAL3,", r" ,7, VAL4,", r" ,5, VAL1,", r13" )" @ smlaltb pc, r1, r2, r3" )" @ smlaltb r1, pc, r2, r3" )"smlalbt r" ,0, VAL1,", r" ,1, VAL2,", r" ,2, VAL3,", r" ,3, VAL4)"smlalbtle r" ,8, VAL4,", r" ,9, VAL1,", r" ,10,VAL2,", r" ,11,VAL3)"smlalbt r" ,14,VAL3,", r" ,7, VAL4,", r" ,5, VAL1,", r13" )" @ smlalbt pc, r1, r2, r3" )" @ smlalbt r1, pc, r2, r3" )"smlaltt r" ,0, VAL1,", r" ,1, VAL2,", r" ,2, VAL3,", r" ,3, VAL4)"smlalttle r" ,8, VAL4,", r" ,9, VAL1,", r" ,10,VAL2,", r" ,11,VAL3)"smlaltt r" ,14,VAL3,", r" ,7, VAL4,", r" ,5, VAL1,", r13" )" @ smlalbb pc, r1, r2, r3" )" @ smlalbb r0, pc, r2, r3" )" @ smlalbb r0, r1, pc, r3" )" @ smlalbb r0, r1, r2, pc" )"smulbb r0, r" ,1, VAL1,", r" ,2, VAL2,"" )"smulbbge r7, r" ,8, VAL3,", r" ,9, VAL1,"" )"smulbb lr, r" ,1, VAL2,", r13" )" @ smulbb pc, r1, r2" )"smultb r0, r" ,1, VAL1,", r" ,2, VAL2,"" )"smultbge r7, r" ,8, VAL3,", r" ,9, VAL1,"" )"smultb lr, r" ,1, VAL2,", r13" )" @ smultb pc, r1, r2" )"smulbt r0, r" ,1, VAL1,", r" ,2, VAL2,"" )"smulbtge r7, r" ,8, VAL3,", r" ,9, VAL1,"" )"smulbt lr, r" ,1, VAL2,", r13" )" @ smultb pc, r1, r2" )"smultt r0, r" ,1, VAL1,", r" ,2, VAL2,"" )"smulttge r7, r" ,8, VAL3,", r" ,9, VAL1,"" )"smultt lr, r" ,1, VAL2,", r13" )" @ smultt pc, r1, r2" )" @ smultt r0, pc, r2" )" @ smultt r0, r1, pc" )#endif "Multiply and multiply-accumulate" )"mul r0, r" ,1, VAL1,", r" ,2, VAL2,"" )"mulls r7, r" ,8, VAL2,", r" ,9, VAL2,"" )"mul lr, r" ,4, VAL3,", r13" )" @ mul pc, r1, r2" )" @ mul r0, pc, r2" )" @ mul r0, r1, pc" )"muls r0, r" ,1, VAL1,", r" ,2, VAL2,"" )"mulsls r7, r" ,8, VAL2,", r" ,9, VAL2,"" )"muls lr, r" ,4, VAL3,", r13" )" @ muls pc, r1, r2" )"mla r0, r" ,1, VAL1,", r" ,2, VAL2,", r" ,3, VAL3,"" )"mlahi r7, r" ,8, VAL3,", r" ,9, VAL1,", r" ,10, VAL2,"" )"mla lr, r" ,1, VAL2,", r" ,2, VAL3,", r13" )" @ mla pc, r1, r2, r3" )"mlas r0, r" ,1, VAL1,", r" ,2, VAL2,", r" ,3, VAL3,"" )"mlashi r7, r" ,8, VAL3,", r" ,9, VAL1,", r" ,10, VAL2,"" )"mlas lr, r" ,1, VAL2,", r" ,2, VAL3,", r13" )" @ mlas pc, r1, r2, r3" )#if __LINUX_ARM_ARCH__ >= 6"umaal r0, r1, r" ,2, VAL1,", r" ,3, VAL2,"" )"umaalls r7, r8, r" ,9, VAL2,", r" ,10, VAL1,"" )"umaal lr, r12, r" ,11,VAL3,", r13" )" @ umaal pc, r1, r2, r3" )" @ umaal r0, pc, r2, r3" )" @ undef" )" @ undef" )#endif #if __LINUX_ARM_ARCH__ >= 7"mls r0, r" ,1, VAL1,", r" ,2, VAL2,", r" ,3, VAL3,"" )"mlshi r7, r" ,8, VAL3,", r" ,9, VAL1,", r" ,10, VAL2,"" )"mls lr, r" ,1, VAL2,", r" ,2, VAL3,", r13" )" @ mls pc, r1, r2, r3" )" @ mls r0, pc, r2, r3" )" @ mls r0, r1, pc, r3" )" @ mls r0, r1, r2, pc" )#endif " @ undef" )" @ undef" )"umull r0, r1, r" ,2, VAL1,", r" ,3, VAL2,"" )"umullls r7, r8, r" ,9, VAL2,", r" ,10, VAL1,"" )"umull lr, r12, r" ,11,VAL3,", r13" )" @ umull pc, r1, r2, r3" )" @ umull r1, pc, r2, r3" )"umulls r0, r1, r" ,2, VAL1,", r" ,3, VAL2,"" )"umullsls r7, r8, r" ,9, VAL2,", r" ,10, VAL1,"" )"umulls lr, r12, r" ,11,VAL3,", r13" )" @ umulls pc, r1, r2, r3" )" @ umulls r1, pc, r2, r3" )"umlal r" ,0, VAL1,", r" ,1, VAL2,", r" ,2, VAL3,", r" ,3, VAL4)"umlalle r" ,8, VAL4,", r" ,9, VAL1,", r" ,10,VAL2,", r" ,11,VAL3)"umlal r" ,14,VAL3,", r" ,7, VAL4,", r" ,5, VAL1,", r13" )" @ umlal pc, r1, r2, r3" )" @ umlal r1, pc, r2, r3" )"umlals r" ,0, VAL1,", r" ,1, VAL2,", r" ,2, VAL3,", r" ,3, VAL4)"umlalsle r" ,8, VAL4,", r" ,9, VAL1,", r" ,10,VAL2,", r" ,11,VAL3)"umlals r" ,14,VAL3,", r" ,7, VAL4,", r" ,5, VAL1,", r13" )" @ umlals pc, r1, r2, r3" )" @ umlals r1, pc, r2, r3" )"smull r0, r1, r" ,2, VAL1,", r" ,3, VAL2,"" )"smullls r7, r8, r" ,9, VAL2,", r" ,10, VAL1,"" )"smull lr, r12, r" ,11,VAL3,", r13" )" @ smull pc, r1, r2, r3" )" @ smull r1, pc, r2, r3" )"smulls r0, r1, r" ,2, VAL1,", r" ,3, VAL2,"" )"smullsls r7, r8, r" ,9, VAL2,", r" ,10, VAL1,"" )"smulls lr, r12, r" ,11,VAL3,", r13" )" @ smulls pc, r1, r2, r3" )" @ smulls r1, pc, r2, r3" )"smlal r" ,0, VAL1,", r" ,1, VAL2,", r" ,2, VAL3,", r" ,3, VAL4)"smlalle r" ,8, VAL4,", r" ,9, VAL1,", r" ,10,VAL2,", r" ,11,VAL3)"smlal r" ,14,VAL3,", r" ,7, VAL4,", r" ,5, VAL1,", r13" )" @ smlal pc, r1, r2, r3" )" @ smlal r1, pc, r2, r3" )"smlals r" ,0, VAL1,", r" ,1, VAL2,", r" ,2, VAL3,", r" ,3, VAL4)"smlalsle r" ,8, VAL4,", r" ,9, VAL1,", r" ,10,VAL2,", r" ,11,VAL3)"smlals r" ,14,VAL3,", r" ,7, VAL4,", r" ,5, VAL1,", r13" )" @ smlals pc, r1, r2, r3" )" @ smlals r0, pc, r2, r3" )" @ smlals r0, r1, pc, r3" )" @ smlals r0, r1, r2, pc" )"Synchronization primitives" )#if __LINUX_ARM_ARCH__ < 6"swp lr, r" ,7,VAL2,", [r" ,8,0,"]" )"swpvs r0, r" ,1,VAL1,", [sp]" )"swp sp, r" ,14,VAL2,", [r" ,12,13*4,"]" )#else " @ swp lr, r7, [r8]" )" @ swpvs r0, r1, [sp]" )" @ swp sp, r14 [r12]" )#endif " @ swp pc, r1, [r2]" )" @ swp r0, pc, [r2]" )" @ swp r0, r1, [pc]" )#if __LINUX_ARM_ARCH__ < 6"swpb lr, r" ,7,VAL2,", [r" ,8,0,"]" )"swpbvs r0, r" ,1,VAL1,", [sp]" )#else " @ swpb lr, r7, [r8]" )" @ swpvsb r0, r1, [sp]" )#endif " @ swpb pc, r1, [r2]" )/* Unallocated space */ /* Unallocated space */ /* Unallocated space */ /* Unallocated space */ /* Unallocated space */ /* Unallocated space */ #if __LINUX_ARM_ARCH__ >= 6"ldrex r2, [sp]" )#endif #if (__LINUX_ARM_ARCH__ >= 7) || defined (CONFIG_CPU_32v6K)"strexd r0, r2, r3, [sp]" )"ldrexd r2, r3, [sp]" )"strexb r0, r2, [sp]" )"ldrexb r2, [sp]" )"strexh r0, r2, [sp]" )"ldrexh r2, [sp]" )#endif "Extra load/store instructions" )"strh r" ,0, VAL1,", [r" ,1, 48,", -r" ,2, 24,"]" )"strheq r" ,14,VAL2,", [r" ,11,0, ", r" ,12, 48,"]" )"strheq r14, [r13, r12]" )"strheq r14, [r12, r13]" )"strh r" ,1, VAL1,", [r" ,2, 24,", r" ,3, 48,"]!" )"strhne r" ,12,VAL2,", [r" ,11,48,", -r" ,10,24,"]!" )"strh r" ,2, VAL1,", [r" ,3, 24,"], r" ,4, 48,"" )"strh r" ,10,VAL2,", [r" ,9, 48,"], -r" ,11,24,"" )" @ strh r12, [pc, r10]!" )" @ strh pc, [r9], r11" )" @ strh r10, [r9], pc" )"ldrh r0, [r" ,0, 48,", -r" ,2, 24,"]" )"ldrhcs r14, [r" ,13,0, ", r" ,12, 48,"]" )"ldrh r1, [r" ,2, 24,", r" ,3, 48,"]!" )"ldrhcc r12, [r" ,11,48,", -r" ,10,24,"]!" )"ldrh r2, [r" ,3, 24,"], r" ,4, 48,"" )"ldrh r10, [r" ,9, 48,"], -r" ,11,24,"" )" @ ldrh r12, [pc, r10]!" )" @ ldrh pc, [r9], r11" )" @ ldrh r10, [r9], pc" )"strh r" ,0, VAL1,", [r" ,1, 24,", #-2]" )"strhmi r" ,14,VAL2,", [r" ,13,0, ", #2]" )"strh r" ,1, VAL1,", [r" ,2, 24,", #4]!" )"strhpl r" ,12,VAL2,", [r" ,11,24,", #-4]!" )"strh r" ,2, VAL1,", [r" ,3, 24,"], #48" )"strh r" ,10,VAL2,", [r" ,9, 64,"], #-48" )"strh r" ,3, VAL1,", [r" ,13,TEST_MEMORY_SIZE,", #-" __stringify(MAX_STACK_SIZE)"]!" )"strh r3, [r13, #-" __stringify(MAX_STACK_SIZE)"-8]!" )"strh r" ,4, VAL1,", [r" ,14,TEST_MEMORY_SIZE,", #-" __stringify(MAX_STACK_SIZE)"-8]!" )" @ strh r12, [pc, #48]!" )" @ strh pc, [r9], #48" )"ldrh r0, [r" ,0, 24,", #-2]" )"ldrhvs r14, [r" ,13,0, ", #2]" )"ldrh r1, [r" ,2, 24,", #4]!" )"ldrhvc r12, [r" ,11,24,", #-4]!" )"ldrh r2, [r" ,3, 24,"], #48" )"ldrh r10, [r" ,9, 64,"], #-48" )"ldrh r0, [pc, #0]" )" @ ldrh r12, [pc, #48]!" )" @ ldrh pc, [r9], #48" )"ldrsb r0, [r" ,0, 48,", -r" ,2, 24,"]" )"ldrsbhi r14, [r" ,13,0,", r" ,12, 48,"]" )"ldrsb r1, [r" ,2, 24,", r" ,3, 48,"]!" )"ldrsbls r12, [r" ,11,48,", -r" ,10,24,"]!" )"ldrsb r2, [r" ,3, 24,"], r" ,4, 48,"" )"ldrsb r10, [r" ,9, 48,"], -r" ,11,24,"" )" @ ldrsb r12, [pc, r10]!" )" @ ldrsb pc, [r9], r11" )"ldrsb r0, [r" ,0, 24,", #-1]" )"ldrsbge r14, [r" ,13,0, ", #1]" )"ldrsb r1, [r" ,2, 24,", #4]!" )"ldrsblt r12, [r" ,11,24,", #-4]!" )"ldrsb r2, [r" ,3, 24,"], #48" )"ldrsb r10, [r" ,9, 64,"], #-48" )"ldrsb r0, [pc, #0]" )" @ ldrsb r12, [pc, #48]!" )" @ ldrsb pc, [r9], #48" )"ldrsh r0, [r" ,0, 48,", -r" ,2, 24,"]" )"ldrshgt r14, [r" ,13,0, ", r" ,12, 48,"]" )"ldrsh r1, [r" ,2, 24,", r" ,3, 48,"]!" )"ldrshle r12, [r" ,11,48,", -r" ,10,24,"]!" )"ldrsh r2, [r" ,3, 24,"], r" ,4, 48,"" )"ldrsh r10, [r" ,9, 48,"], -r" ,11,24,"" )" @ ldrsh r12, [pc, r10]!" )" @ ldrsh pc, [r9], r11" )"ldrsh r0, [r" ,0, 24,", #-1]" )"ldrsheq r14, [r" ,13,0 ,", #1]" )"ldrsh r1, [r" ,2, 24,", #4]!" )"ldrshne r12, [r" ,11,24,", #-4]!" )"ldrsh r2, [r" ,3, 24,"], #48" )"ldrsh r10, [r" ,9, 64,"], #-48" )"ldrsh r0, [pc, #0]" )" @ ldrsh r12, [pc, #48]!" )" @ ldrsh pc, [r9], #48" )#if __LINUX_ARM_ARCH__ >= 7"strht r1, [r2], r3" )"ldrht r1, [r2], r3" )"strht r1, [r2], #48" )"ldrht r1, [r2], #48" )"ldrsbt r1, [r2], r3" )"ldrsbt r1, [r2], #48" )"ldrsht r1, [r2], r3" )"ldrsht r1, [r2], #48" )#endif #if __LINUX_ARM_ARCH__ >= 5"strd r" ,0, VAL1,", [r" ,1, 48,", -r" ,2,24,"]" )"strdcc r" ,8, VAL2,", [r" ,11,0, ", r" ,12,48,"]" )"strdcc r8, [r13, r12]" )"strdcc r8, [r12, r13]" )"strd r" ,4, VAL1,", [r" ,2, 24,", r" ,3, 48,"]!" )"strdcs r" ,12,VAL2,", r13, [r" ,11,48,", -r" ,10,24,"]!" )"strd r" ,2, VAL1,", r3, [r" ,5, 24,"], r" ,4,48,"" )"strd r" ,10,VAL2,", r11, [r" ,9, 48,"], -r" ,7,24,"" )" @ strd r12, [pc, r10]!" )"ldrd r0, [r" ,0, 48,", -r" ,2,24,"]" )"ldrdmi r8, [r" ,13,0, ", r" ,12,48,"]" )"ldrd r4, [r" ,2, 24,", r" ,3, 48,"]!" )"ldrdpl r6, [r" ,11,48,", -r" ,10,24,"]!" )"ldrd r2, r3, [r" ,5, 24,"], r" ,4,48,"" )"ldrd r10, r11, [r" ,9,48,"], -r" ,7,24,"" )" @ ldrd r12, [pc, r10]!" )" @ ldrd pc, [r9], r11" )" @ ldrd lr, [r9], r11" )" @ ldrd r12, [r9], pc" )"strd r" ,0, VAL1,", [r" ,1, 24,", #-8]" )"strdvs r" ,8, VAL2,", [r" ,13,0, ", #8]" )"strd r" ,4, VAL1,", [r" ,2, 24,", #16]!" )"strdvc r" ,12,VAL2,", r13, [r" ,11,24,", #-16]!" )"strd r" ,2, VAL1,", [r" ,4, 24,"], #48" )"strd r" ,10,VAL2,", [r" ,9, 64,"], #-48" )"strd r" ,6, VAL1,", [r" ,13,TEST_MEMORY_SIZE,", #-" __stringify(MAX_STACK_SIZE)"]!" )"strd r6, [r13, #-" __stringify(MAX_STACK_SIZE)"-8]!" )"strd r" ,4, VAL1,", [r" ,12,TEST_MEMORY_SIZE,", #-" __stringify(MAX_STACK_SIZE)"-8]!" )" @ strd r12, [pc, #48]!" )"ldrd r0, [r" ,0, 24,", #-8]" )"ldrdhi r8, [r" ,13,0, ", #8]" )"ldrd r4, [r" ,2, 24,", #16]!" )"ldrdls r6, [r" ,11,24,", #-16]!" )"ldrd r2, [r" ,5, 24,"], #48" )"ldrd r10, [r" ,9,6,"], #-48" )" @ ldrd r12, [pc, #48]!" )" @ ldrd pc, [r9], #48" )" @ ldrd lr, [r9], #48" )#endif "Miscellaneous" )#if __LINUX_ARM_ARCH__ >= 7"movw r0, #0" )"movw r0, #0xffff" )"movw lr, #0xffff" )" @ movw pc, #0" )"movt r" ,0, VAL1,", #0" )"movt r" ,0, VAL2,", #0xffff" )"movt r" ,14,VAL1,", #0xffff" )" @ movt pc, #0" )#endif "msr cpsr, 0x13" )"msr cpsr_f, 0xf0000000" )"msr spsr, 0x13" )#if __LINUX_ARM_ARCH__ >= 7"yield" )"sev" )"nop" )"wfi" )"wfe" )"dbg #0" )#endif "Load/store word and unsigned byte" )#define LOAD_STORE(byte) \"str" byte" r" ,0, VAL1,", [r" ,1, 24,", #-2]" ) \"str" byte" r" ,14,VAL2,", [r" ,13,0, ", #2]" ) \"str" byte" r" ,1, VAL1,", [r" ,2, 24,", #4]!" ) \"str" byte" r" ,12,VAL2,", [r" ,11,24,", #-4]!" ) \"str" byte" r" ,2, VAL1,", [r" ,3, 24,"], #48" ) \"str" byte" r" ,10,VAL2,", [r" ,9, 64,"], #-48" ) \"str" byte" r" ,3, VAL1,", [r" ,13,TEST_MEMORY_SIZE,", #-" __stringify(MAX_STACK_SIZE)"]!" ) \"str" byte" r3, [r13, #-" __stringify(MAX_STACK_SIZE)"-8]!" ) \"str" byte" r" ,4, VAL1,", [r" ,10,TEST_MEMORY_SIZE,", #-" __stringify(MAX_STACK_SIZE)"-8]!" ) \"str" byte" r" ,0, VAL1,", [r" ,1, 48,", -r" ,2, 24,"]" ) \"str" byte" r" ,14,VAL2,", [r" ,11,0, ", r" ,12, 48,"]" ) \"str" byte" r14, [r13, r12]" ) \"str" byte" r14, [r12, r13]" ) \"str" byte" r" ,1, VAL1,", [r" ,2, 24,", r" ,3, 48,"]!" ) \"str" byte" r" ,12,VAL2,", [r" ,11,48,", -r" ,10,24,"]!" ) \"str" byte" r" ,2, VAL1,", [r" ,3, 24,"], r" ,4, 48,"" ) \"str" byte" r" ,10,VAL2,", [r" ,9, 48,"], -r" ,11,24,"" ) \"str" byte" r" ,0, VAL1,", [r" ,1, 24,", r" ,2, 32,", asl #1]" )\"str" byte" r" ,14,VAL2,", [r" ,11,0, ", r" ,12, 32,", lsr #2]" )\"str" byte" r14, [r13, r12, lsr #2]" ) \"str" byte" r" ,1, VAL1,", [r" ,2, 24,", r" ,3, 32,", asr #3]!" )\"str" byte" r" ,12,VAL2,", [r" ,11,24,", r" ,10, 4,", ror #31]!" )\"ldr" byte" r0, [r" ,0, 24,", #-2]" ) \"ldr" byte" r14, [r" ,13,0, ", #2]" ) \"ldr" byte" r1, [r" ,2, 24,", #4]!" ) \"ldr" byte" r12, [r" ,11,24,", #-4]!" ) \"ldr" byte" r2, [r" ,3, 24,"], #48" ) \"ldr" byte" r10, [r" ,9, 64,"], #-48" ) \"ldr" byte" r0, [r" ,0, 48,", -r" ,2, 24,"]" ) \"ldr" byte" r14, [r" ,13,0, ", r" ,12, 48,"]" ) \"ldr" byte" r1, [r" ,2, 24,", r" ,3, 48,"]!" ) \"ldr" byte" r12, [r" ,11,48,", -r" ,10,24,"]!" ) \"ldr" byte" r2, [r" ,3, 24,"], r" ,4, 48,"" ) \"ldr" byte" r10, [r" ,9, 48,"], -r" ,11,24,"" ) \"ldr" byte" r0, [r" ,0, 24,", r" ,2, 32,", asl #1]" ) \"ldr" byte" r14, [r" ,13,0, ", r" ,12, 32,", lsr #2]" ) \"ldr" byte" r1, [r" ,2, 24,", r" ,3, 32,", asr #3]!" ) \"ldr" byte" r12, [r" ,11,24,", r" ,10, 4,", ror #31]!" ) \"ldr" byte" r0, [pc, #0]" ) \"ldr" byte" r12, [pc, r" ,14,0,"]" )"" )"str pc, [r" ,0,0,", #15*4]" )"str pc, [sp, r2]" )"ldr pc, [sp, #15*4]" )"ldr pc, [sp, r" ,2,15*4,"]" )"str sp, [r" ,0,0,", #13*4]" )"str sp, [sp, r2]" )"ldr sp, [sp, #13*4]" )"ldr sp, [sp, r" ,2,13*4,"]" )#ifdef CONFIG_THUMB2_KERNEL"ldr pc, [r" ,0,0,", #15*4]" )#endif " @ str r6, [pc, #8]!" )" @ str r6, [pc, r8]!" )" @ ldr r6, [pc, #8]!" )" @ ldr r6, [pc, r8]!" )" @ str r6, [r8, pc]" )" @ ldr r6, [r8, pc]" )"b" )" @ ldrb pc, [r7, #8]!" )" @ ldrb pc, [r7, r8]!" )" @ strb r6, [pc, #8]!" )" @ strb r6, [pc, r3]!" )" @ ldrb r6, [pc, #8]!" )" @ ldrb r6, [pc, r3]!" )"ldrt r0, [r1], #4" )"ldrt r1, [r2], r3" )"strt r2, [r3], #4" )"strt r3, [r4], r5" )"ldrbt r4, [r5], #4" )"ldrbt r5, [r6], r7" )"strbt r6, [r7], #4" )"strbt r7, [r8], r9" )#if __LINUX_ARM_ARCH__ >= 7"Parallel addition and subtraction, signed" )"" ) /* Unallocated space */ "" ) /* Unallocated space */ "sadd16 r0, r" ,0, HH1,", r" ,1, HH2,"" )"sadd16 r14, r" ,12,HH2,", r" ,10,HH1,"" )" @ sadd16 pc, r12, r10" )"sasx r0, r" ,0, HH1,", r" ,1, HH2,"" )"sasx r14, r" ,12,HH2,", r" ,10,HH1,"" )" @ sasx pc, r12, r10" )"ssax r0, r" ,0, HH1,", r" ,1, HH2,"" )"ssax r14, r" ,12,HH2,", r" ,10,HH1,"" )" @ ssax pc, r12, r10" )"ssub16 r0, r" ,0, HH1,", r" ,1, HH2,"" )"ssub16 r14, r" ,12,HH2,", r" ,10,HH1,"" )" @ ssub16 pc, r12, r10" )"sadd8 r0, r" ,0, HH1,", r" ,1, HH2,"" )"sadd8 r14, r" ,12,HH2,", r" ,10,HH1,"" )" @ sadd8 pc, r12, r10" )"" ) /* Unallocated space */ "" ) /* Unallocated space */ "" ) /* Unallocated space */ "" ) /* Unallocated space */ "ssub8 r0, r" ,0, HH1,", r" ,1, HH2,"" )"ssub8 r14, r" ,12,HH2,", r" ,10,HH1,"" )" @ ssub8 pc, r12, r10" )"qadd16 r0, r" ,0, HH1,", r" ,1, HH2,"" )"qadd16 r14, r" ,12,HH2,", r" ,10,HH1,"" )" @ qadd16 pc, r12, r10" )"qasx r0, r" ,0, HH1,", r" ,1, HH2,"" )"qasx r14, r" ,12,HH2,", r" ,10,HH1,"" )" @ qasx pc, r12, r10" )"qsax r0, r" ,0, HH1,", r" ,1, HH2,"" )"qsax r14, r" ,12,HH2,", r" ,10,HH1,"" )" @ qsax pc, r12, r10" )"qsub16 r0, r" ,0, HH1,", r" ,1, HH2,"" )"qsub16 r14, r" ,12,HH2,", r" ,10,HH1,"" )" @ qsub16 pc, r12, r10" )"qadd8 r0, r" ,0, HH1,", r" ,1, HH2,"" )"qadd8 r14, r" ,12,HH2,", r" ,10,HH1,"" )" @ qadd8 pc, r12, r10" )"" ) /* Unallocated space */ "" ) /* Unallocated space */ "" ) /* Unallocated space */ "" ) /* Unallocated space */ "qsub8 r0, r" ,0, HH1,", r" ,1, HH2,"" )"qsub8 r14, r" ,12,HH2,", r" ,10,HH1,"" )" @ qsub8 pc, r12, r10" )"shadd16 r0, r" ,0, HH1,", r" ,1, HH2,"" )"shadd16 r14, r" ,12,HH2,", r" ,10,HH1,"" )" @ shadd16 pc, r12, r10" )"shasx r0, r" ,0, HH1,", r" ,1, HH2,"" )"shasx r14, r" ,12,HH2,", r" ,10,HH1,"" )" @ shasx pc, r12, r10" )"shsax r0, r" ,0, HH1,", r" ,1, HH2,"" )"shsax r14, r" ,12,HH2,", r" ,10,HH1,"" )" @ shsax pc, r12, r10" )"shsub16 r0, r" ,0, HH1,", r" ,1, HH2,"" )"shsub16 r14, r" ,12,HH2,", r" ,10,HH1,"" )" @ shsub16 pc, r12, r10" )"shadd8 r0, r" ,0, HH1,", r" ,1, HH2,"" )"shadd8 r14, r" ,12,HH2,", r" ,10,HH1,"" )" @ shadd8 pc, r12, r10" )"" ) /* Unallocated space */ "" ) /* Unallocated space */ "" ) /* Unallocated space */ "" ) /* Unallocated space */ "shsub8 r0, r" ,0, HH1,", r" ,1, HH2,"" )"shsub8 r14, r" ,12,HH2,", r" ,10,HH1,"" )" @ shsub8 pc, r12, r10" )"Parallel addition and subtraction, unsigned" )"" ) /* Unallocated space */ "" ) /* Unallocated space */ "uadd16 r0, r" ,0, HH1,", r" ,1, HH2,"" )"uadd16 r14, r" ,12,HH2,", r" ,10,HH1,"" )" @ uadd16 pc, r12, r10" )"uasx r0, r" ,0, HH1,", r" ,1, HH2,"" )"uasx r14, r" ,12,HH2,", r" ,10,HH1,"" )" @ uasx pc, r12, r10" )"usax r0, r" ,0, HH1,", r" ,1, HH2,"" )"usax r14, r" ,12,HH2,", r" ,10,HH1,"" )" @ usax pc, r12, r10" )"usub16 r0, r" ,0, HH1,", r" ,1, HH2,"" )"usub16 r14, r" ,12,HH2,", r" ,10,HH1,"" )" @ usub16 pc, r12, r10" )"uadd8 r0, r" ,0, HH1,", r" ,1, HH2,"" )"uadd8 r14, r" ,12,HH2,", r" ,10,HH1,"" )" @ uadd8 pc, r12, r10" )"" ) /* Unallocated space */ "" ) /* Unallocated space */ "" ) /* Unallocated space */ "" ) /* Unallocated space */ "usub8 r0, r" ,0, HH1,", r" ,1, HH2,"" )"usub8 r14, r" ,12,HH2,", r" ,10,HH1,"" )" @ usub8 pc, r12, r10" )"uqadd16 r0, r" ,0, HH1,", r" ,1, HH2,"" )"uqadd16 r14, r" ,12,HH2,", r" ,10,HH1,"" )" @ uqadd16 pc, r12, r10" )"uqasx r0, r" ,0, HH1,", r" ,1, HH2,"" )"uqasx r14, r" ,12,HH2,", r" ,10,HH1,"" )" @ uqasx pc, r12, r10" )"uqsax r0, r" ,0, HH1,", r" ,1, HH2,"" )"uqsax r14, r" ,12,HH2,", r" ,10,HH1,"" )" @ uqsax pc, r12, r10" )"uqsub16 r0, r" ,0, HH1,", r" ,1, HH2,"" )"uqsub16 r14, r" ,12,HH2,", r" ,10,HH1,"" )" @ uqsub16 pc, r12, r10" )"uqadd8 r0, r" ,0, HH1,", r" ,1, HH2,"" )"uqadd8 r14, r" ,12,HH2,", r" ,10,HH1,"" )" @ uqadd8 pc, r12, r10" )"" ) /* Unallocated space */ "" ) /* Unallocated space */ "" ) /* Unallocated space */ "" ) /* Unallocated space */ "uqsub8 r0, r" ,0, HH1,", r" ,1, HH2,"" )"uqsub8 r14, r" ,12,HH2,", r" ,10,HH1,"" )" @ uqsub8 pc, r12, r10" )"uhadd16 r0, r" ,0, HH1,", r" ,1, HH2,"" )"uhadd16 r14, r" ,12,HH2,", r" ,10,HH1,"" )" @ uhadd16 pc, r12, r10" )"uhasx r0, r" ,0, HH1,", r" ,1, HH2,"" )"uhasx r14, r" ,12,HH2,", r" ,10,HH1,"" )" @ uhasx pc, r12, r10" )"uhsax r0, r" ,0, HH1,", r" ,1, HH2,"" )"uhsax r14, r" ,12,HH2,", r" ,10,HH1,"" )" @ uhsax pc, r12, r10" )"uhsub16 r0, r" ,0, HH1,", r" ,1, HH2,"" )"uhsub16 r14, r" ,12,HH2,", r" ,10,HH1,"" )" @ uhsub16 pc, r12, r10" )"uhadd8 r0, r" ,0, HH1,", r" ,1, HH2,"" )"uhadd8 r14, r" ,12,HH2,", r" ,10,HH1,"" )" @ uhadd8 pc, r12, r10" )"" ) /* Unallocated space */ "" ) /* Unallocated space */ "" ) /* Unallocated space */ "" ) /* Unallocated space */ "uhsub8 r0, r" ,0, HH1,", r" ,1, HH2,"" )"uhsub8 r14, r" ,12,HH2,", r" ,10,HH1,"" )" @ uhsub8 pc, r12, r10" )" @ uhsub8 r14, pc, r10" )" @ uhsub8 r14, r12, pc" )#endif /* __LINUX_ARM_ARCH__ >= 7 */ #if __LINUX_ARM_ARCH__ >= 6"Packing, unpacking, saturation, and reversal" )"pkhbt r0, r" ,0, HH1,", r" ,1, HH2,"" )"pkhbt r14,r" ,12, HH1,", r" ,10,HH2,", lsl #2" )" @ pkhbt pc, r12, r10, lsl #2" )"pkhtb r0, r" ,0, HH1,", r" ,1, HH2,"" )"pkhtb r14,r" ,12, HH1,", r" ,10,HH2,", asr #2" )" @ pkhtb pc, r12, r10, asr #2" )" @ pkhtb r14, pc, r10, asr #2" )" @ pkhtb r14, r12, pc, asr #2" )"" ) /* Unallocated space */ "" ) /* Unallocated space */ "ssat r0, #24, r" ,0, VAL1,"" )"ssat r14, #24, r" ,12, VAL2,"" )"ssat r0, #24, r" ,0, VAL1,", lsl #8" )"ssat r14, #24, r" ,12, VAL2,", asr #8" )" @ ssat pc, #24, r12" )"usat r0, #24, r" ,0, VAL1,"" )"usat r14, #24, r" ,12, VAL2,"" )"usat r0, #24, r" ,0, VAL1,", lsl #8" )"usat r14, #24, r" ,12, VAL2,", asr #8" )" @ usat pc, #24, r12" )"sxtab16 r0, r" ,0, HH1,", r" ,1, HH2,"" )"sxtab16 r14,r" ,12, HH2,", r" ,10,HH1,", ror #8" )"sxtb16 r8, r" ,7, HH1,"" )" @ sxtab16 pc,r12, r10, ror #8" )"sel r0, r" ,0, VAL1,", r" ,1, VAL2,"" )"sel r14, r" ,12,VAL1,", r" ,10, VAL2,"" )" @ sel pc, r12, r10" )" @ sel r14, pc, r10" )" @ sel r14, r12, pc" )"ssat16 r0, #12, r" ,0, HH1,"" )"ssat16 r14, #12, r" ,12, HH2,"" )" @ ssat16 pc, #12, r12" )"sxtab r0, r" ,0, HH1,", r" ,1, HH2,"" )"sxtab r14,r" ,12, HH2,", r" ,10,HH1,", ror #8" )"sxtb r8, r" ,7, HH1,"" )" @ sxtab pc,r12, r10, ror #8" )"rev r0, r" ,0, VAL1,"" )"rev r14, r" ,12, VAL2,"" )" @ rev pc, r12" )"sxtah r0, r" ,0, HH1,", r" ,1, HH2,"" )"sxtah r14,r" ,12, HH2,", r" ,10,HH1,", ror #8" )"sxth r8, r" ,7, HH1,"" )" @ sxtah pc,r12, r10, ror #8" )"rev16 r0, r" ,0, VAL1,"" )"rev16 r14, r" ,12, VAL2,"" )" @ rev16 pc, r12" )"uxtab16 r0, r" ,0, HH1,", r" ,1, HH2,"" )"uxtab16 r14,r" ,12, HH2,", r" ,10,HH1,", ror #8" )"uxtb16 r8, r" ,7, HH1,"" )" @ uxtab16 pc,r12, r10, ror #8" )"usat16 r0, #12, r" ,0, HH1,"" )"usat16 r14, #12, r" ,12, HH2,"" )" @ usat16 pc, #12, r12" )" @ usat16 r14, #12, pc" )"uxtab r0, r" ,0, HH1,", r" ,1, HH2,"" )"uxtab r14,r" ,12, HH2,", r" ,10,HH1,", ror #8" )"uxtb r8, r" ,7, HH1,"" )" @ uxtab pc,r12, r10, ror #8" )#if __LINUX_ARM_ARCH__ >= 7"rbit r0, r" ,0, VAL1,"" )"rbit r14, r" ,12, VAL2,"" )" @ rbit pc, r12" )#endif "uxtah r0, r" ,0, HH1,", r" ,1, HH2,"" )"uxtah r14,r" ,12, HH2,", r" ,10,HH1,", ror #8" )"uxth r8, r" ,7, HH1,"" )" @ uxth pc, r7" )" @ uxth r8, pc" )" @ uxtah pc, r12, r10, ror #8" )" @ uxtah r14, r12, pc, ror #8" )"revsh r0, r" ,0, VAL1,"" )"revsh r14, r" ,12, VAL2,"" )" @ revsh pc, r12" )" @ revsh r14, pc" )"" ) /* Unallocated space */ "" ) /* Unallocated space */ "" ) /* Unallocated space */ "" ) /* Unallocated space */ #endif /* __LINUX_ARM_ARCH__ >= 6 */ #if __LINUX_ARM_ARCH__ >= 6"Signed multiplies" )"smlad r0, r" ,0, HH1,", r" ,1, HH2,", r" ,2, VAL1,"" )"smlad r14, r" ,12,HH2,", r" ,10,HH1,", r" ,8, VAL2,"" )" @ smlad pc, r12, r10, r8" )"smladx r0, r" ,0, HH1,", r" ,1, HH2,", r" ,2, VAL1,"" )"smladx r14, r" ,12,HH2,", r" ,10,HH1,", r" ,8, VAL2,"" )" @ smladx pc, r12, r10, r8" )"smuad r0, r" ,0, HH1,", r" ,1, HH2,"" )"smuad r14, r" ,12,HH2,", r" ,10,HH1,"" )" @ smuad pc, r12, r10" )"smuadx r0, r" ,0, HH1,", r" ,1, HH2,"" )"smuadx r14, r" ,12,HH2,", r" ,10,HH1,"" )" @ smuadx pc, r12, r10" )"smlsd r0, r" ,0, HH1,", r" ,1, HH2,", r" ,2, VAL1,"" )"smlsd r14, r" ,12,HH2,", r" ,10,HH1,", r" ,8, VAL2,"" )" @ smlsd pc, r12, r10, r8" )"smlsdx r0, r" ,0, HH1,", r" ,1, HH2,", r" ,2, VAL1,"" )"smlsdx r14, r" ,12,HH2,", r" ,10,HH1,", r" ,8, VAL2,"" )" @ smlsdx pc, r12, r10, r8" )"smusd r0, r" ,0, HH1,", r" ,1, HH2,"" )"smusd r14, r" ,12,HH2,", r" ,10,HH1,"" )" @ smusd pc, r12, r10" )"smusdx r0, r" ,0, HH1,", r" ,1, HH2,"" )"smusdx r14, r" ,12,HH2,", r" ,10,HH1,"" )" @ smusdx pc, r12, r10" )"smlald r" ,0, VAL1,", r" ,1, VAL2, ", r" ,0, HH1,", r" ,1, HH2)"smlald r" ,11,VAL2,", r" ,10,VAL1, ", r" ,9, HH2,", r" ,8, HH1)" @ smlald pc, r10, r9, r8" )" @ smlald r11, pc, r9, r8" )" @ smlald r11, r10, pc, r8" )" @ smlald r11, r10, r9, pc" )"smlaldx r" ,0, VAL1,", r" ,1, VAL2, ", r" ,0, HH1,", r" ,1, HH2)"smlaldx r" ,11,VAL2,", r" ,10,VAL1, ", r" ,9, HH2,", r" ,8, HH1)" @ smlaldx pc, r10, r9, r8" )" @ smlaldx r11, pc, r9, r8" )"smmla r0, r" ,0, VAL1,", r" ,1, VAL2,", r" ,2, VAL1,"" )"smmla r14, r" ,12,VAL2,", r" ,10,VAL1,", r" ,8, VAL2,"" )" @ smmla pc, r12, r10, r8" )"smmlar r0, r" ,0, VAL1,", r" ,1, VAL2,", r" ,2, VAL1,"" )"smmlar r14, r" ,12,VAL2,", r" ,10,VAL1,", r" ,8, VAL2,"" )" @ smmlar pc, r12, r10, r8" )"smmul r0, r" ,0, VAL1,", r" ,1, VAL2,"" )"smmul r14, r" ,12,VAL2,", r" ,10,VAL1,"" )" @ smmul pc, r12, r10" )"smmulr r0, r" ,0, VAL1,", r" ,1, VAL2,"" )"smmulr r14, r" ,12,VAL2,", r" ,10,VAL1,"" )" @ smmulr pc, r12, r10" )"smmls r0, r" ,0, VAL1,", r" ,1, VAL2,", r" ,2, VAL1,"" )"smmls r14, r" ,12,VAL2,", r" ,10,VAL1,", r" ,8, VAL2,"" )" @ smmls pc, r12, r10, r8" )"smmlsr r0, r" ,0, VAL1,", r" ,1, VAL2,", r" ,2, VAL1,"" )"smmlsr r14, r" ,12,VAL2,", r" ,10,VAL1,", r" ,8, VAL2,"" )" @ smmlsr pc, r12, r10, r8" )" @ smmlsr r14, pc, r10, r8" )" @ smmlsr r14, r12, pc, r8" )" @ smmlsr r14, r12, r10, pc" )"usad8 r0, r" ,0, VAL1,", r" ,1, VAL2,"" )"usad8 r14, r" ,12,VAL2,", r" ,10,VAL1,"" )" @ usad8 pc, r12, r10" )" @ usad8 r14, pc, r10" )" @ usad8 r14, r12, pc" )"usada8 r0, r" ,0, VAL1,", r" ,1, VAL2,", r" ,2, VAL3,"" )"usada8 r14, r" ,12,VAL2,", r" ,10,VAL1,", r" ,8, VAL3,"" )" @ usada8 pc, r12, r10, r8" )" @ usada8 r14, pc, r10, r8" )" @ usada8 r14, r12, pc, r8" )#endif /* __LINUX_ARM_ARCH__ >= 6 */ #if __LINUX_ARM_ARCH__ >= 7"Bit Field" )"sbfx r0, r" ,0 , VAL1,", #0, #31" )"sbfxeq r14, r" ,12, VAL2,", #8, #16" )"sbfx r4, r" ,10, VAL1,", #16, #15" )" @ sbfx pc, r12, #8, #16" )"ubfx r0, r" ,0 , VAL1,", #0, #31" )"ubfxcs r14, r" ,12, VAL2,", #8, #16" )"ubfx r4, r" ,10, VAL1,", #16, #15" )" @ ubfx pc, r12, #8, #16" )" @ ubfx r12, pc, #8, #16" )"bfc r" ,0, VAL1,", #4, #20" )"bfcvs r" ,14,VAL2,", #4, #20" )"bfc r" ,7, VAL1,", #0, #31" )"bfc r" ,8, VAL2,", #0, #31" )" @ bfc pc, #0, #31" );"bfi r" ,0, VAL1,", r" ,0 , VAL2,", #0, #31" )"bfipl r" ,12,VAL1,", r" ,14 , VAL2,", #4, #20" )" @ bfi pc, r14, #4, #20" )"" ) /* Permanently UNDEFINED */ "" ) /* Permanently UNDEFINED */ #endif /* __LINUX_ARM_ARCH__ >= 6 */ "Branch, branch with link, and block data transfer" )"stmda r" ,0, 16*4,", {r0}" )"stmdaeq r" ,4, 16*4,", {r0-r15}" )"stmdane r" ,8, 16*4,"!, {r8-r15}" )"stmda r" ,12,16*4,"!, {r1,r3,r5,r7,r8-r11,r14}" )"stmda r" ,13,0, "!, {pc}" )"ldmda r" ,0, 16*4,", {r0}" )"ldmdacs r" ,4, 15*4,", {r0-r15}" )"ldmdacc r" ,7, 15*4,"!, {r8-r15}" )"ldmda r" ,12,16*4,"!, {r1,r3,r5,r7,r8-r11,r14}" )"ldmda r" ,14,15*4,"!, {pc}" )"stmia r" ,0, 16*4,", {r0}" )"stmiami r" ,4, 16*4,", {r0-r15}" )"stmiapl r" ,8, 16*4,"!, {r8-r15}" )"stmia r" ,12,16*4,"!, {r1,r3,r5,r7,r8-r11,r14}" )"stmia r" ,14,0, "!, {pc}" )"ldmia r" ,0, 16*4,", {r0}" )"ldmiavs r" ,4, 0, ", {r0-r15}" )"ldmiavc r" ,7, 8*4, "!, {r8-r15}" )"ldmia r" ,12,16*4,"!, {r1,r3,r5,r7,r8-r11,r14}" )"ldmia r" ,14,15*4,"!, {pc}" )"stmdb r" ,0, 16*4,", {r0}" )"stmdbhi r" ,4, 16*4,", {r0-r15}" )"stmdbls r" ,8, 16*4,"!, {r8-r15}" )"stmdb r" ,12,16*4,"!, {r1,r3,r5,r7,r8-r11,r14}" )"stmdb r" ,13,4, "!, {pc}" )"ldmdb r" ,0, 16*4,", {r0}" )"ldmdbge r" ,4, 16*4,", {r0-r15}" )"ldmdblt r" ,7, 16*4,"!, {r8-r15}" )"ldmdb r" ,12,16*4,"!, {r1,r3,r5,r7,r8-r11,r14}" )"ldmdb r" ,14,16*4,"!, {pc}" )"stmib r" ,0, 16*4,", {r0}" )"stmibgt r" ,4, 16*4,", {r0-r15}" )"stmible r" ,8, 16*4,"!, {r8-r15}" )"stmib r" ,12,16*4,"!, {r1,r3,r5,r7,r8-r11,r14}" )"stmib r" ,13,-4, "!, {pc}" )"ldmib r" ,0, 16*4,", {r0}" )"ldmibeq r" ,4, -4,", {r0-r15}" )"ldmibne r" ,7, 7*4,"!, {r8-r15}" )"ldmib r" ,12,16*4,"!, {r1,r3,r5,r7,r8-r11,r14}" )"ldmib r" ,14,14*4,"!, {pc}" )"stmdb r" ,13,16*4,"!, {r3-r12,lr}" )"stmdbeq r" ,13,16*4,"!, {r3-r12}" )"stmdbne r" ,2, 16*4,", {r3-r12,lr}" )"stmdb r" ,13,16*4,"!, {r2-r12,lr}" )"stmdb r" ,0, 16*4,", {r0-r12}" )"stmdb r" ,0, 16*4,", {r0-r12,lr}" )"ldmia r" ,13,5*4, "!, {r3-r12,pc}" )"ldmiacc r" ,13,5*4, "!, {r3-r12}" )"ldmiacs r" ,2, 5*4, "!, {r3-r12,pc}" )"ldmia r" ,13,4*4, "!, {r2-r12,pc}" )"ldmia r" ,0, 16*4,", {r0-r12}" )"ldmia r" ,0, 16*4,", {r0-r12,lr}" )#ifdef CONFIG_THUMB2_KERNEL"ldmplia r" ,0,15*4,", {pc}" )"ldmmiia r" ,13,0,", {r0-r15}" )#endif "b 2f" )"bl 2f" )"b 2b" )"bl 2b" )"beq 2f" )"bleq 2f" )"bne 2b" )"blne 2b" )"bgt 2f" )"blgt 2f" )"blt 2b" )"bllt 2b" )"Supervisor Call, and coprocessor instructions" )/* * We can't really test these by executing them, so all * we can do is check that probes are, or are not allowed. * At the moment none are allowed... #define TEST_COPROCESSOR(code) TEST_UNSUPPORTED(code)#define COPROCESSOR_INSTRUCTIONS_ST_LD(two,cc) \"stc" two" p0, cr0, [r13, #4]" ) \"stc" two" p0, cr0, [r13, #-4]" ) \"stc" two" p0, cr0, [r13, #4]!" ) \"stc" two" p0, cr0, [r13, #-4]!" ) \"stc" two" p0, cr0, [r13], #4" ) \"stc" two" p0, cr0, [r13], #-4" ) \"stc" two" p0, cr0, [r13], {1}" ) \"stc" two"l p0, cr0, [r13, #4]" ) \"stc" two"l p0, cr0, [r13, #-4]" ) \"stc" two"l p0, cr0, [r13, #4]!" ) \"stc" two"l p0, cr0, [r13, #-4]!" ) \"stc" two"l p0, cr0, [r13], #4" ) \"stc" two"l p0, cr0, [r13], #-4" ) \"stc" two"l p0, cr0, [r13], {1}" ) \"ldc" two" p0, cr0, [r13, #4]" ) \"ldc" two" p0, cr0, [r13, #-4]" ) \"ldc" two" p0, cr0, [r13, #4]!" ) \"ldc" two" p0, cr0, [r13, #-4]!" ) \"ldc" two" p0, cr0, [r13], #4" ) \"ldc" two" p0, cr0, [r13], #-4" ) \"ldc" two" p0, cr0, [r13], {1}" ) \"ldc" two"l p0, cr0, [r13, #4]" ) \"ldc" two"l p0, cr0, [r13, #-4]" ) \"ldc" two"l p0, cr0, [r13, #4]!" ) \"ldc" two"l p0, cr0, [r13, #-4]!" ) \"ldc" two"l p0, cr0, [r13], #4" ) \"ldc" two"l p0, cr0, [r13], #-4" ) \"ldc" two"l p0, cr0, [r13], {1}" ) \"stc" two" p0, cr0, [r15, #4]" ) \"stc" two" p0, cr0, [r15, #-4]" ) \## cc## daf0001) " @ stc" two" 0, cr0, [r15, #4]!" ) \## cc## d2f0001) " @ stc" two" 0, cr0, [r15, #-4]!" ) \## cc## caf0001) " @ stc" two" 0, cr0, [r15], #4" ) \## cc## c2f0001) " @ stc" two" 0, cr0, [r15], #-4" ) \"stc" two" p0, cr0, [r15], {1}" ) \"stc" two"l p0, cr0, [r15, #4]" ) \"stc" two"l p0, cr0, [r15, #-4]" ) \## cc## def0001) " @ stc" two"l 0, cr0, [r15, #4]!" ) \## cc## d6f0001) " @ stc" two"l 0, cr0, [r15, #-4]!" ) \## cc## cef0001) " @ stc" two"l 0, cr0, [r15], #4" ) \## cc## c6f0001) " @ stc" two"l 0, cr0, [r15], #-4" ) \"stc" two"l p0, cr0, [r15], {1}" ) \"ldc" two" p0, cr0, [r15, #4]" ) \"ldc" two" p0, cr0, [r15, #-4]" ) \## cc## dbf0001) " @ ldc" two" 0, cr0, [r15, #4]!" ) \## cc## d3f0001) " @ ldc" two" 0, cr0, [r15, #-4]!" ) \## cc## cbf0001) " @ ldc" two" 0, cr0, [r15], #4" ) \## cc## c3f0001) " @ ldc" two" 0, cr0, [r15], #-4" ) \"ldc" two" p0, cr0, [r15], {1}" ) \"ldc" two"l p0, cr0, [r15, #4]" ) \"ldc" two"l p0, cr0, [r15, #-4]" ) \## cc## dff0001) " @ ldc" two"l 0, cr0, [r15, #4]!" ) \## cc## d7f0001) " @ ldc" two"l 0, cr0, [r15, #-4]!" ) \## cc## cff0001) " @ ldc" two"l 0, cr0, [r15], #4" ) \## cc## c7f0001) " @ ldc" two"l 0, cr0, [r15], #-4" ) \"ldc" two"l p0, cr0, [r15], {1}" )#define COPROCESSOR_INSTRUCTIONS_MC_MR(two,cc) \"mcrr" two" p0, 15, r0, r14, cr0" ) \"mcrr" two" p15, 0, r14, r0, cr15" ) \## cc## c4f00f0) " @ mcrr" two" 0, 15, r0, r15, cr0" ) \## cc## c40ff0f) " @ mcrr" two" 15, 0, r15, r0, cr15" ) \"mrrc" two" p0, 15, r0, r14, cr0" ) \"mrrc" two" p15, 0, r14, r0, cr15" ) \## cc## c5f00f0) " @ mrrc" two" 0, 15, r0, r15, cr0" ) \## cc## c50ff0f) " @ mrrc" two" 15, 0, r15, r0, cr15" ) \"cdp" two" p15, 15, cr15, cr15, cr15, 7" ) \"cdp" two" p0, 0, cr0, cr0, cr0, 0" ) \"mcr" two" p15, 7, r15, cr15, cr15, 7" ) \"mcr" two" p0, 0, r0, cr0, cr0, 0" ) \"mrc" two" p15, 7, r14, cr15, cr15, 7" ) \"mrc" two" p0, 0, r0, cr0, cr0, 0" )"" ,e)#if __LINUX_ARM_ARCH__ >= 5"" ,e)#endif "svc 0" )"svc 0xffffff" )"svc 0" )"Unconditional instruction" )#if __LINUX_ARM_ARCH__ >= 6"srsda sp, 0x13" )"srsdb sp, 0x13" )"srsia sp, 0x13" )"srsib sp, 0x13" )"srsda sp!, 0x13" )"srsdb sp!, 0x13" )"srsia sp!, 0x13" )"srsib sp!, 0x13" )"rfeda sp" )"rfedb sp" )"rfeia sp" )"rfeib sp" )"rfeda sp!" )"rfedb sp!" )"rfeia sp!" )"rfeib sp!" )" @ rfeda pc" )" @ rfedb pc" )" @ rfeia pc" )" @ rfeib pc" )" @ rfeda pc!" )" @ rfedb pc!" )" @ rfeia pc!" )" @ rfeib pc!" )#endif /* __LINUX_ARM_ARCH__ >= 6 */ #if __LINUX_ARM_ARCH__ >= 6"blx __dummy_thumb_subroutine_even" ,".thumb \n\t" ".space 4 \n\t" ".type __dummy_thumb_subroutine_even, %%function \n\t" "__dummy_thumb_subroutine_even: \n\t" "mov r0, pc \n\t" "bx lr \n\t" ".arm \n\t" "blx __dummy_thumb_subroutine_even" )"blx __dummy_thumb_subroutine_odd" ,".thumb \n\t" ".space 2 \n\t" ".type __dummy_thumb_subroutine_odd, %%function \n\t" "__dummy_thumb_subroutine_odd: \n\t" "mov r0, pc \n\t" "bx lr \n\t" ".arm \n\t" "blx __dummy_thumb_subroutine_odd" )#endif /* __LINUX_ARM_ARCH__ >= 6 */ #if __LINUX_ARM_ARCH__ >= 5"2" ,f)#endif #if __LINUX_ARM_ARCH__ >= 6"2" ,f)#endif "Miscellaneous instructions, memory hints, and Advanced SIMD instructions" )#if __LINUX_ARM_ARCH__ >= 6"cps 0x13" )"cpsie i" )"cpsid i" )"cpsie i,0x13" )"cpsid i,0x13" )"setend le" )"setend be" )#endif #if __LINUX_ARM_ARCH__ >= 7"pli [r" ,0,0b,", #16]" )"pli [pc, #0]" )"pli [r" ,12,0b,", r" ,0, 16,"]" )"pli [r" ,0, 0b,", -r" ,12,16,", lsl #4]" )#endif #if __LINUX_ARM_ARCH__ >= 5"pld [r" ,0,32,", #-16]" )"pld [pc, #0]" )"pld [r" ,7, 24, ", r" ,0, 16,"]" )"pld [r" ,8, 24, ", -r" ,12,16,", lsl #4]" )#endif #if __LINUX_ARM_ARCH__ >= 7" @ pldw [r0, #0]" )" @ pldw [r7, r0]" )" @ pldw [r8, r12, lsl #3]" );#endif #if __LINUX_ARM_ARCH__ >= 7"clrex" )"dsb" )"dmb" )"isb" )#endif "\n" );
Messung V0.5 C=96 H=80 G=88
