// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree Include file for Marvell Armada 38x family of SoCs.
*
* Copyright (C) 2014 Marvell
*
* Lior Amsalem <alior@marvell.com>
* Gregory CLEMENT <gregory.clement@free-electrons.com>
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
/ {
#address-cells = <1>;
#size-cells = <1>;
model = "Marvell Armada 38x family SoC";
compatible = "marvell,armada380";
aliases {
gpio0 = &gpio0;
gpio1 = &gpio1;
serial0 = &uart0;
serial1 = &uart1;
};
pmu {
compatible = "arm,cortex-a9-pmu";
interrupts-extended = <&mpic 3>;
};
soc {
compatible = "marvell,armada380-mbus", "simple-bus";
#address-cells = <2>;
#size-cells = <1>;
controller = <&mbusc>;
interrupt-parent = <&gic>;
pcie-mem-aperture = <0xe0000000 0x8000000>;
pcie-io-aperture = <0xe8000000 0x100000>;
bootrom {
compatible = "marvell,bootrom";
reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
};
devbus_bootcs: devbus-bootcs {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&coreclk 0>;
status = "disabled";
};
devbus_cs0: devbus-cs0 {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&coreclk 0>;
status = "disabled";
};
devbus_cs1: devbus-cs1 {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&coreclk 0>;
status = "disabled";
};
devbus_cs2: devbus-cs2 {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&coreclk 0>;
status = "disabled";
};
devbus_cs3: devbus-cs3 {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&coreclk 0>;
status = "disabled";
};
internal-regs {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
sdramc: sdramc@1400 {
compatible = "marvell,armada-xp-sdram-controller";
reg = <0x1400 0x500>;
};
L2: cache-controller@8000 {
compatible = "arm,pl310-cache";
reg = <0x8000 0x1000>;
cache-unified;
cache-level = <2>;
arm,double-linefill-incr = <0>;
arm,double-linefill-wrap = <0>;
arm,double-linefill = <0>;
prefetch-data = <1>;
};
scu@c000 {
compatible = "arm,cortex-a9-scu";
reg = <0xc000 0x58>;
};
timer@c200 {
compatible = "arm,cortex-a9-global-timer";
reg = <0xc200 0x20>;
interrupts = <GIC_PPI 11 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
clocks = <&coreclk 2>;
};
timer@c600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0xc600 0x20>;
interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
clocks = <&coreclk 2>;
};
gic: interrupt-controller@d000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
#size-cells = <0>;
interrupt-controller;
reg = <0xd000 0x1000>,
<0xc100 0x100>;
};
i2c0: i2c@11000 {
compatible = "marvell,mv78230-a0-i2c", "marvell,mv64xxx-i2c";
reg = <0x11000 0x20>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&coreclk 0>;
status = "disabled";
};
i2c1: i2c@11100 {
compatible = "marvell,mv78230-a0-i2c", "marvell,mv64xxx-i2c";
reg = <0x11100 0x20>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&coreclk 0>;
status = "disabled";
};
uart0: serial@12000 {
compatible = "marvell,armada-38x-uart", "ns16550a";
reg = <0x12000 0x100>;
reg-shift = <2>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
reg-io-width = <1>;
clocks = <&coreclk 0>;
status = "disabled";
};
uart1: serial@12100 {
compatible = "marvell,armada-38x-uart", "ns16550a";
reg = <0x12100 0x100>;
reg-shift = <2>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
reg-io-width = <1>;
clocks = <&coreclk 0>;
status = "disabled";
};
pinctrl: pinctrl@18000 {
reg = <0x18000 0x20>;
ge0_rgmii_pins: ge-rgmii-pins-0 {
marvell,pins = "mpp6", "mpp7", "mpp8",
"mpp9", "mpp10", "mpp11",
"mpp12", "mpp13", "mpp14",
"mpp15", "mpp16", "mpp17";
marvell,function = "ge0";
};
ge1_rgmii_pins: ge-rgmii-pins-1 {
marvell,pins = "mpp21", "mpp27", "mpp28",
"mpp29", "mpp30", "mpp31",
"mpp32", "mpp37", "mpp38",
"mpp39", "mpp40", "mpp41";
marvell,function = "ge1";
};
i2c0_pins: i2c-pins-0 {
marvell,pins = "mpp2", "mpp3";
marvell,function = "i2c0";
};
mdio_pins: mdio-pins {
marvell,pins = "mpp4", "mpp5";
marvell,function = "ge";
};
ref_clk0_pins: ref-clk-pins-0 {
marvell,pins = "mpp45";
marvell,function = "ref";
};
ref_clk1_pins: ref-clk-pins-1 {
marvell,pins = "mpp46";
marvell,function = "ref";
};
spi0_pins: spi-pins-0 {
marvell,pins = "mpp22", "mpp23", "mpp24",
"mpp25";
marvell,function = "spi0";
};
spi1_pins: spi-pins-1 {
marvell,pins = "mpp56", "mpp57", "mpp58",
"mpp59";
marvell,function = "spi1";
};
nand_pins: nand-pins {
marvell,pins = "mpp22", "mpp34", "mpp23",
"mpp33", "mpp38", "mpp28",
"mpp40", "mpp42", "mpp35",
"mpp36", "mpp25", "mpp30",
"mpp32";
marvell,function = "dev";
};
nand_rb: nand-rb {
marvell,pins = "mpp41";
marvell,function = "nand";
};
uart0_pins: uart-pins-0 {
marvell,pins = "mpp0", "mpp1";
marvell,function = "ua0";
};
uart1_pins: uart-pins-1 {
marvell,pins = "mpp19", "mpp20";
marvell,function = "ua1";
};
sdhci_pins: sdhci-pins {
marvell,pins = "mpp48", "mpp49", "mpp50",
"mpp52", "mpp53", "mpp54",
"mpp55", "mpp57", "mpp58",
"mpp59";
marvell,function = "sd0";
};
sata0_pins: sata-pins-0 {
marvell,pins = "mpp20";
marvell,function = "sata0";
};
sata1_pins: sata-pins-1 {
marvell,pins = "mpp19";
marvell,function = "sata1";
};
sata2_pins: sata-pins-2 {
marvell,pins = "mpp47";
marvell,function = "sata2";
};
sata3_pins: sata-pins-3 {
marvell,pins = "mpp44";
marvell,function = "sata3";
};
i2s_pins: i2s-pins {
marvell,pins = "mpp48", "mpp49",
"mpp50", "mpp51",
"mpp52", "mpp53";
marvell,function = "audio";
};
spdif_pins: spdif-pins {
marvell,pins = "mpp51";
marvell,function = "audio";
};
};
gpio0: gpio@18100 {
compatible = "marvell,armada-370-gpio",
"marvell,orion-gpio";
reg = <0x18100 0x40>, <0x181c0 0x08>;
reg-names = "gpio", "pwm";
ngpios = <32>;
gpio-controller;
gpio-ranges = <&pinctrl 0 0 32>;
#gpio-cells = <2>;
#pwm-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&coreclk 0>;
};
gpio1: gpio@18140 {
compatible = "marvell,armada-370-gpio",
"marvell,orion-gpio";
reg = <0x18140 0x40>, <0x181c8 0x08>;
reg-names = "gpio", "pwm";
ngpios = <28>;
gpio-controller;
gpio-ranges = <&pinctrl 0 32 28>;
#gpio-cells = <2>;
#pwm-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&coreclk 0>;
};
systemc: system-controller@18200 {
compatible = "marvell,armada-380-system-controller",
"marvell,armada-370-xp-system-controller";
reg = <0x18200 0x100>;
};
gateclk: clock-gating-control@18220 {
compatible = "marvell,armada-380-gating-clock";
reg = <0x18220 0x4>;
clocks = <&coreclk 0>;
#clock-cells = <1>;
};
comphy: phy@18300 {
compatible = "marvell,armada-380-comphy";
reg-names = "comphy", "conf";
reg = <0x18300 0x100>, <0x18460 4>;
#address-cells = <1>;
#size-cells = <0>;
comphy0: phy@0 {
reg = <0>;
#phy-cells = <1>;
};
comphy1: phy@1 {
reg = <1>;
#phy-cells = <1>;
};
comphy2: phy@2 {
reg = <2>;
#phy-cells = <1>;
};
comphy3: phy@3 {
reg = <3>;
#phy-cells = <1>;
};
comphy4: phy@4 {
reg = <4>;
#phy-cells = <1>;
};
comphy5: phy@5 {
reg = <5>;
#phy-cells = <1>;
};
};
coreclk: mvebu-sar@18600 {
compatible = "marvell,armada-380-core-clock";
reg = <0x18600 0x04>;
#clock-cells = <1>;
};
mbusc: mbus-controller@20000 {
compatible = "marvell,mbus-controller";
reg = <0x20000 0x100>, <0x20180 0x20>,
<0x20250 0x8>;
};
mpic: interrupt-controller@20a00 {
compatible = "marvell,mpic";
reg = <0x20a00 0x2d0>, <0x21070 0x58>;
#interrupt-cells = <1>;
interrupt-controller;
msi-controller;
interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
};
timer: timer@20300 {
compatible = "marvell,armada-380-timer",
"marvell,armada-xp-timer";
reg = <0x20300 0x30>, <0x21040 0x30>;
interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
<&mpic 5>,
<&mpic 6>;
clocks = <&coreclk 2>, <&refclk>;
clock-names = "nbclk", "fixed";
};
watchdog: watchdog@20300 {
compatible = "marvell,armada-380-wdt";
reg = <0x20300 0x34>, <0x20704 0x4>, <0x18260 0x4>;
clocks = <&coreclk 2>, <&refclk>;
clock-names = "nbclk", "fixed";
interrupts-extended = <&gic GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
cpurst: cpurst@20800 {
compatible = "marvell,armada-370-cpu-reset";
reg = <0x20800 0x10>;
};
mpcore-soc-ctrl@20d20 {
compatible = "marvell,armada-380-mpcore-soc-ctrl";
reg = <0x20d20 0x6c>;
};
coherencyfab: coherency-fabric@21010 {
compatible = "marvell,armada-380-coherency-fabric";
reg = <0x21010 0x1c>;
};
pmsu: pmsu@22000 {
compatible = "marvell,armada-380-pmsu";
reg = <0x22000 0x1000>;
};
/*
* As a special exception to the "order by
* register address" rule, the eth0 node is
* placed here to ensure that it gets
* registered as the first interface, since
* the network subsystem doesn't allow naming
* interfaces using DT aliases. Without this,
* the ordering of interfaces is different
* from the one used in U-Boot and the
* labeling of interfaces on the boards, which
* is very confusing for users.
*/
eth0: ethernet@70000 {
compatible = "marvell,armada-370-neta";
reg = <0x70000 0x4000>;
interrupts-extended = <&mpic 8>;
clocks = <&gateclk 4>;
tx-csum-limit = <9800>;
status = "disabled";
};
eth1: ethernet@30000 {
compatible = "marvell,armada-370-neta";
reg = <0x30000 0x4000>;
interrupts-extended = <&mpic 10>;
clocks = <&gateclk 3>;
status = "disabled";
};
eth2: ethernet@34000 {
compatible = "marvell,armada-370-neta";
reg = <0x34000 0x4000>;
interrupts-extended = <&mpic 12>;
clocks = <&gateclk 2>;
status = "disabled";
};
usb0: usb@58000 {
compatible = "marvell,orion-ehci";
reg = <0x58000 0x500>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gateclk 18>;
status = "disabled";
};
xor0: xor@60800 {
compatible = "marvell,armada-380-xor", "marvell,orion-xor";
reg = <0x60800 0x100
0x60a00 0x100>;
clocks = <&gateclk 22>;
status = "okay";
xor00 {
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
dmacap,memcpy;
dmacap,xor;
};
xor01 {
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
dmacap,memcpy;
dmacap,xor;
dmacap,memset;
};
};
xor1: xor@60900 {
compatible = "marvell,armada-380-xor", "marvell,orion-xor";
reg = <0x60900 0x100
0x60b00 0x100>;
clocks = <&gateclk 28>;
status = "okay";
xor10 {
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
dmacap,memcpy;
dmacap,xor;
};
xor11 {
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
dmacap,memcpy;
dmacap,xor;
dmacap,memset;
};
};
mdio: mdio@72004 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "marvell,orion-mdio";
reg = <0x72004 0x4>;
clocks = <&gateclk 4>;
};
cesa: crypto@90000 {
compatible = "marvell,armada-38x-crypto";
reg = <0x90000 0x10000>;
reg-names = "regs";
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gateclk 23>, <&gateclk 21>,
<&gateclk 14>, <&gateclk 16>;
clock-names = "cesa0", "cesa1",
"cesaz0", "cesaz1";
marvell,crypto-srams = <&crypto_sram0>,
<&crypto_sram1>;
marvell,crypto-sram-size = <0x800>;
};
rtc: rtc@a3800 {
compatible = "marvell,armada-380-rtc";
reg = <0xa3800 0x20>, <0x184a0 0x0c>;
reg-names = "rtc", "rtc-soc";
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
};
ahci0: sata@a8000 {
compatible = "marvell,armada-380-ahci";
reg = <0xa8000 0x2000>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gateclk 15>;
status = "disabled";
};
bm: bm@c8000 {
compatible = "marvell,armada-380-neta-bm";
reg = <0xc8000 0xac>;
clocks = <&gateclk 13>;
internal-mem = <&bm_bppi>;
status = "disabled";
};
ahci1: sata@e0000 {
compatible = "marvell,armada-380-ahci";
reg = <0xe0000 0x2000>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gateclk 30>;
status = "disabled";
};
coredivclk: clock@e4250 {
compatible = "marvell,armada-380-corediv-clock";
reg = <0xe4250 0xc>;
#clock-cells = <1>;
clocks = <&mainpll>;
clock-output-names = "nand";
};
thermal: thermal@e8078 {
compatible = "marvell,armada380-thermal";
reg = <0xe4078 0x4>, <0xe4070 0x8>;
status = "okay";
};
nand_controller: nand-controller@d0000 {
compatible = "marvell,armada370-nand-controller";
reg = <0xd0000 0x54>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&coredivclk 0>;
status = "disabled";
};
sdhci: sdhci@d8000 {
compatible = "marvell,armada-380-sdhci";
reg-names = "sdhci", "mbus", "conf-sdio3";
reg = <0xd8000 0x1000>,
<0xdc000 0x100>,
<0x18454 0x4>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gateclk 17>;
mrvl,clk-delay-cycles = <0x1F>;
status = "disabled";
};
audio_controller: audio-controller@e8000 {
#sound-dai-cells = <1>;
compatible = "marvell,armada-380-audio";
reg = <0xe8000 0x4000>, <0x18410 0xc>,
<0x18204 0x4>;
reg-names = "i2s_regs", "pll_regs", "soc_ctrl";
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gateclk 0>;
clock-names = "internal";
status = "disabled";
};
usb3_0: usb3@f0000 {
compatible = "marvell,armada-380-xhci";
reg = <0xf0000 0x4000>,<0xf4000 0x4000>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gateclk 9>;
status = "disabled";
};
usb3_1: usb3@f8000 {
compatible = "marvell,armada-380-xhci";
reg = <0xf8000 0x4000>,<0xfc000 0x4000>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gateclk 10>;
status = "disabled";
};
};
crypto_sram0: sa-sram0 {
compatible = "mmio-sram";
reg = <MBUS_ID(0x09, 0x19) 0 0x800>;
clocks = <&gateclk 23>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 MBUS_ID(0x09, 0x19) 0 0x800>;
};
crypto_sram1: sa-sram1 {
compatible = "mmio-sram";
reg = <MBUS_ID(0x09, 0x15) 0 0x800>;
clocks = <&gateclk 21>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 MBUS_ID(0x09, 0x15) 0 0x800>;
};
bm_bppi: bm-bppi {
compatible = "mmio-sram";
reg = <MBUS_ID(0x0c, 0x04) 0 0x100000>;
ranges = <0 MBUS_ID(0x0c, 0x04) 0 0x100000>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&gateclk 13>;
no-memory-wc;
status = "disabled";
};
spi0: spi@10600 {
compatible = "marvell,armada-380-spi",
"marvell,orion-spi";
reg = <MBUS_ID(0xf0, 0x01) 0x10600 0x50>;
#address-cells = <1>;
#size-cells = <0>;
cell-index = <0>;
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&coreclk 0>;
status = "disabled";
};
spi1: spi@10680 {
compatible = "marvell,armada-380-spi",
"marvell,orion-spi";
reg = <MBUS_ID(0xf0, 0x01) 0x10680 0x50>;
#address-cells = <1>;
#size-cells = <0>;
cell-index = <1>;
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&coreclk 0>;
status = "disabled";
};
};
clocks {
/* 1 GHz fixed main PLL */
mainpll: mainpll {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <1000000000>;
};
/* 25 MHz reference crystal */
refclk: oscillator {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
};
};
