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# SPDX-License-Identifier: (GPL-
2.
0-only OR BSD-
2-Clause)
%YAML
1.
2
---
$id:
http://devicetree.org/schemas/crypto/fsl,sec2.0.yaml#
$schema:
http://devicetree.org/meta-schemas/core.yaml#
title: Freescale SoC SEC Security Engines versions
1.x-
2.x-
3.x
maintainers:
- J. Neuschäfer <j.ne@posteo.net>
properties:
compatible:
description:
Should contain entries for this and backward compatible SEC versions,
high to low. Warning - SEC1 and SEC2 are mutually exclusive.
oneOf:
- items:
- const: fsl,sec3.
3
- const: fsl,sec3.
1
- const: fsl,sec3.
0
- const: fsl,sec2.
4
- const: fsl,sec2.
2
- const: fsl,sec2.
1
- const: fsl,sec2.
0
- items:
- const: fsl,sec3.
1
- const: fsl,sec3.
0
- const: fsl,sec2.
4
- const: fsl,sec2.
2
- const: fsl,sec2.
1
- const: fsl,sec2.
0
- items:
- const: fsl,sec3.
0
- const: fsl,sec2.
4
- const: fsl,sec2.
2
- const: fsl,sec2.
1
- const: fsl,sec2.
0
- items:
- const: fsl,sec2.
4
- const: fsl,sec2.
2
- const: fsl,sec2.
1
- const: fsl,sec2.
0
- items:
- const: fsl,sec2.
2
- const: fsl,sec2.
1
- const: fsl,sec2.
0
- items:
- const: fsl,sec2.
1
- const: fsl,sec2.
0
- items:
- const: fsl,sec2.
0
- items:
- const: fsl,sec1.
2
- const: fsl,sec1.
0
- items:
- const: fsl,sec1.
0
reg:
maxItems:
1
interrupts:
maxItems:
1
fsl,num-channels:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [
1,
4 ]
description: An integer representing the number of channels available.
fsl,channel-fifo-len:
$ref: /schemas/types.yaml#/definitions/uint32
maximum:
100
description:
An integer representing the number of descriptor pointers each channel
fetch fifo can hold.
fsl,exec-units-mask:
$ref: /schemas/types.yaml#/definitions/uint32
maximum:
0xfff
description: |
The bitmask representing what execution units (EUs) are available.
EU information should be encoded following the SEC's Descriptor Header
Dword EU_SEL0 field documentation, i.e. as follows:
bit
0 = reserved - should be
0
bit
1 = set if SEC has the ARC4 EU (AFEU)
bit
2 = set if SEC has the DES/
3DES EU (DEU)
bit
3 = set if SEC has the message digest EU (MDEU/MDEU-A)
bit
4 = set if SEC has the random number generator EU (RNG)
bit
5 = set if SEC has the public key EU (PKEU)
bit
6 = set if SEC has the AES EU (AESU)
bit
7 = set if SEC has the Kasumi EU (KEU)
bit
8 = set if SEC has the CRC EU (CRCU)
bit
11 = set if SEC has the message digest EU extended alg set (MDEU-B)
remaining bits are reserved for future SEC EUs.
fsl,descriptor-types-mask:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
The bitmask representing what descriptors are available. Descriptor type
information should be encoded following the SEC's Descriptor Header Dword
DESC_TYPE field documentation, i.e. as follows:
bit
0 = SEC supports descriptor type aesu_ctr_nonsnoop
bit
1 = SEC supports descriptor type ipsec_esp
bit
2 = SEC supports descriptor type common_nonsnoop
bit
3 = SEC supports descriptor type
802.
11i AES ccmp
bit
4 = SEC supports descriptor type hmac_snoop_no_afeu
bit
5 = SEC supports descriptor type srtp
bit
6 = SEC supports descriptor type non_hmac_snoop_no_afeu
bit
7 = SEC supports descriptor type pkeu_assemble
bit
8 = SEC supports descriptor type aesu_key_expand_output
bit
9 = SEC supports descriptor type pkeu_ptmul
bit
10 = SEC supports descriptor type common_nonsnoop_afeu
bit
11 = SEC supports descriptor type pkeu_ptadd_dbl
..and so on and so forth.
required:
- compatible
- reg
- fsl,num-channels
- fsl,channel-fifo-len
- fsl,exec-units-mask
- fsl,descriptor-types-mask
unevaluatedProperties: false
examples:
- |
/* MPC8548E */
crypto@
30000 {
compatible = "fsl,sec2.
1", "fsl,sec2.
0";
reg = <
0x30000
0x10000>;
interrupts = <
29 2>;
interrupt-parent = <&mpic>;
fsl,num-channels = <
4>;
fsl,channel-fifo-len = <
24>;
fsl,exec-units-mask = <
0xfe>;
fsl,descriptor-types-mask = <
0x12b0ebf>;
};
...
