Quelle  snps,dwc-ahci.yaml   Sprache: unbekannt

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/ata/snps,dwc-ahci.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Synopsys DWC AHCI SATA controller

maintainers:
  - Serge Semin <fancer.lancer@gmail.com>

description:
  This document defines device tree bindings for the generic Synopsys DWC
  implementation of the AHCI SATA controller.

select:
  properties:
    compatible:
      enum:
        - snps,dwc-ahci
        - snps,spear-ahci
  required:
    - compatible

allOf:
  - $ref: snps,dwc-ahci-common.yaml#

properties:
  compatible:
    oneOf:
      - description: Synopsys AHCI SATA-compatible devices
        const: snps,dwc-ahci
      - description: SPEAr1340 AHCI SATA device
        const: snps,spear-ahci

patternProperties:
  "^sata-port@[0-9a-e]$":
    $ref: /schemas/ata/snps,dwc-ahci-common.yaml#/$defs/dwc-ahci-port

    unevaluatedProperties: false

required:
  - compatible
  - reg
  - interrupts

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/ata/ahci.h>

    sata@122f0000 {
      compatible = "snps,dwc-ahci";
      reg = <0x122F0000 0x1ff>;
      #address-cells = <1>;
      #size-cells = <0>;

      interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;

      clocks = <&clock1>, <&clock2>;
      clock-names = "aclk", "ref";

      phys = <&sata_phy>;
      phy-names = "sata-phy";

      ports-implemented = <0x1>;

      sata-port@0 {
        reg = <0>;

        hba-port-cap = <HBA_PORT_FBSCP>;

        snps,tx-ts-max = <512>;
        snps,rx-ts-max = <512>;
      };
    };

...