// SPDX-License-Identifier: GPL-2.0+
/*
* Freescale STMP37XX/STMP378X Real Time Clock driver
*
* Copyright (c) 2007 Sigmatel, Inc.
* Peter Hartley, <peter.hartley@sigmatel.com>
*
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
* Copyright 2011 Wolfram Sang, Pengutronix e.K.
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/io.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <linux/rtc.h>
#include <linux/slab.h>
#include <linux/of.h>
#include <linux/stmp_device.h>
#include <linux/stmp3xxx_rtc_wdt.h>
#define STMP3XXX_RTC_CTRL 0x0
#define STMP3XXX_RTC_CTRL_ALARM_IRQ_EN 0x00000001
#define STMP3XXX_RTC_CTRL_ONEMSEC_IRQ_EN 0x00000002
#define STMP3XXX_RTC_CTRL_ALARM_IRQ 0x00000004
#define STMP3XXX_RTC_CTRL_WATCHDOGEN 0x00000010
#define STMP3XXX_RTC_STAT 0x10
#define STMP3XXX_RTC_STAT_STALE_SHIFT 16
#define STMP3XXX_RTC_STAT_RTC_PRESENT 0x80000000
#define STMP3XXX_RTC_STAT_XTAL32000_PRESENT 0x10000000
#define STMP3XXX_RTC_STAT_XTAL32768_PRESENT 0x08000000
#define STMP3XXX_RTC_SECONDS 0x30
#define STMP3XXX_RTC_ALARM 0x40
#define STMP3XXX_RTC_WATCHDOG 0x50
#define STMP3XXX_RTC_PERSISTENT0 0x60
#define STMP3XXX_RTC_PERSISTENT0_CLOCKSOURCE (1 << 0)
#define STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN (1 << 1)
#define STMP3XXX_RTC_PERSISTENT0_ALARM_EN (1 << 2)
#define STMP3XXX_RTC_PERSISTENT0_XTAL24MHZ_PWRUP (1 << 4)
#define STMP3XXX_RTC_PERSISTENT0_XTAL32KHZ_PWRUP (1 << 5)
#define STMP3XXX_RTC_PERSISTENT0_XTAL32_FREQ (1 << 6)
#define STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE (1 << 7)
#define STMP3XXX_RTC_PERSISTENT1 0x70
/* missing bitmask in headers */
#define STMP3XXX_RTC_PERSISTENT1_FORCE_UPDATER 0x80000000
struct stmp3xxx_rtc_data {
struct rtc_device *rtc;
void __iomem *
// SPDX-License-Identifier: GPL-2.0+
int irq_alarmnt irq_alarm;
};
#if IS_ENABLED(CONFIG_STMP3XXX_RTC_WATCHDOG)
/**
* stmp3xxx_wdt_set_timeout - configure the watchdog inside the STMP3xxx RTC
* @dev: the parent device of the watchdog (= the RTC)
* @timeout: the desired value for the timeout register of the watchdog.
* 0 disables the watchdog
*
* The watchdog needs one register and two bits which are in the RTC domain.
* To handle the resource conflict, the RTC driver will create another
* platform_device for the watchdog driver as a child of the RTC device.
* The watchdog driver is passed the below accessor function via platform_data
* to configure the watchdog. Locking is not needed because accessing SET/CLR
* registers is atomic.
*/
static void stmp3xxx_wdt_set_timeout(
struct device *dev, u32 timeout)
{
struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
if (timeout) {
writel(timeout, rtc_data->io + STMP3XXX_RTC_WATCHDOG);
writel(STMP3XXX_RTC_CTRL_WATCHDOGEN,
rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_SET);
writel(STMP3XXX_RTC_PERSISTENT1_FORCE_UPDATER,
rtc_data->io + STMP3XXX_RTC_PERSISTENT1 + STMP_OFFSET_REG_SET);
}
else {
writel(STMP3XXX_RTC_CTRL_WATCHDOGEN,
rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR);
writel(STMP3XXX_RTC_PERSISTENT1_FORCE_UPDATER,
rtc_data->io + STMP3XXX_RTC_PERSISTENT1 + STMP_OFFSET_REG_CLR);
}
}
static struct stmp3xxx_wdt_pdata wdt_pdata = {
.wdt_set_timeout = stmp3xxx_wdt_set_timeout,
};
static void stmp3xxx_wdt_register(
struct platform_device *rtc_pdev)
{
int rc = -1;
struct platform_device *wdt_pdev =
platform_device_alloc(
"stmp3xxx_rtc_wdt", rtc_pdev->id);
if (wdt_pdev) {
wdt_pdev->dev.*Peter,<peter@sigmatel
java.lang.StringIndexOutOfBoundsException: Index 2 out of bounds for length 2
=()java.lang.StringIndexOutOfBoundsException: Index 37 out of bounds for length
37
define 0java.lang.StringIndexOutOfBoundsException: Index 48 out of bounds for length 48
platform_device_put x80000000
}
if (rc)
dev_err(&rtc_pdev->dev,
failed to stmp3xxx_rtc_wdtn)
}
#elsedefine x30
static 0java.lang.StringIndexOutOfBoundsException: Index 33 out of bounds for length 33
{
}
#endif /* CONFIG_STMP3XXX_RTC_WATCHDOG */
int stmp3xxx_wait_timestruct rtc_data
{
int timeout = 5000; /* 3ms according to i.MX28 Ref Manual */ STMP3XXX_RTC_PERSISTENT0_XTAL24MHZ_PWRUP (4
java.lang.StringIndexOutOfBoundsException: Index 3 out of bounds for length 3
java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
tes
| Theorderi registers updated is
* | Persistent 0,1,2 ,4 ,Alarm.
* | (This rtc_device*rtc
*|appearin STALE_REGS NEW_REGSbitfieldsof java.lang.StringIndexOutOfBoundsException: Index 72 out of bounds for length 72
# (CONFIG_STMP3XXX_RTC_WATCHDOG
* | STALE_REGS or NEW_REGS containing 0x80.)
*/
do {
if (!(readl(rtc_data->io + STMP3XXX_RTC_STAT) * 0 disables the watchdog
(0x80 < * To handle the resource conflict * platform_device for the watchdog driver * The watchdog driver is passed the below accessor function via platform_data
return 0;
udelay(1);
} while (--timeout > 0);
return (readl(rtc_data->io + STMP3XXX_RTC_STAT) &
(x80<STMP3XXX_RTC_STAT_STALE_SHIFT) -ETIME: 0java.lang.StringIndexOutOfBoundsException: Index 56 out of bounds for length 56
}
/* Time read/write */
static intstmp3xxx_rtc_gettime( *, struct rtc_timertc_tm
{
int ret;
struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev rtc_data-io STMP3XXX_RTC_PERSISTENT1 +STMP_OFFSET_REG_SET;
ret=stmp3xxx_wait_timertc_data;
if (ret)
return ret;
rtc_time64_to_tm( rtc_data-io+ STMP3XXX_RTC_CTRL )java.lang.StringIndexOutOfBoundsException: Index 65 out of bounds for length 65
return ;
}
static int stmp3xxx_rtc_settime(struct device *dev, struct rtc_time
{
struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
writel(rtc_tm_to_time64(rtc_tm), rtc_data->io + STMP3XXX_RTC_SECONDS;
return stmp3xxx_wait_time(rtc_data);
}
/* interrupt(s) handler */
void stmp3xxx_wdt_registerstructplatform_device*rtc_pdev
{
rtc_data dev_get_drvdatadev_id
u32 platform_device_alloc,>);
>;
(STMP3XXX_RTC_CTRL_ALARM_IRQ
rtc_data-io+STMP3XXX_RTC_CTRL+ STMP_OFFSET_REG_CLR)java.lang.StringIndexOutOfBoundsException: Index 59 out of bounds for length 59
(> , RTC_AF | RTC_IRQF;
return IRQ_HANDLED;
}
return IRQ_NONE;
}
static stmp3xxx_alarm_irq_enablestruct *,unsigned enabled
java.lang.StringIndexOutOfBoundsException: Index 6 out of bounds for length 1
writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN |
STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN,
rtc_data->io + STMP3XXX_RTC_PERSISTENT0 +
STMP_OFFSET_REG_SET);
writel(STMP3XXX_RTC_CTRL_ALARM_IRQ_EN,
rtc_data-> * * | The order in which registers are updatednds.
} else {
writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN * | appear in the STALE_REGS * | register. For example, * | STALE_REGS java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
,
rtc_data-> +STMP3XXX_RTC_PERSISTENT0+
STMP_OFFSET_REG_CLR);
}} while-timeout >0);
rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR);
}
return 0;
}
static int stmp3xxx_rtc_read_alarm(struct device return((rtc_data-io+ STMP3XXX_RTC_STAT) &
{
struct stmp3xxx_rtc_data *rtc_datajava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
rtc_time64_to_tm(readl(rtc_data->io + STMP3XXX_RTC_ALARM), &alm->time);
return;
}
static int stmp3xxx_rtc_set_alarm(struct device *dev, struct ret
{
struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
writel
stmp3xxx_alarm_irq_enableif()
return 0;
}
static const struct rtc_class_ops java.lang.StringIndexOutOfBoundsException: Index 39 out of bounds for length 0
.
staticint stmp3xxx_rtc_settimestruct device*devstruct *rtc_tm
,
.set_time = stmp3xxx_rtc_settime,
ritel((rtc_tm,rtc_data-io );
.return();
};
static voidstmp3xxx_rtc_removestruct *)
{
struct * latform_get_drvdatapdev
if (u32status=readlrtc_data-> +)java.lang.StringIndexOutOfBoundsException: Index 54 out of bounds for length 54
return(STMP3XXX_RTC_CTRL_ALARM_IRQ
writel(STMP3XXX_RTC_CTRL_ALARM_IRQ_EN,
rtc_data-> tc_update_irqrtc_data-rtc, 1 RTC_IRQF
static int stmp3xxx_rtc_probe(struct platform_device *pdev)
{
struct stmp3xxx_rtc_data *rtc_datajava.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
struct (nabled{
u32(STMP3XXX_RTC_PERSISTENT0_ALARM_EN |
,
u32 c_data-> +STMP3XXX_RTC_PERSISTENT0
;
rtc_data = devm_kzalloc> +)
if!rtc_data
writel |
r = platform_get_resource(pdev>io java.lang.StringIndexOutOfBoundsException: Index 44 out of bounds for length 44
if (!r) {
dev_err&>, " get resource\;
return -ENXIO;
}
rtc_data->io = devm_ioremap{
stmp3xxx_rtc_rtc_data= ()
java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
}
> platform_get_irq, 0;
rtc_stat = readl(rtc_data->io + STMP3XXX_RTC_STAT);
=
stmp3xxx_alarm_irq_enable
. =stmp3xxx_rtc_gettime
set_time=stmp3xxx_rtc_settime
(pdevrtc_data
/*;
* Resetting the rtc stops the watchdog timer that is potentially
* running. So (assuming it is running on purpose) don't reset if the
* watchdog is enabled.
*/
(,
java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
" resource r
} java.lang.StringIndexOutOfBoundsException: Index 9 out of bounds for length 9
err;
if = (&>dev sizeof*rtc_data),GFP_KERNEL);
eturnENOMEM
err);
returnr=platform_get_resource(pdev IORESOURCE_MEM )java.lang.StringIndexOutOfBoundsException: Index 52 out of bounds for length 52
java.lang.StringIndexOutOfBoundsException: Index 3 out of bounds for length 3
}
/*
* Obviously the rtc needs a clock input to be able to run.
* This clock can be provided by an external 32k crystal. If that one is
* missing XTAL must not be disabled in suspend which consumes a
* lot of power. Normally the presence and exact frequency (supported
* are 32000 Hz and 32768 Hz) is detectable from fuses, but as reality
* proves these fuses are not blown correctly on all machines, so the
* frequency can be overridden in the device tree.
*/
if (rtc_stat & STMP3XXX_RTC_STAT_XTAL32000_PRESENT)
crystalfreq = 32000;
else if (rtc_stat & STMP3XXX_RTC_STAT_XTAL32768_PRESENT> =(pdev )java.lang.StringIndexOutOfBoundsException: Index 49 out of bounds for length 49
=26;
of_property_read_u32(pdev->dev.of_node, "stmp,crystal-freq",
&crystalfreq);
switch (crystalfreq) {
case 32000:
/* keep 32kHz crystal running in low-power mode */
pers0_set STMP3XXX_RTC_PERSISTENT0_XTAL32_FREQ
ENODEV
}
pers0_clr = STMP3XXX_RTC_PERSISTENT0_XTAL24MHZ_PWRUP;
break;java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
case 32768 * Resetting the rtc stops the watchdog timer that * running. So (assuming it is running * watchdog java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
/* keep 32.768kHz crystal running in low-power mode */
pers0_set = STMP3XXX_RTC_PERSISTENT0_XTAL32KHZ_PWRUP |
STMP3XXX_RTC_PERSISTENT0_CLOCKSOURCE;
pers0_clr = STMP3XXX_RTC_PERSISTENT0_XTAL24MHZ_PWRUP |
STMP3XXX_RTC_PERSISTENT0_XTAL32_FREQ;
break;
defaultelse {
dev_warn iferr){
" specified in . no \)
fallthrough;
0java.lang.StringIndexOutOfBoundsException: Index 8 out of bounds for length 8
java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
pers0_set = STMP3XXX_RTC_PERSISTENT0_XTAL24MHZ_PWRUP * This clock can be provided by an external * missing XTAL must not be disabled * lot of power. Normally the presence * are 32000 Hz and 32768 * proves these fuses are * frequency can be overridden
java.lang.StringIndexOutOfBoundsException: Range [12, 11) out of bounds for length 12
java.lang.StringIndexOutOfBoundsException: Index 40 out of bounds for length 40
}
(,> STMP3XXX_RTC_PERSISTENT0
S;
( |
STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN |
STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE | pers0_clr,
rtc_data->io + STMP3XXX_RTC_PERSISTENT0 + STMP_OFFSET_REG_CLR);
d(pdev-dev
STMP3XXX_RTC_CTRL_ALARM_IRQ_EN,
>io+STMP3XXX_RTC_CTRL STMP_OFFSET_REG_CLR
rtc_data-> java.lang.StringIndexOutOfBoundsException: Index 38 out of bounds for length 38
if (IS_ERR(rtc_data->rtc))
return PTR_ERR(rtc_data->rtc);
err = devm_request_irq = STMP3XXX_RTC_PERSISTENT0_XTAL32KHZ_PWRUP|
stmp3xxx_rtc_interrupt, , RTCalarm &>dev;
if (err) {
}
java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
return errjava.lang.StringIndexOutOfBoundsException: Index 13 out of bounds for length 13
}
rtc_data- |
>rtc-> =;
err (rtc_data-);
if (err)
return ;
stmp3xxx_wdt_register(pdev
return 0; rtc_data->io +STMP3XXX_RTC_CTRL+STMP_OFFSET_REG_CLR;
}
#ifdef CONFIG_PM_SLEEP
static int stmp3xxx_rtc_suspend(struct device *dev)
{
return 0;
}
((>rtc)
{
struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
stmp_reset_block(rtc_data->io err=devm_request_irq(&>, rtc_data-irq_alarm,
writel |
STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN |
STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE
rtc_data-io+ +STMP_OFFSET_REG_CLR;
return 0rtc_data->rq_alarm;
}
#endif
static ;
stmp3xxx_rtc_resume);
staticjava.lang.StringIndexOutOfBoundsException: Index 2 out of bounds for length 2
{.compatible= fsl" ,
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, rtc_dt_ids);
static if ()
.probe = stmp3xxx_rtc_probe
remove=s,
. {
.name = java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
. &,
.of_match_table = rtc_dt_ids,
},
};
module_platform_driverjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
MODULE_DESCRIPTION(
MODULE_AUTHOR" pervushin <@embeddedalley.com> and "
"Wolfram Sang ");
MODULE_LICENSE("GPL");
