/* SPDX-License-Identifier: GPL-2.0 */ /* * Netburst Performance Events ( P4 , old Xeon ) #ifndef PERF_EVENT_P4_H#define PERF_EVENT_P4_H#include <linux/cpu.h>#include <linux/bitops.h>/* * NetBurst has performance MSRs shared between * threads if HT is turned on , ie for both logical * processors ( mem : in turn in Atom with HT support * perf - MSRs are not shared and every thread has its * own perf - MSRs set ) #define ARCH_P4_TOTAL_ESCR (46 )#define ARCH_P4_RESERVED_ESCR (2 ) /* IQ_ESCR(0,1) not always present */ #define ARCH_P4_MAX_ESCR (ARCH_P4_TOTAL_ESCR - ARCH_P4_RESERVED_ESCR)#define ARCH_P4_MAX_CCCR (18 )#define ARCH_P4_CNTRVAL_BITS (40 )#define ARCH_P4_CNTRVAL_MASK ((1 ULL << ARCH_P4_CNTRVAL_BITS) - 1 )#define ARCH_P4_UNFLAGGED_BIT ((1 ULL) << (ARCH_P4_CNTRVAL_BITS - 1 ))#define P4_ESCR_EVENT_MASK 0 x7e000000ULL#define P4_ESCR_EVENT_SHIFT 25 #define P4_ESCR_EVENTMASK_MASK 0 x01fffe00ULL#define P4_ESCR_EVENTMASK_SHIFT 9 #define P4_ESCR_TAG_MASK 0 x000001e0ULL#define P4_ESCR_TAG_SHIFT 5 #define P4_ESCR_TAG_ENABLE 0 x00000010ULL#define P4_ESCR_T0_OS 0 x00000008ULL#define P4_ESCR_T0_USR 0 x00000004ULL#define P4_ESCR_T1_OS 0 x00000002ULL#define P4_ESCR_T1_USR 0 x00000001ULL#define P4_ESCR_EVENT(v) ((v) << P4_ESCR_EVENT_SHIFT)#define P4_ESCR_EMASK(v) ((v) << P4_ESCR_EVENTMASK_SHIFT)#define P4_ESCR_TAG(v) ((v) << P4_ESCR_TAG_SHIFT)#define P4_CCCR_OVF 0 x80000000ULL#define P4_CCCR_CASCADE 0 x40000000ULL#define P4_CCCR_OVF_PMI_T0 0 x04000000ULL#define P4_CCCR_OVF_PMI_T1 0 x08000000ULL#define P4_CCCR_FORCE_OVF 0 x02000000ULL#define P4_CCCR_EDGE 0 x01000000ULL#define P4_CCCR_THRESHOLD_MASK 0 x00f00000ULL#define P4_CCCR_THRESHOLD_SHIFT 20 #define P4_CCCR_COMPLEMENT 0 x00080000ULL#define P4_CCCR_COMPARE 0 x00040000ULL#define P4_CCCR_ESCR_SELECT_MASK 0 x0000e000ULL#define P4_CCCR_ESCR_SELECT_SHIFT 13 #define P4_CCCR_ENABLE 0 x00001000ULL#define P4_CCCR_THREAD_SINGLE 0 x00010000ULL#define P4_CCCR_THREAD_BOTH 0 x00020000ULL#define P4_CCCR_THREAD_ANY 0 x00030000ULL#define P4_CCCR_RESERVED 0 x00000fffULL#define P4_CCCR_THRESHOLD(v) ((v) << P4_CCCR_THRESHOLD_SHIFT)#define P4_CCCR_ESEL(v) ((v) << P4_CCCR_ESCR_SELECT_SHIFT)#define P4_GEN_ESCR_EMASK(class , name, bit) \class ## __## name = ((1 ULL << bit) << P4_ESCR_EVENTMASK_SHIFT)#define P4_ESCR_EMASK_BIT(class , name) class ## __## name/* * config field is 64 bit width and consists of * HT < < 63 | ESCR < < 32 | CCCR * where HT is HyperThreading bit ( since ESCR * has it reserved we may use it for own purpose ) * * note that this is NOT the addresses of respective * ESCR and CCCR but rather an only packed value should * be unpacked and written to a proper addresses * * the base idea is to pack as much info as possible #define p4_config_pack_escr(v) (((u64)(v)) << 32 )#define p4_config_pack_cccr(v) (((u64)(v)) & 0 xffffffffULL)#define p4_config_unpack_escr(v) (((u64)(v)) >> 32 )#define p4_config_unpack_cccr(v) (((u64)(v)) & 0 xffffffffULL)#define p4_config_unpack_emask(v) \#define p4_config_unpack_event(v) \#define P4_CONFIG_HT_SHIFT 63 #define P4_CONFIG_HT (1 ULL << P4_CONFIG_HT_SHIFT)/* * If an event has alias it should be marked * with a special bit . ( Don ' t forget to check * P4_PEBS_CONFIG_MASK and related bits on * modification . ) #define P4_CONFIG_ALIASABLE (1 ULL << 9 )/* * The bits we allow to pass for RAW events #define P4_CONFIG_MASK_ESCR \#define P4_CONFIG_MASK_CCCR \/* some dangerous bits are reserved for kernel internals */ #define P4_CONFIG_MASK \/* * In case of event aliasing we need to preserve some * caller bits , otherwise the mapping won ' t be complete . #define P4_CONFIG_EVENT_ALIAS_MASK \#define P4_CONFIG_EVENT_ALIAS_IMMUTABLE_BITS \static inline bool p4_is_event_cascaded(u64 config)return !!(cccr & P4_CCCR_CASCADE);static inline int p4_ht_config_thread(u64 config)return !!(config & P4_CONFIG_HT);static inline u64 p4_set_ht_bit(u64 config)return config | P4_CONFIG_HT;static inline u64 p4_clear_ht_bit(u64 config)return config & ~P4_CONFIG_HT;static inline int p4_ht_active(void )#ifdef CONFIG_SMPreturn __max_threads_per_core > 1 ;#endif return 0 ;static inline int p4_ht_thread(int cpu)#ifdef CONFIG_SMPif (__max_threads_per_core == 2 )return cpu != cpumask_first(this_cpu_cpumask_var_ptr(cpu_sibling_map));#endif return 0 ;static inline int p4_should_swap_ts(u64 config, int cpu)return p4_ht_config_thread(config) ^ p4_ht_thread(cpu);static inline u32 p4_default_cccr_conf(int cpu)/* * Note that P4_CCCR_THREAD_ANY is " required " on * non - HT machines ( on HT machines we count TS events * regardless the state of second logical processor if (!p4_ht_thread(cpu))else return cccr;static inline u32 p4_default_escr_conf(int cpu, int exclude_os, int exclude_usr)0 ;if (!p4_ht_thread(cpu)) {if (!exclude_os)if (!exclude_usr)else {if (!exclude_os)if (!exclude_usr)return escr;/* * This are the events which should be used in " Event Select " * field of ESCR register , they are like unique keys which allow * the kernel to determinate which CCCR and COUNTER should be * used to track an event enum P4_EVENTS {#define P4_OPCODE(event) event## _OPCODE#define P4_OPCODE_ESEL(opcode) ((opcode & 0 x00ff) >> 0 )#define P4_OPCODE_EVNT(opcode) ((opcode & 0 xff00) >> 8 )#define P4_OPCODE_PACK(event, sel) (((event) << 8 ) | sel)/* * Comments below the event represent ESCR restriction * for this event and counter index per ESCR * * MSR_P4_IQ_ESCR0 and MSR_P4_IQ_ESCR1 are available only on early * processor builds ( family 0 FH , models 01 H - 02 H ) . These MSRs * are not available on later versions , so that we don ' t use * them completely * * Also note that CCCR1 do not have P4_CCCR_ENABLE bit properly * working so that we should not use this CCCR and respective * counter as result enum P4_EVENT_OPCODES {0 x01, 0 x01),/* * MSR_P4_TC_ESCR0 : 4 , 5 * MSR_P4_TC_ESCR1 : 6 , 7 0 x03, 0 x00),/* * MSR_P4_BPU_ESCR0 : 0 , 1 * MSR_P4_BPU_ESCR1 : 2 , 3 0 x18, 0 x03),/* * MSR_P4_ITLB_ESCR0 : 0 , 1 * MSR_P4_ITLB_ESCR1 : 2 , 3 0 x02, 0 x05),/* * MSR_P4_DAC_ESCR0 : 8 , 9 * MSR_P4_DAC_ESCR1 : 10 , 11 0 x08, 0 x02),/* * MSR_P4_SAAT_ESCR0 : 8 , 9 * MSR_P4_SAAT_ESCR1 : 10 , 11 0 x04, 0 x02),/* * MSR_P4_SAAT_ESCR0 : 8 , 9 * MSR_P4_SAAT_ESCR1 : 10 , 11 0 x05, 0 x02),/* * MSR_P4_SAAT_ESCR0 : 8 , 9 * MSR_P4_SAAT_ESCR1 : 10 , 11 0 x03, 0 x02),/* * MSR_P4_MOB_ESCR0 : 0 , 1 * MSR_P4_MOB_ESCR1 : 2 , 3 0 x01, 0 x04),/* * MSR_P4_PMH_ESCR0 : 0 , 1 * MSR_P4_PMH_ESCR1 : 2 , 3 0 x0c, 0 x07),/* * MSR_P4_BSU_ESCR0 : 0 , 1 * MSR_P4_BSU_ESCR1 : 2 , 3 0 x03, 0 x06),/* * MSR_P4_FSB_ESCR0 : 0 , 1 * MSR_P4_FSB_ESCR1 : 2 , 3 0 x1a, 0 x06),/* * MSR_P4_FSB_ESCR1 : 2 , 3 0 x17, 0 x06),/* * MSR_P4_FSB_ESCR0 : 0 , 1 * MSR_P4_FSB_ESCR1 : 2 , 3 0 x05, 0 x07),/* * MSR_P4_BSU_ESCR0 : 0 , 1 0 x06, 0 x07),/* * NOTE : no ESCR name in docs , it ' s guessed * MSR_P4_BSU_ESCR1 : 2 , 3 0 x34, 0 x01),/* * MSR_P4_FIRM_ESCR0 : 8 , 9 * MSR_P4_FIRM_ESCR1 : 10 , 11 0 x08, 0 x01),/* * MSR_P4_FIRM_ESCR0 : 8 , 9 * MSR_P4_FIRM_ESCR1 : 10 , 11 0 x0c, 0 x01),/* * MSR_P4_FIRM_ESCR0 : 8 , 9 * MSR_P4_FIRM_ESCR1 : 10 , 11 0 x0a, 0 x01),/* * MSR_P4_FIRM_ESCR0 : 8 , 9 * MSR_P4_FIRM_ESCR1 : 10 , 11 0 x0e, 0 x01),/* * MSR_P4_FIRM_ESCR0 : 8 , 9 * MSR_P4_FIRM_ESCR1 : 10 , 11 0 x02, 0 x01),/* * MSR_P4_FIRM_ESCR0 : 8 , 9 * MSR_P4_FIRM_ESCR1 : 10 , 11 0 x1a, 0 x01),/* * MSR_P4_FIRM_ESCR0 : 8 , 9 * MSR_P4_FIRM_ESCR1 : 10 , 11 0 x04, 0 x01),/* * MSR_P4_FIRM_ESCR0 : 8 , 9 * MSR_P4_FIRM_ESCR1 : 10 , 11 0 x06, 0 x01),/* * MSR_P4_TC_ESCR0 : 4 , 5 * MSR_P4_TC_ESCR1 : 6 , 7 0 x13, 0 x06),/* * MSR_P4_FSB_ESCR0 : 0 , 1 * MSR_P4_FSB_ESCR1 : 2 , 3 0 x05, 0 x00),/* * MSR_P4_MS_ESCR0 : 4 , 5 * MSR_P4_MS_ESCR1 : 6 , 7 0 x09, 0 x00),/* * MSR_P4_MS_ESCR0 : 4 , 5 * MSR_P4_MS_ESCR1 : 6 , 7 0 x05, 0 x02),/* * MSR_P4_TBPU_ESCR0 : 4 , 5 * MSR_P4_TBPU_ESCR1 : 6 , 7 0 x04, 0 x02),/* * MSR_P4_TBPU_ESCR0 : 4 , 5 * MSR_P4_TBPU_ESCR1 : 6 , 7 0 x01, 0 x01),/* * MSR_P4_ALF_ESCR0 : 12 , 13 , 16 * MSR_P4_ALF_ESCR1 : 14 , 15 , 17 0 x05, 0 x05),/* * MSR_P4_DAC_ESCR0 : 8 , 9 * MSR_P4_DAC_ESCR1 : 10 , 11 0 x16, 0 x03),/* * MSR_P4_FSB_ESCR0 : 0 , 1 * MSR_P4_FSB_ESCR1 : 2 , 3 0 x08, 0 x03),/* * MSR_P4_FSB_ESCR0 : 0 , 1 * MSR_P4_FSB_ESCR1 : 2 , 3 0 x06, 0 x03),/* * MSR_P4_FSB_ESCR0 : 0 , 1 * MSR_P4_FSB_ESCR1 : 2 , 3 0 x04, 0 x03),/* * MSR_P4_FSB_ESCR0 : 0 , 1 * MSR_P4_FSB_ESCR1 : 2 , 3 0 x08, 0 x05),/* * MSR_P4_CRU_ESCR2 : 12 , 13 , 16 * MSR_P4_CRU_ESCR3 : 14 , 15 , 17 0 x0c, 0 x05),/* * MSR_P4_CRU_ESCR2 : 12 , 13 , 16 * MSR_P4_CRU_ESCR3 : 14 , 15 , 17 0 x09, 0 x05),/* * MSR_P4_CRU_ESCR2 : 12 , 13 , 16 * MSR_P4_CRU_ESCR3 : 14 , 15 , 17 0 x02, 0 x04),/* * MSR_P4_CRU_ESCR0 : 12 , 13 , 16 * MSR_P4_CRU_ESCR1 : 14 , 15 , 17 0 x01, 0 x04),/* * MSR_P4_CRU_ESCR0 : 12 , 13 , 16 * MSR_P4_CRU_ESCR1 : 14 , 15 , 17 0 x02, 0 x02),/* * MSR_P4_RAT_ESCR0 : 12 , 13 , 16 * MSR_P4_RAT_ESCR1 : 14 , 15 , 17 0 x06, 0 x05),/* * MSR_P4_CRU_ESCR2 : 12 , 13 , 16 * MSR_P4_CRU_ESCR3 : 14 , 15 , 17 0 x03, 0 x04),/* * MSR_P4_CRU_ESCR0 : 12 , 13 , 16 * MSR_P4_CRU_ESCR1 : 14 , 15 , 17 0 x03, 0 x05),/* * MSR_P4_CRU_ESCR2 : 12 , 13 , 16 * MSR_P4_CRU_ESCR3 : 14 , 15 , 17 0 x02, 0 x05),/* * MSR_P4_CRU_ESCR2 : 12 , 13 , 16 * MSR_P4_CRU_ESCR3 : 14 , 15 , 17 0 x07, 0 x04),/* * MSR_P4_CRU_ESCR0 : 12 , 13 , 16 * MSR_P4_CRU_ESCR1 : 14 , 15 , 17 /* * a caller should use P4_ESCR_EMASK_NAME helper to * pick the EventMask needed , for example * * P4_ESCR_EMASK_BIT ( P4_EVENT_TC_DELIVER_MODE , DD ) enum P4_ESCR_EMASKS {0 ),1 ),2 ),3 ),4 ),5 ),6 ),0 ),0 ),1 ),2 ),2 ),64 K_CONF, 3 ),0 ),1 ),1 ),1 ),1 ),3 ),4 ),5 ),0 ),1 ),0 ),1 ),2 ),3 ),4 ),5 ),8 ),9 ),10 ),DEFAULT , 0 ),5 ),6 ),7 ),8 ),9 ),10 ),11 ),13 ),14 ),15 ),DEFAULT , 0 ),5 ),6 ),7 ),8 ),9 ),10 ),11 ),13 ),14 ),15 ),0 ),1 ),2 ),3 ),4 ),5 ),0 ),1 ),2 ),3 ),5 ),6 ),7 ),8 ),9 ),10 ),11 ),12 ),13 ),0 ),1 ),2 ),3 ),5 ),6 ),7 ),8 ),9 ),10 ),11 ),12 ),13 ),15 ),15 ),15 ),15 ),15 ),15 ),15 ),15 ),4 ),0 ),0 ),0 ),1 ),2 ),1 ),2 ),RETURN , 3 ),4 ),1 ),2 ),RETURN , 3 ),4 ),5 ),0 ),1 ),0 ),1 ),0 ),1 ),2 ),3 ),4 ),5 ),6 ),7 ),0 ),1 ),0 ),1 ),2 ),3 ),0 ),1 ),1 ),2 ),0 ),1 ),2 ),3 ),0 ),0 ),1 ),2 ),3 ),4 ),0 ),1 ),2 ),0 ),1 ),/* * Note we have UOP and PEBS bits reserved for now * just in case if we will need them once #define P4_PEBS_CONFIG_ENABLE (1 ULL << 7 )#define P4_PEBS_CONFIG_UOP_TAG (1 ULL << 8 )#define P4_PEBS_CONFIG_METRIC_MASK 0 x3FLL#define P4_PEBS_CONFIG_MASK 0 xFFLL/* * mem : Only counters MSR_IQ_COUNTER4 ( 16 ) and * MSR_IQ_COUNTER5 ( 17 ) are allowed for PEBS sampling #define P4_PEBS_ENABLE 0 x02000000ULL#define P4_PEBS_ENABLE_UOP_TAG 0 x01000000ULL#define p4_config_unpack_metric(v) (((u64)(v)) & P4_PEBS_CONFIG_METRIC_MASK)#define p4_config_unpack_pebs(v) (((u64)(v)) & P4_PEBS_CONFIG_MASK)#define p4_config_pebs_has(v, mask) (p4_config_unpack_pebs(v) & (mask))enum P4_PEBS_METRIC {/* * Notes on internal configuration of ESCR + CCCR tuples * * Since P4 has quite the different architecture of * performance registers in compare with " architectural " * once and we have on 64 bits to keep configuration * of performance event , the following trick is used . * * 1 ) Since both ESCR and CCCR registers have only low * 32 bits valuable , we pack them into a single 64 bit * configuration . Low 32 bits of such config correspond * to low 32 bits of CCCR register and high 32 bits * correspond to low 32 bits of ESCR register . * * 2 ) The meaning of every bit of such config field can * be found in Intel SDM but it should be noted that * we " borrow " some reserved bits for own usage and * clean them or set to a proper value when we do * a real write to hardware registers . * * 3 ) The format of bits of config is the following * and should be either 0 or set to some predefined * values : * * Low 32 bits * - - - - - - - - - - - * 0 - 6 : P4_PEBS_METRIC enum * 7 - 11 : reserved * 12 : reserved ( Enable ) * 13 - 15 : reserved ( ESCR select ) * 16 - 17 : Active Thread * 18 : Compare * 19 : Complement * 20 - 23 : Threshold * 24 : Edge * 25 : reserved ( FORCE_OVF ) * 26 : reserved ( OVF_PMI_T0 ) * 27 : reserved ( OVF_PMI_T1 ) * 28 - 29 : reserved * 30 : reserved ( Cascade ) * 31 : reserved ( OVF ) * * High 32 bits * - - - - - - - - - - - - * 0 : reserved ( T1_USR ) * 1 : reserved ( T1_OS ) * 2 : reserved ( T0_USR ) * 3 : reserved ( T0_OS ) * 4 : Tag Enable * 5 - 8 : Tag Value * 9 - 24 : Event Mask ( may use P4_ESCR_EMASK_BIT helper ) * 25 - 30 : enum P4_EVENTS * 31 : reserved ( HT thread ) #endif /* PERF_EVENT_P4_H */
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