Quelle cache.json
Sprache: unbekannt
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[
{
"BriefDescription": "Cycles L1D locked",
"Counter": "0,1",
"EventCode": "0x63",
"EventName": "CACHE_LOCK_CYCLES.L1D",
"SampleAfterValue": "2000000",
"UMask": "0x2"
},
{
"BriefDescription": "Cycles L1D and L2 locked",
"Counter": "0,1",
"EventCode": "0x63",
"EventName": "CACHE_LOCK_CYCLES.L1D_L2",
"SampleAfterValue": "2000000",
"UMask": "0x1"
},
{
"BriefDescription": "L1D cache lines replaced in M state",
"Counter": "0,1",
"EventCode": "0x51",
"EventName": "L1D.M_EVICT",
"SampleAfterValue": "2000000",
"UMask": "0x4"
},
{
"BriefDescription": "L1D cache lines allocated in the M state",
"Counter": "0,1",
"EventCode": "0x51",
"EventName": "L1D.M_REPL",
"SampleAfterValue": "2000000",
"UMask": "0x2"
},
{
"BriefDescription": "L1D snoop eviction of cache lines in M state",
"Counter": "0,1",
"EventCode": "0x51",
"EventName": "L1D.M_SNOOP_EVICT",
"SampleAfterValue": "2000000",
"UMask": "0x8"
},
{
"BriefDescription": "L1 data cache lines allocated",
"Counter": "0,1",
"EventCode": "0x51",
"EventName": "L1D.REPL",
"SampleAfterValue": "2000000",
"UMask": "0x1"
},
{
"BriefDescription": "All references to the L1 data cache",
"Counter": "0,1",
"EventCode": "0x43",
"EventName": "L1D_ALL_REF.ANY",
"SampleAfterValue": "2000000",
"UMask": "0x1"
},
{
"BriefDescription": "L1 data cacheable reads and writes",
"Counter": "0,1",
"EventCode": "0x43",
"EventName": "L1D_ALL_REF.CACHEABLE",
"SampleAfterValue": "2000000",
"UMask": "0x2"
},
{
"BriefDescription": "L1 data cache read in E state",
"Counter": "0,1",
"EventCode": "0x40",
"EventName": "L1D_CACHE_LD.E_STATE",
"SampleAfterValue": "2000000",
"UMask": "0x4"
},
{
"BriefDescription": "L1 data cache read in I state (misses)",
"Counter": "0,1",
"EventCode": "0x40",
"EventName": "L1D_CACHE_LD.I_STATE",
"SampleAfterValue": "2000000",
"UMask": "0x1"
},
{
"BriefDescription": "L1 data cache reads",
"Counter": "0,1",
"EventCode": "0x40",
"EventName": "L1D_CACHE_LD.MESI",
"SampleAfterValue": "2000000",
"UMask": "0xf"
},
{
"BriefDescription": "L1 data cache read in M state",
"Counter": "0,1",
"EventCode": "0x40",
"EventName": "L1D_CACHE_LD.M_STATE",
"SampleAfterValue": "2000000",
"UMask": "0x8"
},
{
"BriefDescription": "L1 data cache read in S state",
"Counter": "0,1",
"EventCode": "0x40",
"EventName": "L1D_CACHE_LD.S_STATE",
"SampleAfterValue": "2000000",
"UMask": "0x2"
},
{
"BriefDescription": "L1 data cache load locks in E state",
"Counter": "0,1",
"EventCode": "0x42",
"EventName": "L1D_CACHE_LOCK.E_STATE",
"SampleAfterValue": "2000000",
"UMask": "0x4"
},
{
"BriefDescription": "L1 data cache load lock hits",
"Counter": "0,1",
"EventCode": "0x42",
"EventName": "L1D_CACHE_LOCK.HIT",
"SampleAfterValue": "2000000",
"UMask": "0x1"
},
{
"BriefDescription": "L1 data cache load locks in M state",
"Counter": "0,1",
"EventCode": "0x42",
"EventName": "L1D_CACHE_LOCK.M_STATE",
"SampleAfterValue": "2000000",
"UMask": "0x8"
},
{
"BriefDescription": "L1 data cache load locks in S state",
"Counter": "0,1",
"EventCode": "0x42",
"EventName": "L1D_CACHE_LOCK.S_STATE",
"SampleAfterValue": "2000000",
"UMask": "0x2"
},
{
"BriefDescription": "L1D load lock accepted in fill buffer",
"Counter": "0,1",
"EventCode": "0x53",
"EventName": "L1D_CACHE_LOCK_FB_HIT",
"SampleAfterValue": "2000000",
"UMask": "0x1"
},
{
"BriefDescription": "L1D prefetch load lock accepted in fill buffer",
"Counter": "0,1",
"EventCode": "0x52",
"EventName": "L1D_CACHE_PREFETCH_LOCK_FB_HIT",
"SampleAfterValue": "2000000",
"UMask": "0x1"
},
{
"BriefDescription": "L1 data cache stores in E state",
"Counter": "0,1",
"EventCode": "0x41",
"EventName": "L1D_CACHE_ST.E_STATE",
"SampleAfterValue": "2000000",
"UMask": "0x4"
},
{
"BriefDescription": "L1 data cache stores in M state",
"Counter": "0,1",
"EventCode": "0x41",
"EventName": "L1D_CACHE_ST.M_STATE",
"SampleAfterValue": "2000000",
"UMask": "0x8"
},
{
"BriefDescription": "L1 data cache stores in S state",
"Counter": "0,1",
"EventCode": "0x41",
"EventName": "L1D_CACHE_ST.S_STATE",
"SampleAfterValue": "2000000",
"UMask": "0x2"
},
{
"BriefDescription": "L1D hardware prefetch misses",
"Counter": "0,1",
"EventCode": "0x4E",
"EventName": "L1D_PREFETCH.MISS",
"SampleAfterValue": "200000",
"UMask": "0x2"
},
{
"BriefDescription": "L1D hardware prefetch requests",
"Counter": "0,1",
"EventCode": "0x4E",
"EventName": "L1D_PREFETCH.REQUESTS",
"SampleAfterValue": "200000",
"UMask": "0x1"
},
{
"BriefDescription": "L1D hardware prefetch requests triggered",
"Counter": "0,1",
"EventCode": "0x4E",
"EventName": "L1D_PREFETCH.TRIGGERS",
"SampleAfterValue": "200000",
"UMask": "0x4"
},
{
"BriefDescription": "L1 writebacks to L2 in E state",
"Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "L1D_WB_L2.E_STATE",
"SampleAfterValue": "100000",
"UMask": "0x4"
},
{
"BriefDescription": "L1 writebacks to L2 in I state (misses)",
"Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "L1D_WB_L2.I_STATE",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "All L1 writebacks to L2",
"Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "L1D_WB_L2.MESI",
"SampleAfterValue": "100000",
"UMask": "0xf"
},
{
"BriefDescription": "L1 writebacks to L2 in M state",
"Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "L1D_WB_L2.M_STATE",
"SampleAfterValue": "100000",
"UMask": "0x8"
},
{
"BriefDescription": "L1 writebacks to L2 in S state",
"Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "L1D_WB_L2.S_STATE",
"SampleAfterValue": "100000",
"UMask": "0x2"
},
{
"BriefDescription": "L1I instruction fetch stall cycles",
"Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "L1I.CYCLES_STALLED",
"SampleAfterValue": "2000000",
"UMask": "0x4"
},
{
"BriefDescription": "L1I instruction fetch hits",
"Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "L1I.HITS",
"SampleAfterValue": "2000000",
"UMask": "0x1"
},
{
"BriefDescription": "L1I instruction fetch misses",
"Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "L1I.MISSES",
"SampleAfterValue": "2000000",
"UMask": "0x2"
},
{
"BriefDescription": "L1I Instruction fetches",
"Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "L1I.READS",
"SampleAfterValue": "2000000",
"UMask": "0x3"
},
{
"BriefDescription": "All L2 data requests",
"Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.ANY",
"SampleAfterValue": "200000",
"UMask": "0xff"
},
{
"BriefDescription": "L2 data demand loads in E state",
"Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.DEMAND.E_STATE",
"SampleAfterValue": "200000",
"UMask": "0x4"
},
{
"BriefDescription": "L2 data demand loads in I state (misses)",
"Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.DEMAND.I_STATE",
"SampleAfterValue": "200000",
"UMask": "0x1"
},
{
"BriefDescription": "L2 data demand requests",
"Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.DEMAND.MESI",
"SampleAfterValue": "200000",
"UMask": "0xf"
},
{
"BriefDescription": "L2 data demand loads in M state",
"Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.DEMAND.M_STATE",
"SampleAfterValue": "200000",
"UMask": "0x8"
},
{
"BriefDescription": "L2 data demand loads in S state",
"Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.DEMAND.S_STATE",
"SampleAfterValue": "200000",
"UMask": "0x2"
},
{
"BriefDescription": "L2 data prefetches in E state",
"Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.PREFETCH.E_STATE",
"SampleAfterValue": "200000",
"UMask": "0x40"
},
{
"BriefDescription": "L2 data prefetches in the I state (misses)",
"Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.PREFETCH.I_STATE",
"SampleAfterValue": "200000",
"UMask": "0x10"
},
{
"BriefDescription": "All L2 data prefetches",
"Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.PREFETCH.MESI",
"SampleAfterValue": "200000",
"UMask": "0xf0"
},
{
"BriefDescription": "L2 data prefetches in M state",
"Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.PREFETCH.M_STATE",
"SampleAfterValue": "200000",
"UMask": "0x80"
},
{
"BriefDescription": "L2 data prefetches in the S state",
"Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.PREFETCH.S_STATE",
"SampleAfterValue": "200000",
"UMask": "0x20"
},
{
"BriefDescription": "L2 lines allocated",
"Counter": "0,1,2,3",
"EventCode": "0xF1",
"EventName": "L2_LINES_IN.ANY",
"SampleAfterValue": "100000",
"UMask": "0x7"
},
{
"BriefDescription": "L2 lines allocated in the E state",
"Counter": "0,1,2,3",
"EventCode": "0xF1",
"EventName": "L2_LINES_IN.E_STATE",
"SampleAfterValue": "100000",
"UMask": "0x4"
},
{
"BriefDescription": "L2 lines allocated in the S state",
"Counter": "0,1,2,3",
"EventCode": "0xF1",
"EventName": "L2_LINES_IN.S_STATE",
"SampleAfterValue": "100000",
"UMask": "0x2"
},
{
"BriefDescription": "L2 lines evicted",
"Counter": "0,1,2,3",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.ANY",
"SampleAfterValue": "100000",
"UMask": "0xf"
},
{
"BriefDescription": "L2 lines evicted by a demand request",
"Counter": "0,1,2,3",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.DEMAND_CLEAN",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "L2 modified lines evicted by a demand request",
"Counter": "0,1,2,3",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.DEMAND_DIRTY",
"SampleAfterValue": "100000",
"UMask": "0x2"
},
{
"BriefDescription": "L2 lines evicted by a prefetch request",
"Counter": "0,1,2,3",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.PREFETCH_CLEAN",
"SampleAfterValue": "100000",
"UMask": "0x4"
},
{
"BriefDescription": "L2 modified lines evicted by a prefetch request",
"Counter": "0,1,2,3",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.PREFETCH_DIRTY",
"SampleAfterValue": "100000",
"UMask": "0x8"
},
{
"BriefDescription": "L2 instruction fetches",
"Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.IFETCHES",
"SampleAfterValue": "200000",
"UMask": "0x30"
},
{
"BriefDescription": "L2 instruction fetch hits",
"Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.IFETCH_HIT",
"SampleAfterValue": "200000",
"UMask": "0x10"
},
{
"BriefDescription": "L2 instruction fetch misses",
"Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.IFETCH_MISS",
"SampleAfterValue": "200000",
"UMask": "0x20"
},
{
"BriefDescription": "L2 load hits",
"Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.LD_HIT",
"SampleAfterValue": "200000",
"UMask": "0x1"
},
{
"BriefDescription": "L2 load misses",
"Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.LD_MISS",
"SampleAfterValue": "200000",
"UMask": "0x2"
},
{
"BriefDescription": "L2 requests",
"Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.LOADS",
"SampleAfterValue": "200000",
"UMask": "0x3"
},
{
"BriefDescription": "All L2 misses",
"Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.MISS",
"SampleAfterValue": "200000",
"UMask": "0xaa"
},
{
"BriefDescription": "All L2 prefetches",
"Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.PREFETCHES",
"SampleAfterValue": "200000",
"UMask": "0xc0"
},
{
"BriefDescription": "L2 prefetch hits",
"Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.PREFETCH_HIT",
"SampleAfterValue": "200000",
"UMask": "0x40"
},
{
"BriefDescription": "L2 prefetch misses",
"Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.PREFETCH_MISS",
"SampleAfterValue": "200000",
"UMask": "0x80"
},
{
"BriefDescription": "All L2 requests",
"Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.REFERENCES",
"SampleAfterValue": "200000",
"UMask": "0xff"
},
{
"BriefDescription": "L2 RFO requests",
"Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.RFOS",
"SampleAfterValue": "200000",
"UMask": "0xc"
},
{
"BriefDescription": "L2 RFO hits",
"Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.RFO_HIT",
"SampleAfterValue": "200000",
"UMask": "0x4"
},
{
"BriefDescription": "L2 RFO misses",
"Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.RFO_MISS",
"SampleAfterValue": "200000",
"UMask": "0x8"
},
{
"BriefDescription": "All L2 transactions",
"Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANSACTIONS.ANY",
"SampleAfterValue": "200000",
"UMask": "0x80"
},
{
"BriefDescription": "L2 fill transactions",
"Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANSACTIONS.FILL",
"SampleAfterValue": "200000",
"UMask": "0x20"
},
{
"BriefDescription": "L2 instruction fetch transactions",
"Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANSACTIONS.IFETCH",
"SampleAfterValue": "200000",
"UMask": "0x4"
},
{
"BriefDescription": "L1D writeback to L2 transactions",
"Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANSACTIONS.L1D_WB",
"SampleAfterValue": "200000",
"UMask": "0x10"
},
{
"BriefDescription": "L2 Load transactions",
"Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANSACTIONS.LOAD",
"SampleAfterValue": "200000",
"UMask": "0x1"
},
{
"BriefDescription": "L2 prefetch transactions",
"Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANSACTIONS.PREFETCH",
"SampleAfterValue": "200000",
"UMask": "0x8"
},
{
"BriefDescription": "L2 RFO transactions",
"Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANSACTIONS.RFO",
"SampleAfterValue": "200000",
"UMask": "0x2"
},
{
"BriefDescription": "L2 writeback to LLC transactions",
"Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANSACTIONS.WB",
"SampleAfterValue": "200000",
"UMask": "0x40"
},
{
"BriefDescription": "L2 demand lock RFOs in E state",
"Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.LOCK.E_STATE",
"SampleAfterValue": "100000",
"UMask": "0x40"
},
{
"BriefDescription": "All demand L2 lock RFOs that hit the cache",
"Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.LOCK.HIT",
"SampleAfterValue": "100000",
"UMask": "0xe0"
},
{
"BriefDescription": "L2 demand lock RFOs in I state (misses)",
"Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.LOCK.I_STATE",
"SampleAfterValue": "100000",
"UMask": "0x10"
},
{
"BriefDescription": "All demand L2 lock RFOs",
"Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.LOCK.MESI",
"SampleAfterValue": "100000",
"UMask": "0xf0"
},
{
"BriefDescription": "L2 demand lock RFOs in M state",
"Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.LOCK.M_STATE",
"SampleAfterValue": "100000",
"UMask": "0x80"
},
{
"BriefDescription": "L2 demand lock RFOs in S state",
"Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.LOCK.S_STATE",
"SampleAfterValue": "100000",
"UMask": "0x20"
},
{
"BriefDescription": "All L2 demand store RFOs that hit the cache",
"Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.RFO.HIT",
"SampleAfterValue": "100000",
"UMask": "0xe"
},
{
"BriefDescription": "L2 demand store RFOs in I state (misses)",
"Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.RFO.I_STATE",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "All L2 demand store RFOs",
"Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.RFO.MESI",
"SampleAfterValue": "100000",
"UMask": "0xf"
},
{
"BriefDescription": "L2 demand store RFOs in M state",
"Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.RFO.M_STATE",
"SampleAfterValue": "100000",
"UMask": "0x8"
},
{
"BriefDescription": "L2 demand store RFOs in S state",
"Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.RFO.S_STATE",
"SampleAfterValue": "100000",
"UMask": "0x2"
},
{
"BriefDescription": "Longest latency cache miss",
"Counter": "0,1,2,3",
"EventCode": "0x2E",
"EventName": "LONGEST_LAT_CACHE.MISS",
"SampleAfterValue": "100000",
"UMask": "0x41"
},
{
"BriefDescription": "Longest latency cache reference",
"Counter": "0,1,2,3",
"EventCode": "0x2E",
"EventName": "LONGEST_LAT_CACHE.REFERENCE",
"SampleAfterValue": "200000",
"UMask": "0x4f"
},
{
"BriefDescription": "Memory instructions retired above 0 clocks (Precise Event)",
"Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_0",
"MSRIndex": "0x3F6",
"PEBS": "2",
"SampleAfterValue": "2000000",
"UMask": "0x10"
},
{
"BriefDescription": "Memory instructions retired above 1024 clocks (Precise Event)",
"Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_1024",
"MSRIndex": "0x3F6",
"MSRValue": "0x400",
"PEBS": "2",
"SampleAfterValue": "100",
"UMask": "0x10"
},
{
"BriefDescription": "Memory instructions retired above 128 clocks (Precise Event)",
"Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_128",
"MSRIndex": "0x3F6",
"MSRValue": "0x80",
"PEBS": "2",
"SampleAfterValue": "1000",
"UMask": "0x10"
},
{
"BriefDescription": "Memory instructions retired above 16 clocks (Precise Event)",
"Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16",
"MSRIndex": "0x3F6",
"MSRValue": "0x10",
"PEBS": "2",
"SampleAfterValue": "10000",
"UMask": "0x10"
},
{
"BriefDescription": "Memory instructions retired above 16384 clocks (Precise Event)",
"Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16384",
"MSRIndex": "0x3F6",
"MSRValue": "0x4000",
"PEBS": "2",
"SampleAfterValue": "5",
"UMask": "0x10"
},
{
"BriefDescription": "Memory instructions retired above 2048 clocks (Precise Event)",
"Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_2048",
"MSRIndex": "0x3F6",
"MSRValue": "0x800",
"PEBS": "2",
"SampleAfterValue": "50",
"UMask": "0x10"
},
{
"BriefDescription": "Memory instructions retired above 256 clocks (Precise Event)",
"Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_256",
"MSRIndex": "0x3F6",
"MSRValue": "0x100",
"PEBS": "2",
"SampleAfterValue": "500",
"UMask": "0x10"
},
{
"BriefDescription": "Memory instructions retired above 32 clocks (Precise Event)",
"Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32",
"MSRIndex": "0x3F6",
"MSRValue": "0x20",
"PEBS": "2",
"SampleAfterValue": "5000",
"UMask": "0x10"
},
{
"BriefDescription": "Memory instructions retired above 32768 clocks (Precise Event)",
"Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32768",
"MSRIndex": "0x3F6",
"MSRValue": "0x8000",
"PEBS": "2",
"SampleAfterValue": "3",
"UMask": "0x10"
},
{
"BriefDescription": "Memory instructions retired above 4 clocks (Precise Event)",
"Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4",
"MSRIndex": "0x3F6",
"MSRValue": "0x4",
"PEBS": "2",
"SampleAfterValue": "50000",
"UMask": "0x10"
},
{
"BriefDescription": "Memory instructions retired above 4096 clocks (Precise Event)",
"Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4096",
"MSRIndex": "0x3F6",
"MSRValue": "0x1000",
"PEBS": "2",
"SampleAfterValue": "20",
"UMask": "0x10"
},
{
"BriefDescription": "Memory instructions retired above 512 clocks (Precise Event)",
"Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_512",
"MSRIndex": "0x3F6",
"MSRValue": "0x200",
"PEBS": "2",
"SampleAfterValue": "200",
"UMask": "0x10"
},
{
"BriefDescription": "Memory instructions retired above 64 clocks (Precise Event)",
"Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_64",
"MSRIndex": "0x3F6",
"MSRValue": "0x40",
"PEBS": "2",
"SampleAfterValue": "2000",
"UMask": "0x10"
},
{
"BriefDescription": "Memory instructions retired above 8 clocks (Precise Event)",
"Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8",
"MSRIndex": "0x3F6",
"MSRValue": "0x8",
"PEBS": "2",
"SampleAfterValue": "20000",
"UMask": "0x10"
},
{
"BriefDescription": "Memory instructions retired above 8192 clocks (Precise Event)",
"Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8192",
"MSRIndex": "0x3F6",
"MSRValue": "0x2000",
"PEBS": "2",
"SampleAfterValue": "10",
"UMask": "0x10"
},
{
"BriefDescription": "Instructions retired which contains a load (Precise Event)",
"Counter": "0,1,2,3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LOADS",
"PEBS": "1",
"SampleAfterValue": "2000000",
"UMask": "0x1"
},
{
"BriefDescription": "Instructions retired which contains a store (Precise Event)",
"Counter": "0,1,2,3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.STORES",
"PEBS": "1",
"SampleAfterValue": "2000000",
"UMask": "0x2"
},
{
"BriefDescription": "Retired loads that miss L1D and hit an previously allocated LFB (Precise Event)",
"Counter": "0,1,2,3",
"EventCode": "0xCB",
"EventName": "MEM_LOAD_RETIRED.HIT_LFB",
"PEBS": "1",
"SampleAfterValue": "200000",
"UMask": "0x40"
},
{
"BriefDescription": "Retired loads that hit the L1 data cache (Precise Event)",
"Counter": "0,1,2,3",
"EventCode": "0xCB",
"EventName": "MEM_LOAD_RETIRED.L1D_HIT",
"PEBS": "1",
"SampleAfterValue": "2000000",
"UMask": "0x1"
},
{
"BriefDescription": "Retired loads that hit the L2 cache (Precise Event)",
"Counter": "0,1,2,3",
"EventCode": "0xCB",
"EventName": "MEM_LOAD_RETIRED.L2_HIT",
"PEBS": "1",
"SampleAfterValue": "200000",
"UMask": "0x2"
},
{
"BriefDescription": "Retired loads that miss the LLC cache (Precise Event)",
"Counter": "0,1,2,3",
"EventCode": "0xCB",
"EventName": "MEM_LOAD_RETIRED.LLC_MISS",
"PEBS": "1",
"SampleAfterValue": "10000",
"UMask": "0x10"
},
{
"BriefDescription": "Retired loads that hit valid versions in the LLC cache (Precise Event)",
"Counter": "0,1,2,3",
"EventCode": "0xCB",
"EventName": "MEM_LOAD_RETIRED.LLC_UNSHARED_HIT",
"PEBS": "1",
"SampleAfterValue": "40000",
"UMask": "0x4"
},
{
"BriefDescription": "Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)",
"Counter": "0,1,2,3",
"EventCode": "0xCB",
"EventName": "MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM",
"PEBS": "1",
"SampleAfterValue": "40000",
"UMask": "0x8"
},
{
"BriefDescription": "Offcore L1 data cache writebacks",
"Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.L1D_WRITEBACK",
"SampleAfterValue": "100000",
"UMask": "0x40"
},
{
"BriefDescription": "Offcore requests blocked due to Super Queue full",
"Counter": "0,1,2,3",
"EventCode": "0xB2",
"EventName": "OFFCORE_REQUESTS_SQ_FULL",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads satisfied by any cache or DRAM",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x7F11",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "All offcore data reads",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LOCATION",
"MSRIndex": "0x1A6",
"MSRValue": "0xFF11",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads satisfied by the IO, CSR, MMIO unit",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
"MSRValue": "0x8011",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads satisfied by the LLC and not found in a sibling core",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
"MSRValue": "0x111",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads satisfied by the LLC and HIT in a sibling core",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x211",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads satisfied by the LLC and HITM in a sibling core",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x411",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads satisfied by the LLC",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x711",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads satisfied by the LLC or local DRAM",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4711",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads satisfied by a remote cache",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x1811",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads satisfied by a remote cache or remote DRAM",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x3811",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads that HIT in a remote cache",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x1011",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads that HITM in a remote cache",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x811",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code reads satisfied by any cache or DRAM",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x7F44",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "All offcore code reads",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LOCATION",
"MSRIndex": "0x1A6",
"MSRValue": "0xFF44",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code reads satisfied by the IO, CSR, MMIO unit",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
"MSRValue": "0x8044",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code reads satisfied by the LLC and not found in a sibling core",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
"MSRValue": "0x144",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code reads satisfied by the LLC and HIT in a sibling core",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x244",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code reads satisfied by the LLC and HITM in a sibling core",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x444",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code reads satisfied by the LLC",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x744",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code reads satisfied by the LLC or local DRAM",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4744",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code reads satisfied by a remote cache",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x1844",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code reads satisfied by a remote cache or remote DRAM",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x3844",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code reads that HIT in a remote cache",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x1044",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code reads that HITM in a remote cache",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x844",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore requests satisfied by any cache or DRAM",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x7FFF",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "All offcore requests",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LOCATION",
"MSRIndex": "0x1A6",
"MSRValue": "0xFFFF",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore requests satisfied by the IO, CSR, MMIO unit",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
"MSRValue": "0x80FF",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore requests satisfied by the LLC and not found in a sibling core",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
"MSRValue": "0x1FF",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore requests satisfied by the LLC and HIT in a sibling core",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x2FF",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore requests satisfied by the LLC and HITM in a sibling core",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4FF",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore requests satisfied by the LLC",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x7FF",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore requests satisfied by the LLC or local DRAM",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x47FF",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore requests satisfied by a remote cache",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x18FF",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore requests satisfied by a remote cache or remote DRAM",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x38FF",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore requests that HIT in a remote cache",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x10FF",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore requests that HITM in a remote cache",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x8FF",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore RFO requests satisfied by any cache or DRAM",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x7F22",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "All offcore RFO requests",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LOCATION",
"MSRIndex": "0x1A6",
"MSRValue": "0xFF22",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore RFO requests satisfied by the IO, CSR, MMIO unit",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
"MSRValue": "0x8022",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore RFO requests satisfied by the LLC and not found in a sibling core",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
"MSRValue": "0x122",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore RFO requests satisfied by the LLC and HIT in a sibling core",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x222",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore RFO requests satisfied by the LLC and HITM in a sibling core",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x422",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore RFO requests satisfied by the LLC",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x722",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore RFO requests satisfied by the LLC or local DRAM",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4722",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore RFO requests satisfied by a remote cache",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x1822",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore RFO requests satisfied by a remote cache or remote DRAM",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x3822",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore RFO requests that HIT in a remote cache",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x1022",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore RFO requests that HITM in a remote cache",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x822",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore writebacks to any cache or DRAM.",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x7F08",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "All offcore writebacks",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.ANY_LOCATION",
"MSRIndex": "0x1A6",
"MSRValue": "0xFF08",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore writebacks to the IO, CSR, MMIO unit.",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
"MSRValue": "0x8008",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore writebacks to the LLC and not found in a sibling core",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
"MSRValue": "0x108",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore writebacks to the LLC and HITM in a sibling core",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x408",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore writebacks to the LLC",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x708",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore writebacks to the LLC or local DRAM",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4708",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore writebacks to a remote cache",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x1808",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore writebacks to a remote cache or remote DRAM",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x3808",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore writebacks that HIT in a remote cache",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x1008",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore writebacks that HITM in a remote cache",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x808",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code or data read requests satisfied by any cache or DRAM.",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x7F77",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "All offcore code or data read requests",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LOCATION",
"MSRIndex": "0x1A6",
"MSRValue": "0xFF77",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code or data read requests satisfied by the IO, CSR, MMIO unit.",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
"MSRValue": "0x8077",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code or data read requests satisfied by the LLC and not found in a sibling core",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
"MSRValue": "0x177",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code or data read requests satisfied by the LLC and HIT in a sibling core",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x277",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code or data read requests satisfied by the LLC and HITM in a sibling core",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x477",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code or data read requests satisfied by the LLC",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x777",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code or data read requests satisfied by the LLC or local DRAM",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4777",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code or data read requests satisfied by a remote cache",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x1877",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code or data read requests satisfied by a remote cache or remote DRAM",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x3877",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code or data read requests that HIT in a remote cache",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x1077",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore code or data read requests that HITM in a remote cache",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x877",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore request = all data, response = any cache_dram",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x7F33",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore request = all data, response = any location",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LOCATION",
"MSRIndex": "0x1A6",
"MSRValue": "0xFF33",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the IO, CSR, MMIO unit",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
"MSRValue": "0x8033",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC and not found in a sibling core",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
"MSRValue": "0x133",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC and HIT in a sibling core",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x233",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC and HITM in a sibling core",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x433",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore request = all data, response = local cache",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x733",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore request = all data, response = local cache or dram",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4733",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore request = all data, response = remote cache",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x1833",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore request = all data, response = remote cache or dram",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x3833",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads, RFOs, and prefetches that HIT in a remote cache",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x1033",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore data reads, RFOs, and prefetches that HITM in a remote cache",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x833",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data requests satisfied by any cache or DRAM",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x7F03",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "All offcore demand data requests",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LOCATION",
"MSRIndex": "0x1A6",
"MSRValue": "0xFF03",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data requests satisfied by the IO, CSR, MMIO unit.",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
"MSRValue": "0x8003",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data requests satisfied by the LLC and not found in a sibling core",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
"MSRValue": "0x103",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data requests satisfied by the LLC and HIT in a sibling core",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x203",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data requests satisfied by the LLC and HITM in a sibling core",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x403",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data requests satisfied by the LLC",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x703",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data requests satisfied by the LLC or local DRAM",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4703",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data requests satisfied by a remote cache",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x1803",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data requests satisfied by a remote cache or remote DRAM",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x3803",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data requests that HIT in a remote cache",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x1003",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data requests that HITM in a remote cache",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x803",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data reads satisfied by any cache or DRAM.",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x7F01",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "All offcore demand data reads",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LOCATION",
"MSRIndex": "0x1A6",
"MSRValue": "0xFF01",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data reads satisfied by the IO, CSR, MMIO unit",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
"MSRValue": "0x8001",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data reads satisfied by the LLC and not found in a sibling core",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
"MSRValue": "0x101",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data reads satisfied by the LLC and HIT in a sibling core",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x201",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data reads satisfied by the LLC and HITM in a sibling core",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
"MSRValue": "0x401",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data reads satisfied by the LLC",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x701",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data reads satisfied by the LLC or local DRAM",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x4701",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data reads satisfied by a remote cache",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE",
"MSRIndex": "0x1A6",
"MSRValue": "0x1801",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data reads satisfied by a remote cache or remote DRAM",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
"MSRValue": "0x3801",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Offcore demand data reads that HIT in a remote cache",
"Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
"MSRValue": "0x1001",
"SampleAfterValue": "100000",
--> --------------------
--> maximum size reached
--> --------------------
[ Dauer der Verarbeitung: 0.12 Sekunden
(vorverarbeitet)
]
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2026-04-07
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