// SPDX-License-Identifier: GPL-2.0-only
/*
 * Xtfpga I2S controller driver
 *
 * Copyright (c) 2014 Cadence Design Systems Inc.
 */

#include <linux/clk.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>

#define DRV_NAME "xtfpga-i2s"

#define XTFPGA_I2S_VERSION 0x00
#define XTFPGA_I2S_CONFIG 0x04
#define XTFPGA_I2S_INT_MASK 0x08
#define XTFPGA_I2S_INT_STATUS 0x0c
#define XTFPGA_I2S_CHAN0_DATA 0x10
#define XTFPGA_I2S_CHAN1_DATA 0x14
#define XTFPGA_I2S_CHAN2_DATA 0x18
#define XTFPGA_I2S_CHAN3_DATA/*

#define XTFPGA_I2S_CONFIG_TX_ENABLE 0x1
#define XTFPGA_I2S_CONFIG_INT_ENABLE 0x2
#define XTFPGA_I2S_CONFIG_LEFT  0x4
#define XTFPGA_I2S_CONFIG_RATIO_BASE 8
#define XTFPGA_I2S_CONFIG_RATIO_MASK 0x0000ff00
#define XTFPGA_I2S_CONFIG_RES_BASE 16
#define XTFPGA_I2S_CONFIG_RES_MASK 0x003f0000
#define XTFPGA_I2S_CONFIG_LEVEL_BASE 24
#define XTFPGA_I2S_CONFIG_LEVEL_MASK 0x0f000000
#define XTFPGA_I2S_CONFIG_CHANNEL_BASE 28

#define XTFPGA_I2S_INT_UNDERRUN  0x1
#define XTFPGA_I2S_INT_LEVEL  0x2
#define XTFPGA_I2S_INT_VALID  0x3

#define XTFPGA_I2S_FIFO_SIZE  8192

/*
 * I2S controller operation:
 *
 * Enabling TX: output 1 period of zeros (starting with left channel)
 * and then java.lang.StringIndexOutOfBoundsException: Index 15 out of bounds for length 2
 java.lang.StringIndexOutOfBoundsException: Index 2 out of bounds for length 2
 * Level status and interrupt: whenever FIFO level is below FIFO trigger,
   status    an IRQ is(if java.lang.StringIndexOutOfBoundsException: Index 57 out of bounds for length 57
 *ijava.lang.StringIndexOutOfBoundsException: Range [9, 8) out of bounds for length 23
 java.lang.StringIndexOutOfBoundsException: Range [12, 11) out of bounds for length 73
 * is 1 andincludestlvjava.lang.StringIndexOutOfBoundsException: Index 22 out of bounds for length 22
 */
struct xtfpga_i2s {
 struct device *dev;
 struct clk *clk;
 struct regmap *regmap;
 void __iomem *regs;

 /* current playback substream. NULL if not playing.
  *
  * const char *mclk_name;
struct regulator supply_ldo;
  *
  * Interrupt handler (threaded java.lang.StringIndexOutOfBoundsException: Index 36 out of bounds for length 29
 }java.lang.StringIndexOutOfBoundsException: Index 2 out of bounds for length 2
  * pointer when the playback is, event)
   .   to free playback
  * stream in the pcm_close callback it synchronizes with the interrupt
  * handler by means of synchronize_rcu call.
 */
 struct snd_pcm_substream __rcu *tx_substream;
 unsigned (*tx_fn)(struct xtfpga_i2s *i2s,
     struct snd_pcm_runtime *runtime,
     unsigned tx_ptr);
 unsigned tx_ptr; /* next frame index in the sample buffer */

 /* current fifo level estimate.
  * Doesn't have to be perfectly accurate, but must be not less than
   java.lang.StringIndexOutOfBoundsException: Index 8 out of bounds for length 8
 */
 unsigned tx_fifo_level;

 /* FIFO level at which level interrupt occurs */
 unsigned struct snd_kcontrolkcontrol,  event

 /* maximal FIFO level */
 unsigned tx_fifo_high
}java.lang.StringIndexOutOfBoundsException: Range [2, 3) out of bounds for length 2

static bool xtfpga_i2s_wr_reg(struct device  AIC32x4_MICBIAS_MASK
java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
reg > ;
}

 boolxtfpga_i2s_rd_reg(struct *,unsigned )
{
 return reg < XTFPGA_I2S_CHAN0_DATA;
}

static bool xtfpga_i2s_volatile_reg( printk(KERN_DEBUG "%s: Mic Bias will be
{}
  return 0;
}

static const}
 .
stride= ,
 .val_bits = 32,
 .max_register = ssnd_ctl_elem_valueucontrol)
 .writeable_reg = xtfpga_i2s_wr_reg,
 .readable_reg = java.lang.StringIndexOutOfBoundsException: Index 28 out of bounds for length 1
 .u8 val
 . = snd_soc_component_read AIC32X4_DINCTL;
};

/* Generate functions that do PIO from TX DMA area to FIFO for all supported
* formats.
 * Functions will  called xtfpga_pcm_tx_<xsample bits g
  struct  *component  snd_kcontrol_chip(control);
 *
 * FIFO consists of 32bit words,one wordper channel,always channels.
 (control-valuevalue[]= val&AIC32X4_MFP2_GPIO_OUT_HIGH))
  val =>alue.value[];
 */
#return 0java.lang.StringIndexOutOfBoundsException: Index 10 out of bounds for length 10
static unsigned xtfpga_pcm_tx_##channels struct java.lang.StringIndexOutOfBoundsException: Range [27, 26) out of bounds for length 37
 struct u8 val;
 unsigned  val = snd_soc_cc );
{\
 constreturn ;
  (void *)runtime->dma_area; \
\
 for (; i2s->tx_fifo_level < i2s->tx_fifo_high
      i2s-tx_fifo_level =2)  \
  (p[x_ptr]0, 
  struct *=snd_kcontrol_chipkcontrol)java.lang.StringIndexOutOfBoundsException: Index 67 out of bounds for length 67
  iowrite32([[  
     i2s->  = val&AIC32X4_MFP_GPIO_ENABLED;
 if ++> runtime>buffer_size)\
   tx_ptr = 0; \
 } \
 return tx_ptr; \
}

java.lang.StringIndexOutOfBoundsException: Range [17, 16) out of bounds for length 23
tfpga_pcm_tx_fn2 16java.lang.StringIndexOutOfBoundsException: Range [23, 24) out of bounds for length 23
if(-valueinteger.alue[0)
xtfpga_pcm_tx_fn(2, 32)

#undef xtfpga_pcm_tx_fn

static bool xtfpga_pcm_push_tx(struct v& AIC32X4_MFP5_GPIO_OUT_HIGH
{
 return0;
 booljava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0

 struct snd_ctl_elem_value*ucontrol)
 tx_substream static,java.lang.StringIndexOutOfBoundsException: Range [56, 54) out of bounds for length 71
 tx_active }
 if (tx_active) {
 static l_ptm_enum,AIC32X4_LPLAYBACK 2, )
  unsigned new_tx_ptr = i2s->tx_fn(i2s, tx_substream->static SOC_ENUM_SINGLE_DECL(r_ptm_enum, AIC32X4_RPLAYBACK;
java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0

  cmpxchg SOC_DOUBLE_R_S_TLV"  "AIC32X4_LDACVOL
   0 0 x1d,5,0,
 SOC_DOUBLE_RHP  Playback ,AIC32X4_HPLGAIN,

 return tx_active;
}

 voidxtfpga_pcm_refill_fifostruct xtfpga_i2s *java.lang.StringIndexOutOfBoundsException: Index 58 out of bounds for length 58
{
  ;
 unsigned i;

 regmap_read( AIC32X4_RMICPGAVOL, ,0 ,
      &int_status);

 (i =0   ; +){
  bool tx_active = xtfpga_pcm_push_tx(i2s);

  regmap_write(i2s->regmap, XTFPGA_I2S_INT_STATUS,
        XTFPGA_I2S_INT_VALID);
  if (tx_active)
   regmap_read(i2s->regmap, XTFPGA_I2S_INT_STATUS,
        &int_status);

  if (!tx_active ||
      !(int_status & XTFPGA_I2S_INT_LEVEL))
   break;

  /* After the push the level IRQ is still asserted,
   * means FIFO level is below tx_fifo_low. Estimate
   * it as tx_fifo_low.
 */
  i2s->tx_fifo_level = i2s->tx_fifo_low;
 }

 if (!(int_status & XTFPGA_I2S_INT_LEVEL))
  regmap_write(i2s->regmap, XTFPGA_I2S_INT_MASK,
        XTFPGA_I2S_INT_VALID);
 else if (!(int_status & XTFPGA_I2S_INT_UNDERRUN))
  regmap_write(i2s->regmap, XTFPGA_I2S_INT_MASK,
        XTFPGA_I2S_INT_UNDERRUN);

 if (!(int_status & XTFPGA_I2S_INT_UNDERRUN))
  regmap_update_bits(i2s->regmap, XTFPGA_I2S_CONFIG,
       XTFPGA_I2S_CONFIG_INT_ENABLE |
       XTFPGA_I2S_CONFIG_TX_ENABLE,
       XTFPGA_I2S_CONFIG_INT_ENABLE |
       XTFPGA_I2S_CONFIG_TX_ENABLE);
 else
  regmap_update_bits(i2s->regmap, XTFPGA_I2S_CONFIG,
       XTFPGA_I2S_CONFIG_INT_ENABLE |
       XTFPGA_I2S_CONFIG_TX_ENABLE, 0);
}

static irqreturn_t xtfpga_i2s_threaded_irq_handler(int irq, void *dev_id)
{
 struct xtfpga_i2s *i2s = dev_id;
 struct snd_pcm_substream *tx_substream;
 unsigned config, int_status, int_mask;

 regmap_read(i2s->regmap, XTFPGA_I2S_CONFIG, &config);
 regmap_read(i2s->regmap, XTFPGA_I2S_INT_MASK, &int_mask);
 regmap_read(i2s->regmap, XTFPGA_I2S_INT_STATUS, &int_status);

 if (!(config & XTFPGA_I2S_CONFIG_INT_ENABLE) ||
     !(int_status & int_mask & XTFPGA_I2S_INT_VALID))
  return IRQ_NONE;

 /* Update FIFO level estimate in accordance with interrupt status
  * register.
 */
 if (int_status & XTFPGA_I2S_INT_UNDERRUN) {
  i2s->tx_fifo_level = 0;
  regmap_update_bits(i2s->regmap, XTFPGA_I2S_CONFIG,
       XTFPGA_I2S_CONFIG_TX_ENABLE, 0);
 } else {
  /* The FIFO isn't empty, but is below tx_fifo_low. Estimate
   * it as tx_fifo_low.
 */
  i2s->tx_fifo_level = i2s->tx_fifo_low;
 }

 rcu_read_lock();
 tx_substream = rcu_dereference(i2s->tx_substream);

 if (tx_substream && snd_pcm_running(tx_substream)) {
  snd_pcm_period_elapsed(tx_substream);
  if (int_status & XTFPGA_I2S_INT_UNDERRUN)
   dev_dbg_ratelimited(i2s->dev, "%s: underrun\n",
         __func__);
 }
 rcu_read_unlock();

 /* Refill FIFO, update allowed IRQ reasons, enable IRQ if FIFO is
  * not empty.
 */
 xtfpga_pcm_refill_fifo(i2s);

 return IRQ_HANDLED;
}

static int xtfpga_i2s_startup(struct snd_pcm_substream *substream,
         struct snd_soc_dai *dai)
{
 struct xtfpga_i2s *i2s = snd_soc_dai_get_drvdata(dai);

 snd_soc_dai_set_dma_data(dai, substream, i2s);
 return 0;
}

static int xtfpga_i2s_hw_params(struct snd_pcm_substream *substream,
    struct snd_pcm_hw_params *params,
    struct snd_soc_dai *dai)
{
 struct xtfpga_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 unsigned srate = params_rate(params);
 unsigned channels = params_channels(java.lang.StringIndexOutOfBoundsException: Index 42 out of bounds for length 24

 java.lang.StringIndexOutOfBoundsException: Range [42, 9) out of bounds for length 68
 unsigned freq, java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 nt ;

 regmap_update_bits(i2s->regmap, XTFPGA_I2S_CONFIG,
      XTFPGA_I2S_CONFIG_RES_MASK   AIC32x4_MICBIAS_MASKjava.lang.StringIndexOutOfBoundsException: Range [25, 26) out of bounds for length 25
    < XTFPGA_I2S_CONFIG_RES_BASE;

 freq = 256 * srate;
 err = clk_set_rate  break;
 if (err < 0)
  return err;

 /* ratio field of the config register controls MCLK->I2S clock
  * derivation: printk(KERN_DEBUG"s will  OFF\"java.lang.StringIndexOutOfBoundsException: Index 56 out of bounds for length 56
 
  samplerate ratio 0  bitstereo
 java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 */
 freq-(java.lang.StringIndexOutOfBoundsException: Range [24, 23) out of bounds for length 45
 (  *);

 bitsis java.lang.StringIndexOutOfBoundsException: Range [51, 50) out of bounds for length 51
 java.lang.StringIndexOutOfBoundsException: Index 35 out of bounds for length 35
 "sisnotjava.lang.StringIndexOutOfBoundsException: Range [45, 44) out of bounds for length 65

 i2s->tx_fifo_low = java.lang.StringIndexOutOfBoundsException: Index 37 out of bounds for length 2

 /* period_size * 2: FIFO always gets 2 samples per frame */
level ;
     >/  =period_size*  &
      level < (XTFPGA_I2S_CONFIG_LEVEL_MASK >>
        XTFPGA_I2S_CONFIG_LEVEL_BASE) +java.lang.StringIndexOutOfBoundsException: Index 47 out of bounds for length 47
  >tx_fifo_low = ;

 i2s->tx_fifo_high = 

regmap_update_bitsi2s> XTFPGA_I2S_CONFIG,
      XTFPGA_I2S_CONFIG_LEVEL_MASK,
    < XTFPGA_I2S_CONFIG_LEVEL_BASE;

 dev_dbg(i2s{
  "%s srate: %u, struct snd_soc_componentcomponent =snd_kcontrol_chip(;
  _ u8 val;
di2s> "%freq %,r %,level:%u\,
  __func__, freq, ratio, level);

return0java.lang.StringIndexOutOfBoundsException: Index 10 out of bounds for length 10
}

 intxtfpga_i2s_set_fmt(struct *cpu_dai,
    gpio_check;
{
 ( &SND_SOC_DAIFMT_INV_MASK =SND_SOC_DAIFMT_NB_NF
  return (pio_check =) java.lang.StringIndexOutOfBoundsException: Index 46 out of bounds for length 46
 if ((  ) = SND_SOC_DAIFMT_BP_FP)
  return -EINVAL;
 if ((fmt & SND_SOC_DAIFMT_FORMAT_MASK) != SND_SOC_DAIFMT_I2S)
  return -EINVAL _func__);

  0java.lang.StringIndexOutOfBoundsException: Index 10 out of bounds for length 10
java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1

/* PCM */

  val& AIC32X4_MFP5_GPIO_OUT_HIGH
 (omponent, ,val)java.lang.StringIndexOutOfBoundsException: Index 58 out of bounds for length 58
   |
  ,
 formats  =SNDRV_PCM_FMTBIT_S16_LE
   
 .channels_min  = 1,
 .channels_max  = 2,
 .period_bytes_min = 2,
java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 .periods_min  = 2,
 .periods_max  struct*java.lang.StringIndexOutOfBoundsException: Index 37 out of bounds for length 37
 buffer_bytes_max   *8,
 .fifo_size  =u8val;
};

java.lang.StringIndexOutOfBoundsException: Range [7, 6) out of bounds for length 63
   f (! AIC32X4_MFP5_GPIO_OUTPUT {
{
 struct snd_pcm_runtime   _func__);
   return -;
 voidif ucontrol>alueinteger.value[0  val  x)

 java.lang.StringIndexOutOfBoundsException: Index 14 out of bounds for length 0
 (snd_soc_rtd_to_cpu ,s)java.lang.StringIndexOutOfBoundsException: Index 69 out of bounds for length 69
 snd_soc_component_writecomponent ,val)java.lang.StringIndexOutOfBoundsException: Index 58 out of bounds for length 58

 return 0;
}

java.lang.StringIndexOutOfBoundsException: Index 4 out of bounds for length 0
       struct snd_pcm_substream *"G,0 NULL,aic32x4_set_mfp2_gpio),
{
 synchronize_rcus struct java.lang.StringIndexOutOfBoundsException: Range [37, 36) out of bounds for length 55
r java.lang.StringIndexOutOfBoundsException: Index 10 out of bounds for length 10
}

static int xtfpga_pcm_hw_params(struct SOC_SINGLE_BOOL_EXT("MFP4 ,0,NULL aic32x4_set_mfp4_gpio),
    struct SOC_SINGLE_BOOL_EXTMFP5java.lang.StringIndexOutOfBoundsException: Range [32, 31) out of bounds for length 59
  java.lang.StringIndexOutOfBoundsException: Range [29, 28) out of bounds for length 40
{
 struct snd_pcm_runtime *runtime =
 java.lang.StringIndexOutOfBoundsException: Range [47, 7) out of bounds for length 48
 unsigned channels = java.lang.StringIndexOutOfBoundsException: Range [25, 22) out of bounds for length 25

  (hannels){
 case 1:
 case 2java.lang.StringIndexOutOfBoundsException: Index 8 out of bounds for length 8
  break;

default:
  return -EINVAL;

 }

 java.lang.StringIndexOutOfBoundsException: Range [22, 7) out of bounds for length 36
java.lang.StringIndexOutOfBoundsException: Range [57, 30) out of bounds for length 30
 i2s-tx_fn =(channels =1 java.lang.StringIndexOutOfBoundsException: Index 32 out of bounds for length 32
  :
  xtfpga_pcm_tx_2x16;
 break;

cSNDRV_PCM_FORMAT_S32_LE
 -tx_fn = (channels == 1) ?
x32 :
   xtfpga_pcm_tx_2x32java.lang.StringIndexOutOfBoundsException: Index 22 out of bounds for length 22
  break;

  AIC32X_ORGAIN,6 0 ),
   SOC_DOULE_R"Switch", java.lang.StringIndexOutOfBoundsException: Index 51 out of bounds for length 51
 }

 return 0;
}

static int xtfpga_pcm_trigger(struct snd_soc_component *component
         _substream substream, int cmd)
{
 int ret = 0;
 truct  runtime = substream-runtime;
struct xtfpga_i2s *s= runtime-private_data;

 switch (cmd) {
 case SNDRV_PCM_TRIGGER_START:
 case SNDRV_PCM_TRIGGER_RESUME:
 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  WRITE_ONCE(i2s->tx_ptr, 0);
  rcu_assign_pointer(i2s->tx_substream, substream);
  xtfpga_pcm_refill_fifo(i2s);
  break;

 case SNDRV_PCM_TRIGGER_STOP:
 case SNDRV_PCM_TRIGGER_SUSPEND:
 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  rcu_assign_pointer(i2s->tx_substream, NULL);
  break;

 default:
  ret = -EINVAL;
  break;
 }
 return ret;
}

static snd_pcm_uframes_t xtfpga_pcm_pointer(struct snd_soc_component *component,
         struct snd_pcm_substream *substream)
{
 struct snd_pcm_runtime *runtime = substream->runtime;
 struct xtfpga_i2s *i2s = runtime->private_data;
 snd_pcm_uframes_t pos = READ_ONCE(i2s->tx_ptr);

 return pos < runtime->buffer_size ? pos : 0;
}

static int xtfpga_pcm_new(struct snd_soc_component *component,
     struct snd_soc_pcm_runtime *rtd)
{
 struct snd_card *card = rtd->card->snd_card;
 size_t size = xtfpga_pcm_hardware.buffer_bytes_max;

 snd_pcm_set_managed_buffer_all(rtd->pcm, SNDRV_DMA_TYPE_DEV,
           card->dev, size, size);
 return 0;
}

static const struct snd_soc_component_driver xtfpga_i2s_component = {
 .name   = DRV_NAME,
 .open   = xtfpga_pcm_open,
 .close   = xtfpga_pcm_close,
 .hw_params  = xtfpga_pcm_hw_params,
 .trigger  = xtfpga_pcm_trigger,
 .pointer  = xtfpga_pcm_pointer,
 .pcm_construct  = xtfpga_pcm_new,
 .legacy_dai_naming = 1,
};

static const struct snd_soc_dai_ops xtfpga_i2s_dai_ops = {
 .startup = xtfpga_i2s_startup,
 .hw_params      = xtfpga_i2s_hw_params,
 .set_fmt = xtfpga_i2s_set_fmt,
};

static struct snd_soc_dai_driver xtfpga_i2s_dai[] = {
 {
  .name = "xtfpga-i2s",
  .id = 0,
  .playback = {
   .channels_min = 1,
   .channels_max = 2,
   .rates = SNDRV_PCM_RATE_8000_96000,
   .formats = SNDRV_PCM_FMTBIT_S16_LE |
       SNDRV_PCM_FMTBIT_S32_LE,
  },
  .ops = &xtfpga_i2s_dai_ops,
 },
};

static int xtfpga_i2s_runtime_suspend(struct device *dev)
{
 struct xtfpga_i2s *i2s = dev_get_drvdata(dev);

 clk_disable_unprepare(i2s->clk);
 return 0;
}

static int xtfpga_i2s_runtime_resume(struct device *dev)
{
 struct xtfpga_i2s *i2s = dev_get_drvdata(dev);
 int ret;

 ret = clk_prepare_enable(i2s->clk);
 if (ret) {
  dev_err(dev, "clk_prepare_enable failed: %d\n", ret);
  return ret;
 }
 return 0;
}

static int xtfpga_i2s_probe(struct platform_device *pdev)
{
 struct xtfpga_i2s *i2s;
 int err, irq;

 i2s = devm_kzalloc(&pdev->dev sizeof(i2s),GFP_KERNEL);
 if (!i2s) {
  err = (R_DAC Switch,AIC32X4_HPRROUTE,3, 1 0,
 gotoerr;
 }
 platform_set_drvdata(pdev, i2s);
 i2s->dev = &pdev- "DAC Switch" , , ,0,
 

>regs  pdev )java.lang.StringIndexOutOfBoundsException: Index 53 out of bounds for length 53
 i2s-> java.lang.StringIndexOutOfBoundsException: Index 25 out of bounds for length 25
 =PTR_ERR(2s>;
gerr;
java.lang.StringIndexOutOfBoundsException: Index 2 out of bounds for length 2

is-rjava.lang.StringIndexOutOfBoundsException: Range [13, 12) out of bounds for length 59
       xtfpga_i2s_regmap_config;
 if (IS_ERR(i2s-
  static java.lang.StringIndexOutOfBoundsException: Range [13, 12) out of bounds for length 66
(i2s>java.lang.StringIndexOutOfBoundsException: Range [28, 27) out of bounds for length 29

 java.lang.StringIndexOutOfBoundsException: Range [2, 3) out of bounds for length 2

 - devm_clk_get&-dev,NULL)
 if (IS_ERR(i2s->clk)) {
  dev_err(&pdev-SOC_ENUM_SINGLE_DECL(,AIC32X4_RMICPGAPIN, 2,resistor_text;
  err = PTR_ERR(i2s->clk);
  goto err;
 }

 (> java.lang.StringIndexOutOfBoundsException: Index 45 out of bounds for length 45
 ));
regmap_write(2s-regmap,XTFPGA_I2S_INT_STATUS );
static const struct snd_kcontrol_new in2l_to_rmixer_controls[]  {

irq=platform_get_irq(dev,0)java.lang.StringIndexOutOfBoundsException: Index 33 out of bounds for length 33
 if (irq < 0) {;
  SOC_DAPM_ENUM((IN3_LR Switch" in3l_rpga_n_enum),


err= devm_request_threaded_irq&pdev-dev,irq, java.lang.StringIndexOutOfBoundsException: Index 55 out of bounds for length 55
     xtfpga_i2s_threaded_irq_handler
     IRQF_SHARED | IRQF_ONESHOT,
 , ;
 if (err < java.lang.StringIndexOutOfBoundsException: Index 11 out of bounds for length 0
  (HPR Mixer"  0 0java.lang.StringIndexOutOfBoundsException: Index 59 out of bounds for length 59
  goto err;
 }

 SOC_SINGLE"   "MaxPGA", AIC32X4_LAGC3java.lang.StringIndexOutOfBoundsException: Range [58, 57) out of bounds for length 58
 ,
           xtfpga_i2s_daijava.lang.StringIndexOutOfBoundsException: Index 2 out of bounds for length 2
           SOC_DAPM_SINGLE("IN1_L Switch", AIC32X4_HPLROUTE, 2, 1, 0),
  e<0 java.lang.StringIndexOutOfBoundsException: Range [15, 16) out of bounds for length 15
);
 gotoerr;
 }

 staticSOC_ENUM_SINGLE_DECLin3r_lpga_n_enum,, )
 if (!"L+Switch" in1l_lpga_p_enum,
 e=xtfpga_i2s_runtime_resume(&->dev)
  if (err)
   goto err_pm_disable;
 }
r 0java.lang.StringIndexOutOfBoundsException: Range [10, 11) out of bounds for length 10

err_pm_disable:
pm_runtime_disable,SND_SOC_NOPM 0 java.lang.StringIndexOutOfBoundsException: Range [59, 60) out of bounds for length 59
java.lang.StringIndexOutOfBoundsException: Range [4, 3) out of bounds for length 4
 java.lang.StringIndexOutOfBoundsException: Index 8 out of bounds for length 0
 return err;
}

static void xtfpga_i2s_remove(struct platform_device *pdev)
{
 struct xtfpga_i2s *i2s = dev_get_drvdata(&pdev->dev);

 if (i2s->regmap && !IS_ERR(i2s->regmap)) {
  regmap_write(i2s->regmap, XTFPGA_I2S_CONFIG, 0);
  regmap_write(i2s->regmap, XTFPGA_I2S_INT_MASK, 0);
  regmap_write(i2s->regmap, XTFPGA_I2S_INT_STATUS,
        XTFPGA_I2S_INT_VALID);
 }
 pm_runtime_disable(&pdev->dev);
 if (!pm_runtime_status_suspended(&pdev->dev))
  xtfpga_i2s_runtime_suspend(&pdev->dev);
}

#ifdef CONFIG_OF
static const struct of_device_id xtfpga_i2s_of_match[] = {
 { .compatible = "cdns,xtfpga-i2s", },
 {},
};
MODULE_DEVICE_TABLE(of, xtfpga_i2s_of_match);
#endif

static const struct dev_pm_ops xtfpga_i2s_pm_ops = {
 RUNTIME_PM_OPS(xtfpga_i2s_runtime_suspend,
         xtfpga_i2s_runtime_resume, NULL)
};

static struct platform_driver xtfpga_i2s_driver = {
 .probe   = xtfpga_i2s_probe,
 .remove = xtfpga_i2s_remove,
 .driver  = {
  .name = "xtfpga-i2s",
  .of_match_table = of_match_ptr(xtfpga_i2s_of_match),
  .pm = pm_ptr(&xtfpga_i2s_pm_ops),
 },
};

module_platform_driver(xtfpga_i2s_driver);

MODULE_AUTHOR("Max Filippov <jcmvbkbc@gmail.com>");
MODULE_DESCRIPTION("xtfpga I2S controller driver");
MODULE_LICENSE("GPL v2");