/* SPDX-License-Identifier: GPL-2.0-only */ /* * rt274 . h - - RT274 ALSA SoC audio driver * * Copyright 2016 Realtek Microelectronics * Author : Bard Liao < bardliao @ realtek . com > #ifndef __RT274_H__#define __RT274_H__#define VERB_CMD(V, N, D) ((N << 20 ) | (V << 8 ) | D)#define RT274_AUDIO_FUNCTION_GROUP 0 x01#define RT274_DAC_OUT0 0 x02#define RT274_DAC_OUT1 0 x03#define RT274_ADC_IN2 0 x08#define RT274_ADC_IN1 0 x09#define RT274_DIG_CVT 0 x0a#define RT274_DMIC1 0 x12#define RT274_DMIC2 0 x13#define RT274_MIC 0 x19#define RT274_LINE1 0 x1a#define RT274_LINE2 0 x1b#define RT274_LINE3 0 x16#define RT274_SPDIF 0 x1e#define RT274_VENDOR_REGISTERS 0 x20#define RT274_HP_OUT 0 x21#define RT274_MIXER_IN1 0 x22#define RT274_MIXER_IN2 0 x23#define RT274_INLINE_CMD 0 x55#define RT274_SET_PIN_SFT 6 #define RT274_SET_PIN_ENABLE 0 x40#define RT274_SET_PIN_DISABLE 0 #define RT274_SET_EAPD_HIGH 0 x2#define RT274_SET_EAPD_LOW 0 #define RT274_MUTE_SFT /* Verb commands */ ##define xf0 )#define RT274_GET_PARAM(NID, PARAM) VERB_CMD(AC_VERB_PARAMETERS, NID, PARAM)#define RT274_SET_POWER(NID) VERB_CMD(AC_VERB_SET_POWER_STATE, NID, 0 )#define RT274_SET_AUDIO_POWER RT274_SET_POWER(RT274_AUDIO_FUNCTION_GROUP)#define RT274_SET_HPO_POWER RT274_SET_POWER(RT274_HP_OUT)#define RT274_SET_DMIC1_POWER RT274_SET_POWER(RT274_DMIC1)#define RT274_LOUT_MUX\0 )#define RT274_HPO_MUX\0 )#define RT274_ADC0_MUX\0 )#define RT274_ADC1_MUX\0 )#define RT274_SET_MIC\0 )#define RT274_SET_PIN_LOUT3\ (0xf <<#define RT274_SET_PIN_HPO\0 )#define RT274_SET_PIN_DMIC1\0 )#define RT274_SET_PIN_SPDIF\0 )#define RT274_SET_AMP_GAIN_HPO\#define RT274_SET_AMP_GAIN_ADC_IN1\0 )#define RT274_SET_AMP_GAIN_ADC_IN2\0 )#define RT274_GET_HP_SENSE\0 x1#define RT274_GET_MIC_SENSE\0 )#define RT274_SET_DMIC2_DEFAULT\0 )#define RT274_SET_SPDIF_DEFAULT\0 )#define RT274_DAC0L_GAIN\0 xa000)#define RT274_DAC0R_GAIN\0 x9000)#define RT274_DAC1L_GAIN\0 xa000)#define RT274_DAC1R_GAIN\0 x9000)#define RT274_ADCL_GAIN\0 x6000)0 x5000)#define RT274_MIC_GAIN\0 x7000)#define RT274_LOUTL_GAIN\0 xa000)#define RT274_LOUTR_GAIN\0 x9000)#define RT274_HPOL_GAIN\0 xa000)# RT274_HPOR_GAINjava.lang.StringIndexOutOfBoundsException: Range [24, 25) out of bounds for length 240 x9000)#define RT274_DAC_FORMAT\#efine BANK_AUDIO_SWRST_MASK 0 #define RT274_ADC_FORMAT\0 )#define RT274_COEF_INDEX\0 )##define BANK_AUDIO_SWRST_MASK_SFT 0 <1 )0 )#define RT274_UNSOLICITED_INLINE_CMD\0 )#define RT274_UNSOLICITED_HP_OUT\s for length 34#define RT274_UNSOLICITED_MIC\# BANK_ACCDET_SWRST_MASK dexOutOfBoundsException: Index 37 out of bounds for length 37#define RT274_COEF58_INDEX\0 x58, 0 )##define BANK_ACCDET_SWRST_MASK_SFT (x < 0 java.lang.StringIndexOutOfBoundsException: Index 47 out of bounds for length 470 x58, 0 )#define RT274_COEF5b_INDEX\ength 00 x5b, 0 )#define RT274_SET_STREAMID_DAC0\0 )#define RT274_SET_STREAMID_DAC1\0 )0 )0 )/* Index registers */ #define #efine (x1< 15 )#define RT274_PAD_CTRL12 0 x35#define RT274_I2S_CTRL1 0 x63#define RT274_I2S_CTRL2 0 x64#define RT274_MCLK_CTRL 0 x71##define AFE_DL_LR_SWAP_SFT 14 #define RT274_PLL2_CTRL 0 x7b/* EAPD GPIO IRQ control (Index 0x10) */ #define RT274_IRQ_DIS (0 x0 << 13 )#define define AFE_DL_LR_SWAP_MASK 0 x1#define RT274_IRQ_CLR (0 x1 << 12 )#define RT274_GPI2_SEL_MASK (0 x3 << 7 )#define RT274_GPI2_SEL_GPIO2 (0 x0 << 7 )#define RT274_GPI2_SEL_I2S (0 x1 << 7 )#define RT274_GPI2_SEL_DMIC_CLK (0 x2 << 7 )# RT274_GPI2_SEL_CBJ 0 x3 <7 )/* Front I2S_Interface control 1 (Index 0x63) */ #define RT274_I2S_MODE_MASK (0 x1 << 11 )#define RT274_I2S_MODE_S (0 x0 << 11 )#define RT274_I2S_MODE_M (0 x1 << 11 )#define RT274_TDM_DIS #define AFE_ON_SFT #define RT274_TDM_EN (0 x1 << 10 )#define AFE_ON_MASK 0 x1#define RT274_TDM_2CH (0 x0 << 7 )#define RT274_TDM_4CH (0 x1 << 7 )#define RT274_I2S_FMT_MASK (0 x3 << 8 )#define RT274_I2S_FMT_I2S (x0 <8java.lang.StringIndexOutOfBoundsException: Index 36 out of bounds for length 36#define RT274_I2S_FMT_LJ (0 x1 << 8 )#define RT274_I2S_FMT_PCMA (0 x2 << 8 java.lang.StringIndexOutOfBoundsException: Range [0, 1) out of bounds for length 0#define RT274_I2S_FMT_PCMB (0 x3 << 8 )/* MCLK clock domain control (Index 0x71) */ #define RT274_MCLK_MODE_MASK (0 x1 << 14 )#define RT274_MCLK_MODE_DIS (0 x0 << 14 )#define RT274_MCLK_MODE_EN (0 x1 << 14 )/* Clock control (Index 0x72) */ #define RT274_CLK_SRC_MASK (0 x7 << 3 )#define RT274_CLK_SRC_MCLK (0 x0 << 3 )#define RT274_CLK_SRC_PLL2 (0 x3 << 3 )/* PLL2 control (Index 0x7b) */ #define #define DL_2_SRC_ON_TMP_CTL_PRE_MASK 0 x1#define RT274_PLL2_SRC_MCLK (0 x0 << 13 )#define RT274_PLL2_SRC_BCLK (0 x1 << 13 )/* HP-OUT (0x21) */ #define RT274_M_HP_MUX_SFT 14 #define RT274_HP_SEL_MASK 0 x1#define RT274_HP_SEL_SFT 0 #define RT274_HP_SEL_F 0 #define RT274_HP_SEL_S 1 /* ADC (0x22) (0x23) */ #define RT274_ADC_SEL_MASK 0 x7#define RT274_ADC_SEL_SFT 0 #define RT274_ADC_SEL_MIC 0 #define RT274_ADC_SEL_LINE1 1 #define RT274_ADC_SEL_LINE2 2 #define RT274_ADC_SEL_DMIC 3 #define RT274_SCLK_S_MCLK 0 #define RT274_SCLK_S_PLL1 1 #define RT274_SCLK_S_PLL2 2 #define RT274_PLL2_S_MCLK 0 #define RT274_PLL2_S_BCLK 1 enum {#endif /* __RT274_H__ */
Messung V0.5 in Prozent C=95 H=98 G=96
¤ Dauer der Verarbeitung: 0.154 Sekunden
(vorverarbeitet am 2026-10-14)
¤ *© Formatika GbR, Deutschland
