// SPDX-License-Identifier: GPL-2.0 // // mt6359.c -- mt6359 ALSA SoC audio codec driver // // Copyright (c) 2020 MediaTek Inc. // Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com> #include <linux/delay.h>#include <linux/kthread.h>#include <linux/mfd/mt6397/core.h>#include <linux/module.h>#include <linux/of.h>#include <linux/platform_device.h>#include <linux/regulator/consumer.h>#include <linux/sched.h>#include <sound/soc.h>#include <sound/tlv.h>#include "mt6359.h" static void mt6359_set_gpio_smt(struct mt6359_priv *priv)/* set gpio SMT mode */ static void mt6359_set_gpio_driving(struct mt6359_priv *priv)/* 8:4mA(default), a:8mA, c:12mA, e:16mA */ static void mt6359_set_playback_gpio(struct mt6359_priv *priv)/* set gpio mosi mode, clk / data mosi */ /* sync mosi */ static void mt6359_reset_playback_gpio(struct mt6359_priv *priv)/* set pad_aud_*_mosi to GPIO mode and dir input * reason: * pad_aud_dat_mosi*, because the pin is used as boot strap * don't clean clk/sync, for mtkaif protocol 2 static void mt6359_set_capture_gpio(struct mt6359_priv *priv)/* set gpio miso mode */ static void mt6359_reset_capture_gpio(struct mt6359_priv *priv)/* set pad_aud_*_miso to GPIO mode and dir input * reason: * pad_aud_clk_miso, because when playback only the miso_clk * will also have 26m, so will have power leak * pad_aud_dat_miso*, because the pin is used as boot strap /* use only when doing mtkaif calibraiton at the boot time */ static void mt6359_set_dcxo(struct mt6359_priv *priv, bool enable)/* use only when doing mtkaif calibraiton at the boot time */ static void mt6359_set_clksq(struct mt6359_priv *priv, bool enable)/* Enable/disable CLKSQ 26MHz */ /* use only when doing mtkaif calibraiton at the boot time */ static void mt6359_set_aud_global_bias(struct mt6359_priv *priv, bool enable)/* use only when doing mtkaif calibraiton at the boot time */ static void mt6359_set_topck(struct mt6359_priv *priv, bool enable)static void mt6359_set_decoder_clk(struct mt6359_priv *priv, bool enable)static void mt6359_mtkaif_tx_enable(struct mt6359_priv *priv)switch (priv->mtkaif_protocol) {case MT6359_MTKAIF_PROTOCOL_2_CLK_P2:/* MTKAIF TX format setting */ /* enable aud_pad TX fifos */ break ;case MT6359_MTKAIF_PROTOCOL_2:/* MTKAIF TX format setting */ /* enable aud_pad TX fifos */ break ;case MT6359_MTKAIF_PROTOCOL_1:default :/* MTKAIF TX format setting */ /* enable aud_pad TX fifos */ break ;static void mt6359_mtkaif_tx_disable(struct mt6359_priv *priv)/* disable aud_pad TX fifos */ void mt6359_set_mtkaif_protocol(struct snd_soc_component *cmpnt,int mtkaif_protocol)struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);void mt6359_mtkaif_calibration_enable(struct snd_soc_component *cmpnt)struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);true );true );true );true );/* set dat_miso_loopback on */ void mt6359_mtkaif_calibration_disable(struct snd_soc_component *cmpnt)struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);/* set dat_miso_loopback off */ false );false );false );false );void mt6359_set_mtkaif_calibration_phase(struct snd_soc_component *cmpnt,int phase_1, int phase_2, int phase_3)struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);static void zcd_disable(struct mt6359_priv *priv)static void hp_main_output_ramp(struct mt6359_priv *priv, bool up)int i, stage;int target = 7;/* Enable/Reduce HPL/R main output stage step by step */ for (i = 0; i <= target; i++) {static void hp_aux_feedback_loop_gain_ramp(struct mt6359_priv *priv, bool up)int i, stage;int target = 0xf;/* Enable/Reduce HP aux feedback loop gain step by step */ for (i = 0; i <= target; i++) {static void hp_in_pair_current(struct mt6359_priv *priv, bool increase)int i, stage;int target = 0x3;/* Set input diff pair bias select (Hi-Fi mode) */ if (priv->hp_hifi_mode) {/* Reduce HP aux feedback loop gain step by step */ for (i = 0; i <= target; i++) {static void hp_pull_down(struct mt6359_priv *priv, bool enable)int i;if (enable) {for (i = 0x0; i <= 0x7; i++) {else {for (i = 0x7; i >= 0x0; i--) {static bool is_valid_hp_pga_idx(int reg_idx)return (reg_idx >= DL_GAIN_8DB && reg_idx <= DL_GAIN_N_22DB) ||static void headset_volume_ramp(struct mt6359_priv *priv,int from, int to)int offset = 0, count = 1, reg_idx;if (!is_valid_hp_pga_idx(from) || !is_valid_hp_pga_idx(to)) {"%s(), volume index is not valid, from %d, to %d\n" ,return ;"%s(), from %d, to %d\n" , __func__, from, to);if (to > from)else while (offset > 0) {if (to > from)else if (is_valid_hp_pga_idx(reg_idx)) {static int mt6359_put_volsw(struct snd_kcontrol *kcontrol,struct snd_ctl_elem_value *ucontrol)struct snd_soc_component *component =struct mt6359_priv *priv = snd_soc_component_get_drvdata(component);struct soc_mixer_control *mc =struct soc_mixer_control *)kcontrol->private_value;unsigned int reg = 0;int index = ucontrol->value.integer.value[0];int orig_gain[2], new_gain[2];int ret;switch (mc->reg) {case MT6359_ZCD_CON2:break ;case MT6359_ZCD_CON1:break ;case MT6359_ZCD_CON3:break ;case MT6359_AUDENC_ANA_CON0:break ;case MT6359_AUDENC_ANA_CON1:break ;case MT6359_AUDENC_ANA_CON2:break ;default :return -EINVAL;if (ret < 0)return ret;switch (mc->reg) {case MT6359_ZCD_CON2:break ;case MT6359_ZCD_CON1:break ;case MT6359_ZCD_CON3:break ;case MT6359_AUDENC_ANA_CON0:break ;case MT6359_AUDENC_ANA_CON1:break ;case MT6359_AUDENC_ANA_CON2:break ;if (orig_gain[0] != new_gain[0]) {else if (snd_soc_volsw_is_stereo(mc)) {if (orig_gain[1] != new_gain[1])"%s(), name %s, reg(0x%x) = 0x%x, set index = %x\n" ,return ret;static int mt6359_get_playback_volsw(struct snd_kcontrol *kcontrol,struct snd_ctl_elem_value *ucontrol)struct snd_soc_component *component =struct mt6359_priv *priv = snd_soc_component_get_drvdata(component);struct soc_mixer_control *mc =struct soc_mixer_control *)kcontrol->private_value;switch (mc->reg) {case MT6359_ZCD_CON2:break ;case MT6359_ZCD_CON1:break ;case MT6359_ZCD_CON3:break ;default :return -EINVAL;return 0;/* MUX */ /* LOL MUX */ static const char * const lo_in_mux_map[] = {"Open" , "Playback_L_DAC" , "Playback" , "Test Mode" static SOC_ENUM_SINGLE_DECL(lo_in_mux_map_enum, SND_SOC_NOPM, 0, lo_in_mux_map);static const struct snd_kcontrol_new lo_in_mux_control ="LO Select" , lo_in_mux_map_enum);/*HP MUX */ static const char * const hp_in_mux_map[] = {"Open" ,"LoudSPK Playback" ,"Audio Playback" ,"Test Mode" ,"HP Impedance" ,static SOC_ENUM_SINGLE_DECL(hp_in_mux_map_enum,static const struct snd_kcontrol_new hp_in_mux_control ="HP Select" , hp_in_mux_map_enum);/* RCV MUX */ static const char * const rcv_in_mux_map[] = {"Open" , "Mute" , "Voice Playback" , "Test Mode" static SOC_ENUM_SINGLE_DECL(rcv_in_mux_map_enum,static const struct snd_kcontrol_new rcv_in_mux_control ="RCV Select" , rcv_in_mux_map_enum);/* DAC In MUX */ static const char * const dac_in_mux_map[] = {"Normal Path" , "Sgen" static int dac_in_mux_map_value[] = {static SOC_VALUE_ENUM_SINGLE_DECL(dac_in_mux_map_enum,static const struct snd_kcontrol_new dac_in_mux_control ="DAC Select" , dac_in_mux_map_enum);/* AIF Out MUX */ static SOC_VALUE_ENUM_SINGLE_DECL(aif_out_mux_map_enum,static const struct snd_kcontrol_new aif_out_mux_control ="AIF Out Select" , aif_out_mux_map_enum);static SOC_VALUE_ENUM_SINGLE_DECL(aif2_out_mux_map_enum,static const struct snd_kcontrol_new aif2_out_mux_control ="AIF Out Select" , aif2_out_mux_map_enum);static const char * const ul_src_mux_map[] = {"AMIC" ,"DMIC" ,static int ul_src_mux_map_value[] = {static SOC_VALUE_ENUM_SINGLE_DECL(ul_src_mux_map_enum,static const struct snd_kcontrol_new ul_src_mux_control ="UL_SRC_MUX Select" , ul_src_mux_map_enum);static SOC_VALUE_ENUM_SINGLE_DECL(ul2_src_mux_map_enum,static const struct snd_kcontrol_new ul2_src_mux_control ="UL_SRC_MUX Select" , ul2_src_mux_map_enum);static const char * const miso_mux_map[] = {"UL1_CH1" ,"UL1_CH2" ,"UL2_CH1" ,"UL2_CH2" ,static int miso_mux_map_value[] = {static SOC_VALUE_ENUM_SINGLE_DECL(miso0_mux_map_enum,static const struct snd_kcontrol_new miso0_mux_control ="MISO_MUX Select" , miso0_mux_map_enum);static SOC_VALUE_ENUM_SINGLE_DECL(miso1_mux_map_enum,static const struct snd_kcontrol_new miso1_mux_control ="MISO_MUX Select" , miso1_mux_map_enum);static SOC_VALUE_ENUM_SINGLE_DECL(miso2_mux_map_enum,static const struct snd_kcontrol_new miso2_mux_control ="MISO_MUX Select" , miso2_mux_map_enum);static const char * const dmic_mux_map[] = {"DMIC_DATA0" ,"DMIC_DATA1_L" ,"DMIC_DATA1_L_1" ,"DMIC_DATA1_R" ,static int dmic_mux_map_value[] = {static SOC_VALUE_ENUM_SINGLE_DECL(dmic0_mux_map_enum,static const struct snd_kcontrol_new dmic0_mux_control ="DMIC_MUX Select" , dmic0_mux_map_enum);/* ul1 ch2 use RG_DMIC_ADC3_SOURCE_SEL */ static SOC_VALUE_ENUM_SINGLE_DECL(dmic1_mux_map_enum,static const struct snd_kcontrol_new dmic1_mux_control ="DMIC_MUX Select" , dmic1_mux_map_enum);/* ul2 ch1 use RG_DMIC_ADC2_SOURCE_SEL */ static SOC_VALUE_ENUM_SINGLE_DECL(dmic2_mux_map_enum,static const struct snd_kcontrol_new dmic2_mux_control ="DMIC_MUX Select" , dmic2_mux_map_enum);/* ADC L MUX */ static const char * const adc_left_mux_map[] = {"Idle" , "AIN0" , "Left Preamplifier" , "Idle_1" static int adc_mux_map_value[] = {static SOC_VALUE_ENUM_SINGLE_DECL(adc_left_mux_map_enum,static const struct snd_kcontrol_new adc_left_mux_control ="ADC L Select" , adc_left_mux_map_enum);/* ADC R MUX */ static const char * const adc_right_mux_map[] = {"Idle" , "AIN0" , "Right Preamplifier" , "Idle_1" static SOC_VALUE_ENUM_SINGLE_DECL(adc_right_mux_map_enum,static const struct snd_kcontrol_new adc_right_mux_control ="ADC R Select" , adc_right_mux_map_enum);/* ADC 3 MUX */ static const char * const adc_3_mux_map[] = {"Idle" , "AIN0" , "Preamplifier" , "Idle_1" static SOC_VALUE_ENUM_SINGLE_DECL(adc_3_mux_map_enum,static const struct snd_kcontrol_new adc_3_mux_control ="ADC 3 Select" , adc_3_mux_map_enum);static const char * const pga_l_mux_map[] = {"None" , "AIN0" , "AIN1" static int pga_l_mux_map_value[] = {static SOC_VALUE_ENUM_SINGLE_DECL(pga_left_mux_map_enum,static const struct snd_kcontrol_new pga_left_mux_control ="PGA L Select" , pga_left_mux_map_enum);static const char * const pga_r_mux_map[] = {"None" , "AIN2" , "AIN3" , "AIN0" static int pga_r_mux_map_value[] = {static SOC_VALUE_ENUM_SINGLE_DECL(pga_right_mux_map_enum,static const struct snd_kcontrol_new pga_right_mux_control ="PGA R Select" , pga_right_mux_map_enum);static const char * const pga_3_mux_map[] = {"None" , "AIN3" , "AIN2" static int pga_3_mux_map_value[] = {static SOC_VALUE_ENUM_SINGLE_DECL(pga_3_mux_map_enum,static const struct snd_kcontrol_new pga_3_mux_control ="PGA 3 Select" , pga_3_mux_map_enum);static int mt_sgen_event(struct snd_soc_dapm_widget *w,struct snd_kcontrol *kcontrol,int event)struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);"%s(), event = 0x%x\n" , __func__, event);switch (event) {case SND_SOC_DAPM_PRE_PMU:/* sdm audio fifo clock power on */ /* scrambler clock on enable */ /* sdm power on */ /* sdm fifo enable */ break ;case SND_SOC_DAPM_POST_PMD:/* DL scrambler disabling sequence */ break ;default :break ;return 0;static void mtk_hp_enable(struct mt6359_priv *priv)if (priv->hp_hifi_mode) {/* Set HP DR bias current optimization, 010: 6uA */ /* Set HP & ZCD bias current optimization */ /* 01: ZCD: 4uA, HP/HS/LO: 5uA */ else {/* Set HP DR bias current optimization, 001: 5uA */ /* Set HP & ZCD bias current optimization */ /* 00: ZCD: 3uA, HP/HS/LO: 4uA */ /* HP damp circuit enable */ /* Enable HPRN/HPLN output 4K to VCM */ /* HP Feedback Cap select 2'b00: 15pF */ /* for >= 96KHz sampling rate: 2'b01: 10.5pF */ if (priv->dl_rate[MT6359_AIF_1] >= 96000)else /* Set HPP/N STB enhance circuits */ /* Enable HP aux output stage */ /* Enable HP aux feedback loop */ /* Enable HP aux CMFB loop */ /* Enable HP driver bias circuits */ /* Enable HP driver core circuits */ /* Short HP main output to HP aux output stage */ /* Increase HP input pair current to HPM step by step */ true );/* Enable HP main CMFB loop */ /* Disable HP aux CMFB loop */ /* Enable HP main output stage */ /* Enable HPR/L main output stage step by step */ true );/* Reduce HP aux feedback loop gain */ true );/* Disable HP aux feedback loop */ /* apply volume setting */ /* Disable HP aux output stage */ /* Unshort HP main output to HP aux output stage */ /* Enable AUD_CLK */ true );/* Enable Audio DAC */ if (priv->hp_hifi_mode) {/* Enable low-noise mode of DAC */ else {/* Disable low-noise mode of DAC */ /* Switch HPL MUX to audio DAC */ /* Switch HPR MUX to audio DAC */ /* Disable Pull-down HPL/R to AVSS28_AUD */ false );static void mtk_hp_disable(struct mt6359_priv *priv)/* Pull-down HPL/R to AVSS28_AUD */ true );/* HPR/HPL mux to open */ /* Disable low-noise mode of DAC */ /* Disable Audio DAC */ /* Disable AUD_CLK */ false );/* Short HP main output to HP aux output stage */ /* Enable HP aux output stage */ /* decrease HPL/R gain to normal gain step by step */ /* Enable HP aux feedback loop */ /* Reduce HP aux feedback loop gain */ false );/* decrease HPR/L main output stage step by step */ false );/* Disable HP main output stage */ /* Enable HP aux CMFB loop */ /* Disable HP main CMFB loop */ /* Decrease HP input pair current to 2'b00 step by step */ false );/* Unshort HP main output to HP aux output stage */ /* Disable HP driver core circuits */ /* Disable HP driver bias circuits */ /* Disable HP aux CMFB loop */ /* Disable HP aux feedback loop */ /* Disable HP aux output stage */ static int mt_hp_event(struct snd_soc_dapm_widget *w,struct snd_kcontrol *kcontrol,int event)struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);int device = DEVICE_HP;"%s(), event 0x%x, dev_counter[DEV_HP] %d, mux %u\n" ,switch (event) {case SND_SOC_DAPM_PRE_PMU:if (mux == HP_MUX_HP)break ;case SND_SOC_DAPM_PRE_PMD:if (mux == HP_MUX_HP)break ;default :break ;return 0;static int mt_rcv_event(struct snd_soc_dapm_widget *w,struct snd_kcontrol *kcontrol,int event)struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);"%s(), event 0x%x, mux %u\n" ,switch (event) {case SND_SOC_DAPM_PRE_PMU:/* Disable handset short-circuit protection */ /* Set RCV DR bias current optimization, 010: 6uA */ /* Set RCV & ZCD bias current optimization */ /* 01: ZCD: 4uA, HP/HS/LO: 5uA */ /* Set HS STB enhance circuits */ /* Set HS output stage (3'b111 = 8x) */ /* Enable HS driver bias circuits */ /* Enable HS driver core circuits */ /* Set HS gain to normal gain step by step */ /* Enable AUD_CLK */ true );/* Enable Audio DAC */ /* Enable low-noise mode of DAC */ /* Switch HS MUX to audio DAC */ break ;case SND_SOC_DAPM_PRE_PMD:/* HS mux to open */ /* Disable Audio DAC */ /* Disable AUD_CLK */ false );/* decrease HS gain to minimum gain step by step */ /* Disable HS driver core circuits */ /* Disable HS driver bias circuits */ break ;default :break ;return 0;static int mt_lo_event(struct snd_soc_dapm_widget *w,struct snd_kcontrol *kcontrol,int event)struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);"%s(), event 0x%x, mux %u\n" ,switch (event) {case SND_SOC_DAPM_PRE_PMU:/* Disable handset short-circuit protection */ /* Set LO DR bias current optimization, 010: 6uA */ /* Set LO & ZCD bias current optimization */ /* 01: ZCD: 4uA, HP/HS/LO: 5uA */ if (priv->dev_counter[DEVICE_HP] == 0)/* Set LO STB enhance circuits */ /* Enable LO driver bias circuits */ /* Enable LO driver core circuits */ /* Set LO gain to normal gain step by step */ /* Enable AUD_CLK */ true );/* Switch LOL MUX to audio DAC */ if (mux == LO_MUX_L_DAC) {if (priv->dev_counter[DEVICE_HP] > 0) {"%s(), can not enable DAC, hp count %d\n" ,break ;/* Enable DACL and switch HP MUX to open*/ /* Disable low-noise mode of DAC */ /* Switch LOL MUX to DACL */ else if (mux == LO_MUX_3RD_DAC) {/* Enable Audio DAC (3rd DAC) */ /* Enable low-noise mode of DAC */ if (priv->dev_counter[DEVICE_HP] == 0)/* Switch LOL MUX to audio 3rd DAC */ break ;case SND_SOC_DAPM_PRE_PMD:/* Switch LOL MUX to open */ /* Disable Audio DAC */ if (mux == LO_MUX_L_DAC) {/* Disable HP driver core circuits */ /* Disable HP driver bias circuits */ /* Disable AUD_CLK */ false );/* decrease LO gain to minimum gain step by step */ /* Disable LO driver core circuits */ /* Disable LO driver bias circuits */ break ;default :break ;return 0;static int mt_adc_clk_gen_event(struct snd_soc_dapm_widget *w,struct snd_kcontrol *kcontrol,int event)struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);"%s(), event 0x%x\n" , __func__, event);switch (event) {case SND_SOC_DAPM_POST_PMU:/* ADC CLK from CLKGEN (6.5MHz) */ break ;case SND_SOC_DAPM_PRE_PMD:break ;default :break ;return 0;static int mt_dcc_clk_event(struct snd_soc_dapm_widget *w,struct snd_kcontrol *kcontrol,int event)struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);"%s(), event 0x%x\n" , __func__, event);switch (event) {case SND_SOC_DAPM_PRE_PMU:/* DCC 50k CLK (from 26M) */ /* MT6359_AFE_DCCLK_CFG0, bit 3 for dm ck swap */ break ;case SND_SOC_DAPM_POST_PMD:break ;default :break ;return 0;static int mt_mic_bias_0_event(struct snd_soc_dapm_widget *w,struct snd_kcontrol *kcontrol,int event)struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);unsigned int mic_type = priv->mux_select[MUX_MIC_TYPE_0];"%s(), event 0x%x, mic_type %d\n" ,switch (event) {case SND_SOC_DAPM_PRE_PMU:switch (mic_type) {case MIC_TYPE_MUX_DCC_ECM_DIFF:break ;case MIC_TYPE_MUX_DCC_ECM_SINGLE:break ;default :break ;/* DMIC enable */ /* MISBIAS0 = 1P9V */ /* normal power select */ break ;case SND_SOC_DAPM_POST_PMD:/* Disable MICBIAS0, MISBIAS0 = 1P7V */ break ;default :break ;return 0;static int mt_mic_bias_1_event(struct snd_soc_dapm_widget *w,struct snd_kcontrol *kcontrol,int event)struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);unsigned int mic_type = priv->mux_select[MUX_MIC_TYPE_1];"%s(), event 0x%x, mic_type %d\n" ,switch (event) {case SND_SOC_DAPM_PRE_PMU:/* MISBIAS1 = 2P6V */ if (mic_type == MIC_TYPE_MUX_DCC_ECM_SINGLE)else /* normal power select */ break ;default :break ;return 0;static int mt_mic_bias_2_event(struct snd_soc_dapm_widget *w,struct snd_kcontrol *kcontrol,int event)struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);unsigned int mic_type = priv->mux_select[MUX_MIC_TYPE_2];"%s(), event 0x%x, mic_type %d\n" ,switch (event) {case SND_SOC_DAPM_PRE_PMU:switch (mic_type) {case MIC_TYPE_MUX_DCC_ECM_DIFF:break ;case MIC_TYPE_MUX_DCC_ECM_SINGLE:break ;default :break ;/* MISBIAS2 = 1P9V */ /* normal power select */ break ;case SND_SOC_DAPM_POST_PMD:/* Disable MICBIAS2, MISBIAS0 = 1P7V */ break ;default :break ;return 0;static int mt_mtkaif_tx_event(struct snd_soc_dapm_widget *w,struct snd_kcontrol *kcontrol,int event)struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);"%s(), event = 0x%x\n" , __func__, event);switch (event) {case SND_SOC_DAPM_PRE_PMU:break ;case SND_SOC_DAPM_POST_PMD:break ;default :break ;return 0;static int mt_ul_src_dmic_event(struct snd_soc_dapm_widget *w,struct snd_kcontrol *kcontrol,int event)struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);"%s(), event = 0x%x\n" , __func__, event);switch (event) {case SND_SOC_DAPM_PRE_PMU:/* UL dmic setting */ if (priv->dmic_one_wire_mode)else /* default one wire, 3.25M */ break ;case SND_SOC_DAPM_POST_PMD:break ;default :break ;return 0;static int mt_ul_src_34_dmic_event(struct snd_soc_dapm_widget *w,struct snd_kcontrol *kcontrol,int event)struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);"%s(), event = 0x%x\n" , __func__, event);switch (event) {case SND_SOC_DAPM_PRE_PMU:/* default two wire, 3.25M */ break ;case SND_SOC_DAPM_POST_PMD:break ;default :break ;return 0;static int mt_adc_l_event(struct snd_soc_dapm_widget *w,struct snd_kcontrol *kcontrol,int event)struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);"%s(), event = 0x%x\n" , __func__, event);switch (event) {case SND_SOC_DAPM_POST_PMU:/* Audio L preamplifier DCC precharge off */ break ;default :break ;return 0;static int mt_adc_r_event(struct snd_soc_dapm_widget *w,struct snd_kcontrol *kcontrol,int event)struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);"%s(), event = 0x%x\n" , __func__, event);switch (event) {case SND_SOC_DAPM_POST_PMU:/* Audio R preamplifier DCC precharge off */ break ;default :break ;return 0;static int mt_adc_3_event(struct snd_soc_dapm_widget *w,struct snd_kcontrol *kcontrol,int event)struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);"%s(), event = 0x%x\n" , __func__, event);switch (event) {case SND_SOC_DAPM_POST_PMU:/* Audio R preamplifier DCC precharge off */ break ;default :break ;return 0;static int mt_pga_l_mux_event(struct snd_soc_dapm_widget *w,struct snd_kcontrol *kcontrol,int event)struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);"%s(), mux %d\n" , __func__, mux);return 0;static int mt_pga_r_mux_event(struct snd_soc_dapm_widget *w,struct snd_kcontrol *kcontrol,int event)struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);"%s(), mux %d\n" , __func__, mux);return 0;static int mt_pga_3_mux_event(struct snd_soc_dapm_widget *w,struct snd_kcontrol *kcontrol,int event)struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);"%s(), mux %d\n" , __func__, mux);return 0;static int mt_pga_l_event(struct snd_soc_dapm_widget *w,struct snd_kcontrol *kcontrol,int event)struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);int mic_gain_l = priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP1];unsigned int mux_pga = priv->mux_select[MUX_PGA_L];unsigned int mic_type;switch (mux_pga) {case PGA_L_MUX_AIN0:break ;case PGA_L_MUX_AIN1:break ;default :"%s(), invalid pga mux %d\n" ,return -EINVAL;switch (event) {case SND_SOC_DAPM_PRE_PMU:if (IS_DCC_BASE(mic_type)) {/* Audio L preamplifier DCC precharge */ break ;case SND_SOC_DAPM_POST_PMU:/* set mic pga gain */ if (IS_DCC_BASE(mic_type)) {/* L preamplifier DCCEN */ break ;case SND_SOC_DAPM_POST_PMD:/* L preamplifier DCCEN */ break ;default :break ;return 0;static int mt_pga_r_event(struct snd_soc_dapm_widget *w,struct snd_kcontrol *kcontrol,int event)struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);int mic_gain_r = priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP2];unsigned int mux_pga = priv->mux_select[MUX_PGA_R];unsigned int mic_type;switch (mux_pga) {case PGA_R_MUX_AIN0:break ;case PGA_R_MUX_AIN2:case PGA_R_MUX_AIN3:break ;default :"%s(), invalid pga mux %d\n" ,return -EINVAL;switch (event) {case SND_SOC_DAPM_PRE_PMU:if (IS_DCC_BASE(mic_type)) {/* Audio R preamplifier DCC precharge */ break ;case SND_SOC_DAPM_POST_PMU:/* set mic pga gain */ if (IS_DCC_BASE(mic_type)) {/* R preamplifier DCCEN */ break ;case SND_SOC_DAPM_POST_PMD:/* R preamplifier DCCEN */ break ;default :break ;return 0;static int mt_pga_3_event(struct snd_soc_dapm_widget *w,struct snd_kcontrol *kcontrol,int event)struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);int mic_gain_3 = priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP3];unsigned int mux_pga = priv->mux_select[MUX_PGA_3];unsigned int mic_type;switch (mux_pga) {case PGA_3_MUX_AIN2:case PGA_3_MUX_AIN3:break ;default :"%s(), invalid pga mux %d\n" ,return -EINVAL;switch (event) {case SND_SOC_DAPM_PRE_PMU:if (IS_DCC_BASE(mic_type)) {/* Audio 3 preamplifier DCC precharge */ break ;case SND_SOC_DAPM_POST_PMU:/* set mic pga gain */ if (IS_DCC_BASE(mic_type)) {/* 3 preamplifier DCCEN */ break ;case SND_SOC_DAPM_POST_PMD:/* 3 preamplifier DCCEN */ break ;default :break ;return 0;/* It is based on hw's control sequenece to add some delay when PMU/PMD */ static int mt_delay_250_event(struct snd_soc_dapm_widget *w,struct snd_kcontrol *kcontrol,int event)switch (event) {case SND_SOC_DAPM_POST_PMU:case SND_SOC_DAPM_PRE_PMD:break ;default :break ;return 0;static int mt_delay_100_event(struct snd_soc_dapm_widget *w,struct snd_kcontrol *kcontrol,int event)switch (event) {case SND_SOC_DAPM_POST_PMU:case SND_SOC_DAPM_PRE_PMD:break ;default :break ;return 0;static int mt_hp_pull_down_event(struct snd_soc_dapm_widget *w,struct snd_kcontrol *kcontrol,int event)struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);switch (event) {case SND_SOC_DAPM_PRE_PMU:true );break ;case SND_SOC_DAPM_POST_PMD:false );break ;default :break ;return 0;static int mt_hp_mute_event(struct snd_soc_dapm_widget *w,struct snd_kcontrol *kcontrol,int event)struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);switch (event) {case SND_SOC_DAPM_PRE_PMU:/* Set HPR/HPL gain to -22dB */ break ;case SND_SOC_DAPM_POST_PMD:/* Set HPL/HPR gain to mute */ break ;default :break ;return 0;static int mt_hp_damp_event(struct snd_soc_dapm_widget *w,struct snd_kcontrol *kcontrol,int event)struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);switch (event) {case SND_SOC_DAPM_POST_PMD:/* Disable HP damping circuit & HPN 4K load */ /* reset CMFB PW level */ break ;default :break ;return 0;static int mt_esd_resist_event(struct snd_soc_dapm_widget *w,struct snd_kcontrol *kcontrol,int event)struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);switch (event) {case SND_SOC_DAPM_PRE_PMU:/* Reduce ESD resistance of AU_REFN */ break ;case SND_SOC_DAPM_POST_PMD:/* Increase ESD resistance of AU_REFN */ break ;default :break ;return 0;static int mt_sdm_event(struct snd_soc_dapm_widget *w,struct snd_kcontrol *kcontrol,int event)struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);switch (event) {case SND_SOC_DAPM_PRE_PMU:/* sdm audio fifo clock power on */ /* scrambler clock on enable */ /* sdm power on */ /* sdm fifo enable */ break ;case SND_SOC_DAPM_POST_PMD:/* DL scrambler disabling sequence */ break ;default :break ;return 0;static int mt_sdm_3rd_event(struct snd_soc_dapm_widget *w,struct snd_kcontrol *kcontrol,int event)struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);switch (event) {case SND_SOC_DAPM_PRE_PMU:/* sdm audio fifo clock power on */ /* scrambler clock on enable */ /* sdm power on */ /* sdm fifo enable */ break ;case SND_SOC_DAPM_POST_PMD:/* DL scrambler disabling sequence */ break ;default :break ;return 0;static int mt_ncp_event(struct snd_soc_dapm_widget *w,struct snd_kcontrol *kcontrol,int event)struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);switch (event) {case SND_SOC_DAPM_PRE_PMU:break ;default :break ;return 0;/* DAPM Widgets */ static const struct snd_soc_dapm_widget mt6359_dapm_widgets[] = {/* Global Supply*/ "CLK_BUF" , SUPPLY_SEQ_CLK_BUF,"AUDGLB" , SUPPLY_SEQ_AUD_GLB,"CLKSQ Audio" , SUPPLY_SEQ_CLKSQ,"AUDNCP_CK" , SUPPLY_SEQ_TOP_CK,"ZCD13M_CK" , SUPPLY_SEQ_TOP_CK,"AUD_CK" , SUPPLY_SEQ_TOP_CK_LAST,"AUDIF_CK" , SUPPLY_SEQ_TOP_CK,"vaud18" , 0, 0),/* Digital Clock */ "AUDIO_TOP_AFE_CTL" , SUPPLY_SEQ_AUD_TOP_LAST,"AUDIO_TOP_DAC_CTL" , SUPPLY_SEQ_AUD_TOP,"AUDIO_TOP_ADC_CTL" , SUPPLY_SEQ_AUD_TOP,"AUDIO_TOP_ADDA6_ADC_CTL" , SUPPLY_SEQ_AUD_TOP,"AUDIO_TOP_I2S_DL" , SUPPLY_SEQ_AUD_TOP,"AUDIO_TOP_PWR_CLK" , SUPPLY_SEQ_AUD_TOP,"AUDIO_TOP_PDN_AFE_TESTMODEL" , SUPPLY_SEQ_AUD_TOP,"AUDIO_TOP_PDN_RESERVED" , SUPPLY_SEQ_AUD_TOP,"SDM" , SUPPLY_SEQ_DL_SDM,"SDM_3RD" , SUPPLY_SEQ_DL_SDM,/* ch123 share SDM FIFO CLK */ "SDM_FIFO_CLK" , SUPPLY_SEQ_DL_SDM_FIFO_CLK,"NCP" , SUPPLY_SEQ_DL_NCP,"DL Digital Clock" , SND_SOC_NOPM,"DL Digital Clock CH_1_2" , SND_SOC_NOPM,"DL Digital Clock CH_3" , SND_SOC_NOPM,/* AFE ON */ "AFE_ON" , SUPPLY_SEQ_AFE,/* AIF Rx*/ "AIF_RX" , "AIF1 Playback" , 0,"AIF2_RX" , "AIF2 Playback" , 0,"AFE_DL_SRC" , SUPPLY_SEQ_DL_SRC,/* DL Supply */ "DL Power Supply" , SND_SOC_NOPM,"ESD_RESIST" , SUPPLY_SEQ_DL_ESD_RESIST,"LDO" , SUPPLY_SEQ_DL_LDO,"LDO_REMOTE" , SUPPLY_SEQ_DL_LDO_REMOTE_SENSE,"NV_REGULATOR" , SUPPLY_SEQ_DL_NV,"IBIST" , SUPPLY_SEQ_DL_IBIST,/* DAC */ "DAC In Mux" , SND_SOC_NOPM, 0, 0, &dac_in_mux_control),"DACL" , NULL, SND_SOC_NOPM, 0, 0),"DACR" , NULL, SND_SOC_NOPM, 0, 0),"DAC_3RD" , NULL, SND_SOC_NOPM, 0, 0),/* Headphone */ "HP Mux" , SND_SOC_NOPM, 0, 0,"HP_Supply" , SND_SOC_NOPM,"HP_PULL_DOWN" , SUPPLY_SEQ_HP_PULL_DOWN,"HP_MUTE" , SUPPLY_SEQ_HP_MUTE,"HP_DAMP" , SUPPLY_SEQ_HP_DAMPING_OFF_RESET_CMFB,/* Receiver */ "RCV Mux" , SND_SOC_NOPM, 0, 0,/* LOL */ "LOL Mux" , SND_SOC_NOPM, 0, 0,/* Outputs */ "Receiver" ),"Headphone L" ),"Headphone R" ),"Headphone L Ext Spk Amp" ),"Headphone R Ext Spk Amp" ),"LINEOUT L" ),/* SGEN */ "SGEN DL Enable" , MT6359_AFE_SGEN_CFG0,"SGEN MUTE" , MT6359_AFE_SGEN_CFG0,"SGEN DL SRC" , MT6359_AFE_DL_SRC2_CON0_L,"SGEN DL" ),/* Uplinks */ "AIF1TX" , "AIF1 Capture" , 0,"AIF2TX" , "AIF2 Capture" , 0,"ADC_CLKGEN" , SUPPLY_SEQ_ADC_CLKGEN,"DCC_CLK" , SUPPLY_SEQ_DCC_CLK,/* Uplinks MUX */ "AIF Out Mux" , SND_SOC_NOPM, 0, 0,"AIF2 Out Mux" , SND_SOC_NOPM, 0, 0,"AIFTX_Supply" , SND_SOC_NOPM, 0, 0, NULL, 0),"MTKAIF_TX" , SUPPLY_SEQ_UL_MTKAIF,"UL_SRC" , SUPPLY_SEQ_UL_SRC,"UL_SRC_DMIC" , SUPPLY_SEQ_UL_SRC_DMIC,"UL_SRC_34" , SUPPLY_SEQ_UL_SRC,"UL_SRC_34_DMIC" , SUPPLY_SEQ_UL_SRC_DMIC,"MISO0_MUX" , SND_SOC_NOPM, 0, 0, &miso0_mux_control),"MISO1_MUX" , SND_SOC_NOPM, 0, 0, &miso1_mux_control),"MISO2_MUX" , SND_SOC_NOPM, 0, 0, &miso2_mux_control),"UL_SRC_MUX" , SND_SOC_NOPM, 0, 0,"UL2_SRC_MUX" , SND_SOC_NOPM, 0, 0,"DMIC0_MUX" , SND_SOC_NOPM, 0, 0, &dmic0_mux_control),"DMIC1_MUX" , SND_SOC_NOPM, 0, 0, &dmic1_mux_control),"DMIC2_MUX" , SND_SOC_NOPM, 0, 0, &dmic2_mux_control),"ADC_L_Mux" , SND_SOC_NOPM, 0, 0,"ADC_R_Mux" , SND_SOC_NOPM, 0, 0,"ADC_3_Mux" , SND_SOC_NOPM, 0, 0,"ADC_L" , NULL, SND_SOC_NOPM, 0, 0),"ADC_R" , NULL, SND_SOC_NOPM, 0, 0),"ADC_3" , NULL, SND_SOC_NOPM, 0, 0),"ADC_L_EN" , SUPPLY_SEQ_UL_ADC,"ADC_R_EN" , SUPPLY_SEQ_UL_ADC,"ADC_3_EN" , SUPPLY_SEQ_UL_ADC,"PGA_L_Mux" , SND_SOC_NOPM, 0, 0,"PGA_R_Mux" , SND_SOC_NOPM, 0, 0,"PGA_3_Mux" , SND_SOC_NOPM, 0, 0,"PGA_L" , SND_SOC_NOPM, 0, 0, NULL, 0),"PGA_R" , SND_SOC_NOPM, 0, 0, NULL, 0),"PGA_3" , SND_SOC_NOPM, 0, 0, NULL, 0),"PGA_L_EN" , SUPPLY_SEQ_UL_PGA,"PGA_R_EN" , SUPPLY_SEQ_UL_PGA,"PGA_3_EN" , SUPPLY_SEQ_UL_PGA,/* UL input */ "AIN0" ),"AIN1" ),"AIN2" ),"AIN3" ),"AIN0_DMIC" ),"AIN2_DMIC" ),"AIN3_DMIC" ),/* mic bias */ "MIC_BIAS_0" , SUPPLY_SEQ_MIC_BIAS,"MIC_BIAS_1" , SUPPLY_SEQ_MIC_BIAS,"MIC_BIAS_2" , SUPPLY_SEQ_MIC_BIAS,/* dmic */ "DMIC_0" , SUPPLY_SEQ_DMIC,"DMIC_1" , SUPPLY_SEQ_DMIC,static int mt_dcc_clk_connect(struct snd_soc_dapm_widget *source,struct snd_soc_dapm_widget *sink)struct snd_soc_dapm_widget *w = sink;struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);if (IS_DCC_BASE(priv->mux_select[MUX_MIC_TYPE_0]) ||return 1;else return 0;static const struct snd_soc_dapm_route mt6359_dapm_routes[] = {/* Capture */ "AIFTX_Supply" , NULL, "CLK_BUF" },"AIFTX_Supply" , NULL, "vaud18" },"AIFTX_Supply" , NULL, "AUDGLB" },"AIFTX_Supply" , NULL, "CLKSQ Audio" },"AIFTX_Supply" , NULL, "AUD_CK" },"AIFTX_Supply" , NULL, "AUDIF_CK" },"AIFTX_Supply" , NULL, "AUDIO_TOP_AFE_CTL" },"AIFTX_Supply" , NULL, "AUDIO_TOP_PWR_CLK" },"AIFTX_Supply" , NULL, "AUDIO_TOP_PDN_RESERVED" },"AIFTX_Supply" , NULL, "AUDIO_TOP_I2S_DL" },/* * *_ADC_CTL should enable only if UL_SRC in use, * but dm ck may be needed even UL_SRC_x not in use "AIFTX_Supply" , NULL, "AUDIO_TOP_ADC_CTL" },"AIFTX_Supply" , NULL, "AUDIO_TOP_ADDA6_ADC_CTL" },"AIFTX_Supply" , NULL, "AFE_ON" },/* ul ch 12 */ "AIF1TX" , NULL, "AIF Out Mux" },"AIF1TX" , NULL, "AIFTX_Supply" },"AIF1TX" , NULL, "MTKAIF_TX" },"AIF2TX" , NULL, "AIF2 Out Mux" },"AIF2TX" , NULL, "AIFTX_Supply" },"AIF2TX" , NULL, "MTKAIF_TX" },"AIF Out Mux" , "Normal Path" , "MISO0_MUX" },"AIF Out Mux" , "Normal Path" , "MISO1_MUX" },"AIF2 Out Mux" , "Normal Path" , "MISO2_MUX" },"MISO0_MUX" , "UL1_CH1" , "UL_SRC_MUX" },"MISO0_MUX" , "UL1_CH2" , "UL_SRC_MUX" },"MISO0_MUX" , "UL2_CH1" , "UL2_SRC_MUX" },"MISO0_MUX" , "UL2_CH2" , "UL2_SRC_MUX" },"MISO1_MUX" , "UL1_CH1" , "UL_SRC_MUX" },"MISO1_MUX" , "UL1_CH2" , "UL_SRC_MUX" },"MISO1_MUX" , "UL2_CH1" , "UL2_SRC_MUX" },"MISO1_MUX" , "UL2_CH2" , "UL2_SRC_MUX" },"MISO2_MUX" , "UL1_CH1" , "UL_SRC_MUX" },"MISO2_MUX" , "UL1_CH2" , "UL_SRC_MUX" },"MISO2_MUX" , "UL2_CH1" , "UL2_SRC_MUX" },"MISO2_MUX" , "UL2_CH2" , "UL2_SRC_MUX" },"MISO0_MUX" , NULL, "UL_SRC" },"MISO1_MUX" , NULL, "UL_SRC" },"MISO2_MUX" , NULL, "UL_SRC_34" },"UL_SRC_MUX" , "AMIC" , "ADC_L" },"UL_SRC_MUX" , "AMIC" , "ADC_R" },"UL_SRC_MUX" , "DMIC" , "DMIC0_MUX" },"UL_SRC_MUX" , "DMIC" , "DMIC1_MUX" },"UL_SRC_MUX" , NULL, "UL_SRC" },"UL2_SRC_MUX" , "AMIC" , "ADC_3" },"UL2_SRC_MUX" , "DMIC" , "DMIC2_MUX" },"UL2_SRC_MUX" , NULL, "UL_SRC_34" },"DMIC0_MUX" , "DMIC_DATA0" , "AIN0_DMIC" },"DMIC0_MUX" , "DMIC_DATA1_L" , "AIN2_DMIC" },"DMIC0_MUX" , "DMIC_DATA1_L_1" , "AIN2_DMIC" },"DMIC0_MUX" , "DMIC_DATA1_R" , "AIN3_DMIC" },"DMIC1_MUX" , "DMIC_DATA0" , "AIN0_DMIC" },"DMIC1_MUX" , "DMIC_DATA1_L" , "AIN2_DMIC" },"DMIC1_MUX" , "DMIC_DATA1_L_1" , "AIN2_DMIC" },"DMIC1_MUX" , "DMIC_DATA1_R" , "AIN3_DMIC" },"DMIC2_MUX" , "DMIC_DATA0" , "AIN0_DMIC" },"DMIC2_MUX" , "DMIC_DATA1_L" , "AIN2_DMIC" },"DMIC2_MUX" , "DMIC_DATA1_L_1" , "AIN2_DMIC" },"DMIC2_MUX" , "DMIC_DATA1_R" , "AIN3_DMIC" },"DMIC0_MUX" , NULL, "UL_SRC_DMIC" },"DMIC1_MUX" , NULL, "UL_SRC_DMIC" },"DMIC2_MUX" , NULL, "UL_SRC_34_DMIC" },"AIN0_DMIC" , NULL, "DMIC_0" },"AIN2_DMIC" , NULL, "DMIC_1" },"AIN3_DMIC" , NULL, "DMIC_1" },"AIN0_DMIC" , NULL, "MIC_BIAS_0" },"AIN2_DMIC" , NULL, "MIC_BIAS_2" },"AIN3_DMIC" , NULL, "MIC_BIAS_2" },/* adc */ "ADC_L" , NULL, "ADC_L_Mux" },"ADC_L" , NULL, "ADC_CLKGEN" },"ADC_L" , NULL, "ADC_L_EN" },"ADC_R" , NULL, "ADC_R_Mux" },"ADC_R" , NULL, "ADC_CLKGEN" },"ADC_R" , NULL, "ADC_R_EN" },/* * amic fifo ch1/2 clk from ADC_L, * enable ADC_L even use ADC_R only "ADC_R" , NULL, "ADC_L_EN" },"ADC_3" , NULL, "ADC_3_Mux" },"ADC_3" , NULL, "ADC_CLKGEN" },"ADC_3" , NULL, "ADC_3_EN" },"ADC_L_Mux" , "Left Preamplifier" , "PGA_L" },"ADC_R_Mux" , "Right Preamplifier" , "PGA_R" },"ADC_3_Mux" , "Preamplifier" , "PGA_3" },"PGA_L" , NULL, "PGA_L_Mux" },"PGA_L" , NULL, "PGA_L_EN" },"PGA_R" , NULL, "PGA_R_Mux" },"PGA_R" , NULL, "PGA_R_EN" },"PGA_3" , NULL, "PGA_3_Mux" },"PGA_3" , NULL, "PGA_3_EN" },"PGA_L" , NULL, "DCC_CLK" , mt_dcc_clk_connect},"PGA_R" , NULL, "DCC_CLK" , mt_dcc_clk_connect},"PGA_3" , NULL, "DCC_CLK" , mt_dcc_clk_connect},"PGA_L_Mux" , "AIN0" , "AIN0" },"PGA_L_Mux" , "AIN1" , "AIN1" },"PGA_R_Mux" , "AIN0" , "AIN0" },"PGA_R_Mux" , "AIN2" , "AIN2" },"PGA_R_Mux" , "AIN3" , "AIN3" },"PGA_3_Mux" , "AIN2" , "AIN2" },"PGA_3_Mux" , "AIN3" , "AIN3" },"AIN0" , NULL, "MIC_BIAS_0" },"AIN1" , NULL, "MIC_BIAS_1" },"AIN2" , NULL, "MIC_BIAS_0" },"AIN2" , NULL, "MIC_BIAS_2" },"AIN3" , NULL, "MIC_BIAS_2" },/* DL Supply */ "DL Power Supply" , NULL, "CLK_BUF" },"DL Power Supply" , NULL, "vaud18" },"DL Power Supply" , NULL, "AUDGLB" },"DL Power Supply" , NULL, "CLKSQ Audio" },"DL Power Supply" , NULL, "AUDNCP_CK" },"DL Power Supply" , NULL, "ZCD13M_CK" },"DL Power Supply" , NULL, "AUD_CK" },"DL Power Supply" , NULL, "AUDIF_CK" },"DL Power Supply" , NULL, "ESD_RESIST" },"DL Power Supply" , NULL, "LDO" },"DL Power Supply" , NULL, "LDO_REMOTE" },"DL Power Supply" , NULL, "NV_REGULATOR" },"DL Power Supply" , NULL, "IBIST" },/* DL Digital Supply */ "DL Digital Clock" , NULL, "AUDIO_TOP_AFE_CTL" },"DL Digital Clock" , NULL, "AUDIO_TOP_DAC_CTL" },"DL Digital Clock" , NULL, "AUDIO_TOP_PWR_CLK" },"DL Digital Clock" , NULL, "AUDIO_TOP_PDN_RESERVED" },"DL Digital Clock" , NULL, "SDM_FIFO_CLK" },"DL Digital Clock" , NULL, "NCP" },"DL Digital Clock" , NULL, "AFE_ON" },"DL Digital Clock" , NULL, "AFE_DL_SRC" },"DL Digital Clock CH_1_2" , NULL, "DL Digital Clock" },"DL Digital Clock CH_1_2" , NULL, "SDM" },"DL Digital Clock CH_3" , NULL, "DL Digital Clock" },"DL Digital Clock CH_3" , NULL, "SDM_3RD" },"AIF_RX" , NULL, "DL Digital Clock CH_1_2" },"AIF2_RX" , NULL, "DL Digital Clock CH_3" },/* DL Path */ "DAC In Mux" , "Normal Path" , "AIF_RX" },"DAC In Mux" , "Sgen" , "SGEN DL" },"SGEN DL" , NULL, "SGEN DL SRC" },"SGEN DL" , NULL, "SGEN MUTE" },"SGEN DL" , NULL, "SGEN DL Enable" },"SGEN DL" , NULL, "DL Digital Clock CH_1_2" },"SGEN DL" , NULL, "DL Digital Clock CH_3" },"SGEN DL" , NULL, "AUDIO_TOP_PDN_AFE_TESTMODEL" },"DACL" , NULL, "DAC In Mux" },"DACL" , NULL, "DL Power Supply" },"DACR" , NULL, "DAC In Mux" },"DACR" , NULL, "DL Power Supply" },/* DAC 3RD */ "DAC In Mux" , "Normal Path" , "AIF2_RX" },"DAC_3RD" , NULL, "DAC In Mux" },"DAC_3RD" , NULL, "DL Power Supply" },/* Lineout Path */ "LOL Mux" , "Playback" , "DAC_3RD" },"LOL Mux" , "Playback_L_DAC" , "DACL" },"LINEOUT L" , NULL, "LOL Mux" },/* Headphone Path */ "HP_Supply" , NULL, "HP_PULL_DOWN" },"HP_Supply" , NULL, "HP_MUTE" },"HP_Supply" , NULL, "HP_DAMP" },"HP Mux" , NULL, "HP_Supply" },"HP Mux" , "Audio Playback" , "DACL" },"HP Mux" , "Audio Playback" , "DACR" },"HP Mux" , "HP Impedance" , "DACL" },"HP Mux" , "HP Impedance" , "DACR" },"HP Mux" , "LoudSPK Playback" , "DACL" },"HP Mux" , "LoudSPK Playback" , "DACR" },"Headphone L" , NULL, "HP Mux" },"Headphone R" , NULL, "HP Mux" },"Headphone L Ext Spk Amp" , NULL, "HP Mux" },"Headphone R Ext Spk Amp" , NULL, "HP Mux" },/* Receiver Path */ "RCV Mux" , "Voice Playback" , "DACL" },"Receiver" , NULL, "RCV Mux" },static int mt6359_codec_dai_hw_params(struct snd_pcm_substream *substream,struct snd_pcm_hw_params *params,struct snd_soc_dai *dai)struct snd_soc_component *cmpnt = dai->component;struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);unsigned int rate = params_rate(params);int id = dai->id;"%s(), id %d, substream->stream %d, rate %d, number %d\n" ,if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)return 0;static int mt6359_codec_dai_startup(struct snd_pcm_substream *substream,struct snd_soc_dai *dai)struct snd_soc_component *cmpnt = dai->component;struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);"%s stream %d\n" , __func__, substream->stream);if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)return 0;static void mt6359_codec_dai_shutdown(struct snd_pcm_substream *substream,struct snd_soc_dai *dai)struct snd_soc_component *cmpnt = dai->component;struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);"%s stream %d\n" , __func__, substream->stream);if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)static const struct snd_soc_dai_ops mt6359_codec_dai_ops = {#define MT6359_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_U16_LE |\static struct snd_soc_dai_driver mt6359_dai_driver[] = {"mt6359-snd-codec-aif1" ,"AIF1 Playback" ,"AIF1 Capture" ,"mt6359-snd-codec-aif2" ,"AIF2 Playback" ,"AIF2 Capture" ,static int mt6359_codec_init_reg(struct snd_soc_component *cmpnt)struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);/* enable clk buf */ /* set those not controlled by dapm widget */ /* audio clk source from internal dcxo */ /* Disable HeadphoneL/HeadphoneR short circuit protection */ /* Disable voice short circuit protection */ /* disable LO buffer left short circuit protection */ /* set gpio */ /* hp hifi mode, default normal mode */ /* Disable AUD_ZCD */ /* disable clk buf */ return 0;static int mt6359_codec_probe(struct snd_soc_component *cmpnt)struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);return mt6359_codec_init_reg(cmpnt);static void mt6359_codec_remove(struct snd_soc_component *cmpnt)static const DECLARE_TLV_DB_SCALE(playback_tlv, -1000, 100, 0);static const DECLARE_TLV_DB_SCALE(capture_tlv, 0, 600, 0);static const struct snd_kcontrol_new mt6359_snd_controls[] = {/* dl pga gain */ "Headset Volume" ,"Lineout Volume" ,"Handset Volume" ,/* ul pga gain */ "PGA1 Volume" ,"PGA2 Volume" ,"PGA3 Volume" ,static const struct snd_soc_component_driver mt6359_soc_component_driver = {static int mt6359_parse_dt(struct mt6359_priv *priv)int ret;struct device *dev = priv->dev;struct device_node *np;"audio-codec" );if (!np) {"mt6359codec" );if (!np)return -EINVAL;"mediatek,dmic-mode" ,if (ret) {"%s() failed to read dmic-mode, use default (0)\n" ,"mediatek,mic-type-0" ,if (ret) {"%s() failed to read mic-type-0, use default (%d)\n" ,"mediatek,mic-type-1" ,if (ret) {"%s() failed to read mic-type-1, use default (%d)\n" ,"mediatek,mic-type-2" ,if (ret) {"%s() failed to read mic-type-2, use default (%d)\n" ,return 0;static int mt6359_platform_driver_probe(struct platform_device *pdev)struct mt6359_priv *priv;int ret;struct mt6397_chip *mt6397 = dev_get_drvdata(pdev->dev.parent);"%s(), dev name %s\n" ,sizeof (*priv), GFP_KERNEL);if (!priv)return -ENOMEM;if (IS_ERR(priv->regmap))return PTR_ERR(priv->regmap);if (ret) {"%s() failed to parse dts\n" , __func__);return ret;return devm_snd_soc_register_component(&pdev->dev,static struct platform_driver mt6359_platform_driver = {"mt6359-sound" ,/* Module information */ "MT6359 ALSA SoC codec driver" );"KaiChieh Chuang <kaichieh.chuang@mediatek.com>" );"Eason Yen <eason.yen@mediatek.com>" );"GPL v2" );
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(vorverarbeitet am 2026-04-25)
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