Impressum wm2200.h
Sprache: C
/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * wm2200 . h - WM2200 audio codec interface * * Copyright 2012 Wolfson Microelectronics PLC . * Author : Mark Brown < broonie @ opensource . wolfsonmicro . com > #ifndef _WM2200_H#define _WM2200_H#define WM2200_CLK_SYSCLK 1 #define WM2200_CLKSRC_MCLK1 0 #define WM2200_CLKSRC_MCLK2 1 #define WM2200_CLKSRC_FLL 4 #define WM2200_CLKSRC_BCLK1 8 #define WM2200_FLL_SRC_MCLK1 0 #define WM2200_FLL_SRC_MCLK2 1 #define WM2200_FLL_SRC_BCLK 2 /* * Register values . #define WM2200_SOFTWARE_RESET 0 x00#define WM2200_DEVICE_REVISION 0 x01#define WM2200_TONE_GENERATOR_1 0 x0B#define WM2200_CLOCKING_3 0 x102#define WM2200_CLOCKING_4 0 x103#define WM2200_FLL_CONTROL_1 0 x111#define WM2200_FLL_CONTROL_2 0 x112#define WM2200_FLL_CONTROL_3 0 x113#define WM2200_FLL_CONTROL_4 0 x114#define WM2200_FLL_CONTROL_6 0 x116#define WM2200_FLL_CONTROL_7 0 x117#define WM2200_FLL_EFS_1 0 x119#define WM2200_FLL_EFS_2 0 x11A#define WM2200_MIC_CHARGE_PUMP_1 0 x200#define WM2200_MIC_CHARGE_PUMP_2 0 x201#define WM2200_DM_CHARGE_PUMP_1 0 x202#define WM2200_MIC_BIAS_CTRL_1 0 x20C#define WM2200_MIC_BIAS_CTRL_2 0 x20D#define WM2200_EAR_PIECE_CTRL_1 0 x20F#define WM2200_EAR_PIECE_CTRL_2 0 x210#define WM2200_INPUT_ENABLES 0 x301#define WM2200_IN1L_CONTROL 0 x302#define WM2200_IN1R_CONTROL 0 x303#define WM2200_IN2L_CONTROL 0 x304#define WM2200_IN2R_CONTROL 0 x305#define WM2200_IN3L_CONTROL 0 x306#define WM2200_IN3R_CONTROL 0 x307#define WM2200_RXANC_SRC 0 x30A#define WM2200_INPUT_VOLUME_RAMP 0 x30B#define WM2200_ADC_DIGITAL_VOLUME_1L 0 x30C#define WM2200_ADC_DIGITAL_VOLUME_1R 0 x30D#define WM2200_ADC_DIGITAL_VOLUME_2L 0 x30E#define WM2200_ADC_DIGITAL_VOLUME_2R 0 x30F#define WM2200_ADC_DIGITAL_VOLUME_3L 0 x310#define WM2200_ADC_DIGITAL_VOLUME_3R 0 x311#define WM2200_OUTPUT_ENABLES 0 x400#define WM2200_DAC_VOLUME_LIMIT_1L 0 x401#define WM2200_DAC_VOLUME_LIMIT_1R 0 x402#define WM2200_DAC_VOLUME_LIMIT_2L 0 x403#define WM2200_DAC_VOLUME_LIMIT_2R 0 x404#define WM2200_DAC_AEC_CONTROL_1 0 x409#define WM2200_OUTPUT_VOLUME_RAMP 0 x40A#define WM2200_DAC_DIGITAL_VOLUME_1L 0 x40B#define WM2200_DAC_DIGITAL_VOLUME_1R 0 x40C#define WM2200_DAC_DIGITAL_VOLUME_2L 0 x40D#define WM2200_DAC_DIGITAL_VOLUME_2R 0 x40E#define WM2200_PDM_1 0 x417#define WM2200_PDM_2 0 x418#define WM2200_AUDIO_IF_1_1 0 x500#define WM2200_AUDIO_IF_1_2 0 x501#define WM2200_AUDIO_IF_1_3 0 x502#define WM2200_AUDIO_IF_1_4 0 x503#define WM2200_AUDIO_IF_1_5 0 x504#define WM2200_AUDIO_IF_1_6 0 x505#define WM2200_AUDIO_IF_1_7 0 x506#define WM2200_AUDIO_IF_1_8 0 x507#define WM2200_AUDIO_IF_1_9 0 x508#define WM2200_AUDIO_IF_1_10 0 x509#define WM2200_AUDIO_IF_1_11 0 x50A#define WM2200_AUDIO_IF_1_12 0 x50B#define WM2200_AUDIO_IF_1_13 0 x50C#define WM2200_AUDIO_IF_1_14 0 x50D#define WM2200_AUDIO_IF_1_15 0 x50E#define WM2200_AUDIO_IF_1_16 0 x50F#define WM2200_AUDIO_IF_1_17 0 x510#define WM2200_AUDIO_IF_1_18 0 x511#define WM2200_AUDIO_IF_1_19 0 x512#define WM2200_AUDIO_IF_1_20 0 x513#define WM2200_AUDIO_IF_1_21 0 x514#define WM2200_AUDIO_IF_1_22 0 x515#define WM2200_OUT1LMIX_INPUT_1_SOURCE 0 x600#define WM2200_OUT1LMIX_INPUT_1_VOLUME 0 x601#define WM2200_OUT1LMIX_INPUT_2_SOURCE 0 x602#define WM2200_OUT1LMIX_INPUT_2_VOLUME 0 x603#define WM2200_OUT1LMIX_INPUT_3_SOURCE 0 x604#define WM2200_OUT1LMIX_INPUT_3_VOLUME 0 x605#define WM2200_OUT1LMIX_INPUT_4_SOURCE 0 x606#define WM2200_OUT1LMIX_INPUT_4_VOLUME 0 x607#define WM2200_OUT1RMIX_INPUT_1_SOURCE 0 x608#define WM2200_OUT1RMIX_INPUT_1_VOLUME 0 x609#define WM2200_OUT1RMIX_INPUT_2_SOURCE 0 x60A#define WM2200_OUT1RMIX_INPUT_2_VOLUME 0 x60B#define WM2200_OUT1RMIX_INPUT_3_SOURCE 0 x60C#define WM2200_OUT1RMIX_INPUT_3_VOLUME 0 x60D#define WM2200_OUT1RMIX_INPUT_4_SOURCE 0 x60E#define WM2200_OUT1RMIX_INPUT_4_VOLUME 0 x60F#define WM2200_OUT2LMIX_INPUT_1_SOURCE 0 x610#define WM2200_OUT2LMIX_INPUT_1_VOLUME 0 x611#define WM2200_OUT2LMIX_INPUT_2_SOURCE 0 x612#define WM2200_OUT2LMIX_INPUT_2_VOLUME 0 x613#define WM2200_OUT2LMIX_INPUT_3_SOURCE 0 x614#define WM2200_OUT2LMIX_INPUT_3_VOLUME 0 x615#define WM2200_OUT2LMIX_INPUT_4_SOURCE 0 x616#define WM2200_OUT2LMIX_INPUT_4_VOLUME 0 x617#define WM2200_OUT2RMIX_INPUT_1_SOURCE 0 x618#define WM2200_OUT2RMIX_INPUT_1_VOLUME 0 x619#define WM2200_OUT2RMIX_INPUT_2_SOURCE 0 x61A#define WM2200_OUT2RMIX_INPUT_2_VOLUME 0 x61B#define WM2200_OUT2RMIX_INPUT_3_SOURCE 0 x61C#define WM2200_OUT2RMIX_INPUT_3_VOLUME 0 x61D#define WM2200_OUT2RMIX_INPUT_4_SOURCE 0 x61E#define WM2200_OUT2RMIX_INPUT_4_VOLUME 0 x61F#define WM2200_AIF1TX1MIX_INPUT_1_SOURCE 0 x620#define WM2200_AIF1TX1MIX_INPUT_1_VOLUME 0 x621#define WM2200_AIF1TX1MIX_INPUT_2_SOURCE 0 x622#define WM2200_AIF1TX1MIX_INPUT_2_VOLUME 0 x623#define WM2200_AIF1TX1MIX_INPUT_3_SOURCE 0 x624#define WM2200_AIF1TX1MIX_INPUT_3_VOLUME 0 x625#define WM2200_AIF1TX1MIX_INPUT_4_SOURCE 0 x626#define WM2200_AIF1TX1MIX_INPUT_4_VOLUME 0 x627#define WM2200_AIF1TX2MIX_INPUT_1_SOURCE 0 x628#define WM2200_AIF1TX2MIX_INPUT_1_VOLUME 0 x629#define WM2200_AIF1TX2MIX_INPUT_2_SOURCE 0 x62A#define WM2200_AIF1TX2MIX_INPUT_2_VOLUME 0 x62B#define WM2200_AIF1TX2MIX_INPUT_3_SOURCE 0 x62C#define WM2200_AIF1TX2MIX_INPUT_3_VOLUME 0 x62D#define WM2200_AIF1TX2MIX_INPUT_4_SOURCE 0 x62E#define WM2200_AIF1TX2MIX_INPUT_4_VOLUME 0 x62F#define WM2200_AIF1TX3MIX_INPUT_1_SOURCE 0 x630#define WM2200_AIF1TX3MIX_INPUT_1_VOLUME 0 x631#define WM2200_AIF1TX3MIX_INPUT_2_SOURCE 0 x632#define WM2200_AIF1TX3MIX_INPUT_2_VOLUME 0 x633#define WM2200_AIF1TX3MIX_INPUT_3_SOURCE 0 x634#define WM2200_AIF1TX3MIX_INPUT_3_VOLUME 0 x635#define WM2200_AIF1TX3MIX_INPUT_4_SOURCE 0 x636#define WM2200_AIF1TX3MIX_INPUT_4_VOLUME 0 x637#define WM2200_AIF1TX4MIX_INPUT_1_SOURCE 0 x638#define WM2200_AIF1TX4MIX_INPUT_1_VOLUME 0 x639#define WM2200_AIF1TX4MIX_INPUT_2_SOURCE 0 x63A#define WM2200_AIF1TX4MIX_INPUT_2_VOLUME 0 x63B#define WM2200_AIF1TX4MIX_INPUT_3_SOURCE 0 x63C#define WM2200_AIF1TX4MIX_INPUT_3_VOLUME 0 x63D#define WM2200_AIF1TX4MIX_INPUT_4_SOURCE 0 x63E#define WM2200_AIF1TX4MIX_INPUT_4_VOLUME 0 x63F#define WM2200_AIF1TX5MIX_INPUT_1_SOURCE 0 x640#define WM2200_AIF1TX5MIX_INPUT_1_VOLUME 0 x641#define WM2200_AIF1TX5MIX_INPUT_2_SOURCE 0 x642#define WM2200_AIF1TX5MIX_INPUT_2_VOLUME 0 x643#define WM2200_AIF1TX5MIX_INPUT_3_SOURCE 0 x644#define WM2200_AIF1TX5MIX_INPUT_3_VOLUME 0 x645#define WM2200_AIF1TX5MIX_INPUT_4_SOURCE 0 x646#define WM2200_AIF1TX5MIX_INPUT_4_VOLUME 0 x647#define WM2200_AIF1TX6MIX_INPUT_1_SOURCE 0 x648#define WM2200_AIF1TX6MIX_INPUT_1_VOLUME 0 x649#define WM2200_AIF1TX6MIX_INPUT_2_SOURCE 0 x64A#define WM2200_AIF1TX6MIX_INPUT_2_VOLUME 0 x64B#define WM2200_AIF1TX6MIX_INPUT_3_SOURCE 0 x64C#define WM2200_AIF1TX6MIX_INPUT_3_VOLUME 0 x64D#define WM2200_AIF1TX6MIX_INPUT_4_SOURCE 0 x64E#define WM2200_AIF1TX6MIX_INPUT_4_VOLUME 0 x64F#define WM2200_EQLMIX_INPUT_1_SOURCE 0 x650#define WM2200_EQLMIX_INPUT_1_VOLUME 0 x651#define WM2200_EQLMIX_INPUT_2_SOURCE 0 x652#define WM2200_EQLMIX_INPUT_2_VOLUME 0 x653#define WM2200_EQLMIX_INPUT_3_SOURCE 0 x654#define WM2200_EQLMIX_INPUT_3_VOLUME 0 x655#define WM2200_EQLMIX_INPUT_4_SOURCE 0 x656#define WM2200_EQLMIX_INPUT_4_VOLUME 0 x657#define WM2200_EQRMIX_INPUT_1_SOURCE 0 x658#define WM2200_EQRMIX_INPUT_1_VOLUME 0 x659#define WM2200_EQRMIX_INPUT_2_SOURCE 0 x65A#define WM2200_EQRMIX_INPUT_2_VOLUME 0 x65B#define WM2200_EQRMIX_INPUT_3_SOURCE 0 x65C#define WM2200_EQRMIX_INPUT_3_VOLUME 0 x65D#define WM2200_EQRMIX_INPUT_4_SOURCE 0 x65E#define WM2200_EQRMIX_INPUT_4_VOLUME 0 x65F#define WM2200_LHPF1MIX_INPUT_1_SOURCE 0 x660#define WM2200_LHPF1MIX_INPUT_1_VOLUME 0 x661#define WM2200_LHPF1MIX_INPUT_2_SOURCE 0 x662#define WM2200_LHPF1MIX_INPUT_2_VOLUME 0 x663#define WM2200_LHPF1MIX_INPUT_3_SOURCE 0 x664#define WM2200_LHPF1MIX_INPUT_3_VOLUME 0 x665#define WM2200_LHPF1MIX_INPUT_4_SOURCE 0 x666#define WM2200_LHPF1MIX_INPUT_4_VOLUME 0 x667#define WM2200_LHPF2MIX_INPUT_1_SOURCE 0 x668#define WM2200_LHPF2MIX_INPUT_1_VOLUME 0 x669#define WM2200_LHPF2MIX_INPUT_2_SOURCE 0 x66A#define WM2200_LHPF2MIX_INPUT_2_VOLUME 0 x66B#define WM2200_LHPF2MIX_INPUT_3_SOURCE 0 x66C#define WM2200_LHPF2MIX_INPUT_3_VOLUME 0 x66D#define WM2200_LHPF2MIX_INPUT_4_SOURCE 0 x66E#define WM2200_LHPF2MIX_INPUT_4_VOLUME 0 x66F#define WM2200_DSP1LMIX_INPUT_1_SOURCE 0 x670#define WM2200_DSP1LMIX_INPUT_1_VOLUME 0 x671#define WM2200_DSP1LMIX_INPUT_2_SOURCE 0 x672#define WM2200_DSP1LMIX_INPUT_2_VOLUME 0 x673#define WM2200_DSP1LMIX_INPUT_3_SOURCE 0 x674#define WM2200_DSP1LMIX_INPUT_3_VOLUME 0 x675#define WM2200_DSP1LMIX_INPUT_4_SOURCE 0 x676#define WM2200_DSP1LMIX_INPUT_4_VOLUME 0 x677#define WM2200_DSP1RMIX_INPUT_1_SOURCE 0 x678#define WM2200_DSP1RMIX_INPUT_1_VOLUME 0 x679#define WM2200_DSP1RMIX_INPUT_2_SOURCE 0 x67A#define WM2200_DSP1RMIX_INPUT_2_VOLUME 0 x67B#define WM2200_DSP1RMIX_INPUT_3_SOURCE 0 x67C#define WM2200_DSP1RMIX_INPUT_3_VOLUME 0 x67D#define WM2200_DSP1RMIX_INPUT_4_SOURCE 0 x67E#define WM2200_DSP1RMIX_INPUT_4_VOLUME 0 x67F#define WM2200_DSP1AUX1MIX_INPUT_1_SOURCE 0 x680#define WM2200_DSP1AUX2MIX_INPUT_1_SOURCE 0 x681#define WM2200_DSP1AUX3MIX_INPUT_1_SOURCE 0 x682#define WM2200_DSP1AUX4MIX_INPUT_1_SOURCE 0 x683#define WM2200_DSP1AUX5MIX_INPUT_1_SOURCE 0 x684#define WM2200_DSP1AUX6MIX_INPUT_1_SOURCE 0 x685#define WM2200_DSP2LMIX_INPUT_1_SOURCE 0 x686#define WM2200_DSP2LMIX_INPUT_1_VOLUME 0 x687#define WM2200_DSP2LMIX_INPUT_2_SOURCE 0 x688#define WM2200_DSP2LMIX_INPUT_2_VOLUME 0 x689#define WM2200_DSP2LMIX_INPUT_3_SOURCE 0 x68A#define WM2200_DSP2LMIX_INPUT_3_VOLUME 0 x68B#define WM2200_DSP2LMIX_INPUT_4_SOURCE 0 x68C#define WM2200_DSP2LMIX_INPUT_4_VOLUME 0 x68D#define WM2200_DSP2RMIX_INPUT_1_SOURCE 0 x68E#define WM2200_DSP2RMIX_INPUT_1_VOLUME 0 x68F#define WM2200_DSP2RMIX_INPUT_2_SOURCE 0 x690#define WM2200_DSP2RMIX_INPUT_2_VOLUME 0 x691#define WM2200_DSP2RMIX_INPUT_3_SOURCE 0 x692#define WM2200_DSP2RMIX_INPUT_3_VOLUME 0 x693#define WM2200_DSP2RMIX_INPUT_4_SOURCE 0 x694#define WM2200_DSP2RMIX_INPUT_4_VOLUME 0 x695#define WM2200_DSP2AUX1MIX_INPUT_1_SOURCE 0 x696#define WM2200_DSP2AUX2MIX_INPUT_1_SOURCE 0 x697#define WM2200_DSP2AUX3MIX_INPUT_1_SOURCE 0 x698#define WM2200_DSP2AUX4MIX_INPUT_1_SOURCE 0 x699#define WM2200_DSP2AUX5MIX_INPUT_1_SOURCE 0 x69A#define WM2200_DSP2AUX6MIX_INPUT_1_SOURCE 0 x69B#define WM2200_GPIO_CTRL_1 0 x700#define WM2200_GPIO_CTRL_2 0 x701#define WM2200_GPIO_CTRL_3 0 x702#define WM2200_GPIO_CTRL_4 0 x703#define WM2200_ADPS1_IRQ0 0 x707#define WM2200_ADPS1_IRQ1 0 x708#define WM2200_MISC_PAD_CTRL_1 0 x709#define WM2200_INTERRUPT_STATUS_1 0 x800#define WM2200_INTERRUPT_STATUS_1_MASK 0 x801#define WM2200_INTERRUPT_STATUS_2 0 x802#define WM2200_INTERRUPT_RAW_STATUS_2 0 x803#define WM2200_INTERRUPT_STATUS_2_MASK 0 x804#define WM2200_INTERRUPT_CONTROL 0 x808#define WM2200_EQL_1 0 x900#define WM2200_EQL_2 0 x901#define WM2200_EQL_3 0 x902#define WM2200_EQL_4 0 x903#define WM2200_EQL_5 0 x904#define WM2200_EQL_6 0 x905#define WM2200_EQL_7 0 x906#define WM2200_EQL_8 0 x907#define WM2200_EQL_9 0 x908#define WM2200_EQL_10 0 x909#define WM2200_EQL_11 0 x90A#define WM2200_EQL_12 0 x90B#define WM2200_EQL_13 0 x90C#define WM2200_EQL_14 0 x90D#define WM2200_EQL_15 0 x90E#define WM2200_EQL_16 0 x90F#define WM2200_EQL_17 0 x910#define WM2200_EQL_18 0 x911#define WM2200_EQL_19 0 x912#define WM2200_EQL_20 0 x913#define WM2200_EQR_1 0 x916#define WM2200_EQR_2 0 x917#define WM2200_EQR_3 0 x918#define WM2200_EQR_4 0 x919#define WM2200_EQR_5 0 x91A#define WM2200_EQR_6 0 x91B#define WM2200_EQR_7 0 x91C#define WM2200_EQR_8 0 x91D#define WM2200_EQR_9 0 x91E#define WM2200_EQR_10 0 x91F#define WM2200_EQR_11 0 x920#define WM2200_EQR_12 0 x921#define WM2200_EQR_13 0 x922#define WM2200_EQR_14 0 x923#define WM2200_EQR_15 0 x924#define WM2200_EQR_16 0 x925#define WM2200_EQR_17 0 x926#define WM2200_EQR_18 0 x927#define WM2200_EQR_19 0 x928#define WM2200_EQR_20 0 x929#define WM2200_HPLPF1_1 0 x93E#define WM2200_HPLPF1_2 0 x93F#define WM2200_HPLPF2_1 0 x942#define WM2200_HPLPF2_2 0 x943#define WM2200_DSP1_CONTROL_1 0 xA00#define WM2200_DSP1_CONTROL_2 0 xA02#define WM2200_DSP1_CONTROL_3 0 xA03#define WM2200_DSP1_CONTROL_4 0 xA04#define WM2200_DSP1_CONTROL_5 0 xA06#define WM2200_DSP1_CONTROL_6 0 xA07#define WM2200_DSP1_CONTROL_7 0 xA08#define WM2200_DSP1_CONTROL_8 0 xA09#define WM2200_DSP1_CONTROL_9 0 xA0A#define WM2200_DSP1_CONTROL_10 0 xA0B#define WM2200_DSP1_CONTROL_11 0 xA0C#define WM2200_DSP1_CONTROL_12 0 xA0D#define WM2200_DSP1_CONTROL_13 0 xA0F#define WM2200_DSP1_CONTROL_14 0 xA10#define WM2200_DSP1_CONTROL_15 0 xA11#define WM2200_DSP1_CONTROL_16 0 xA12#define WM2200_DSP1_CONTROL_17 0 xA13#define WM2200_DSP1_CONTROL_18 0 xA14#define WM2200_DSP1_CONTROL_19 0 xA16#define WM2200_DSP1_CONTROL_20 0 xA17#define WM2200_DSP1_CONTROL_21 0 xA18#define WM2200_DSP1_CONTROL_22 0 xA1A#define WM2200_DSP1_CONTROL_23 0 xA1B#define WM2200_DSP1_CONTROL_24 0 xA1C#define WM2200_DSP1_CONTROL_25 0 xA1E#define WM2200_DSP1_CONTROL_26 0 xA20#define WM2200_DSP1_CONTROL_27 0 xA21#define WM2200_DSP1_CONTROL_28 0 xA22#define WM2200_DSP1_CONTROL_29 0 xA23#define WM2200_DSP1_CONTROL_30 0 xA24#define WM2200_DSP1_CONTROL_31 0 xA26#define WM2200_DSP2_CONTROL_1 0 xB00#define WM2200_DSP2_CONTROL_2 0 xB02#define WM2200_DSP2_CONTROL_3 0 xB03#define WM2200_DSP2_CONTROL_4 0 xB04#define WM2200_DSP2_CONTROL_5 0 xB06#define WM2200_DSP2_CONTROL_6 0 xB07#define WM2200_DSP2_CONTROL_7 0 xB08#define WM2200_DSP2_CONTROL_8 0 xB09#define WM2200_DSP2_CONTROL_9 0 xB0A#define WM2200_DSP2_CONTROL_10 0 xB0B#define WM2200_DSP2_CONTROL_11 0 xB0C#define WM2200_DSP2_CONTROL_12 0 xB0D#define WM2200_DSP2_CONTROL_13 0 xB0F#define WM2200_DSP2_CONTROL_14 0 xB10#define WM2200_DSP2_CONTROL_15 0 xB11#define WM2200_DSP2_CONTROL_16 0 xB12#define WM2200_DSP2_CONTROL_17 0 xB13#define WM2200_DSP2_CONTROL_18 0 xB14#define WM2200_DSP2_CONTROL_19 0 xB16#define WM2200_DSP2_CONTROL_20 0 xB17#define WM2200_DSP2_CONTROL_21 0 xB18#define WM2200_DSP2_CONTROL_22 0 xB1A#define WM2200_DSP2_CONTROL_23 0 xB1B#define WM2200_DSP2_CONTROL_24 0 xB1C#define WM2200_DSP2_CONTROL_25 0 xB1E#define WM2200_DSP2_CONTROL_26 0 xB20#define WM2200_DSP2_CONTROL_27 0 xB21#define WM2200_DSP2_CONTROL_28 0 xB22#define WM2200_DSP2_CONTROL_29 0 xB23#define WM2200_DSP2_CONTROL_30 0 xB24#define WM2200_DSP2_CONTROL_31 0 xB26#define WM2200_ANC_CTRL1 0 xD00#define WM2200_ANC_CTRL2 0 xD01#define WM2200_ANC_CTRL3 0 xD02#define WM2200_ANC_CTRL7 0 xD08#define WM2200_ANC_CTRL8 0 xD09#define WM2200_ANC_CTRL9 0 xD0A#define WM2200_ANC_CTRL10 0 xD0B#define WM2200_ANC_CTRL11 0 xD0C#define WM2200_ANC_CTRL12 0 xD0D#define WM2200_ANC_CTRL13 0 xD0E#define WM2200_ANC_CTRL14 0 xD0F#define WM2200_ANC_CTRL15 0 xD10#define WM2200_ANC_CTRL16 0 xD11#define WM2200_ANC_CTRL17 0 xD12#define WM2200_ANC_CTRL18 0 xD15#define WM2200_ANC_CTRL19 0 xD16#define WM2200_ANC_CTRL20 0 xD17#define WM2200_ANC_CTRL21 0 xD18#define WM2200_ANC_CTRL22 0 xD19#define WM2200_ANC_CTRL23 0 xD1A#define WM2200_ANC_CTRL24 0 xD1B#define WM2200_ANC_CTRL25 0 xD1C#define WM2200_ANC_CTRL26 0 xD1D#define WM2200_ANC_CTRL27 0 xD1E#define WM2200_ANC_CTRL28 0 xD1F#define WM2200_ANC_CTRL29 0 xD20#define WM2200_ANC_CTRL30 0 xD21#define WM2200_ANC_CTRL31 0 xD23#define WM2200_ANC_CTRL32 0 xD24#define WM2200_ANC_CTRL33 0 xD25#define WM2200_ANC_CTRL34 0 xD27#define WM2200_ANC_CTRL35 0 xD28#define WM2200_ANC_CTRL36 0 xD29#define WM2200_ANC_CTRL37 0 xD2A#define WM2200_ANC_CTRL38 0 xD2B#define WM2200_ANC_CTRL39 0 xD2C#define WM2200_ANC_CTRL40 0 xD2D#define WM2200_ANC_CTRL41 0 xD2E#define WM2200_ANC_CTRL42 0 xD2F#define WM2200_ANC_CTRL43 0 xD30#define WM2200_ANC_CTRL44 0 xD31#define WM2200_ANC_CTRL45 0 xD32#define WM2200_ANC_CTRL46 0 xD33#define WM2200_ANC_CTRL47 0 xD34#define WM2200_ANC_CTRL48 0 xD35#define WM2200_ANC_CTRL49 0 xD36#define WM2200_ANC_CTRL50 0 xD37#define WM2200_ANC_CTRL51 0 xD38#define WM2200_ANC_CTRL52 0 xD39#define WM2200_ANC_CTRL53 0 xD3A#define WM2200_ANC_CTRL54 0 xD3B#define WM2200_ANC_CTRL55 0 xD3C#define WM2200_ANC_CTRL56 0 xD3D#define WM2200_ANC_CTRL57 0 xD3E#define WM2200_ANC_CTRL58 0 xD3F#define WM2200_ANC_CTRL59 0 xD40#define WM2200_ANC_CTRL60 0 xD41#define WM2200_ANC_CTRL61 0 xD42#define WM2200_ANC_CTRL62 0 xD43#define WM2200_ANC_CTRL63 0 xD44#define WM2200_ANC_CTRL64 0 xD45#define WM2200_ANC_CTRL65 0 xD46#define WM2200_ANC_CTRL66 0 xD47#define WM2200_ANC_CTRL67 0 xD48#define WM2200_ANC_CTRL68 0 xD49#define WM2200_ANC_CTRL69 0 xD4A#define WM2200_ANC_CTRL70 0 xD4B#define WM2200_ANC_CTRL71 0 xD4C#define WM2200_ANC_CTRL72 0 xD4D#define WM2200_ANC_CTRL73 0 xD4E#define WM2200_ANC_CTRL74 0 xD4F#define WM2200_ANC_CTRL75 0 xD50#define WM2200_ANC_CTRL76 0 xD51#define WM2200_ANC_CTRL77 0 xD52#define WM2200_ANC_CTRL78 0 xD53#define WM2200_ANC_CTRL79 0 xD54#define WM2200_ANC_CTRL80 0 xD55#define WM2200_ANC_CTRL81 0 xD56#define WM2200_ANC_CTRL82 0 xD57#define WM2200_ANC_CTRL83 0 xD58#define WM2200_ANC_CTRL84 0 xD5B#define WM2200_ANC_CTRL85 0 xD5C#define WM2200_ANC_CTRL86 0 xD5F#define WM2200_ANC_CTRL87 0 xD60#define WM2200_ANC_CTRL88 0 xD61#define WM2200_ANC_CTRL89 0 xD62#define WM2200_ANC_CTRL90 0 xD63#define WM2200_ANC_CTRL91 0 xD64#define WM2200_ANC_CTRL92 0 xD65#define WM2200_ANC_CTRL93 0 xD66#define WM2200_ANC_CTRL94 0 xD67#define WM2200_ANC_CTRL95 0 xD68#define WM2200_ANC_CTRL96 0 xD69#define WM2200_DSP1_DM_0 0 x3000#define WM2200_DSP1_DM_1 0 x3001#define WM2200_DSP1_DM_2 0 x3002#define WM2200_DSP1_DM_3 0 x3003#define WM2200_DSP1_DM_2044 0 x37FC#define WM2200_DSP1_DM_2045 0 x37FD#define WM2200_DSP1_DM_2046 0 x37FE#define WM2200_DSP1_DM_2047 0 x37FF#define WM2200_DSP1_PM_0 0 x3800#define WM2200_DSP1_PM_1 0 x3801#define WM2200_DSP1_PM_2 0 x3802#define WM2200_DSP1_PM_3 0 x3803#define WM2200_DSP1_PM_4 0 x3804#define WM2200_DSP1_PM_5 0 x3805#define WM2200_DSP1_PM_762 0 x3AFA#define WM2200_DSP1_PM_763 0 x3AFB#define WM2200_DSP1_PM_764 0 x3AFC#define WM2200_DSP1_PM_765 0 x3AFD#define WM2200_DSP1_PM_766 0 x3AFE#define WM2200_DSP1_PM_767 0 x3AFF#define WM2200_DSP1_ZM_0 0 x3C00#define WM2200_DSP1_ZM_1 0 x3C01#define WM2200_DSP1_ZM_2 0 x3C02#define WM2200_DSP1_ZM_3 0 x3C03#define WM2200_DSP1_ZM_1020 0 x3FFC#define WM2200_DSP1_ZM_1021 0 x3FFD#define WM2200_DSP1_ZM_1022 0 x3FFE#define WM2200_DSP1_ZM_1023 0 x3FFF#define WM2200_DSP2_DM_0 0 x4000#define WM2200_DSP2_DM_1 0 x4001#define WM2200_DSP2_DM_2 0 x4002#define WM2200_DSP2_DM_3 0 x4003#define WM2200_DSP2_DM_2044 0 x47FC#define WM2200_DSP2_DM_2045 0 x47FD#define WM2200_DSP2_DM_2046 0 x47FE#define WM2200_DSP2_DM_2047 0 x47FF#define WM2200_DSP2_PM_0 0 x4800#define WM2200_DSP2_PM_1 0 x4801#define WM2200_DSP2_PM_2 0 x4802#define WM2200_DSP2_PM_3 0 x4803#define WM2200_DSP2_PM_4 0 x4804#define WM2200_DSP2_PM_5 0 x4805#define WM2200_DSP2_PM_762 0 x4AFA#define WM2200_DSP2_PM_763 0 x4AFB#define WM2200_DSP2_PM_764 0 x4AFC#define WM2200_DSP2_PM_765 0 x4AFD#define WM2200_DSP2_PM_766 0 x4AFE#define WM2200_DSP2_PM_767 0 x4AFF#define WM2200_DSP2_ZM_0 0 x4C00#define WM2200_DSP2_ZM_1 0 x4C01#define WM2200_DSP2_ZM_2 0 x4C02#define WM2200_DSP2_ZM_3 0 x4C03#define WM2200_DSP2_ZM_1020 0 x4FFC#define WM2200_DSP2_ZM_1021 0 x4FFD#define WM2200_DSP2_ZM_1022 0 x4FFE#define WM2200_DSP2_ZM_1023 0 x4FFF#define WM2200_REGISTER_COUNT 494 #define WM2200_MAX_REGISTER 0 x4FFF/* * Field Definitions . /* * R0 ( 0 x00 ) - software reset #define WM2200_SW_RESET_CHIP_ID1_MASK 0 xFFFF /* SW_RESET_CHIP_ID1 - [15:0] */ #define WM2200_SW_RESET_CHIP_ID1_SHIFT 0 /* SW_RESET_CHIP_ID1 - [15:0] */ #define WM2200_SW_RESET_CHIP_ID1_WIDTH 16 /* SW_RESET_CHIP_ID1 - [15:0] */ /* * R1 ( 0 x01 ) - Device Revision #define WM2200_DEVICE_REVISION_MASK 0 x000F /* DEVICE_REVISION - [3:0] */ #define WM2200_DEVICE_REVISION_SHIFT 0 /* DEVICE_REVISION - [3:0] */ #define WM2200_DEVICE_REVISION_WIDTH 4 /* DEVICE_REVISION - [3:0] */ /* * R11 ( 0 x0B ) - Tone Generator 1 #define WM2200_TONE_ENA 0 x0001 /* TONE_ENA */ #define WM2200_TONE_ENA_MASK 0 x0001 /* TONE_ENA */ #define WM2200_TONE_ENA_SHIFT 0 /* TONE_ENA */ #define WM2200_TONE_ENA_WIDTH 1 /* TONE_ENA */ /* * R258 ( 0 x102 ) - Clocking 3 #define WM2200_SYSCLK_FREQ_MASK 0 x0700 /* SYSCLK_FREQ - [10:8] */ #define WM2200_SYSCLK_FREQ_SHIFT 8 /* SYSCLK_FREQ - [10:8] */ #define WM2200_SYSCLK_FREQ_WIDTH 3 /* SYSCLK_FREQ - [10:8] */ #define WM2200_SYSCLK_ENA 0 x0040 /* SYSCLK_ENA */ #define WM2200_SYSCLK_ENA_MASK 0 x0040 /* SYSCLK_ENA */ #define WM2200_SYSCLK_ENA_SHIFT 6 /* SYSCLK_ENA */ #define WM2200_SYSCLK_ENA_WIDTH 1 /* SYSCLK_ENA */ #define WM2200_SYSCLK_SRC_MASK 0 x000F /* SYSCLK_SRC - [3:0] */ #define WM2200_SYSCLK_SRC_SHIFT 0 /* SYSCLK_SRC - [3:0] */ #define WM2200_SYSCLK_SRC_WIDTH 4 /* SYSCLK_SRC - [3:0] */ /* * R259 ( 0 x103 ) - Clocking 4 #define WM2200_SAMPLE_RATE_1_MASK 0 x001F /* SAMPLE_RATE_1 - [4:0] */ #define WM2200_SAMPLE_RATE_1_SHIFT 0 /* SAMPLE_RATE_1 - [4:0] */ #define WM2200_SAMPLE_RATE_1_WIDTH 5 /* SAMPLE_RATE_1 - [4:0] */ /* * R273 ( 0 x111 ) - FLL Control 1 #define WM2200_FLL_ENA 0 x0001 /* FLL_ENA */ #define WM2200_FLL_ENA_MASK 0 x0001 /* FLL_ENA */ #define WM2200_FLL_ENA_SHIFT 0 /* FLL_ENA */ #define WM2200_FLL_ENA_WIDTH 1 /* FLL_ENA */ /* * R274 ( 0 x112 ) - FLL Control 2 #define WM2200_FLL_OUTDIV_MASK 0 x3F00 /* FLL_OUTDIV - [13:8] */ #define WM2200_FLL_OUTDIV_SHIFT 8 /* FLL_OUTDIV - [13:8] */ #define WM2200_FLL_OUTDIV_WIDTH 6 /* FLL_OUTDIV - [13:8] */ #define WM2200_FLL_FRATIO_MASK 0 x0007 /* FLL_FRATIO - [2:0] */ #define WM2200_FLL_FRATIO_SHIFT 0 /* FLL_FRATIO - [2:0] */ #define WM2200_FLL_FRATIO_WIDTH 3 /* FLL_FRATIO - [2:0] */ /* * R275 ( 0 x113 ) - FLL Control 3 #define WM2200_FLL_FRACN_ENA 0 x0001 /* FLL_FRACN_ENA */ #define WM2200_FLL_FRACN_ENA_MASK 0 x0001 /* FLL_FRACN_ENA */ #define WM2200_FLL_FRACN_ENA_SHIFT 0 /* FLL_FRACN_ENA */ #define WM2200_FLL_FRACN_ENA_WIDTH 1 /* FLL_FRACN_ENA */ /* * R276 ( 0 x114 ) - FLL Control 4 #define WM2200_FLL_THETA_MASK 0 xFFFF /* FLL_THETA - [15:0] */ #define WM2200_FLL_THETA_SHIFT 0 /* FLL_THETA - [15:0] */ #define WM2200_FLL_THETA_WIDTH 16 /* FLL_THETA - [15:0] */ /* * R278 ( 0 x116 ) - FLL Control 6 #define WM2200_FLL_N_MASK 0 x03FF /* FLL_N - [9:0] */ #define WM2200_FLL_N_SHIFT 0 /* FLL_N - [9:0] */ #define WM2200_FLL_N_WIDTH 10 /* FLL_N - [9:0] */ /* * R279 ( 0 x117 ) - FLL Control 7 #define WM2200_FLL_CLK_REF_DIV_MASK 0 x0030 /* FLL_CLK_REF_DIV - [5:4] */ #define WM2200_FLL_CLK_REF_DIV_SHIFT 4 /* FLL_CLK_REF_DIV - [5:4] */ #define WM2200_FLL_CLK_REF_DIV_WIDTH 2 /* FLL_CLK_REF_DIV - [5:4] */ #define WM2200_FLL_CLK_REF_SRC_MASK 0 x0003 /* FLL_CLK_REF_SRC - [1:0] */ #define WM2200_FLL_CLK_REF_SRC_SHIFT 0 /* FLL_CLK_REF_SRC - [1:0] */ #define WM2200_FLL_CLK_REF_SRC_WIDTH 2 /* FLL_CLK_REF_SRC - [1:0] */ /* * R281 ( 0 x119 ) - FLL EFS 1 #define WM2200_FLL_LAMBDA_MASK 0 xFFFF /* FLL_LAMBDA - [15:0] */ #define WM2200_FLL_LAMBDA_SHIFT 0 /* FLL_LAMBDA - [15:0] */ #define WM2200_FLL_LAMBDA_WIDTH 16 /* FLL_LAMBDA - [15:0] */ /* * R282 ( 0 x11A ) - FLL EFS 2 #define WM2200_FLL_EFS_ENA 0 x0001 /* FLL_EFS_ENA */ #define WM2200_FLL_EFS_ENA_MASK 0 x0001 /* FLL_EFS_ENA */ #define WM2200_FLL_EFS_ENA_SHIFT 0 /* FLL_EFS_ENA */ #define WM2200_FLL_EFS_ENA_WIDTH 1 /* FLL_EFS_ENA */ /* * R512 ( 0 x200 ) - Mic Charge Pump 1 #define WM2200_CPMIC_BYPASS_MODE 0 x0020 /* CPMIC_BYPASS_MODE */ #define WM2200_CPMIC_BYPASS_MODE_MASK 0 x0020 /* CPMIC_BYPASS_MODE */ #define WM2200_CPMIC_BYPASS_MODE_SHIFT 5 /* CPMIC_BYPASS_MODE */ #define WM2200_CPMIC_BYPASS_MODE_WIDTH 1 /* CPMIC_BYPASS_MODE */ #define WM2200_CPMIC_ENA 0 x0001 /* CPMIC_ENA */ #define WM2200_CPMIC_ENA_MASK 0 x0001 /* CPMIC_ENA */ #define WM2200_CPMIC_ENA_SHIFT 0 /* CPMIC_ENA */ #define WM2200_CPMIC_ENA_WIDTH 1 /* CPMIC_ENA */ /* * R513 ( 0 x201 ) - Mic Charge Pump 2 #define WM2200_CPMIC_LDO_VSEL_OVERRIDE_MASK 0 xF800 /* CPMIC_LDO_VSEL_OVERRIDE - [15:11] */ #define WM2200_CPMIC_LDO_VSEL_OVERRIDE_SHIFT 11 /* CPMIC_LDO_VSEL_OVERRIDE - [15:11] */ #define WM2200_CPMIC_LDO_VSEL_OVERRIDE_WIDTH 5 /* CPMIC_LDO_VSEL_OVERRIDE - [15:11] */ /* * R514 ( 0 x202 ) - DM Charge Pump 1 #define WM2200_CPDM_ENA 0 x0001 /* CPDM_ENA */ #define WM2200_CPDM_ENA_MASK 0 x0001 /* CPDM_ENA */ #define WM2200_CPDM_ENA_SHIFT 0 /* CPDM_ENA */ #define WM2200_CPDM_ENA_WIDTH 1 /* CPDM_ENA */ /* * R524 ( 0 x20C ) - Mic Bias Ctrl 1 #define WM2200_MICB1_DISCH 0 x0040 /* MICB1_DISCH */ #define WM2200_MICB1_DISCH_MASK 0 x0040 /* MICB1_DISCH */ #define WM2200_MICB1_DISCH_SHIFT 6 /* MICB1_DISCH */ #define WM2200_MICB1_DISCH_WIDTH 1 /* MICB1_DISCH */ #define WM2200_MICB1_RATE 0 x0020 /* MICB1_RATE */ #define WM2200_MICB1_RATE_MASK 0 x0020 /* MICB1_RATE */ #define WM2200_MICB1_RATE_SHIFT 5 /* MICB1_RATE */ #define WM2200_MICB1_RATE_WIDTH 1 /* MICB1_RATE */ #define WM2200_MICB1_LVL_MASK 0 x001C /* MICB1_LVL - [4:2] */ #define WM2200_MICB1_LVL_SHIFT 2 /* MICB1_LVL - [4:2] */ #define WM2200_MICB1_LVL_WIDTH 3 /* MICB1_LVL - [4:2] */ #define WM2200_MICB1_MODE 0 x0002 /* MICB1_MODE */ #define WM2200_MICB1_MODE_MASK 0 x0002 /* MICB1_MODE */ #define WM2200_MICB1_MODE_SHIFT 1 /* MICB1_MODE */ #define WM2200_MICB1_MODE_WIDTH 1 /* MICB1_MODE */ #define WM2200_MICB1_ENA 0 x0001 /* MICB1_ENA */ #define WM2200_MICB1_ENA_MASK 0 x0001 /* MICB1_ENA */ #define WM2200_MICB1_ENA_SHIFT 0 /* MICB1_ENA */ #define WM2200_MICB1_ENA_WIDTH 1 /* MICB1_ENA */ /* * R525 ( 0 x20D ) - Mic Bias Ctrl 2 #define WM2200_MICB2_DISCH 0 x0040 /* MICB2_DISCH */ #define WM2200_MICB2_DISCH_MASK 0 x0040 /* MICB2_DISCH */ #define WM2200_MICB2_DISCH_SHIFT 6 /* MICB2_DISCH */ #define WM2200_MICB2_DISCH_WIDTH 1 /* MICB2_DISCH */ #define WM2200_MICB2_RATE 0 x0020 /* MICB2_RATE */ #define WM2200_MICB2_RATE_MASK 0 x0020 /* MICB2_RATE */ #define WM2200_MICB2_RATE_SHIFT 5 /* MICB2_RATE */ #define WM2200_MICB2_RATE_WIDTH 1 /* MICB2_RATE */ #define WM2200_MICB2_LVL_MASK 0 x001C /* MICB2_LVL - [4:2] */ #define WM2200_MICB2_LVL_SHIFT 2 /* MICB2_LVL - [4:2] */ #define WM2200_MICB2_LVL_WIDTH 3 /* MICB2_LVL - [4:2] */ #define WM2200_MICB2_MODE 0 x0002 /* MICB2_MODE */ #define WM2200_MICB2_MODE_MASK 0 x0002 /* MICB2_MODE */ #define WM2200_MICB2_MODE_SHIFT 1 /* MICB2_MODE */ #define WM2200_MICB2_MODE_WIDTH 1 /* MICB2_MODE */ #define WM2200_MICB2_ENA 0 x0001 /* MICB2_ENA */ #define WM2200_MICB2_ENA_MASK 0 x0001 /* MICB2_ENA */ #define WM2200_MICB2_ENA_SHIFT 0 /* MICB2_ENA */ #define WM2200_MICB2_ENA_WIDTH 1 /* MICB2_ENA */ /* * R527 ( 0 x20F ) - Ear Piece Ctrl 1 #define WM2200_EPD_LP_ENA 0 x4000 /* EPD_LP_ENA */ #define WM2200_EPD_LP_ENA_MASK 0 x4000 /* EPD_LP_ENA */ #define WM2200_EPD_LP_ENA_SHIFT 14 /* EPD_LP_ENA */ #define WM2200_EPD_LP_ENA_WIDTH 1 /* EPD_LP_ENA */ #define WM2200_EPD_OUTP_LP_ENA 0 x2000 /* EPD_OUTP_LP_ENA */ #define WM2200_EPD_OUTP_LP_ENA_MASK 0 x2000 /* EPD_OUTP_LP_ENA */ #define WM2200_EPD_OUTP_LP_ENA_SHIFT 13 /* EPD_OUTP_LP_ENA */ #define WM2200_EPD_OUTP_LP_ENA_WIDTH 1 /* EPD_OUTP_LP_ENA */ #define WM2200_EPD_RMV_SHRT_LP 0 x1000 /* EPD_RMV_SHRT_LP */ #define WM2200_EPD_RMV_SHRT_LP_MASK 0 x1000 /* EPD_RMV_SHRT_LP */ #define WM2200_EPD_RMV_SHRT_LP_SHIFT 12 /* EPD_RMV_SHRT_LP */ #define WM2200_EPD_RMV_SHRT_LP_WIDTH 1 /* EPD_RMV_SHRT_LP */ #define WM2200_EPD_LN_ENA 0 x0800 /* EPD_LN_ENA */ #define WM2200_EPD_LN_ENA_MASK 0 x0800 /* EPD_LN_ENA */ #define WM2200_EPD_LN_ENA_SHIFT 11 /* EPD_LN_ENA */ #define WM2200_EPD_LN_ENA_WIDTH 1 /* EPD_LN_ENA */ #define WM2200_EPD_OUTP_LN_ENA 0 x0400 /* EPD_OUTP_LN_ENA */ #define WM2200_EPD_OUTP_LN_ENA_MASK 0 x0400 /* EPD_OUTP_LN_ENA */ #define WM2200_EPD_OUTP_LN_ENA_SHIFT 10 /* EPD_OUTP_LN_ENA */ #define WM2200_EPD_OUTP_LN_ENA_WIDTH 1 /* EPD_OUTP_LN_ENA */ #define WM2200_EPD_RMV_SHRT_LN 0 x0200 /* EPD_RMV_SHRT_LN */ #define WM2200_EPD_RMV_SHRT_LN_MASK 0 x0200 /* EPD_RMV_SHRT_LN */ #define WM2200_EPD_RMV_SHRT_LN_SHIFT 9 /* EPD_RMV_SHRT_LN */ #define WM2200_EPD_RMV_SHRT_LN_WIDTH 1 /* EPD_RMV_SHRT_LN */ /* * R528 ( 0 x210 ) - Ear Piece Ctrl 2 #define WM2200_EPD_RP_ENA 0 x4000 /* EPD_RP_ENA */ #define WM2200_EPD_RP_ENA_MASK 0 x4000 /* EPD_RP_ENA */ #define WM2200_EPD_RP_ENA_SHIFT 14 /* EPD_RP_ENA */ #define WM2200_EPD_RP_ENA_WIDTH 1 /* EPD_RP_ENA */ #define WM2200_EPD_OUTP_RP_ENA 0 x2000 /* EPD_OUTP_RP_ENA */ #define WM2200_EPD_OUTP_RP_ENA_MASK 0 x2000 /* EPD_OUTP_RP_ENA */ #define WM2200_EPD_OUTP_RP_ENA_SHIFT 13 /* EPD_OUTP_RP_ENA */ #define WM2200_EPD_OUTP_RP_ENA_WIDTH 1 /* EPD_OUTP_RP_ENA */ #define WM2200_EPD_RMV_SHRT_RP 0 x1000 /* EPD_RMV_SHRT_RP */ #define WM2200_EPD_RMV_SHRT_RP_MASK 0 x1000 /* EPD_RMV_SHRT_RP */ #define WM2200_EPD_RMV_SHRT_RP_SHIFT 12 /* EPD_RMV_SHRT_RP */ #define WM2200_EPD_RMV_SHRT_RP_WIDTH 1 /* EPD_RMV_SHRT_RP */ #define WM2200_EPD_RN_ENA 0 x0800 /* EPD_RN_ENA */ #define WM2200_EPD_RN_ENA_MASK 0 x0800 /* EPD_RN_ENA */ #define WM2200_EPD_RN_ENA_SHIFT 11 /* EPD_RN_ENA */ #define WM2200_EPD_RN_ENA_WIDTH 1 /* EPD_RN_ENA */ #define WM2200_EPD_OUTP_RN_ENA 0 x0400 /* EPD_OUTP_RN_ENA */ #define WM2200_EPD_OUTP_RN_ENA_MASK 0 x0400 /* EPD_OUTP_RN_ENA */ #define WM2200_EPD_OUTP_RN_ENA_SHIFT 10 /* EPD_OUTP_RN_ENA */ #define WM2200_EPD_OUTP_RN_ENA_WIDTH 1 /* EPD_OUTP_RN_ENA */ #define WM2200_EPD_RMV_SHRT_RN 0 x0200 /* EPD_RMV_SHRT_RN */ #define WM2200_EPD_RMV_SHRT_RN_MASK 0 x0200 /* EPD_RMV_SHRT_RN */ #define WM2200_EPD_RMV_SHRT_RN_SHIFT 9 /* EPD_RMV_SHRT_RN */ #define WM2200_EPD_RMV_SHRT_RN_WIDTH 1 /* EPD_RMV_SHRT_RN */ /* * R769 ( 0 x301 ) - Input Enables #define WM2200_IN3L_ENA 0 x0020 /* IN3L_ENA */ #define WM2200_IN3L_ENA_MASK 0 x0020 /* IN3L_ENA */ #define WM2200_IN3L_ENA_SHIFT 5 /* IN3L_ENA */ #define WM2200_IN3L_ENA_WIDTH 1 /* IN3L_ENA */ #define WM2200_IN3R_ENA 0 x0010 /* IN3R_ENA */ #define WM2200_IN3R_ENA_MASK 0 x0010 /* IN3R_ENA */ #define WM2200_IN3R_ENA_SHIFT 4 /* IN3R_ENA */ #define WM2200_IN3R_ENA_WIDTH 1 /* IN3R_ENA */ #define WM2200_IN2L_ENA 0 x0008 /* IN2L_ENA */ #define WM2200_IN2L_ENA_MASK 0 x0008 /* IN2L_ENA */ #define WM2200_IN2L_ENA_SHIFT 3 /* IN2L_ENA */ #define WM2200_IN2L_ENA_WIDTH 1 /* IN2L_ENA */ #define WM2200_IN2R_ENA 0 x0004 /* IN2R_ENA */ #define WM2200_IN2R_ENA_MASK 0 x0004 /* IN2R_ENA */ #define WM2200_IN2R_ENA_SHIFT 2 /* IN2R_ENA */ #define WM2200_IN2R_ENA_WIDTH 1 /* IN2R_ENA */ #define WM2200_IN1L_ENA 0 x0002 /* IN1L_ENA */ #define WM2200_IN1L_ENA_MASK 0 x0002 /* IN1L_ENA */ #define WM2200_IN1L_ENA_SHIFT 1 /* IN1L_ENA */ #define WM2200_IN1L_ENA_WIDTH 1 /* IN1L_ENA */ #define WM2200_IN1R_ENA 0 x0001 /* IN1R_ENA */ #define WM2200_IN1R_ENA_MASK 0 x0001 /* IN1R_ENA */ #define WM2200_IN1R_ENA_SHIFT 0 /* IN1R_ENA */ #define WM2200_IN1R_ENA_WIDTH 1 /* IN1R_ENA */ /* * R770 ( 0 x302 ) - IN1L Control #define WM2200_IN1_OSR 0 x2000 /* IN1_OSR */ #define WM2200_IN1_OSR_MASK 0 x2000 /* IN1_OSR */ #define WM2200_IN1_OSR_SHIFT 13 /* IN1_OSR */ #define WM2200_IN1_OSR_WIDTH 1 /* IN1_OSR */ #define WM2200_IN1_DMIC_SUP_MASK 0 x1800 /* IN1_DMIC_SUP - [12:11] */ #define WM2200_IN1_DMIC_SUP_SHIFT 11 /* IN1_DMIC_SUP - [12:11] */ #define WM2200_IN1_DMIC_SUP_WIDTH 2 /* IN1_DMIC_SUP - [12:11] */ #define WM2200_IN1_MODE_MASK 0 x0600 /* IN1_MODE - [10:9] */ #define WM2200_IN1_MODE_SHIFT 9 /* IN1_MODE - [10:9] */ #define WM2200_IN1_MODE_WIDTH 2 /* IN1_MODE - [10:9] */ #define WM2200_IN1L_PGA_VOL_MASK 0 x00FE /* IN1L_PGA_VOL - [7:1] */ #define WM2200_IN1L_PGA_VOL_SHIFT 1 /* IN1L_PGA_VOL - [7:1] */ #define WM2200_IN1L_PGA_VOL_WIDTH 7 /* IN1L_PGA_VOL - [7:1] */ /* * R771 ( 0 x303 ) - IN1R Control #define WM2200_IN1R_PGA_VOL_MASK 0 x00FE /* IN1R_PGA_VOL - [7:1] */ #define WM2200_IN1R_PGA_VOL_SHIFT 1 /* IN1R_PGA_VOL - [7:1] */ #define WM2200_IN1R_PGA_VOL_WIDTH 7 /* IN1R_PGA_VOL - [7:1] */ /* * R772 ( 0 x304 ) - IN2L Control #define WM2200_IN2_OSR 0 x2000 /* IN2_OSR */ #define WM2200_IN2_OSR_MASK 0 x2000 /* IN2_OSR */ #define WM2200_IN2_OSR_SHIFT 13 /* IN2_OSR */ #define WM2200_IN2_OSR_WIDTH 1 /* IN2_OSR */ #define WM2200_IN2_DMIC_SUP_MASK 0 x1800 /* IN2_DMIC_SUP - [12:11] */ #define WM2200_IN2_DMIC_SUP_SHIFT 11 /* IN2_DMIC_SUP - [12:11] */ #define WM2200_IN2_DMIC_SUP_WIDTH 2 /* IN2_DMIC_SUP - [12:11] */ #define WM2200_IN2_MODE_MASK 0 x0600 /* IN2_MODE - [10:9] */ #define WM2200_IN2_MODE_SHIFT 9 /* IN2_MODE - [10:9] */ #define WM2200_IN2_MODE_WIDTH 2 /* IN2_MODE - [10:9] */ #define WM2200_IN2L_PGA_VOL_MASK 0 x00FE /* IN2L_PGA_VOL - [7:1] */ #define WM2200_IN2L_PGA_VOL_SHIFT 1 /* IN2L_PGA_VOL - [7:1] */ #define WM2200_IN2L_PGA_VOL_WIDTH 7 /* IN2L_PGA_VOL - [7:1] */ /* * R773 ( 0 x305 ) - IN2R Control #define WM2200_IN2R_PGA_VOL_MASK 0 x00FE /* IN2R_PGA_VOL - [7:1] */ #define WM2200_IN2R_PGA_VOL_SHIFT 1 /* IN2R_PGA_VOL - [7:1] */ #define WM2200_IN2R_PGA_VOL_WIDTH 7 /* IN2R_PGA_VOL - [7:1] */ /* * R774 ( 0 x306 ) - IN3L Control #define WM2200_IN3_OSR 0 x2000 /* IN3_OSR */ #define WM2200_IN3_OSR_MASK 0 x2000 /* IN3_OSR */ #define WM2200_IN3_OSR_SHIFT 13 /* IN3_OSR */ #define WM2200_IN3_OSR_WIDTH 1 /* IN3_OSR */ #define WM2200_IN3_DMIC_SUP_MASK 0 x1800 /* IN3_DMIC_SUP - [12:11] */ #define WM2200_IN3_DMIC_SUP_SHIFT 11 /* IN3_DMIC_SUP - [12:11] */ #define WM2200_IN3_DMIC_SUP_WIDTH 2 /* IN3_DMIC_SUP - [12:11] */ #define WM2200_IN3_MODE_MASK 0 x0600 /* IN3_MODE - [10:9] */ #define WM2200_IN3_MODE_SHIFT 9 /* IN3_MODE - [10:9] */ #define WM2200_IN3_MODE_WIDTH 2 /* IN3_MODE - [10:9] */ #define WM2200_IN3L_PGA_VOL_MASK 0 x00FE /* IN3L_PGA_VOL - [7:1] */ #define WM2200_IN3L_PGA_VOL_SHIFT 1 /* IN3L_PGA_VOL - [7:1] */ #define WM2200_IN3L_PGA_VOL_WIDTH 7 /* IN3L_PGA_VOL - [7:1] */ /* * R775 ( 0 x307 ) - IN3R Control #define WM2200_IN3R_PGA_VOL_MASK 0 x00FE /* IN3R_PGA_VOL - [7:1] */ #define WM2200_IN3R_PGA_VOL_SHIFT 1 /* IN3R_PGA_VOL - [7:1] */ #define WM2200_IN3R_PGA_VOL_WIDTH 7 /* IN3R_PGA_VOL - [7:1] */ /* * R778 ( 0 x30A ) - RXANC_SRC #define WM2200_IN_RXANC_SEL_MASK 0 x0007 /* IN_RXANC_SEL - [2:0] */ #define WM2200_IN_RXANC_SEL_SHIFT 0 /* IN_RXANC_SEL - [2:0] */ #define WM2200_IN_RXANC_SEL_WIDTH 3 /* IN_RXANC_SEL - [2:0] */ /* * R779 ( 0 x30B ) - Input Volume Ramp #define WM2200_IN_VD_RAMP_MASK 0 x0070 /* IN_VD_RAMP - [6:4] */ #define WM2200_IN_VD_RAMP_SHIFT 4 /* IN_VD_RAMP - [6:4] */ #define WM2200_IN_VD_RAMP_WIDTH 3 /* IN_VD_RAMP - [6:4] */ #define WM2200_IN_VI_RAMP_MASK 0 x0007 /* IN_VI_RAMP - [2:0] */ #define WM2200_IN_VI_RAMP_SHIFT 0 /* IN_VI_RAMP - [2:0] */ #define WM2200_IN_VI_RAMP_WIDTH 3 /* IN_VI_RAMP - [2:0] */ /* * R780 ( 0 x30C ) - ADC Digital Volume 1 L * / # define WM2200_IN_VU 0 x0200 #define WM2200_IN_VU 0x0200 /* IN_VU */ #define WM2200_IN_VU_MASK 0 x0200 /* IN_VU */ #define WM2200_IN_VU_SHIFT 9 /* IN_VU */ #define WM2200_IN_VU_WIDTH 1 /* IN_VU */ #define WM2200_IN1L_MUTE 0 x0100 /* IN1L_MUTE */ #define WM2200_IN1L_MUTE_MASK 0 x0100 /* IN1L_MUTE */ #define WM2200_IN1L_MUTE_SHIFT 8 /* IN1L_MUTE */ #define WM2200_IN1L_MUTE_WIDTH 1 /* IN1L_MUTE */ #define WM2200_IN1L_DIG_VOL_MASK 0 x00FF /* IN1L_DIG_VOL - [7:0] */ #define WM2200_IN1L_DIG_VOL_SHIFT 0 /* IN1L_DIG_VOL - [7:0] */ #define WM2200_IN1L_DIG_VOL_WIDTH 8 /* IN1L_DIG_VOL - [7:0] */ /* * R781 ( 0 x30D ) - ADC Digital Volume 1 R #define WM2200_IN_VU 0 x0200 /* IN_VU */ #define WM2200_IN_VU_MASK 0 x0200 /* IN_VU */ #define WM2200_IN_VU_SHIFT 9 /* IN_VU */ #define WM2200_IN_VU_WIDTH 1 /* IN_VU */ #define WM2200_IN1R_MUTE 0 x0100 /* IN1R_MUTE */ #define WM2200_IN1R_MUTE_MASK 0 x0100 /* IN1R_MUTE */ #define WM2200_IN1R_MUTE_SHIFT 8 /* IN1R_MUTE */ #define WM2200_IN1R_MUTE_WIDTH 1 /* IN1R_MUTE */ #define WM2200_IN1R_DIG_VOL_MASK 0 x00FF /* IN1R_DIG_VOL - [7:0] */ #define WM2200_IN1R_DIG_VOL_SHIFT 0 /* IN1R_DIG_VOL - [7:0] */ #define WM2200_IN1R_DIG_VOL_WIDTH 8 /* IN1R_DIG_VOL - [7:0] */ /* * R782 ( 0 x30E ) - ADC Digital Volume 2 L #define WM2200_IN_VU 0 x0200 /* IN_VU */ #define WM2200_IN_VU_MASK 0 x0200 /* IN_VU */ #define WM2200_IN_VU_SHIFT 9 /* IN_VU */ #define WM2200_IN_VU_WIDTH 1 /* IN_VU */ #define WM2200_IN2L_MUTE 0 x0100 /* IN2L_MUTE */ #define WM2200_IN2L_MUTE_MASK 0 x0100 /* IN2L_MUTE */ #define WM2200_IN2L_MUTE_SHIFT 8 /* IN2L_MUTE */ #define WM2200_IN2L_MUTE_WIDTH 1 /* IN2L_MUTE */ #define WM2200_IN2L_DIG_VOL_MASK 0 x00FF /* IN2L_DIG_VOL - [7:0] */ #define WM2200_IN2L_DIG_VOL_SHIFT 0 /* IN2L_DIG_VOL - [7:0] */ #define WM2200_IN2L_DIG_VOL_WIDTH 8 /* IN2L_DIG_VOL - [7:0] */ /* * R783 ( 0 x30F ) - ADC Digital Volume 2 R #define WM2200_IN_VU 0 x0200 /* IN_VU */ #define WM2200_IN_VU_MASK 0 x0200 /* IN_VU */ #define WM2200_IN_VU_SHIFT 9 /* IN_VU */ #define WM2200_IN_VU_WIDTH 1 /* IN_VU */ #define WM2200_IN2R_MUTE 0 x0100 /* IN2R_MUTE */ #define WM2200_IN2R_MUTE_MASK 0 x0100 /* IN2R_MUTE */ #define WM2200_IN2R_MUTE_SHIFT 8 /* IN2R_MUTE */ #define WM2200_IN2R_MUTE_WIDTH 1 /* IN2R_MUTE */ #define WM2200_IN2R_DIG_VOL_MASK 0 x00FF /* IN2R_DIG_VOL - [7:0] */ #define WM2200_IN2R_DIG_VOL_SHIFT 0 /* IN2R_DIG_VOL - [7:0] */ #define WM2200_IN2R_DIG_VOL_WIDTH 8 /* IN2R_DIG_VOL - [7:0] */ /* * R784 ( 0 x310 ) - ADC Digital Volume 3 L #define WM2200_IN_VU 0 x0200 /* IN_VU */ #define WM2200_IN_VU_MASK 0 x0200 /* IN_VU */ #define WM2200_IN_VU_SHIFT 9 /* IN_VU */ #define WM2200_IN_VU_WIDTH 1 /* IN_VU */ #define WM2200_IN3L_MUTE 0 x0100 /* IN3L_MUTE */ #define WM2200_IN3L_MUTE_MASK 0 x0100 /* IN3L_MUTE */ #define WM2200_IN3L_MUTE_SHIFT 8 /* IN3L_MUTE */ #define WM2200_IN3L_MUTE_WIDTH 1 /* IN3L_MUTE */ #define WM2200_IN3L_DIG_VOL_MASK 0 x00FF /* IN3L_DIG_VOL - [7:0] */ #define WM2200_IN3L_DIG_VOL_SHIFT 0 /* IN3L_DIG_VOL - [7:0] */ #define WM2200_IN3L_DIG_VOL_WIDTH 8 /* IN3L_DIG_VOL - [7:0] */ /* * R785 ( 0 x311 ) - ADC Digital Volume 3 R #define WM2200_IN_VU 0 x0200 /* IN_VU */ #define WM2200_IN_VU_MASK 0 x0200 /* IN_VU */ #define WM2200_IN_VU_SHIFT 9 /* IN_VU */ #define WM2200_IN_VU_WIDTH 1 /* IN_VU */ #define WM2200_IN3R_MUTE 0 x0100 /* IN3R_MUTE */ #define WM2200_IN3R_MUTE_MASK 0 x0100 /* IN3R_MUTE */ #define WM2200_IN3R_MUTE_SHIFT 8 /* IN3R_MUTE */ #define WM2200_IN3R_MUTE_WIDTH 1 /* IN3R_MUTE */ #define WM2200_IN3R_DIG_VOL_MASK 0 x00FF /* IN3R_DIG_VOL - [7:0] */ #define WM2200_IN3R_DIG_VOL_SHIFT 0 /* IN3R_DIG_VOL - [7:0] */ #define WM2200_IN3R_DIG_VOL_WIDTH 8 /* IN3R_DIG_VOL - [7:0] */ /* * R1024 ( 0 x400 ) - Output Enables #define WM2200_OUT2L_ENA 0 x0008 /* OUT2L_ENA */ #define WM2200_OUT2L_ENA_MASK 0 x0008 /* OUT2L_ENA */ #define WM2200_OUT2L_ENA_SHIFT 3 /* OUT2L_ENA */ #define WM2200_OUT2L_ENA_WIDTH 1 /* OUT2L_ENA */ #define WM2200_OUT2R_ENA 0 x0004 /* OUT2R_ENA */ #define WM2200_OUT2R_ENA_MASK 0 x0004 /* OUT2R_ENA */ #define WM2200_OUT2R_ENA_SHIFT 2 /* OUT2R_ENA */ #define WM2200_OUT2R_ENA_WIDTH 1 /* OUT2R_ENA */ #define WM2200_OUT1L_ENA 0 x0002 /* OUT1L_ENA */ #define WM2200_OUT1L_ENA_MASK 0 x0002 /* OUT1L_ENA */ #define WM2200_OUT1L_ENA_SHIFT 1 /* OUT1L_ENA */ #define WM2200_OUT1L_ENA_WIDTH 1 /* OUT1L_ENA */ #define WM2200_OUT1R_ENA 0 x0001 /* OUT1R_ENA */ #define WM2200_OUT1R_ENA_MASK 0 x0001 /* OUT1R_ENA */ #define WM2200_OUT1R_ENA_SHIFT 0 /* OUT1R_ENA */ #define WM2200_OUT1R_ENA_WIDTH 1 /* OUT1R_ENA */ /* * R1025 ( 0 x401 ) - DAC Volume Limit 1 L #define WM2200_OUT1_OSR 0 x2000 /* OUT1_OSR */ #define WM2200_OUT1_OSR_MASK 0 x2000 /* OUT1_OSR */ #define WM2200_OUT1_OSR_SHIFT 13 /* OUT1_OSR */ #define WM2200_OUT1_OSR_WIDTH 1 /* OUT1_OSR */ #define WM2200_OUT1L_ANC_SRC 0 x0800 /* OUT1L_ANC_SRC */ #define WM2200_OUT1L_ANC_SRC_MASK 0 x0800 /* OUT1L_ANC_SRC */ #define WM2200_OUT1L_ANC_SRC_SHIFT 11 /* OUT1L_ANC_SRC */ #define WM2200_OUT1L_ANC_SRC_WIDTH 1 /* OUT1L_ANC_SRC */ #define WM2200_OUT1L_PGA_VOL_MASK 0 x00FE /* OUT1L_PGA_VOL - [7:1] */ #define WM2200_OUT1L_PGA_VOL_SHIFT 1 /* OUT1L_PGA_VOL - [7:1] */ #define WM2200_OUT1L_PGA_VOL_WIDTH 7 /* OUT1L_PGA_VOL - [7:1] */ /* * R1026 ( 0 x402 ) - DAC Volume Limit 1 R #define WM2200_OUT1R_ANC_SRC 0 x0800 /* OUT1R_ANC_SRC */ #define WM2200_OUT1R_ANC_SRC_MASK 0 x0800 /* OUT1R_ANC_SRC */ #define WM2200_OUT1R_ANC_SRC_SHIFT 11 /* OUT1R_ANC_SRC */ #define WM2200_OUT1R_ANC_SRC_WIDTH 1 /* OUT1R_ANC_SRC */ #define WM2200_OUT1R_PGA_VOL_MASK 0 x00FE /* OUT1R_PGA_VOL - [7:1] */ #define WM2200_OUT1R_PGA_VOL_SHIFT 1 /* OUT1R_PGA_VOL - [7:1] */ #define WM2200_OUT1R_PGA_VOL_WIDTH 7 /* OUT1R_PGA_VOL - [7:1] */ /* * R1027 ( 0 x403 ) - DAC Volume Limit 2 L #define WM2200_OUT2_OSR 0 x2000 /* OUT2_OSR */ #define WM2200_OUT2_OSR_MASK 0 x2000 /* OUT2_OSR */ #define WM2200_OUT2_OSR_SHIFT 13 /* OUT2_OSR */ #define WM2200_OUT2_OSR_WIDTH 1 /* OUT2_OSR */ #define WM2200_OUT2L_ANC_SRC 0 x0800 /* OUT2L_ANC_SRC */ #define WM2200_OUT2L_ANC_SRC_MASK 0 x0800 /* OUT2L_ANC_SRC */ #define WM2200_OUT2L_ANC_SRC_SHIFT 11 /* OUT2L_ANC_SRC */ #define WM2200_OUT2L_ANC_SRC_WIDTH 1 /* OUT2L_ANC_SRC */ /* * R1028 ( 0 x404 ) - DAC Volume Limit 2 R #define WM2200_OUT2R_ANC_SRC 0 x0800 /* OUT2R_ANC_SRC */ #define WM2200_OUT2R_ANC_SRC_MASK 0 x0800 /* OUT2R_ANC_SRC */ #define WM2200_OUT2R_ANC_SRC_SHIFT 11 /* OUT2R_ANC_SRC */ #define WM2200_OUT2R_ANC_SRC_WIDTH 1 /* OUT2R_ANC_SRC */ /* * R1033 ( 0 x409 ) - DAC AEC Control 1 #define WM2200_AEC_LOOPBACK_ENA 0 x0004 /* AEC_LOOPBACK_ENA */ #define WM2200_AEC_LOOPBACK_ENA_MASK 0 x0004 /* AEC_LOOPBACK_ENA */ #define WM2200_AEC_LOOPBACK_ENA_SHIFT 2 /* AEC_LOOPBACK_ENA */ #define WM2200_AEC_LOOPBACK_ENA_WIDTH 1 /* AEC_LOOPBACK_ENA */ #define WM2200_AEC_LOOPBACK_SRC_MASK 0 x0003 /* AEC_LOOPBACK_SRC - [1:0] */ #define WM2200_AEC_LOOPBACK_SRC_SHIFT 0 /* AEC_LOOPBACK_SRC - [1:0] */ #define WM2200_AEC_LOOPBACK_SRC_WIDTH 2 /* AEC_LOOPBACK_SRC - [1:0] */ /* * R1034 ( 0 x40A ) - Output Volume Ramp #define WM2200_OUT_VD_RAMP_MASK 0 x0070 /* OUT_VD_RAMP - [6:4] */ #define WM2200_OUT_VD_RAMP_SHIFT 4 /* OUT_VD_RAMP - [6:4] */ #define WM2200_OUT_VD_RAMP_WIDTH 3 /* OUT_VD_RAMP - [6:4] */ #define WM2200_OUT_VI_RAMP_MASK 0 x0007 /* OUT_VI_RAMP - [2:0] */ #define WM2200_OUT_VI_RAMP_SHIFT 0 /* OUT_VI_RAMP - [2:0] */ #define WM2200_OUT_VI_RAMP_WIDTH 3 /* OUT_VI_RAMP - [2:0] */ /* * R1035 ( 0 x40B ) - DAC Digital Volume 1 L #define WM2200_OUT_VU 0 x0200 /* OUT_VU */ #define WM2200_OUT_VU_MASK 0 x0200 /* OUT_VU */ #define WM2200_OUT_VU_SHIFT 9 /* OUT_VU */ #define WM2200_OUT_VU_WIDTH 1 /* OUT_VU */ #define WM2200_OUT1L_MUTE 0 x0100 /* OUT1L_MUTE */ #define WM2200_OUT1L_MUTE_MASK 0 x0100 /* OUT1L_MUTE */ #define WM2200_OUT1L_MUTE_SHIFT 8 /* OUT1L_MUTE */ #define WM2200_OUT1L_MUTE_WIDTH 1 /* OUT1L_MUTE */ #define WM2200_OUT1L_VOL_MASK 0 x00FF /* OUT1L_VOL - [7:0] */ #define WM2200_OUT1L_VOL_SHIFT 0 /* OUT1L_VOL - [7:0] */ #define WM2200_OUT1L_VOL_WIDTH 8 /* OUT1L_VOL - [7:0] */ /* * R1036 ( 0 x40C ) - DAC Digital Volume 1 R #define WM2200_OUT_VU 0 x0200 /* OUT_VU */ #define WM2200_OUT_VU_MASK 0 x0200 /* OUT_VU */ #define WM2200_OUT_VU_SHIFT 9 /* OUT_VU */ #define WM2200_OUT_VU_WIDTH 1 /* OUT_VU */ #define WM2200_OUT1R_MUTE 0 x0100 /* OUT1R_MUTE */ #define WM2200_OUT1R_MUTE_MASK 0 x0100 /* OUT1R_MUTE */ #define WM2200_OUT1R_MUTE_SHIFT 8 /* OUT1R_MUTE */ #define WM2200_OUT1R_MUTE_WIDTH 1 /* OUT1R_MUTE */ #define WM2200_OUT1R_VOL_MASK 0 x00FF /* OUT1R_VOL - [7:0] */ #define WM2200_OUT1R_VOL_SHIFT 0 /* OUT1R_VOL - [7:0] */ #define WM2200_OUT1R_VOL_WIDTH 8 /* OUT1R_VOL - [7:0] */ /* * R1037 ( 0 x40D ) - DAC Digital Volume 2 L #define WM2200_OUT_VU 0 x0200 /* OUT_VU */ #define WM2200_OUT_VU_MASK 0 x0200 /* OUT_VU */ #define WM2200_OUT_VU_SHIFT 9 /* OUT_VU */ #define WM2200_OUT_VU_WIDTH 1 /* OUT_VU */ #define WM2200_OUT2L_MUTE 0 x0100 /* OUT2L_MUTE */ #define WM2200_OUT2L_MUTE_MASK 0 x0100 /* OUT2L_MUTE */ #define WM2200_OUT2L_MUTE_SHIFT 8 /* OUT2L_MUTE */ #define WM2200_OUT2L_MUTE_WIDTH 1 /* OUT2L_MUTE */ #define WM2200_OUT2L_VOL_MASK 0 x00FF /* OUT2L_VOL - [7:0] */ #define WM2200_OUT2L_VOL_SHIFT 0 /* OUT2L_VOL - [7:0] */ #define WM2200_OUT2L_VOL_WIDTH 8 /* OUT2L_VOL - [7:0] */ /* * R1038 ( 0 x40E ) - DAC Digital Volume 2 R #define WM2200_OUT_VU 0 x0200 /* OUT_VU */ #define WM2200_OUT_VU_MASK 0 x0200 /* OUT_VU */ #define WM2200_OUT_VU_SHIFT 9 /* OUT_VU */ #define WM2200_OUT_VU_WIDTH 1 /* OUT_VU */ #define WM2200_OUT2R_MUTE 0 x0100 /* OUT2R_MUTE */ #define WM2200_OUT2R_MUTE_MASK 0 x0100 /* OUT2R_MUTE */ #define WM2200_OUT2R_MUTE_SHIFT 8 /* OUT2R_MUTE */ #define WM2200_OUT2R_MUTE_WIDTH 1 /* OUT2R_MUTE */ #define WM2200_OUT2R_VOL_MASK 0 x00FF /* OUT2R_VOL - [7:0] */ #define WM2200_OUT2R_VOL_SHIFT 0 /* OUT2R_VOL - [7:0] */ #define WM2200_OUT2R_VOL_WIDTH 8 /* OUT2R_VOL - [7:0] */ /* * R1047 ( 0 x417 ) - PDM 1 #define WM2200_SPK1R_MUTE 0 x2000 /* SPK1R_MUTE */ #define WM2200_SPK1R_MUTE_MASK 0 x2000 /* SPK1R_MUTE */ #define WM2200_SPK1R_MUTE_SHIFT 13 /* SPK1R_MUTE */ #define WM2200_SPK1R_MUTE_WIDTH 1 /* SPK1R_MUTE */ #define WM2200_SPK1L_MUTE 0 x1000 /* SPK1L_MUTE */ #define WM2200_SPK1L_MUTE_MASK 0 x1000 /* SPK1L_MUTE */ #define WM2200_SPK1L_MUTE_SHIFT 12 /* SPK1L_MUTE */ #define WM2200_SPK1L_MUTE_WIDTH 1 /* SPK1L_MUTE */ #define WM2200_SPK1_MUTE_ENDIAN 0 x0100 /* SPK1_MUTE_ENDIAN */ #define WM2200_SPK1_MUTE_ENDIAN_MASK 0 x0100 /* SPK1_MUTE_ENDIAN */ #define WM2200_SPK1_MUTE_ENDIAN_SHIFT 8 /* SPK1_MUTE_ENDIAN */ #define WM2200_SPK1_MUTE_ENDIAN_WIDTH 1 /* SPK1_MUTE_ENDIAN */ #define WM2200_SPK1_MUTE_SEQL_MASK 0 x00FF /* SPK1_MUTE_SEQL - [7:0] */ #define WM2200_SPK1_MUTE_SEQL_SHIFT 0 /* SPK1_MUTE_SEQL - [7:0] */ #define WM2200_SPK1_MUTE_SEQL_WIDTH 8 /* SPK1_MUTE_SEQL - [7:0] */ /* * R1048 ( 0 x418 ) - PDM 2 #define WM2200_SPK1_FMT 0 x0001 /* SPK1_FMT */ #define WM2200_SPK1_FMT_MASK 0 x0001 /* SPK1_FMT */ #define WM2200_SPK1_FMT_SHIFT 0 /* SPK1_FMT */ #define WM2200_SPK1_FMT_WIDTH 1 /* SPK1_FMT */ /* * R1280 ( 0 x500 ) - Audio IF 1 _ 1 #define WM2200_AIF1_BCLK_INV 0 x0040 /* AIF1_BCLK_INV */ #define WM2200_AIF1_BCLK_INV_MASK 0 x0040 /* AIF1_BCLK_INV */ #define WM2200_AIF1_BCLK_INV_SHIFT 6 /* AIF1_BCLK_INV */ #define WM2200_AIF1_BCLK_INV_WIDTH 1 /* AIF1_BCLK_INV */ #define WM2200_AIF1_BCLK_FRC 0 x0020 /* AIF1_BCLK_FRC */ #define WM2200_AIF1_BCLK_FRC_MASK 0 x0020 /* AIF1_BCLK_FRC */ #define WM2200_AIF1_BCLK_FRC_SHIFT 5 /* AIF1_BCLK_FRC */ #define WM2200_AIF1_BCLK_FRC_WIDTH 1 /* AIF1_BCLK_FRC */ #define WM2200_AIF1_BCLK_MSTR 0 x0010 /* AIF1_BCLK_MSTR */ #define WM2200_AIF1_BCLK_MSTR_MASK 0 x0010 /* AIF1_BCLK_MSTR */ #define WM2200_AIF1_BCLK_MSTR_SHIFT 4 /* AIF1_BCLK_MSTR */ #define WM2200_AIF1_BCLK_MSTR_WIDTH 1 /* AIF1_BCLK_MSTR */ #define WM2200_AIF1_BCLK_DIV_MASK 0 x000F /* AIF1_BCLK_DIV - [3:0] */ #define WM2200_AIF1_BCLK_DIV_SHIFT 0 /* AIF1_BCLK_DIV - [3:0] */ #define WM2200_AIF1_BCLK_DIV_WIDTH 4 /* AIF1_BCLK_DIV - [3:0] */ /* * R1281 ( 0 x501 ) - Audio IF 1 _ 2 #define WM2200_AIF1TX_DAT_TRI 0 x0020 /* AIF1TX_DAT_TRI */ #define WM2200_AIF1TX_DAT_TRI_MASK 0 x0020 /* AIF1TX_DAT_TRI */ #define WM2200_AIF1TX_DAT_TRI_SHIFT 5 /* AIF1TX_DAT_TRI */ #define WM2200_AIF1TX_DAT_TRI_WIDTH 1 /* AIF1TX_DAT_TRI */ #define WM2200_AIF1TX_LRCLK_SRC 0 x0008 /* AIF1TX_LRCLK_SRC */ #define WM2200_AIF1TX_LRCLK_SRC_MASK 0 x0008 /* AIF1TX_LRCLK_SRC */ #define WM2200_AIF1TX_LRCLK_SRC_SHIFT 3 /* AIF1TX_LRCLK_SRC */ #define WM2200_AIF1TX_LRCLK_SRC_WIDTH 1 /* AIF1TX_LRCLK_SRC */ #define WM2200_AIF1TX_LRCLK_INV 0 x0004 /* AIF1TX_LRCLK_INV */ #define WM2200_AIF1TX_LRCLK_INV_MASK 0 x0004 /* AIF1TX_LRCLK_INV */ #define WM2200_AIF1TX_LRCLK_INV_SHIFT 2 /* AIF1TX_LRCLK_INV */ #define WM2200_AIF1TX_LRCLK_INV_WIDTH 1 /* AIF1TX_LRCLK_INV */ #define WM2200_AIF1TX_LRCLK_FRC 0 x0002 /* AIF1TX_LRCLK_FRC */ #define WM2200_AIF1TX_LRCLK_FRC_MASK 0 x0002 /* AIF1TX_LRCLK_FRC */ #define WM2200_AIF1TX_LRCLK_FRC_SHIFT 1 /* AIF1TX_LRCLK_FRC */ #define WM2200_AIF1TX_LRCLK_FRC_WIDTH 1 /* AIF1TX_LRCLK_FRC */ #define WM2200_AIF1TX_LRCLK_MSTR 0 x0001 /* AIF1TX_LRCLK_MSTR */ #define WM2200_AIF1TX_LRCLK_MSTR_MASK 0 x0001 /* AIF1TX_LRCLK_MSTR */ #define WM2200_AIF1TX_LRCLK_MSTR_SHIFT 0 /* AIF1TX_LRCLK_MSTR */ #define WM2200_AIF1TX_LRCLK_MSTR_WIDTH 1 /* AIF1TX_LRCLK_MSTR */ /* * R1282 ( 0 x502 ) - Audio IF 1 _ 3 #define WM2200_AIF1RX_LRCLK_INV 0 x0004 /* AIF1RX_LRCLK_INV */ #define WM2200_AIF1RX_LRCLK_INV_MASK 0 x0004 /* AIF1RX_LRCLK_INV */ #define WM2200_AIF1RX_LRCLK_INV_SHIFT 2 /* AIF1RX_LRCLK_INV */ #define WM2200_AIF1RX_LRCLK_INV_WIDTH 1 /* AIF1RX_LRCLK_INV */ #define WM2200_AIF1RX_LRCLK_FRC 0 x0002 /* AIF1RX_LRCLK_FRC */ #define WM2200_AIF1RX_LRCLK_FRC_MASK 0 x0002 /* AIF1RX_LRCLK_FRC */ #define WM2200_AIF1RX_LRCLK_FRC_SHIFT 1 /* AIF1RX_LRCLK_FRC */ #define WM2200_AIF1RX_LRCLK_FRC_WIDTH 1 /* AIF1RX_LRCLK_FRC */ #define WM2200_AIF1RX_LRCLK_MSTR 0 x0001 /* AIF1RX_LRCLK_MSTR */ #define WM2200_AIF1RX_LRCLK_MSTR_MASK 0 x0001 /* AIF1RX_LRCLK_MSTR */ #define WM2200_AIF1RX_LRCLK_MSTR_SHIFT 0 /* AIF1RX_LRCLK_MSTR */ #define WM2200_AIF1RX_LRCLK_MSTR_WIDTH 1 /* AIF1RX_LRCLK_MSTR */ /* * R1283 ( 0 x503 ) - Audio IF 1 _ 4 #define WM2200_AIF1_TRI 0 x0040 /* AIF1_TRI */ #define WM2200_AIF1_TRI_MASK 0 x0040 /* AIF1_TRI */ #define WM2200_AIF1_TRI_SHIFT 6 /* AIF1_TRI */ #define WM2200_AIF1_TRI_WIDTH 1 /* AIF1_TRI */ /* * R1284 ( 0 x504 ) - Audio IF 1 _ 5 #define WM2200_AIF1_FMT_MASK 0 x0007 /* AIF1_FMT - [2:0] */ #define WM2200_AIF1_FMT_SHIFT 0 /* AIF1_FMT - [2:0] */ #define WM2200_AIF1_FMT_WIDTH 3 /* AIF1_FMT - [2:0] */ /* * R1285 ( 0 x505 ) - Audio IF 1 _ 6 #define WM2200_AIF1TX_BCPF_MASK 0 x07FF /* AIF1TX_BCPF - [10:0] */ #define WM2200_AIF1TX_BCPF_SHIFT 0 /* AIF1TX_BCPF - [10:0] */ #define WM2200_AIF1TX_BCPF_WIDTH 11 /* AIF1TX_BCPF - [10:0] */ /* * R1286 ( 0 x506 ) - Audio IF 1 _ 7 #define WM2200_AIF1RX_BCPF_MASK 0 x07FF /* AIF1RX_BCPF - [10:0] */ #define WM2200_AIF1RX_BCPF_SHIFT 0 /* AIF1RX_BCPF - [10:0] */ #define WM2200_AIF1RX_BCPF_WIDTH 11 /* AIF1RX_BCPF - [10:0] */ /* * R1287 ( 0 x507 ) - Audio IF 1 _ 8 #define WM2200_AIF1TX_WL_MASK 0 x3F00 /* AIF1TX_WL - [13:8] */ #define WM2200_AIF1TX_WL_SHIFT 8 /* AIF1TX_WL - [13:8] */ #define WM2200_AIF1TX_WL_WIDTH 6 /* AIF1TX_WL - [13:8] */ #define WM2200_AIF1TX_SLOT_LEN_MASK 0 x00FF /* AIF1TX_SLOT_LEN - [7:0] */ #define WM2200_AIF1TX_SLOT_LEN_SHIFT 0 /* AIF1TX_SLOT_LEN - [7:0] */ #define WM2200_AIF1TX_SLOT_LEN_WIDTH 8 /* AIF1TX_SLOT_LEN - [7:0] */ /* * R1288 ( 0 x508 ) - Audio IF 1 _ 9 #define WM2200_AIF1RX_WL_MASK 0 x3F00 /* AIF1RX_WL - [13:8] */ #define WM2200_AIF1RX_WL_SHIFT 8 /* AIF1RX_WL - [13:8] */ #define WM2200_AIF1RX_WL_WIDTH 6 /* AIF1RX_WL - [13:8] */ #define WM2200_AIF1RX_SLOT_LEN_MASK 0 x00FF /* AIF1RX_SLOT_LEN - [7:0] */ #define WM2200_AIF1RX_SLOT_LEN_SHIFT 0 /* AIF1RX_SLOT_LEN - [7:0] */ #define WM2200_AIF1RX_SLOT_LEN_WIDTH 8 /* AIF1RX_SLOT_LEN - [7:0] */ /* * R1289 ( 0 x509 ) - Audio IF 1 _ 10 #define WM2200_AIF1TX1_SLOT_MASK 0 x003F /* AIF1TX1_SLOT - [5:0] */ #define WM2200_AIF1TX1_SLOT_SHIFT 0 /* AIF1TX1_SLOT - [5:0] */ #define WM2200_AIF1TX1_SLOT_WIDTH 6 /* AIF1TX1_SLOT - [5:0] */ /* * R1290 ( 0 x50A ) - Audio IF 1 _ 11 #define WM2200_AIF1TX2_SLOT_MASK 0 x003F /* AIF1TX2_SLOT - [5:0] */ #define WM2200_AIF1TX2_SLOT_SHIFT 0 /* AIF1TX2_SLOT - [5:0] */ #define WM2200_AIF1TX2_SLOT_WIDTH 6 /* AIF1TX2_SLOT - [5:0] */ /* * R1291 ( 0 x50B ) - Audio IF 1 _ 12 #define WM2200_AIF1TX3_SLOT_MASK 0 x003F /* AIF1TX3_SLOT - [5:0] */ #define WM2200_AIF1TX3_SLOT_SHIFT 0 /* AIF1TX3_SLOT - [5:0] */ #define WM2200_AIF1TX3_SLOT_WIDTH 6 /* AIF1TX3_SLOT - [5:0] */ /* * R1292 ( 0 x50C ) - Audio IF 1 _ 13 #define WM2200_AIF1TX4_SLOT_MASK 0 x003F /* AIF1TX4_SLOT - [5:0] */ #define WM2200_AIF1TX4_SLOT_SHIFT 0 /* AIF1TX4_SLOT - [5:0] */ #define WM2200_AIF1TX4_SLOT_WIDTH 6 /* AIF1TX4_SLOT - [5:0] */ /* * R1293 ( 0 x50D ) - Audio IF 1 _ 14 #define WM2200_AIF1TX5_SLOT_MASK 0 x003F /* AIF1TX5_SLOT - [5:0] */ #define WM2200_AIF1TX5_SLOT_SHIFT 0 /* AIF1TX5_SLOT - [5:0] */ #define WM2200_AIF1TX5_SLOT_WIDTH 6 /* AIF1TX5_SLOT - [5:0] */ /* * R1294 ( 0 x50E ) - Audio IF 1 _ 15 #define WM2200_AIF1TX6_SLOT_MASK 0 x003F /* AIF1TX6_SLOT - [5:0] */ #define WM2200_AIF1TX6_SLOT_SHIFT 0 /* AIF1TX6_SLOT - [5:0] */ #define WM2200_AIF1TX6_SLOT_WIDTH 6 /* AIF1TX6_SLOT - [5:0] */ /* * R1295 ( 0 x50F ) - Audio IF 1 _ 16 #define WM2200_AIF1RX1_SLOT_MASK 0 x003F /* AIF1RX1_SLOT - [5:0] */ #define WM2200_AIF1RX1_SLOT_SHIFT 0 /* AIF1RX1_SLOT - [5:0] */ #define WM2200_AIF1RX1_SLOT_WIDTH 6 /* AIF1RX1_SLOT - [5:0] */ /* * R1296 ( 0 x510 ) - Audio IF 1 _ 17 #define WM2200_AIF1RX2_SLOT_MASK 0 x003F /* AIF1RX2_SLOT - [5:0] */ #define WM2200_AIF1RX2_SLOT_SHIFT 0 /* AIF1RX2_SLOT - [5:0] */ #define WM2200_AIF1RX2_SLOT_WIDTH 6 /* AIF1RX2_SLOT - [5:0] */ /* * R1297 ( 0 x511 ) - Audio IF 1 _ 18 #define WM2200_AIF1RX3_SLOT_MASK 0 x003F /* AIF1RX3_SLOT - [5:0] */ #define WM2200_AIF1RX3_SLOT_SHIFT 0 /* AIF1RX3_SLOT - [5:0] */ #define WM2200_AIF1RX3_SLOT_WIDTH 6 /* AIF1RX3_SLOT - [5:0] */ /* * R1298 ( 0 x512 ) - Audio IF 1 _ 19 #define WM2200_AIF1RX4_SLOT_MASK 0 x003F /* AIF1RX4_SLOT - [5:0] */ #define WM2200_AIF1RX4_SLOT_SHIFT 0 /* AIF1RX4_SLOT - [5:0] */ #define WM2200_AIF1RX4_SLOT_WIDTH 6 /* AIF1RX4_SLOT - [5:0] */ /* * R1299 ( 0 x513 ) - Audio IF 1 _ 20 #define WM2200_AIF1RX5_SLOT_MASK 0 x003F /* AIF1RX5_SLOT - [5:0] */ #define WM2200_AIF1RX5_SLOT_SHIFT 0 /* AIF1RX5_SLOT - [5:0] */ #define WM2200_AIF1RX5_SLOT_WIDTH 6 /* AIF1RX5_SLOT - [5:0] */ /* * R1300 ( 0 x514 ) - Audio IF 1 _ 21 #define WM2200_AIF1RX6_SLOT_MASK 0 x003F /* AIF1RX6_SLOT - [5:0] */ #define WM2200_AIF1RX6_SLOT_SHIFT 0 /* AIF1RX6_SLOT - [5:0] */ #define WM2200_AIF1RX6_SLOT_WIDTH 6 /* AIF1RX6_SLOT - [5:0] */ /* * R1301 ( 0 x515 ) - Audio IF 1 _ 22 #define WM2200_AIF1RX6_ENA 0 x0800 /* AIF1RX6_ENA */ #define WM2200_AIF1RX6_ENA_MASK 0 x0800 /* AIF1RX6_ENA */ #define WM2200_AIF1RX6_ENA_SHIFT 11 /* AIF1RX6_ENA */ #define WM2200_AIF1RX6_ENA_WIDTH 1 /* AIF1RX6_ENA */ #define WM2200_AIF1RX5_ENA 0 x0400 /* AIF1RX5_ENA */ #define WM2200_AIF1RX5_ENA_MASK 0 x0400 /* AIF1RX5_ENA */ #define WM2200_AIF1RX5_ENA_SHIFT 10 /* AIF1RX5_ENA */ #define WM2200_AIF1RX5_ENA_WIDTH 1 /* AIF1RX5_ENA */ #define WM2200_AIF1RX4_ENA 0 x0200 /* AIF1RX4_ENA */ #define WM2200_AIF1RX4_ENA_MASK 0 x0200 /* AIF1RX4_ENA */ #define WM2200_AIF1RX4_ENA_SHIFT 9 /* AIF1RX4_ENA */ #define WM2200_AIF1RX4_ENA_WIDTH 1 /* AIF1RX4_ENA */ #define WM2200_AIF1RX3_ENA 0 x0100 /* AIF1RX3_ENA */ #define WM2200_AIF1RX3_ENA_MASK 0 x0100 /* AIF1RX3_ENA */ #define WM2200_AIF1RX3_ENA_SHIFT 8 /* AIF1RX3_ENA */ #define WM2200_AIF1RX3_ENA_WIDTH 1 /* AIF1RX3_ENA */ #define WM2200_AIF1RX2_ENA 0 x0080 /* AIF1RX2_ENA */ #define WM2200_AIF1RX2_ENA_MASK 0 x0080 /* AIF1RX2_ENA */ #define WM2200_AIF1RX2_ENA_SHIFT 7 /* AIF1RX2_ENA */ #define WM2200_AIF1RX2_ENA_WIDTH 1 /* AIF1RX2_ENA */ #define WM2200_AIF1RX1_ENA 0 x0040 /* AIF1RX1_ENA */ #define WM2200_AIF1RX1_ENA_MASK 0 x0040 /* AIF1RX1_ENA */ #define WM2200_AIF1RX1_ENA_SHIFT 6 /* AIF1RX1_ENA */ #define WM2200_AIF1RX1_ENA_WIDTH 1 /* AIF1RX1_ENA */ #define WM2200_AIF1TX6_ENA 0 x0020 /* AIF1TX6_ENA */ #define WM2200_AIF1TX6_ENA_MASK 0 x0020 /* AIF1TX6_ENA */ #define WM2200_AIF1TX6_ENA_SHIFT 5 /* AIF1TX6_ENA */ #define WM2200_AIF1TX6_ENA_WIDTH 1 /* AIF1TX6_ENA */ #define WM2200_AIF1TX5_ENA 0 x0010 /* AIF1TX5_ENA */ #define WM2200_AIF1TX5_ENA_MASK 0 x0010 /* AIF1TX5_ENA */ #define WM2200_AIF1TX5_ENA_SHIFT 4 /* AIF1TX5_ENA */ #define WM2200_AIF1TX5_ENA_WIDTH 1 /* AIF1TX5_ENA */ #define WM2200_AIF1TX4_ENA 0 x0008 /* AIF1TX4_ENA */ #define WM2200_AIF1TX4_ENA_MASK 0 x0008 /* AIF1TX4_ENA */ #define WM2200_AIF1TX4_ENA_SHIFT 3 /* AIF1TX4_ENA */ #define WM2200_AIF1TX4_ENA_WIDTH 1 /* AIF1TX4_ENA */ #define WM2200_AIF1TX3_ENA 0 x0004 /* AIF1TX3_ENA */ #define WM2200_AIF1TX3_ENA_MASK 0 x0004 /* AIF1TX3_ENA */ #define WM2200_AIF1TX3_ENA_SHIFT 2 /* AIF1TX3_ENA */ #define WM2200_AIF1TX3_ENA_WIDTH 1 /* AIF1TX3_ENA */ #define WM2200_AIF1TX2_ENA 0 x0002 /* AIF1TX2_ENA */ #define WM2200_AIF1TX2_ENA_MASK 0 x0002 /* AIF1TX2_ENA */ #define WM2200_AIF1TX2_ENA_SHIFT 1 /* AIF1TX2_ENA */ #define WM2200_AIF1TX2_ENA_WIDTH 1 /* AIF1TX2_ENA */ #define WM2200_AIF1TX1_ENA 0 x0001 /* AIF1TX1_ENA */ #define WM2200_AIF1TX1_ENA_MASK 0 x0001 /* AIF1TX1_ENA */ #define WM2200_AIF1TX1_ENA_SHIFT 0 /* AIF1TX1_ENA */ #define WM2200_AIF1TX1_ENA_WIDTH 1 /* AIF1TX1_ENA */ /* * R1536 ( 0 x600 ) - OUT1LMIX Input 1 Source #define WM2200_OUT1LMIX_SRC1_MASK 0 x007F /* OUT1LMIX_SRC1 - [6:0] */ #define WM2200_OUT1LMIX_SRC1_SHIFT 0 /* OUT1LMIX_SRC1 - [6:0] */ #define WM2200_OUT1LMIX_SRC1_WIDTH 7 /* OUT1LMIX_SRC1 - [6:0] */ /* * R1537 ( 0 x601 ) - OUT1LMIX Input 1 Volume #define WM2200_OUT1LMIX_VOL1_MASK 0 x00FE /* OUT1LMIX_VOL1 - [7:1] */ #define WM2200_OUT1LMIX_VOL1_SHIFT 1 /* OUT1LMIX_VOL1 - [7:1] */ #define WM2200_OUT1LMIX_VOL1_WIDTH 7 /* OUT1LMIX_VOL1 - [7:1] */ /* * R1538 ( 0 x602 ) - OUT1LMIX Input 2 Source #define WM2200_OUT1LMIX_SRC2_MASK 0 x007F /* OUT1LMIX_SRC2 - [6:0] */ #define WM2200_OUT1LMIX_SRC2_SHIFT 0 /* OUT1LMIX_SRC2 - [6:0] */ #define WM2200_OUT1LMIX_SRC2_WIDTH 7 /* OUT1LMIX_SRC2 - [6:0] */ /* * R1539 ( 0 x603 ) - OUT1LMIX Input 2 Volume #define WM2200_OUT1LMIX_VOL2_MASK 0 x00FE /* OUT1LMIX_VOL2 - [7:1] */ #define WM2200_OUT1LMIX_VOL2_SHIFT 1 /* OUT1LMIX_VOL2 - [7:1] */ #define WM2200_OUT1LMIX_VOL2_WIDTH 7 /* OUT1LMIX_VOL2 - [7:1] */ /* * R1540 ( 0 x604 ) - OUT1LMIX Input 3 Source #define WM2200_OUT1LMIX_SRC3_MASK 0 x007F /* OUT1LMIX_SRC3 - [6:0] */ #define WM2200_OUT1LMIX_SRC3_SHIFT 0 /* OUT1LMIX_SRC3 - [6:0] */ #define WM2200_OUT1LMIX_SRC3_WIDTH 7 /* OUT1LMIX_SRC3 - [6:0] */ /* * R1541 ( 0 x605 ) - OUT1LMIX Input 3 Volume #define WM2200_OUT1LMIX_VOL3_MASK 0 x00FE /* OUT1LMIX_VOL3 - [7:1] */ #define WM2200_OUT1LMIX_VOL3_SHIFT 1 /* OUT1LMIX_VOL3 - [7:1] */ #define WM2200_OUT1LMIX_VOL3_WIDTH 7 /* OUT1LMIX_VOL3 - [7:1] */ /* * R1542 ( 0 x606 ) - OUT1LMIX Input 4 Source #define WM2200_OUT1LMIX_SRC4_MASK 0 x007F /* OUT1LMIX_SRC4 - [6:0] */ #define WM2200_OUT1LMIX_SRC4_SHIFT 0 /* OUT1LMIX_SRC4 - [6:0] */ #define WM2200_OUT1LMIX_SRC4_WIDTH 7 /* OUT1LMIX_SRC4 - [6:0] */ /* * R1543 ( 0 x607 ) - OUT1LMIX Input 4 Volume #define WM2200_OUT1LMIX_VOL4_MASK 0 x00FE /* OUT1LMIX_VOL4 - [7:1] */ #define WM2200_OUT1LMIX_VOL4_SHIFT 1 /* OUT1LMIX_VOL4 - [7:1] */ #define WM2200_OUT1LMIX_VOL4_WIDTH 7 /* OUT1LMIX_VOL4 - [7:1] */ /* * R1544 ( 0 x608 ) - OUT1RMIX Input 1 Source #define WM2200_OUT1RMIX_SRC1_MASK 0 x007F /* OUT1RMIX_SRC1 - [6:0] */ #define WM2200_OUT1RMIX_SRC1_SHIFT 0 /* OUT1RMIX_SRC1 - [6:0] */ #define WM2200_OUT1RMIX_SRC1_WIDTH 7 /* OUT1RMIX_SRC1 - [6:0] */ /* * R1545 ( 0 x609 ) - OUT1RMIX Input 1 Volume #define WM2200_OUT1RMIX_VOL1_MASK 0 x00FE /* OUT1RMIX_VOL1 - [7:1] */ #define WM2200_OUT1RMIX_VOL1_SHIFT 1 /* OUT1RMIX_VOL1 - [7:1] */ #define WM2200_OUT1RMIX_VOL1_WIDTH 7 /* OUT1RMIX_VOL1 - [7:1] */ /* * R1546 ( 0 x60A ) - OUT1RMIX Input 2 Source #define WM2200_OUT1RMIX_SRC2_MASK 0 x007F /* OUT1RMIX_SRC2 - [6:0] */ #define WM2200_OUT1RMIX_SRC2_SHIFT 0 /* OUT1RMIX_SRC2 - [6:0] */ #define WM2200_OUT1RMIX_SRC2_WIDTH 7 /* OUT1RMIX_SRC2 - [6:0] */ /* * R1547 ( 0 x60B ) - OUT1RMIX Input 2 Volume #define WM2200_OUT1RMIX_VOL2_MASK 0 x00FE /* OUT1RMIX_VOL2 - [7:1] */ #define WM2200_OUT1RMIX_VOL2_SHIFT 1 /* OUT1RMIX_VOL2 - [7:1] */ #define WM2200_OUT1RMIX_VOL2_WIDTH 7 /* OUT1RMIX_VOL2 - [7:1] */ /* * R1548 ( 0 x60C ) - OUT1RMIX Input 3 Source #define WM2200_OUT1RMIX_SRC3_MASK 0 x007F /* OUT1RMIX_SRC3 - [6:0] */ #define WM2200_OUT1RMIX_SRC3_SHIFT 0 /* OUT1RMIX_SRC3 - [6:0] */ #define WM2200_OUT1RMIX_SRC3_WIDTH 7 /* OUT1RMIX_SRC3 - [6:0] */ /* * R1549 ( 0 x60D ) - OUT1RMIX Input 3 Volume #define WM2200_OUT1RMIX_VOL3_MASK 0 x00FE /* OUT1RMIX_VOL3 - [7:1] */ #define WM2200_OUT1RMIX_VOL3_SHIFT 1 /* OUT1RMIX_VOL3 - [7:1] */ #define WM2200_OUT1RMIX_VOL3_WIDTH 7 /* OUT1RMIX_VOL3 - [7:1] */ /* * R1550 ( 0 x60E ) - OUT1RMIX Input 4 Source #define WM2200_OUT1RMIX_SRC4_MASK 0 x007F /* OUT1RMIX_SRC4 - [6:0] */ #define WM2200_OUT1RMIX_SRC4_SHIFT 0 /* OUT1RMIX_SRC4 - [6:0] */ #define WM2200_OUT1RMIX_SRC4_WIDTH 7 /* OUT1RMIX_SRC4 - [6:0] */ /* * R1551 ( 0 x60F ) - OUT1RMIX Input 4 Volume #define WM2200_OUT1RMIX_VOL4_MASK 0 x00FE /* OUT1RMIX_VOL4 - [7:1] */ #define WM2200_OUT1RMIX_VOL4_SHIFT 1 /* OUT1RMIX_VOL4 - [7:1] */ #define WM2200_OUT1RMIX_VOL4_WIDTH 7 /* OUT1RMIX_VOL4 - [7:1] */ /* * R1552 ( 0 x610 ) - OUT2LMIX Input 1 Source #define WM2200_OUT2LMIX_SRC1_MASK 0 x007F /* OUT2LMIX_SRC1 - [6:0] */ #define WM2200_OUT2LMIX_SRC1_SHIFT 0 /* OUT2LMIX_SRC1 - [6:0] */ #define WM2200_OUT2LMIX_SRC1_WIDTH 7 /* OUT2LMIX_SRC1 - [6:0] */ /* * R1553 ( 0 x611 ) - OUT2LMIX Input 1 Volume #define WM2200_OUT2LMIX_VOL1_MASK 0 x00FE /* OUT2LMIX_VOL1 - [7:1] */ #define WM2200_OUT2LMIX_VOL1_SHIFT 1 /* OUT2LMIX_VOL1 - [7:1] */ #define WM2200_OUT2LMIX_VOL1_WIDTH 7 /* OUT2LMIX_VOL1 - [7:1] */ /* * R1554 ( 0 x612 ) - OUT2LMIX Input 2 Source #define WM2200_OUT2LMIX_SRC2_MASK 0 x007F /* OUT2LMIX_SRC2 - [6:0] */ #define WM2200_OUT2LMIX_SRC2_SHIFT 0 /* OUT2LMIX_SRC2 - [6:0] */ #define WM2200_OUT2LMIX_SRC2_WIDTH 7 /* OUT2LMIX_SRC2 - [6:0] */ /* * R1555 ( 0 x613 ) - OUT2LMIX Input 2 Volume #define WM2200_OUT2LMIX_VOL2_MASK 0 x00FE /* OUT2LMIX_VOL2 - [7:1] */ #define WM2200_OUT2LMIX_VOL2_SHIFT 1 /* OUT2LMIX_VOL2 - [7:1] */ #define WM2200_OUT2LMIX_VOL2_WIDTH 7 /* OUT2LMIX_VOL2 - [7:1] */ /* * R1556 ( 0 x614 ) - OUT2LMIX Input 3 Source #define WM2200_OUT2LMIX_SRC3_MASK 0 x007F /* OUT2LMIX_SRC3 - [6:0] */ #define WM2200_OUT2LMIX_SRC3_SHIFT 0 /* OUT2LMIX_SRC3 - [6:0] */ #define WM2200_OUT2LMIX_SRC3_WIDTH 7 /* OUT2LMIX_SRC3 - [6:0] */ /* * R1557 ( 0 x615 ) - OUT2LMIX Input 3 Volume #define WM2200_OUT2LMIX_VOL3_MASK 0 x00FE /* OUT2LMIX_VOL3 - [7:1] */ #define WM2200_OUT2LMIX_VOL3_SHIFT 1 /* OUT2LMIX_VOL3 - [7:1] */ #define WM2200_OUT2LMIX_VOL3_WIDTH 7 /* OUT2LMIX_VOL3 - [7:1] */ /* * R1558 ( 0 x616 ) - OUT2LMIX Input 4 Source #define WM2200_OUT2LMIX_SRC4_MASK 0 x007F /* OUT2LMIX_SRC4 - [6:0] */ #define WM2200_OUT2LMIX_SRC4_SHIFT 0 /* OUT2LMIX_SRC4 - [6:0] */ #define WM2200_OUT2LMIX_SRC4_WIDTH 7 /* OUT2LMIX_SRC4 - [6:0] */ /* * R1559 ( 0 x617 ) - OUT2LMIX Input 4 Volume #define WM2200_OUT2LMIX_VOL4_MASK 0 x00FE /* OUT2LMIX_VOL4 - [7:1] */ #define WM2200_OUT2LMIX_VOL4_SHIFT 1 /* OUT2LMIX_VOL4 - [7:1] */ #define WM2200_OUT2LMIX_VOL4_WIDTH 7 /* OUT2LMIX_VOL4 - [7:1] */ /* * R1560 ( 0 x618 ) - OUT2RMIX Input 1 Source #define WM2200_OUT2RMIX_SRC1_MASK 0 x007F /* OUT2RMIX_SRC1 - [6:0] */ #define WM2200_OUT2RMIX_SRC1_SHIFT 0 /* OUT2RMIX_SRC1 - [6:0] */ #define WM2200_OUT2RMIX_SRC1_WIDTH 7 /* OUT2RMIX_SRC1 - [6:0] */ /* * R1561 ( 0 x619 ) - OUT2RMIX Input 1 Volume #define WM2200_OUT2RMIX_VOL1_MASK 0 x00FE /* OUT2RMIX_VOL1 - [7:1] */ #define WM2200_OUT2RMIX_VOL1_SHIFT 1 /* OUT2RMIX_VOL1 - [7:1] */ #define WM2200_OUT2RMIX_VOL1_WIDTH 7 /* OUT2RMIX_VOL1 - [7:1] */ /* * R1562 ( 0 x61A ) - OUT2RMIX Input 2 Source #define WM2200_OUT2RMIX_SRC2_MASK 0 x007F /* OUT2RMIX_SRC2 - [6:0] */ #define WM2200_OUT2RMIX_SRC2_SHIFT 0 /* OUT2RMIX_SRC2 - [6:0] */ #define WM2200_OUT2RMIX_SRC2_WIDTH 7 /* OUT2RMIX_SRC2 - [6:0] */ /* * R1563 ( 0 x61B ) - OUT2RMIX Input 2 Volume #define WM2200_OUT2RMIX_VOL2_MASK 0 x00FE /* OUT2RMIX_VOL2 - [7:1] */ #define WM2200_OUT2RMIX_VOL2_SHIFT 1 /* OUT2RMIX_VOL2 - [7:1] */ #define WM2200_OUT2RMIX_VOL2_WIDTH 7 /* OUT2RMIX_VOL2 - [7:1] */ /* * R1564 ( 0 x61C ) - OUT2RMIX Input 3 Source #define WM2200_OUT2RMIX_SRC3_MASK 0 x007F /* OUT2RMIX_SRC3 - [6:0] */ #define WM2200_OUT2RMIX_SRC3_SHIFT 0 /* OUT2RMIX_SRC3 - [6:0] */ #define WM2200_OUT2RMIX_SRC3_WIDTH 7 /* OUT2RMIX_SRC3 - [6:0] */ /* * R1565 ( 0 x61D ) - OUT2RMIX Input 3 Volume #define WM2200_OUT2RMIX_VOL3_MASK 0 x00FE /* OUT2RMIX_VOL3 - [7:1] */ #define WM2200_OUT2RMIX_VOL3_SHIFT 1 /* OUT2RMIX_VOL3 - [7:1] */ #define WM2200_OUT2RMIX_VOL3_WIDTH 7 /* OUT2RMIX_VOL3 - [7:1] */ /* * R1566 ( 0 x61E ) - OUT2RMIX Input 4 Source #define WM2200_OUT2RMIX_SRC4_MASK 0 x007F /* OUT2RMIX_SRC4 - [6:0] */ #define WM2200_OUT2RMIX_SRC4_SHIFT 0 /* OUT2RMIX_SRC4 - [6:0] */ #define WM2200_OUT2RMIX_SRC4_WIDTH 7 /* OUT2RMIX_SRC4 - [6:0] */ /* * R1567 ( 0 x61F ) - OUT2RMIX Input 4 Volume #define WM2200_OUT2RMIX_VOL4_MASK 0 x00FE /* OUT2RMIX_VOL4 - [7:1] */ #define WM2200_OUT2RMIX_VOL4_SHIFT 1 /* OUT2RMIX_VOL4 - [7:1] */ #define WM2200_OUT2RMIX_VOL4_WIDTH 7 /* OUT2RMIX_VOL4 - [7:1] */ /* * R1568 ( 0 x620 ) - AIF1TX1MIX Input 1 Source #define WM2200_AIF1TX1MIX_SRC1_MASK 0 x007F /* AIF1TX1MIX_SRC1 - [6:0] */ #define WM2200_AIF1TX1MIX_SRC1_SHIFT 0 /* AIF1TX1MIX_SRC1 - [6:0] */ #define WM2200_AIF1TX1MIX_SRC1_WIDTH 7 /* AIF1TX1MIX_SRC1 - [6:0] */ /* * R1569 ( 0 x621 ) - AIF1TX1MIX Input 1 Volume #define WM2200_AIF1TX1MIX_VOL1_MASK 0 x00FE /* AIF1TX1MIX_VOL1 - [7:1] */ #define WM2200_AIF1TX1MIX_VOL1_SHIFT 1 /* AIF1TX1MIX_VOL1 - [7:1] */ #define WM2200_AIF1TX1MIX_VOL1_WIDTH 7 /* AIF1TX1MIX_VOL1 - [7:1] */ /* * R1570 ( 0 x622 ) - AIF1TX1MIX Input 2 Source #define WM2200_AIF1TX1MIX_SRC2_MASK 0 x007F /* AIF1TX1MIX_SRC2 - [6:0] */ #define WM2200_AIF1TX1MIX_SRC2_SHIFT 0 /* AIF1TX1MIX_SRC2 - [6:0] */ #define WM2200_AIF1TX1MIX_SRC2_WIDTH 7 /* AIF1TX1MIX_SRC2 - [6:0] */ /* * R1571 ( 0 x623 ) - AIF1TX1MIX Input 2 Volume * / # define WM2200_AIF1TX1MIX_VOL2_MASK 0 x00FE #define WM2200_AIF1TX1MIX_VOL2_MASK 0x00FE /* AIF1TX1MIX_VOL2 - [7:1] */ #define WM2200_AIF1TX1MIX_VOL2_SHIFT 1 /* AIF1TX1MIX_VOL2 - [7:1] */ #define WM2200_AIF1TX1MIX_VOL2_WIDTH 7 /* AIF1TX1MIX_VOL2 - [7:1] */ /* * R1572 ( 0 x624 ) - AIF1TX1MIX Input 3 Source #define WM2200_AIF1TX1MIX_SRC3_MASK 0 x007F /* AIF1TX1MIX_SRC3 - [6:0] */ #define WM2200_AIF1TX1MIX_SRC3_SHIFT 0 /* AIF1TX1MIX_SRC3 - [6:0] */ #define WM2200_AIF1TX1MIX_SRC3_WIDTH 7 /* AIF1TX1MIX_SRC3 - [6:0] */ /* * R1573 ( 0 x625 ) - AIF1TX1MIX Input 3 Volume #define WM2200_AIF1TX1MIX_VOL3_MASK 0 x00FE /* AIF1TX1MIX_VOL3 - [7:1] */ #define WM2200_AIF1TX1MIX_VOL3_SHIFT 1 /* AIF1TX1MIX_VOL3 - [7:1] */ #define WM2200_AIF1TX1MIX_VOL3_WIDTH 7 /* AIF1TX1MIX_VOL3 - [7:1] */ /* * R1574 ( 0 x626 ) - AIF1TX1MIX Input 4 Source #define WM2200_AIF1TX1MIX_SRC4_MASK 0 x007F /* AIF1TX1MIX_SRC4 - [6:0] */ #define WM2200_AIF1TX1MIX_SRC4_SHIFT 0 /* AIF1TX1MIX_SRC4 - [6:0] */ #define WM2200_AIF1TX1MIX_SRC4_WIDTH 7 /* AIF1TX1MIX_SRC4 - [6:0] */ /* * R1575 ( 0 x627 ) - AIF1TX1MIX Input 4 Volume #define WM2200_AIF1TX1MIX_VOL4_MASK 0 x00FE /* AIF1TX1MIX_VOL4 - [7:1] */ #define WM2200_AIF1TX1MIX_VOL4_SHIFT 1 /* AIF1TX1MIX_VOL4 - [7:1] */ #define WM2200_AIF1TX1MIX_VOL4_WIDTH 7 /* AIF1TX1MIX_VOL4 - [7:1] */ /* * R1576 ( 0 x628 ) - AIF1TX2MIX Input 1 Source #define WM2200_AIF1TX2MIX_SRC1_MASK 0 x007F /* AIF1TX2MIX_SRC1 - [6:0] */ #define WM2200_AIF1TX2MIX_SRC1_SHIFT 0 /* AIF1TX2MIX_SRC1 - [6:0] */ #define WM2200_AIF1TX2MIX_SRC1_WIDTH 7 /* AIF1TX2MIX_SRC1 - [6:0] */ /* * R1577 ( 0 x629 ) - AIF1TX2MIX Input 1 Volume #define WM2200_AIF1TX2MIX_VOL1_MASK 0 x00FE /* AIF1TX2MIX_VOL1 - [7:1] */ #define WM2200_AIF1TX2MIX_VOL1_SHIFT 1 /* AIF1TX2MIX_VOL1 - [7:1] */ #define WM2200_AIF1TX2MIX_VOL1_WIDTH 7 /* AIF1TX2MIX_VOL1 - [7:1] */ /* * R1578 ( 0 x62A ) - AIF1TX2MIX Input 2 Source #define WM2200_AIF1TX2MIX_SRC2_MASK 0 x007F /* AIF1TX2MIX_SRC2 - [6:0] */ #define WM2200_AIF1TX2MIX_SRC2_SHIFT 0 /* AIF1TX2MIX_SRC2 - [6:0] */ #define WM2200_AIF1TX2MIX_SRC2_WIDTH 7 /* AIF1TX2MIX_SRC2 - [6:0] */ /* * R1579 ( 0 x62B ) - AIF1TX2MIX Input 2 Volume #define WM2200_AIF1TX2MIX_VOL2_MASK 0 x00FE /* AIF1TX2MIX_VOL2 - [7:1] */ #define WM2200_AIF1TX2MIX_VOL2_SHIFT 1 /* AIF1TX2MIX_VOL2 - [7:1] */ #define WM2200_AIF1TX2MIX_VOL2_WIDTH 7 /* AIF1TX2MIX_VOL2 - [7:1] */ /* * R1580 ( 0 x62C ) - AIF1TX2MIX Input 3 Source #define WM2200_AIF1TX2MIX_SRC3_MASK 0 x007F /* AIF1TX2MIX_SRC3 - [6:0] */ #define WM2200_AIF1TX2MIX_SRC3_SHIFT 0 /* AIF1TX2MIX_SRC3 - [6:0] */ #define WM2200_AIF1TX2MIX_SRC3_WIDTH 7 /* AIF1TX2MIX_SRC3 - [6:0] */ /* * R1581 ( 0 x62D ) - AIF1TX2MIX Input 3 Volume #define WM2200_AIF1TX2MIX_VOL3_MASK 0 x00FE /* AIF1TX2MIX_VOL3 - [7:1] */ #define WM2200_AIF1TX2MIX_VOL3_SHIFT 1 /* AIF1TX2MIX_VOL3 - [7:1] */ #define WM2200_AIF1TX2MIX_VOL3_WIDTH 7 /* AIF1TX2MIX_VOL3 - [7:1] */ /* * R1582 ( 0 x62E ) - AIF1TX2MIX Input 4 Source #define WM2200_AIF1TX2MIX_SRC4_MASK 0 x007F /* AIF1TX2MIX_SRC4 - [6:0] */ #define WM2200_AIF1TX2MIX_SRC4_SHIFT 0 /* AIF1TX2MIX_SRC4 - [6:0] */ #define WM2200_AIF1TX2MIX_SRC4_WIDTH 7 /* AIF1TX2MIX_SRC4 - [6:0] */ /* * R1583 ( 0 x62F ) - AIF1TX2MIX Input 4 Volume #define WM2200_AIF1TX2MIX_VOL4_MASK 0 x00FE /* AIF1TX2MIX_VOL4 - [7:1] */ #define WM2200_AIF1TX2MIX_VOL4_SHIFT 1 /* AIF1TX2MIX_VOL4 - [7:1] */ #define WM2200_AIF1TX2MIX_VOL4_WIDTH 7 /* AIF1TX2MIX_VOL4 - [7:1] */ /* * R1584 ( 0 x630 ) - AIF1TX3MIX Input 1 Source #define WM2200_AIF1TX3MIX_SRC1_MASK 0 x007F /* AIF1TX3MIX_SRC1 - [6:0] */ #define WM2200_AIF1TX3MIX_SRC1_SHIFT 0 /* AIF1TX3MIX_SRC1 - [6:0] */ #define WM2200_AIF1TX3MIX_SRC1_WIDTH 7 /* AIF1TX3MIX_SRC1 - [6:0] */ /* * R1585 ( 0 x631 ) - AIF1TX3MIX Input 1 Volume #define WM2200_AIF1TX3MIX_VOL1_MASK 0 x00FE /* AIF1TX3MIX_VOL1 - [7:1] */ #define WM2200_AIF1TX3MIX_VOL1_SHIFT 1 /* AIF1TX3MIX_VOL1 - [7:1] */ #define WM2200_AIF1TX3MIX_VOL1_WIDTH 7 /* AIF1TX3MIX_VOL1 - [7:1] */ /* * R1586 ( 0 x632 ) - AIF1TX3MIX Input 2 Source #define WM2200_AIF1TX3MIX_SRC2_MASK 0 x007F /* AIF1TX3MIX_SRC2 - [6:0] */ #define WM2200_AIF1TX3MIX_SRC2_SHIFT 0 /* AIF1TX3MIX_SRC2 - [6:0] */ #define WM2200_AIF1TX3MIX_SRC2_WIDTH 7 /* AIF1TX3MIX_SRC2 - [6:0] */ /* * R1587 ( 0 x633 ) - AIF1TX3MIX Input 2 Volume #define WM2200_AIF1TX3MIX_VOL2_MASK 0 x00FE /* AIF1TX3MIX_VOL2 - [7:1] */ #define WM2200_AIF1TX3MIX_VOL2_SHIFT 1 /* AIF1TX3MIX_VOL2 - [7:1] */ #define WM2200_AIF1TX3MIX_VOL2_WIDTH 7 /* AIF1TX3MIX_VOL2 - [7:1] */ /* * R1588 ( 0 x634 ) - AIF1TX3MIX Input 3 Source #define WM2200_AIF1TX3MIX_SRC3_MASK 0 x007F /* AIF1TX3MIX_SRC3 - [6:0] */ #define WM2200_AIF1TX3MIX_SRC3_SHIFT 0 /* AIF1TX3MIX_SRC3 - [6:0] */ #define WM2200_AIF1TX3MIX_SRC3_WIDTH 7 /* AIF1TX3MIX_SRC3 - [6:0] */ /* * R1589 ( 0 x635 ) - AIF1TX3MIX Input 3 Volume #define WM2200_AIF1TX3MIX_VOL3_MASK 0 x00FE /* AIF1TX3MIX_VOL3 - [7:1] */ #define WM2200_AIF1TX3MIX_VOL3_SHIFT 1 /* AIF1TX3MIX_VOL3 - [7:1] */ #define WM2200_AIF1TX3MIX_VOL3_WIDTH 7 /* AIF1TX3MIX_VOL3 - [7:1] */ /* * R1590 ( 0 x636 ) - AIF1TX3MIX Input 4 Source #define WM2200_AIF1TX3MIX_SRC4_MASK 0 x007F /* AIF1TX3MIX_SRC4 - [6:0] */ #define WM2200_AIF1TX3MIX_SRC4_SHIFT 0 /* AIF1TX3MIX_SRC4 - [6:0] */ #define WM2200_AIF1TX3MIX_SRC4_WIDTH 7 /* AIF1TX3MIX_SRC4 - [6:0] */ /* * R1591 ( 0 x637 ) - AIF1TX3MIX Input 4 Volume #define WM2200_AIF1TX3MIX_VOL4_MASK 0 x00FE /* AIF1TX3MIX_VOL4 - [7:1] */ #define WM2200_AIF1TX3MIX_VOL4_SHIFT 1 /* AIF1TX3MIX_VOL4 - [7:1] */ #define WM2200_AIF1TX3MIX_VOL4_WIDTH 7 /* AIF1TX3MIX_VOL4 - [7:1] */ /* * R1592 ( 0 x638 ) - AIF1TX4MIX Input 1 Source #define WM2200_AIF1TX4MIX_SRC1_MASK 0 x007F /* AIF1TX4MIX_SRC1 - [6:0] */ #define WM2200_AIF1TX4MIX_SRC1_SHIFT 0 /* AIF1TX4MIX_SRC1 - [6:0] */ #define WM2200_AIF1TX4MIX_SRC1_WIDTH 7 /* AIF1TX4MIX_SRC1 - [6:0] */ /* * R1593 ( 0 x639 ) - AIF1TX4MIX Input 1 Volume #define WM2200_AIF1TX4MIX_VOL1_MASK 0 x00FE /* AIF1TX4MIX_VOL1 - [7:1] */ #define WM2200_AIF1TX4MIX_VOL1_SHIFT 1 /* AIF1TX4MIX_VOL1 - [7:1] */ #define WM2200_AIF1TX4MIX_VOL1_WIDTH 7 /* AIF1TX4MIX_VOL1 - [7:1] */ /* * R1594 ( 0 x63A ) - AIF1TX4MIX Input 2 Source #define WM2200_AIF1TX4MIX_SRC2_MASK 0 x007F /* AIF1TX4MIX_SRC2 - [6:0] */ #define WM2200_AIF1TX4MIX_SRC2_SHIFT 0 /* AIF1TX4MIX_SRC2 - [6:0] */ #define WM2200_AIF1TX4MIX_SRC2_WIDTH 7 /* AIF1TX4MIX_SRC2 - [6:0] */ /* * R1595 ( 0 x63B ) - AIF1TX4MIX Input 2 Volume #define WM2200_AIF1TX4MIX_VOL2_MASK 0 x00FE /* AIF1TX4MIX_VOL2 - [7:1] */ #define WM2200_AIF1TX4MIX_VOL2_SHIFT 1 /* AIF1TX4MIX_VOL2 - [7:1] */ #define WM2200_AIF1TX4MIX_VOL2_WIDTH 7 /* AIF1TX4MIX_VOL2 - [7:1] */ /* * R1596 ( 0 x63C ) - AIF1TX4MIX Input 3 Source #define WM2200_AIF1TX4MIX_SRC3_MASK 0 x007F /* AIF1TX4MIX_SRC3 - [6:0] */ #define WM2200_AIF1TX4MIX_SRC3_SHIFT 0 /* AIF1TX4MIX_SRC3 - [6:0] */ #define WM2200_AIF1TX4MIX_SRC3_WIDTH 7 /* AIF1TX4MIX_SRC3 - [6:0] */ /* * R1597 ( 0 x63D ) - AIF1TX4MIX Input 3 Volume #define WM2200_AIF1TX4MIX_VOL3_MASK 0 x00FE /* AIF1TX4MIX_VOL3 - [7:1] */ #define WM2200_AIF1TX4MIX_VOL3_SHIFT 1 /* AIF1TX4MIX_VOL3 - [7:1] */ #define WM2200_AIF1TX4MIX_VOL3_WIDTH 7 /* AIF1TX4MIX_VOL3 - [7:1] */ /* * R1598 ( 0 x63E ) - AIF1TX4MIX Input 4 Source #define WM2200_AIF1TX4MIX_SRC4_MASK 0 x007F /* AIF1TX4MIX_SRC4 - [6:0] */ #define WM2200_AIF1TX4MIX_SRC4_SHIFT 0 /* AIF1TX4MIX_SRC4 - [6:0] */ #define WM2200_AIF1TX4MIX_SRC4_WIDTH 7 /* AIF1TX4MIX_SRC4 - [6:0] */ /* * R1599 ( 0 x63F ) - AIF1TX4MIX Input 4 Volume #define WM2200_AIF1TX4MIX_VOL4_MASK 0 x00FE /* AIF1TX4MIX_VOL4 - [7:1] */ #define WM2200_AIF1TX4MIX_VOL4_SHIFT 1 /* AIF1TX4MIX_VOL4 - [7:1] */ #define WM2200_AIF1TX4MIX_VOL4_WIDTH 7 /* AIF1TX4MIX_VOL4 - [7:1] */ /* * R1600 ( 0 x640 ) - AIF1TX5MIX Input 1 Source #define WM2200_AIF1TX5MIX_SRC1_MASK 0 x007F /* AIF1TX5MIX_SRC1 - [6:0] */ #define WM2200_AIF1TX5MIX_SRC1_SHIFT 0 /* AIF1TX5MIX_SRC1 - [6:0] */ #define WM2200_AIF1TX5MIX_SRC1_WIDTH 7 /* AIF1TX5MIX_SRC1 - [6:0] */ /* * R1601 ( 0 x641 ) - AIF1TX5MIX Input 1 Volume #define WM2200_AIF1TX5MIX_VOL1_MASK 0 x00FE /* AIF1TX5MIX_VOL1 - [7:1] */ #define WM2200_AIF1TX5MIX_VOL1_SHIFT 1 /* AIF1TX5MIX_VOL1 - [7:1] */ #define WM2200_AIF1TX5MIX_VOL1_WIDTH 7 /* AIF1TX5MIX_VOL1 - [7:1] */ /* * R1602 ( 0 x642 ) - AIF1TX5MIX Input 2 Source #define WM2200_AIF1TX5MIX_SRC2_MASK 0 x007F /* AIF1TX5MIX_SRC2 - [6:0] */ #define WM2200_AIF1TX5MIX_SRC2_SHIFT 0 /* AIF1TX5MIX_SRC2 - [6:0] */ #define WM2200_AIF1TX5MIX_SRC2_WIDTH 7 /* AIF1TX5MIX_SRC2 - [6:0] */ /* * R1603 ( 0 x643 ) - AIF1TX5MIX Input 2 Volume #define WM2200_AIF1TX5MIX_VOL2_MASK 0 x00FE /* AIF1TX5MIX_VOL2 - [7:1] */ #define WM2200_AIF1TX5MIX_VOL2_SHIFT 1 /* AIF1TX5MIX_VOL2 - [7:1] */ #define WM2200_AIF1TX5MIX_VOL2_WIDTH 7 /* AIF1TX5MIX_VOL2 - [7:1] */ /* * R1604 ( 0 x644 ) - AIF1TX5MIX Input 3 Source #define WM2200_AIF1TX5MIX_SRC3_MASK 0 x007F /* AIF1TX5MIX_SRC3 - [6:0] */ #define WM2200_AIF1TX5MIX_SRC3_SHIFT 0 /* AIF1TX5MIX_SRC3 - [6:0] */ #define WM2200_AIF1TX5MIX_SRC3_WIDTH 7 /* AIF1TX5MIX_SRC3 - [6:0] */ /* * R1605 ( 0 x645 ) - AIF1TX5MIX Input 3 Volume #define WM2200_AIF1TX5MIX_VOL3_MASK 0 x00FE /* AIF1TX5MIX_VOL3 - [7:1] */ #define WM2200_AIF1TX5MIX_VOL3_SHIFT 1 /* AIF1TX5MIX_VOL3 - [7:1] */ #define WM2200_AIF1TX5MIX_VOL3_WIDTH 7 /* AIF1TX5MIX_VOL3 - [7:1] */ /* * R1606 ( 0 x646 ) - AIF1TX5MIX Input 4 Source #define WM2200_AIF1TX5MIX_SRC4_MASK 0 x007F /* AIF1TX5MIX_SRC4 - [6:0] */ #define WM2200_AIF1TX5MIX_SRC4_SHIFT 0 /* AIF1TX5MIX_SRC4 - [6:0] */ #define WM2200_AIF1TX5MIX_SRC4_WIDTH 7 /* AIF1TX5MIX_SRC4 - [6:0] */ /* * R1607 ( 0 x647 ) - AIF1TX5MIX Input 4 Volume #define WM2200_AIF1TX5MIX_VOL4_MASK 0 x00FE /* AIF1TX5MIX_VOL4 - [7:1] */ #define WM2200_AIF1TX5MIX_VOL4_SHIFT 1 /* AIF1TX5MIX_VOL4 - [7:1] */ #define WM2200_AIF1TX5MIX_VOL4_WIDTH 7 /* AIF1TX5MIX_VOL4 - [7:1] */ /* * R1608 ( 0 x648 ) - AIF1TX6MIX Input 1 Source #define WM2200_AIF1TX6MIX_SRC1_MASK 0 x007F /* AIF1TX6MIX_SRC1 - [6:0] */ #define WM2200_AIF1TX6MIX_SRC1_SHIFT 0 /* AIF1TX6MIX_SRC1 - [6:0] */ #define WM2200_AIF1TX6MIX_SRC1_WIDTH 7 /* AIF1TX6MIX_SRC1 - [6:0] */ /* * R1609 ( 0 x649 ) - AIF1TX6MIX Input 1 Volume #define WM2200_AIF1TX6MIX_VOL1_MASK 0 x00FE /* AIF1TX6MIX_VOL1 - [7:1] */ #define WM2200_AIF1TX6MIX_VOL1_SHIFT 1 /* AIF1TX6MIX_VOL1 - [7:1] */ #define WM2200_AIF1TX6MIX_VOL1_WIDTH 7 /* AIF1TX6MIX_VOL1 - [7:1] */ /* * R1610 ( 0 x64A ) - AIF1TX6MIX Input 2 Source #define WM2200_AIF1TX6MIX_SRC2_MASK 0 x007F /* AIF1TX6MIX_SRC2 - [6:0] */ #define WM2200_AIF1TX6MIX_SRC2_SHIFT 0 /* AIF1TX6MIX_SRC2 - [6:0] */ #define WM2200_AIF1TX6MIX_SRC2_WIDTH 7 /* AIF1TX6MIX_SRC2 - [6:0] */ /* * R1611 ( 0 x64B ) - AIF1TX6MIX Input 2 Volume #define WM2200_AIF1TX6MIX_VOL2_MASK 0 x00FE /* AIF1TX6MIX_VOL2 - [7:1] */ #define WM2200_AIF1TX6MIX_VOL2_SHIFT 1 /* AIF1TX6MIX_VOL2 - [7:1] */ #define WM2200_AIF1TX6MIX_VOL2_WIDTH 7 /* AIF1TX6MIX_VOL2 - [7:1] */ /* * R1612 ( 0 x64C ) - AIF1TX6MIX Input 3 Source #define WM2200_AIF1TX6MIX_SRC3_MASK 0 x007F /* AIF1TX6MIX_SRC3 - [6:0] */ #define WM2200_AIF1TX6MIX_SRC3_SHIFT 0 /* AIF1TX6MIX_SRC3 - [6:0] */ #define WM2200_AIF1TX6MIX_SRC3_WIDTH 7 /* AIF1TX6MIX_SRC3 - [6:0] */ /* * R1613 ( 0 x64D ) - AIF1TX6MIX Input 3 Volume #define WM2200_AIF1TX6MIX_VOL3_MASK 0 x00FE /* AIF1TX6MIX_VOL3 - [7:1] */ #define WM2200_AIF1TX6MIX_VOL3_SHIFT 1 /* AIF1TX6MIX_VOL3 - [7:1] */ #define WM2200_AIF1TX6MIX_VOL3_WIDTH 7 /* AIF1TX6MIX_VOL3 - [7:1] */ /* * R1614 ( 0 x64E ) - AIF1TX6MIX Input 4 Source #define WM2200_AIF1TX6MIX_SRC4_MASK 0 x007F /* AIF1TX6MIX_SRC4 - [6:0] */ #define WM2200_AIF1TX6MIX_SRC4_SHIFT 0 /* AIF1TX6MIX_SRC4 - [6:0] */ #define WM2200_AIF1TX6MIX_SRC4_WIDTH 7 /* AIF1TX6MIX_SRC4 - [6:0] */ /* * R1615 ( 0 x64F ) - AIF1TX6MIX Input 4 Volume #define WM2200_AIF1TX6MIX_VOL4_MASK 0 x00FE /* AIF1TX6MIX_VOL4 - [7:1] */ #define WM2200_AIF1TX6MIX_VOL4_SHIFT 1 /* AIF1TX6MIX_VOL4 - [7:1] */ #define WM2200_AIF1TX6MIX_VOL4_WIDTH 7 /* AIF1TX6MIX_VOL4 - [7:1] */ /* * R1616 ( 0 x650 ) - EQLMIX Input 1 Source #define WM2200_EQLMIX_SRC1_MASK 0 x007F /* EQLMIX_SRC1 - [6:0] */ #define WM2200_EQLMIX_SRC1_SHIFT 0 /* EQLMIX_SRC1 - [6:0] */ #define WM2200_EQLMIX_SRC1_WIDTH 7 /* EQLMIX_SRC1 - [6:0] */ /* * R1617 ( 0 x651 ) - EQLMIX Input 1 Volume #define WM2200_EQLMIX_VOL1_MASK 0 x00FE /* EQLMIX_VOL1 - [7:1] */ #define WM2200_EQLMIX_VOL1_SHIFT 1 /* EQLMIX_VOL1 - [7:1] */ #define WM2200_EQLMIX_VOL1_WIDTH 7 /* EQLMIX_VOL1 - [7:1] */ /* * R1618 ( 0 x652 ) - EQLMIX Input 2 Source #define WM2200_EQLMIX_SRC2_MASK 0 x007F /* EQLMIX_SRC2 - [6:0] */ #define WM2200_EQLMIX_SRC2_SHIFT 0 /* EQLMIX_SRC2 - [6:0] */ #define WM2200_EQLMIX_SRC2_WIDTH 7 /* EQLMIX_SRC2 - [6:0] */ /* * R1619 ( 0 x653 ) - EQLMIX Input 2 Volume #define WM2200_EQLMIX_VOL2_MASK 0 x00FE /* EQLMIX_VOL2 - [7:1] */ #define WM2200_EQLMIX_VOL2_SHIFT 1 /* EQLMIX_VOL2 - [7:1] */ #define WM2200_EQLMIX_VOL2_WIDTH 7 /* EQLMIX_VOL2 - [7:1] */ /* * R1620 ( 0 x654 ) - EQLMIX Input 3 Source #define WM2200_EQLMIX_SRC3_MASK 0 x007F /* EQLMIX_SRC3 - [6:0] */ #define WM2200_EQLMIX_SRC3_SHIFT 0 /* EQLMIX_SRC3 - [6:0] */ #define WM2200_EQLMIX_SRC3_WIDTH 7 /* EQLMIX_SRC3 - [6:0] */ /* * R1621 ( 0 x655 ) - EQLMIX Input 3 Volume #define WM2200_EQLMIX_VOL3_MASKdefine WM8961_ROUT2_VOLUME x29#define WM2200_EQLMIX_VOL3_SHIFT 1 /* EQLMIX_VOL3 - [7:1] */ WM8961_CLASS_D_CONTROL_2 0 x33#efine WM2200_EQLMIX_VOL3_WIDTH /* EQLMIX_VOL3 - [7:1] */ /* * R1622 ( 0 # x59 #define #define WM8961_IPVU_MASK java.lang.StringIndexOutOfBoundsException: Range [48, 24) out of bounds for length 66# WM2200_EQLMIX_SRC4_SHIFT0 * EQLMIX_SRC4 [: *//* EQLMIX_SRC4 - [6:0] */ /* * R1623 ( 0 x657 ) - EQLMIX define WM8961_IPVU_MASK java.lang.StringIndexOutOfBoundsException: Range [56, 54) out of bounds for length 66 # WM2200_EQLMIX_VOL4_MASK0 /h 81#define WM2200_EQLMIX_VOL4_WIDTH 7 /* EQLMIX_VOL4 - [7:1] */ /* * R1624 ( 0 x658 ) - EQRMIX Input 1 Source 0 x007F /* EQRMIX_SRC1 - [6:0] */ #define WM2200_EQRMIX_SRC1_SHIFT define7 java.lang.StringIndexOutOfBoundsException: Range [78, 79) out of bounds for length 78#define WM2200_EQRMIX_SRC1_WIDTH 7 /* EQRMIX_SRC1 - [6:0] */ /* * R1625 ( 0 x659 ) - EQRMIX Input 1 Volume #efine x0004 /* MCLKDIV */ #define WM2200_EQRMIX_VOL1_SHIFT 1 #define WM2200_EQRMIX_VOL1_WIDTH 7 /* EQRMIX_VOL1 - [7:1] */ /* * R1626 ( 0 x65A ) - EQRMIX Input 2 Source #define WM2200_EQRMIX_SRC2_MASK 0 x007F /* EQRMIX_SRC2 - [6:0] */ # WM2200_EQRMIX_SRC2_SHIFT /* EQRMIX_SRC2 - [6 :0 ] */#define WM2200_EQRMIX_SRC2_WIDTH 7 /** R1627 0 - EQRMIX 2 Volume #define WM2200_EQRMIX_VOL2_MASK 0 x00FE /* EQRMIX_VOL2 - [7:1] */ h 81#define WM2200_EQRMIX_VOL2_WIDTH 7 /* EQRMIX_VOL2 - [7:1] */ /* * R1628 ( 0 x65C ) - EQRMIX Input current configuration 0 x007F * -[6 :]*java.lang.StringIndexOutOfBoundsException: Range [81, 82) out of bounds for length 81#define WM2200_EQRMIX_SRC3_SHIFT 0 /* EQRMIX_SRC3 - [6:0] */ #define WM2200_EQRMIX_SRC3_WIDTH static int wm8994_put_retune_mobile_enumstruct kcontrol,/* 1#define }h 81/* * static aif2dacl_src , 0 x007F * EQRMIX_SRC4 - [6:0] */ #define /* EQRMIX_SRC4 - [6:0] */ #define java.lang.StringIndexOutOfBoundsException: Index 10 out of bounds for length 0/* * R1631 ( 0 #define WM2200_EQRMIX_VOL4_MASK 0 x00FE /* EQRMIX_VOL4 - [7:1] */ #define WM2200_EQRMIX_VOL4_SHIFT 1 /* EQRMIX_VOL4 - [7:1] */ #define WM2200_EQRMIX_VOL4_WIDTH 7 /* EQRMIX_VOL4 - [7:1] */ /* * R1632 ( 0 x660 ) - LHPF1MIX Input 1 Source #define WM2200_LHPF1MIX_SRC1_MASK 0 x007F /* LHPF1MIX_SRC1 - [6:0] */ #define WM2200_LHPF1MIX_SRC1_SHIFT 0 /* LHPF1MIX_SRC1 - [6:0] */ #define WM2200_LHPF1MIX_SRC1_WIDTH 7 /* LHPF1MIX_SRC1 - [6:0] */ /* * R1633 ( 0 x661 ) - LHPF1MIX Input 1 Volume #define WM2200_LHPF1MIX_VOL1_MASK 0 x00FE /* LHPF1MIX_VOL1 - [7:1] */ #define WM2200_LHPF1MIX_VOL1_SHIFT 1 /* LHPF1MIX_VOL1 - [7:1] */ #define WM2200_LHPF1MIX_VOL1_WIDTH 7 /* LHPF1MIX_VOL1 - [7:1] */ /* * R1634 ( 0 x662 ) - LHPF1MIX Input 2 Source #define WM2200_LHPF1MIX_SRC2_MASK 0 x007F /* LHPF1MIX_SRC2 - [6:0] */ #define WM2200_LHPF1MIX_SRC2_SHIFT 0 /* LHPF1MIX_SRC2 - [6:0] */ #define WM2200_LHPF1MIX_SRC2_WIDTH 7 /* LHPF1MIX_SRC2 - [6:0] */ /* * R1635 ( 0 x663 ) - LHPF1MIX Input 2 Volume #define WM2200_LHPF1MIX_VOL2_MASK 0 x00FE /* LHPF1MIX_VOL2 - [7:1] */ #define WM2200_LHPF1MIX_VOL2_SHIFT 1 /* LHPF1MIX_VOL2 - [7:1] */ #define WM2200_LHPF1MIX_VOL2_WIDTH 7 /* LHPF1MIX_VOL2 - [7:1] */ /* * R1636 ( 0 x664 ) - LHPF1MIX Input 3 Source #define WM2200_LHPF1MIX_SRC3_MASK 0 x007F /* LHPF1MIX_SRC3 - [6:0] */ #define WM2200_LHPF1MIX_SRC3_SHIFT 0 /* LHPF1MIX_SRC3 - [6:0] */ #define WM2200_LHPF1MIX_SRC3_WIDTH 7 /* LHPF1MIX_SRC3 - [6:0] */ /* * R1637 ( 0 x665 ) - LHPF1MIX Input 3 Volume #define WM2200_LHPF1MIX_VOL3_MASK 0 x00FE /* LHPF1MIX_VOL3 - [7:1] */ #define WM2200_LHPF1MIX_VOL3_SHIFT 1 /* LHPF1MIX_VOL3 - [7:1] */ #define WM2200_LHPF1MIX_VOL3_WIDTH 7 /* LHPF1MIX_VOL3 - [7:1] */ /* * R1638 ( 0 x666 ) - LHPF1MIX Input 4 Source #define WM2200_LHPF1MIX_SRC4_MASK 0 x007F /* LHPF1MIX_SRC4 - [6:0] */ #define WM2200_LHPF1MIX_SRC4_SHIFT 0 /* LHPF1MIX_SRC4 - [6:0] */ #define WM2200_LHPF1MIX_SRC4_WIDTH 7 /* LHPF1MIX_SRC4 - [6:0] */ /* * R1639 ( 0 x667 ) - LHPF1MIX Input 4 Volume #define WM2200_LHPF1MIX_VOL4_MASK 0 x00FE /* LHPF1MIX_VOL4 - [7:1] */ #define WM2200_LHPF1MIX_VOL4_SHIFT 1 /* LHPF1MIX_VOL4 - [7:1] */ #define WM2200_LHPF1MIX_VOL4_WIDTH 7 /* LHPF1MIX_VOL4 - [7:1] */ /* * R1640 ( 0 x668 ) - LHPF2MIX Input 1 Source #define WM2200_LHPF2MIX_SRC1_MASK 0 x007F /* LHPF2MIX_SRC1 - [6:0] */ #define WM2200_LHPF2MIX_SRC1_SHIFT 0 /* LHPF2MIX_SRC1 - [6:0] */ #define WM2200_LHPF2MIX_SRC1_WIDTH 7 /* LHPF2MIX_SRC1 - [6:0] */ /* * R1641 ( 0 x669 ) - LHPF2MIX Input 1 Volume #define WM2200_LHPF2MIX_VOL1_MASK 0 x00FE /* LHPF2MIX_VOL1 - [7:1] */ #define WM2200_LHPF2MIX_VOL1_SHIFT 1 /* LHPF2MIX_VOL1 - [7:1] */ #define WM2200_LHPF2MIX_VOL1_WIDTH 7 /* LHPF2MIX_VOL1 - [7:1] */ /* * R1642 ( 0 x66A ) - LHPF2MIX Input 2 Source #define WM2200_LHPF2MIX_SRC2_MASK 0 x007F /* LHPF2MIX_SRC2 - [6:0] */ #define WM2200_LHPF2MIX_SRC2_SHIFT 0 /* LHPF2MIX_SRC2 - [6:0] */ #define WM2200_LHPF2MIX_SRC2_WIDTH 7 /* LHPF2MIX_SRC2 - [6:0] */ /* * R1643 ( 0 x66B ) - LHPF2MIX Input 2 Volume #define WM2200_LHPF2MIX_VOL2_MASK 0 x00FE /* LHPF2MIX_VOL2 - [7:1] */ #define WM2200_LHPF2MIX_VOL2_SHIFT 1 /* LHPF2MIX_VOL2 - [7:1] */ #define WM2200_LHPF2MIX_VOL2_WIDTH 7 /* LHPF2MIX_VOL2 - [7:1] */ /* * R1644 ( 0 x66C ) - LHPF2MIX Input 3 Source #define WM2200_LHPF2MIX_SRC3_MASK 0 x007F /* LHPF2MIX_SRC3 - [6:0] */ #define WM2200_LHPF2MIX_SRC3_SHIFT 0 /* LHPF2MIX_SRC3 - [6:0] */ #define WM2200_LHPF2MIX_SRC3_WIDTH 7 /* LHPF2MIX_SRC3 - [6:0] */ /* * R1645 ( 0 x66D ) - LHPF2MIX Input 3 Volume #define WM2200_LHPF2MIX_VOL3_MASK 0 x00FE /* LHPF2MIX_VOL3 - [7:1] */ #define WM2200_LHPF2MIX_VOL3_SHIFT 1 /* LHPF2MIX_VOL3 - [7:1] */ #define WM2200_LHPF2MIX_VOL3_WIDTH 7 /* LHPF2MIX_VOL3 - [7:1] */ /* * R1646 ( 0 x66E ) - LHPF2MIX Input 4 Source #define WM2200_LHPF2MIX_SRC4_MASK 0 x007F /* LHPF2MIX_SRC4 - [6:0] */ #define WM2200_LHPF2MIX_SRC4_SHIFT 0 /* LHPF2MIX_SRC4 - [6:0] */ #define WM2200_LHPF2MIX_SRC4_WIDTH 7 /* LHPF2MIX_SRC4 - [6:0] */ /* * R1647 ( 0 x66F ) - LHPF2MIX Input 4 Volume #define WM2200_LHPF2MIX_VOL4_MASK 0 x00FE /* LHPF2MIX_VOL4 - [7:1] */ #define WM2200_LHPF2MIX_VOL4_SHIFT 1 /* LHPF2MIX_VOL4 - [7:1] */ #define WM2200_LHPF2MIX_VOL4_WIDTH 7 /* LHPF2MIX_VOL4 - [7:1] */ /* * R1648 ( 0 x670 ) - DSP1LMIX Input 1 Source #define WM2200_DSP1LMIX_SRC1_MASK 0 x007F /* DSP1LMIX_SRC1 - [6:0] */ #define WM2200_DSP1LMIX_SRC1_SHIFT 0 /* DSP1LMIX_SRC1 - [6:0] */ #define WM2200_DSP1LMIX_SRC1_WIDTH 7 /* DSP1LMIX_SRC1 - [6:0] */ /* * R1649 ( 0 x671 ) - DSP1LMIX Input 1 Volume #define WM2200_DSP1LMIX_VOL1_MASK 0 x00FE /* DSP1LMIX_VOL1 - [7:1] */ #define WM2200_DSP1LMIX_VOL1_SHIFT 1 /* DSP1LMIX_VOL1 - [7:1] */ #define WM2200_DSP1LMIX_VOL1_WIDTH 7 /* DSP1LMIX_VOL1 - [7:1] */ /* * R1650 ( 0 x672 ) - DSP1LMIX Input 2 Source #define WM2200_DSP1LMIX_SRC2_MASK 0 x007F /* DSP1LMIX_SRC2 - [6:0] */ #define WM2200_DSP1LMIX_SRC2_SHIFT 0 /* DSP1LMIX_SRC2 - [6:0] */ #define WM2200_DSP1LMIX_SRC2_WIDTH 7 /* DSP1LMIX_SRC2 - [6:0] */ /* * R1651 ( 0 x673 ) - DSP1LMIX Input 2 Volume #define WM2200_DSP1LMIX_VOL2_MASK 0 x00FE /* DSP1LMIX_VOL2 - [7:1] */ #define WM2200_DSP1LMIX_VOL2_SHIFT 1 /* DSP1LMIX_VOL2 - [7:1] */ #define WM2200_DSP1LMIX_VOL2_WIDTH 7 /* DSP1LMIX_VOL2 - [7:1] */ /* * R1652 ( 0 x674 ) - DSP1LMIX Input 3 Source #define WM2200_DSP1LMIX_SRC3_MASK 0 x007F /* DSP1LMIX_SRC3 - [6:0] */ #define WM2200_DSP1LMIX_SRC3_SHIFT 0 /* DSP1LMIX_SRC3 - [6:0] */ #define WM2200_DSP1LMIX_SRC3_WIDTH 7 /* DSP1LMIX_SRC3 - [6:0] */ /* * R1653 ( 0 x675 ) - DSP1LMIX Input 3 Volume #define WM2200_DSP1LMIX_VOL3_MASK 0 x00FE /* DSP1LMIX_VOL3 - [7:1] */ #define WM2200_DSP1LMIX_VOL3_SHIFT 1 /* DSP1LMIX_VOL3 - [7:1] */ #define WM2200_DSP1LMIX_VOL3_WIDTH 7 /* DSP1LMIX_VOL3 - [7:1] */ /* * R1654 ( 0 x676 ) - DSP1LMIX Input 4 Source #define WM2200_DSP1LMIX_SRC4_MASK 0 x007F /* DSP1LMIX_SRC4 - [6:0] */ #define WM2200_DSP1LMIX_SRC4_SHIFT 0 /* DSP1LMIX_SRC4 - [6:0] */ #define WM2200_DSP1LMIX_SRC4_WIDTH 7 /* DSP1LMIX_SRC4 - [6:0] */ /* * R1655 ( 0 x677 ) - DSP1LMIX Input 4 Volume #define WM2200_DSP1LMIX_VOL4_MASK 0 x00FE /* DSP1LMIX_VOL4 - [7:1] */ #define WM2200_DSP1LMIX_VOL4_SHIFT 1 /* DSP1LMIX_VOL4 - [7:1] */ #define WM2200_DSP1LMIX_VOL4_WIDTH 7 /* DSP1LMIX_VOL4 - [7:1] */ /* * R1656 ( 0 x678 ) - DSP1RMIX Input 1 Source #define WM2200_DSP1RMIX_SRC1_MASK 0 x007F /* DSP1RMIX_SRC1 - [6:0] */ #define WM2200_DSP1RMIX_SRC1_SHIFT 0 /* DSP1RMIX_SRC1 - [6:0] */ #define WM2200_DSP1RMIX_SRC1_WIDTH 7 /* DSP1RMIX_SRC1 - [6:0] */ /* * R1657 ( 0 x679 ) - DSP1RMIX Input 1 Volume #define WM2200_DSP1RMIX_VOL1_MASK 0 x00FE /* DSP1RMIX_VOL1 - [7:1] */ #define WM2200_DSP1RMIX_VOL1_SHIFT 1 /* DSP1RMIX_VOL1 - [7:1] */ #define WM2200_DSP1RMIX_VOL1_WIDTH 7 /* DSP1RMIX_VOL1 - [7:1] */ /* * R1658 ( 0 x67A ) - DSP1RMIX Input 2 Source #define WM2200_DSP1RMIX_SRC2_MASK 0 x007F /* DSP1RMIX_SRC2 - [6:0] */ #define WM2200_DSP1RMIX_SRC2_SHIFT 0 /* DSP1RMIX_SRC2 - [6:0] */ #define WM2200_DSP1RMIX_SRC2_WIDTH 7 /* DSP1RMIX_SRC2 - [6:0] */ /* * R1659 ( 0 x67B ) - DSP1RMIX Input 2 Volume #define WM2200_DSP1RMIX_VOL2_MASK 0 x00FE /* DSP1RMIX_VOL2 - [7:1] */ #define WM2200_DSP1RMIX_VOL2_SHIFT 1 /* DSP1RMIX_VOL2 - [7:1] */ #define WM2200_DSP1RMIX_VOL2_WIDTH 7 /* DSP1RMIX_VOL2 - [7:1] */ /* * R1660 ( 0 x67C ) - DSP1RMIX Input 3 Source # WM2200_DSP1RMIX_SRC3_MASK 0 x007F /* DSP1RMIX_SRC3 - [6:0] */ #define java.lang.StringIndexOutOfBoundsException: Index 14 out of bounds for length 1#define WM2200_DSP1RMIX_SRC3_WIDTH 7 /* DSP1RMIX_SRC3 - [6:0] */ /* * R1661 ( 0 x67D ) - DSP1RMIX Input 3 Volume #define WM2200_DSP1RMIX_VOL3_MASK 0 x00FE /* DSP1RMIX_VOL3 - [7:1] */ #define WM2200_DSP1RMIX_VOL3_SHIFT 1 /* DSP1RMIX_VOL3 - [7:1] */ #define WM2200_DSP1RMIX_VOL3_WIDTH 7 /* DSP1RMIX_VOL3 - [7:1] */ /* * R1662 ( 0 x67E ) - DSP1RMIX Input 4 Source #define WM2200_DSP1RMIX_SRC4_MASK 0 x007F /* DSP1RMIX_SRC4 - [6:0] */ # WM2200_DSP1RMIX_SRC4_SHIFT /* DSP1RMIX_SRC4 - [6:0] */ #define WM2200_DSP1RMIX_SRC4_WIDTH 7 /* DSP1RMIX_SRC4 - [6:0] */ *R15(x0F) - Reset/* * R1663 ( 0 x67F ) - DSP1RMIX Input 4 Volume #define definejava.lang.StringIndexOutOfBoundsException: Range [53, 26) out of bounds for length 67#define WM2200_DSP1RMIX_VOL4_SHIFT define0 /* HLD - [3:0] */ #define WM2200_DSP1RMIX_VOL4_WIDTH 7 /* DSP1RMIX_VOL4 - [7:1] */ /** R1664 0 - DSP1AUX1MIX 1 Source #define WM2200_DSP1AUX1MIX_SRC1_MASK 0 x007F /* DSP1AUX1MIX_SRC1 - [6:0] */ #define WM2200_DSP1AUX1MIX_SRC1_SHIFT # 0 java.lang.StringIndexOutOfBoundsException: Index 65 out of bounds for length 65h 86/* * R1665 ( 0 x681 ) - DSP1AUX2MIX Input 1 Source #define WM2200_DSP1AUX2MIX_SRC1_MASK 0 x007F /* DSP1AUX2MIX_SRC1 - [6:0] */ #define #define M8961_ADCVU0 /#define define WM8961_ADCVU_WIDTH 1 /* ADCVU */ /* * R1666 ( 0 x682 ) - DSP1AUX3MIX Input 1 Source #define WM2200_DSP1AUX3MIX_SRC1_MASK 0 x007FdefineW0 x0001/* TOEN */ #define WM2200_DSP1AUX3MIX_SRC1_SHIFT 0 /* DSP1AUX3MIX_SRC1 - [6:0] */ 7 /* DSP1AUX3MIX_SRC1 - [6:0] */ /* * R1667 ( 0 x683 ) - DSP1AUX4MIX Input 1 Source #define WM2200_DSP1AUX4MIX_SRC1_MASK 0 x007F /* DSP1AUX4MIX_SRC1 - [6:0] */ #define WM2200_DSP1AUX4MIX_SRC1_SHIFT 0 /* DSP1AUX4MIX_SRC1 - [6:0] */ #define WM2200_DSP1AUX4MIX_SRC1_WIDTH 7 /* DSP1AUX4MIX_SRC1 - [6:0] */ /* * R1668 ( 0 x684 ) - DSP1AUX5MIX Input 1 Source #define " ,WM8994_SPKMIXR_ATTENUATION, #define WM2200_DSP1AUX5MIX_SRC1_SHIFT , ,1 ,15 /* * R1669 ( 0 x685 ) - DSP1AUX6MIX Input 1 Source #define WM2200_DSP1AUX6MIX_SRC1_SHIFT ,119 ,0 ,digital_tlv,#define java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0/* * R1670 ( 0 x686 ) - DSP2LMIX Input 1 Source #define WM2200_DSP2LMIX_SRC1_MASK 0 x007F /* DSP2LMIX_SRC1 - [6:0] */ #define SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0, #define WM2200_DSP2LMIX_SRC1_WIDTH 7 /* DSP2LMIX_SRC1 - [6:0] */ /* * R1671 ( 0 x687 ) - DSP2LMIX Input 1 WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1 java.lang.StringIndexOutOfBoundsException: Range [29, 28) out of bounds for length 57 0 x00FE /* DSP2LMIX_VOL1 - [7:1] */ #define WM2200_DSP2LMIX_VOL1_WIDTH )/** R1672 0 ) Input 2 Source #define WM2200_DSP2LMIX_SRC2_MASK 0 java.lang.StringIndexOutOfBoundsException: Range [0, 54) out of bounds for length 22#define WM2200_DSP2LMIX_SRC2_SHIFT 0 /* DSP2LMIX_SRC2 - [6:0] */ #define WM2200_DSP2LMIX_SRC2_WIDTH 7 /* DSP2LMIX_SRC2 - [6:0] */ /* * R1673 ( 0 x689 ) - DSP2LMIX Input 2 Volume #define WM2200_DSP2LMIX_VOL2_MASK 0 x00FE /* DSP2LMIX_VOL2 - [7:1] */ #define WM2200_DSP2LMIX_VOL2_SHIFT 1 /* DSP2LMIX_VOL2 - [7:1] */ #define WM2200_DSP2LMIX_VOL2_WIDTH 7 /* DSP2LMIX_VOL2 - [7:1] */ /* R1674 ( 0 - DSP2LMIX 3 Source #define WM2200_DSP2LMIX_SRC3_MASK 0 x007F /* DSP2LMIX_SRC3 - [6:0] */ #define WM2200_DSP2LMIX_SRC3_SHIFT 0 /* DSP2LMIX_SRC3 - [6:0] */ #define WM2200_DSP2LMIX_SRC3_WIDTH 7 /* DSP2LMIX_SRC3 - [6:0] */ /* * R1675 ( 0 x68B ) - DSP2LMIX Input 3 Volume #define WM2200_DSP2LMIX_VOL3_MASK 0 x00FE /* DSP2LMIX_VOL3 - [7:1] */ #define WM2200_DSP2LMIX_VOL3_SHIFT 1 /* DSP2LMIX_VOL3 - [7:1] */ #define WM2200_DSP2LMIX_VOL3_WIDTH 7 /* DSP2LMIX_VOL3 - [7:1] */ /* * R1676 ( 0 x68C ) - DSP2LMIX Input 4 Source #define WM2200_DSP2LMIX_SRC4_MASK 0 x007F /* DSP2LMIX_SRC4 - [6:0] */ #define WM2200_DSP2LMIX_SRC4_SHIFT 0 /* DSP2LMIX_SRC4 - [6:0] */ #define WM2200_DSP2LMIX_SRC4_WIDTH 7 /* DSP2LMIX_SRC4 - [6:0] */ /* * R1677 ( 0 x68D ) - DSP2LMIX # efine 1 / * * / #define WM2200_DSP2LMIX_VOL4_MASK 0 x00FE /* DSP2LMIX_VOL4 - [7:1] */ #define WM2200_DSP2LMIX_VOL4_SHIFT 1 /* DSP2LMIX_VOL4 - [7:1] */ #define define WM8961_MICBjava.lang.StringIndexOutOfBoundsException: Range [56, 54) out of bounds for length 660 x0100 /* DACL */ 0 x68E) - #define WM8961_DACL_WIDTH1 /#define WM2200_DSP2RMIX_SRC1_MASK 0 x007F /* DSP2RMIX_SRC1 - [6:0] */ #define WM2200_DSP2RMIX_SRC1_SHIFT 0 /* DSP2RMIX_SRC1 - [6:0] */ #define WM2200_DSP2RMIX_SRC1_WIDTH 7 /* DSP2RMIX_SRC1 - [6:0] */ /*) - DSP2RMIX Volume /* DSP2RMIX_VOL1 - [7:1] */ #define WM2200_DSP2RMIX_VOL1_SHIFT 1 /* DSP2RMIX_VOL1 - [7:1] */ #define WM2200_DSP2RMIX_VOL1_WIDTH 7 /* DSP2RMIX_VOL1 - [7:1] */ /* * 7 , ng_tlv , #define WM2200_DSP2RMIX_SRC2_SHIFT 0 /* DSP2RMIX_SRC2 - [6:0] */ # 7 /* DSP2RMIX_SRC2 - [6:0] */ /* * R1681 ( 0 x691 ) - DSP2RMIX Input 2 Volume #mutex_lock (wm8994>;#define dev_dbg(component->dev, "Active decremented %\", # WM2200_DSP2RMIX_VOL2_WIDTH /* DSP2RMIX_VOL2 - [7:1] */ /* * R1682 ( 0 x692 struct * = snd_soc_dapm_to_component ( w - > apm ) ; #define WM2200_DSP2RMIX_SRC3_MASK 0 x007F /* DSP2RMIX_SRC3 - [6:0] */ #define WM2200_DSP2RMIX_SRC3_SHIFT 0 /* DSP2RMIX_SRC3 - [6:0] */ #define * don't want /* * R1683 ( 0 x693 ) - DSP2RMIX Input 3 Volume # wm899 wm8994-v;#define WM2200_DSP2RMIX_VOL3_SHIFT 1 /* DSP2RMIX_VOL3 - [7:1] */ 3 W 7 /* DSP2RMIX_VOL3 - [7:1] */ /* ( x2 < WM8994_VMID_RAMP_SHIFT ) java.lang.StringIndexOutOfBoundsException: Index 42 out of bounds for length 42 # break #define WM2200_DSP2RMIX_SRC4_SHIFT 0 /* DSP2RMIX_SRC4 - [6:0] */ # WM2200_DSP2RMIX_SRC4_WIDTH 7 /* DSP2RMIX_SRC4 [:] //** R1685 ( ) - DSP2RMIX 4 Volume 0 /* DSP2RMIX_VOL4 - [7:1] */ #define WM2200_DSP2RMIX_VOL4_SHIFT 1 /* DSP2RMIX_VOL4 - [7:1] */ #define WM2200_DSP2RMIX_VOL4_WIDTH 7 /* DSP2RMIX_VOL4 - [7:1] */ /* * R30 ( x1E ) - Clocking 3 #define WM2200_DSP2AUX1MIX_SRC1_MASK 0 x007F /* DSP2AUX1MIX_SRC1 - [6:0] */ 0 /* DSP2AUX1MIX_SRC1 - [6:0] */ #define #define 0 x0001 /* MANUAL_MODE */ /* * R1687 ( 0 x697 ) - # 4 /* DSP2AUX2MIX_SRC1 - [6:0] */ #define * R40 (0x28 volume#define #define WM8961_SPKVU_MASK 0 x0100 /* SPKVU */ /* * R1688 ( 0 x698 ) - DSP2AUX3MIX Input 1 Source #define java.lang.StringIndexOutOfBoundsException: Index 17 out of bounds for length 3#define WM2200_DSP2AUX3MIX_SRC1_SHIFT 0 /* DSP2AUX3MIX_SRC1 - [6:0] */ #define WM2200_DSP2AUX3MIX_SRC1_WIDTH 7 /* DSP2AUX3MIX_SRC1 - [6:0] */ /* * R1689 ( 0 x699 ) - DSP2AUX4MIX Input 1 Source #define WM2200_DSP2AUX4MIX_SRC1_MASK 0 x007F /* DSP2AUX4MIX_SRC1 - [6:0] */ 86#define WM2200_DSP2AUX4MIX_SRC1_WIDTH 7 /* DSP2AUX4MIX_SRC1 - [6:0] */ /* * # WM8961_MBSEL_MASK 0 x0001 / #define WM2200_DSP2AUX5MIX_SRC1_MASK 0 x007F /* DSP2AUX5MIX_SRC1 - [6:0] */ #define WM2200_DSP2AUX5MIX_SRC1_SHIFT 0 /* DSP2AUX5MIX_SRC1 - [6:0] */ #define WM2200_DSP2AUX5MIX_SRC1_WIDTH 7 /* DSP2AUX5MIX_SRC1 - [6:0] */ /* * R1691 ( 0 x69B * #define * R56 (0x38) - Clocking#define M2200_DSP2AUX6MIX_SRC1_SHIFT 0 /* DSP2AUX6MIX_SRC1 - [6:0] */ #define WM2200_DSP2AUX6MIX_SRC1_WIDTH 7 /* DSP2AUX6MIX_SRC1 - [6:0] */ /* * s ( component , WM8994_ANTIPOP_2 , #define WM2200_GP1_DIR 0 x8000 /* GP1_DIR */ #define snd_soc_component_update_bits ,#define WM2200_GP1_DIR_SHIFT 15 /* GP1_DIR */ #define WM2200_GP1_DIR_WIDTH 1 /* GP1_DIR */ #define WM2200_GP1_PU 0 x4000 /* GP1_PU */ #define java.lang.StringIndexOutOfBoundsException: Index 12 out of bounds for length 1#define WM2200_GP1_PU_SHIFT 14 /* GP1_PU */ #define WM2200_GP1_PU_WIDTH 1 /* GP1_PU */ # WM2200_GP1_PD 0 x2000 /* GP1_PD */ #define eg=snd_soc_component_readcomponent,WM8994_DAC1_LEFT_MIXER_ROUTING#define WM2200_GP1_PD_SHIFT 13 /* GP1_PD */ #define WM2200_GP1_PD_WIDTH 1 /* GP1_PD */ 0 /* GP1_POL */ #define WM2200_GP1_POL_MASK}# dev_vdbg component-d L rightDACmixersdifferent\n"; #define snd_soc_component_update_bits(component, WM8994_CLASS_W_1,#define WM2200_GP1_OP_CFG 0 x0200 /* GP1_OP_CFG */ #define WM2200_GP1_OP_CFG_MASK nti;# WM2200_GP1_OP_CFG_SHIFT9 /* GP1_OP_CFG */ #define WM2200_GP1_OP_CFG_WIDTHfor =0 ;i () i+#define WM2200_GP1_DB 0 x0100 /* GP1_DB */ #define WM2200_GP1_DB_MASK 0 x0100 /* GP1_DB */ #define WM2200_GP1_DB_SHIFT 8 /* GP1_DB */ 1 /* GP1_DB */ #define =WM8994_MCLK1java.lang.StringIndexOutOfBoundsException: Index 25 out of bounds for length 25#define WM2200_GP1_LVL_MASK java.lang.StringIndexOutOfBoundsException: Index 2 out of bounds for length 22200 G6 /* GP1_LVL */ #define WM2200_GP1_LVL_WIDTH 1 /* GP1_LVL */ #define WM2200_GP1_FN_MASK 0 x003Fstatic int s snd_soc_dapm_widget *w,#define WM2200_GP1_FN_SHIFTstruct *wm8994 snd_soc_component_get_drvdatacomponent)java.lang.StringIndexOutOfBoundsException: Index 71 out of bounds for length 71#define nt adc;/*; * R1793 ( 0 x701 ) - GPIO CTRL 2 #define WM2200_GP2_DIR 0 x8000 /* GP2_DIR */ #define WM2200_GP2_DIR_MASK 0 x8000 /* GP2_DIR */ #define WM2200_GP2_DIR_SHIFT 15 /* GP2_DIR */ /* GP2_DIR */ #define WM2200_GP2_PU 0 x4000 /* GP2_PU */ #define WM2200_GP2_PU_MASK 0 x4000 /* GP2_PU */ #define define WM8961_ADC_TO_DACL_SHIFT2 /* ADC_TO_DACL - [3:2] */ #define WM2200_GP2_PU_WIDTH 1 /* GP2_PU */ # WM2200_GP2_PD 0 x2000 /* GP2_PD */ 0 x2000 /* GP2_PD */ #define WM2200_GP2_PD_SHIFT 13 /* GP2_PD */ java.lang.StringIndexOutOfBoundsException: Range [68, 69) out of bounds for length 68#define WM2200_GP2_POL 0 x0400 /* GP2_POL */ #define WM2200_GP2_POL_MASK 0 x0400 /* GP2_POL */ /* GP2_POL */ #define WM2200_GP2_POL_WIDTH 1 /* GP2_POL */ #define WM2200_GP2_OP_CFG 0 x0200 /* GP2_OP_CFG */ #define WM2200_GP2_OP_CFG_MASK x0200 * GP2_OP_CFG */ #define WM2200_GP2_OP_CFG_SHIFT 9 /* GP2_OP_CFG */ 1 /* GP2_OP_CFG */ #define WM2200_GP2_DB 0 x0100 /* GP2_DB */ #define WM2200_GP2_DB_MASK 0 x0100 /* GP2_DB */ 8 /* GP2_DB */ #define WM2200_GP2_DB_WIDTH 1 /* GP2_DB */ #define WM2200_GP2_LVL 0 x0040 /* GP2_LVL */ #define WM2200_GP2_LVL_MASK 0 x0040 /* GP2_LVL */ #define WM2200_GP2_LVL_SHIFT 6 /* GP2_LVL */ #define WM2200_GP2_LVL_WIDTH /#define WM2200_GP2_FN_MASK 0 /* GP2_FN - [5:0] */ # WM2200_GP2_FN_SHIFT0 *GP2_FN [0 /6 / [5 :]*//* * R1794 ( 0 x702 ) - GPIO CTRL 3 #define WM2200_GP3_DIR 0 x8000 /* GP3_DIR */ # WM2200_GP3_DIR_MASK 0 x8000 /* GP3_DIR */ #define WM2200_GP3_DIR_SHIFT 15 /* GP3_DIR */ #define WM2200_GP3_DIR_WIDTH#define WM2200_GP3_PU adc=WM8994_AIF1ADC1R_ENA ;0 x4000/* GP3_PU */ #define WM2200_GP3_PU_SHIFT 14 /* GP3_PU */ # /* GP3_PU */ #define java.lang.StringIndexOutOfBoundsException: Index 13 out of bounds for length 6# /* GP3_PD */ #define WM2200_GP3_PD_SHIFT 13 java.lang.StringIndexOutOfBoundsException: Range [68, 69) out of bounds for length 68#define WM2200_GP3_PD_WIDTH 1 WM8994_AIF1ADC2R_ENA |#define WM2200_GP3_POL 0 x0400 /* GP3_POL */ #define WM2200_GP3_POL_MASKwm8994_update_vu_bits(;#define SND_SOC_DAPM_POST_PMD#define WM2200_GP3_POL_WIDTH ,0 ;#define WM2200_GP3_OP_CFG 0 x0200 /* GP3_OP_CFG */ val =WM8994_SYSDSPCLK_ENA;#define WM2200_GP3_OP_CFG_MASK 0 x0200 /* GP3_OP_CFG */ WM8994_AIF1DSPCLK_ENA,val)java.lang.StringIndexOutOfBoundsException: Index 36 out of bounds for length 36#define WM2200_GP3_OP_CFG_SHIFT 9 /* GP3_OP_CFG */ static aif2clk_evstruct snd_soc_dapm_widgetwjava.lang.StringIndexOutOfBoundsException: Index 52 out of bounds for length 52# WM2200_GP3_DB_MASK0 /#define WM2200_GP3_DB_SHIFT 8 /* GP3_DB */ #define adc java.lang.StringIndexOutOfBoundsException: Index 29 out of bounds for length 29#define WM2200_GP3_LVL 0 x0040 /* GP3_LVL */ #define WM2200_GP3_LVL_MASK 0 x0040 /* GP3_LVL */ #define WM2200_GP3_LVL_SHIFT 6 /* GP3_LVL */ # WM2200_GP3_LVL_WIDTH 1 /* GP3_LVL */ #define WM2200_GP3_FN_MASK 0 x003F /* GP3_FN - [5:0] */ #define WM2200_GP3_FN_SHIFT 0 /* GP3_FN - [5:0] */ #define WM2200_GP3_FN_WIDTH 6 /* GP3_FN - [5:0] */ /* * java.lang.StringIndexOutOfBoundsException: Index 7 out of bounds for length 0 #define WM2200_GP4_DIR 0 x8000 /* GP4_DIR */ #define WM2200_GP4_DIR_MASK 0 x8000 /* GP4_DIR */ 15 / *#define WM2200_GP4_DIR_WIDTH 1 /* GP4_DIR */ #define WM2200_GP4_PU 0 x4000 /* GP4_PU */ #define WM2200_GP4_PU_MASK 0 x4000 /* GP4_PU */ #define WM2200_GP4_PU_SHIFT 14 /* GP4_PU */ #define #define WM2200_GP4_PD 0 x2000 /* GP4_PD */ 0 /* GP4_PD */ #define WM2200_GP4_PD_SHIFT 13 /* GP4_PD */ ##define WM8961_HPL_ENA_OUTP_SHIFT6 /#define WM2200_GP4_POL 0 x0400 /* GP4_POL */ # java.lang.StringIndexOutOfBoundsException: Range [53, 32) out of bounds for length 73#define WM2200_GP4_POL_SHIFT 10 /* GP4_POL */ #define WM8961_HPL_ENA_SHIFT4 /* HPL_ENA */ #define WM2200_GP4_POL_WIDTH 1 /* GP4_POL */ */#define WM8961_HPR_RMV_SHORT_WIDTH/* HPR_RMV_SHORT */ #define WM2200_GP4_OP_CFG_MASK 0 x0200 /* GP4_OP_CFG */ #define #efine M8961_HPR_ENA_DLY x #define WM2200_GP4_OP_CFG_WIDTH 1 /* GP4_OP_CFG */ #define define WM8961_HPR_ENA_MASKx0001 /* HPR_ENA */ #define #define WM2200_GP4_DB_SHIFT 8 /* GP4_DB */ #define WM2200_GP4_DB_WIDTH 1 /* GP4_DB */ #define WM2200_GP4_LVL 0 x0040 /* GP4_LVL */ #define WM2200_GP4_LVL_MASK 0 x0040 /* GP4_LVL */ #define WM2200_GP4_LVL_WIDTH 1 /* GP4_LVL */ #define WM2200_GP4_FN_MASK #define WM2200_GP4_FN_SHIFT 0 /* GP4_FN - [5:0] */ #define WM2200_GP4_FN_WIDTH 6 /* GP4_FN - [5:0] */ /* ( 0 x707 ) - ADPS1 #define WM2200_DSP_IRQ1 0 x0002 java.lang.StringIndexOutOfBoundsException: Index 8 out of bounds for length 8#define WM2200_DSP_IRQ1_MASK 0 x0002 /* DSP_IRQ1 */ #define WM2200_DSP_IRQ1_SHIFT 1 /* DSP_IRQ1/#define java.lang.StringIndexOutOfBoundsException: Index 17 out of bounds for length 0#define WM2200_DSP_IRQ0 snd_soc_component_update_bits0 /* DSP_IRQ0 */ #define WM2200_DSP_IRQ0_SHIFT 0 /* DSP_IRQ0 */ #define wm8994-aif2clk_enable= 0 java.lang.StringIndexOutOfBoundsException: Index 30 out of bounds for length 30/* * R1800 ( 0 x708 ) - ADPS1 IRQ1 #define WM2200_DSP_IRQ3 */# /* DSP_IRQ3 */ #define WM2200_DSP_IRQ3_SHIFT 1 /* DSP_IRQ3 */ #define WM2200_DSP_IRQ3_WIDTH 1 /* DSP_IRQ3 */ #define wm8994-aif2clk_disable =0 java.lang.StringIndexOutOfBoundsException: Range [31, 32) out of bounds for length 31#define WM2200_DSP_IRQ2_MASK 0 x0001 /* DSP_IRQ2 */ #define WM2200_DSP_IRQ2_SHIFT 0 /* DSP_IRQ2 */ #define WM2200_DSP_IRQ2_WIDTH 1 /* DSP_IRQ2 */ /* * R1801 static dac_ev struct snd_soc_dapm_widget * ption: Index 48 out of bounds for length 48 #define WM2200_LDO1ENA_PD 0 x8000 /* LDO1ENA_PD */ #define WM2200_LDO1ENA_PD_MASK 0 x8000 /* LDO1ENA_PD */ #define java.lang.StringIndexOutOfBoundsException: Index 21 out of bounds for length 8#define WM2200_LDO1ENA_PD_WIDTH 1 /* LDO1ENA_PD */ 0 x2000 /* MCLK2_PD */ #define WM2200_MCLK2_PD_MASK 0 static const struct snd_kcontrol_new left_speaker_mixer3 /* MCLK2_PD */ #define WM2200_MCLK2_PD_WIDTH#define 0 x0020 * WSEQ_ENA */ #define WM2200_MCLK1_PD 0 x1000 /* MCLK1_PD */ /* MCLK1_PD */ #define WM2200_MCLK1_PD_SHIFT 12 /* MCLK1_PD */ #define WM2200_MCLK1_PD_WIDTH 1 /* MCLK1_PD */ #define WM2200_DACLRCLK1_PU 0 x0400 /* DACLRCLK1_PU */ #define #define WM8961_WSEQ_EOS_SHIFT8 /* /#define WM2200_DACLRCLK1_PU_SHIFT 10 /* DACLRCLK1_PU */ /* DACLRCLK1_PU */ #define WM2200_DACLRCLK1_PD 0 x0200 /* DACLRCLK1_PD */ #define WM2200_DACLRCLK1_PD_MASK 0 x0200 /* DACLRCLK1_PD */ ("Switch,WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING#define WM8961_WSEQ_DATA_SHIFT /* WSEQ_DATA - [7:0] */ static struct snd_kcontrol_new aif1adc1r_mix[ ={#define WM2200_DACLRCLK1_PD_WIDTH 1 /* DACLRCLK1_PD */ #define WM2200_BCLK1_PU 0 define WM8961_WSEQ_ABORT_MASK 0x0100#define WM2200_BCLK1_PU_SHIFT 8 /* BCLK1_PU */ # 0 ,#define WM2200_BCLK1_PD 0 x0080 /* BCLK1_PD */ /* BCLK1_PD */ #define WM2200_BCLK1_PD_SHIFT 7 /* BCLK1_PD */ /* WSEQ_DATA_WIDTH - [6:4] */ #define WM2200_DACDAT1_PU 0 x0040 /* DACDAT1_PU */ #static const define WM8961_WSEQ_DATA_START_WIDTH [#define * R92 (0x5C) - Write Sequencer#define WM2200_DACDAT1_PU_WIDTH 1 /* DACDAT1_PU */ #define WM2200_DACDAT1_PD 0 x0020 /* DACDAT1_PD */ #define WM2200_DACDAT1_PD_MASK 0 x0020 /* DACDAT1_PD */ (x5D) Sequencer#define WM2200_DACDAT1_PD_SHIFT 5 /* DACDAT1_PD */ #define WM2200_DACDAT1_PD_WIDTH 1 /* DACDAT1_PD */ tructsnd_ctl_elem_value*1 java.lang.StringIndexOutOfBoundsException: Index 71 out of bounds for length 71* DMICDAT3_PD */ #define WM2200_DMICDAT3_PD_MASK 0 x0010 /* DMICDAT3_PD */ _ 4 *DMICDAT3_PD1 /* DMICDAT3_PD */ # #define WM8961_AUTO_INC_WIDTH 1 / #define WM2200_DMICDAT2_PD_MASK 0 x0008 /* DMICDAT2_PD */ #define WM2200_DMICDAT2_PD_SHIFT 3 /* DMICDAT2_PD */ #define WM2200_DMICDAT2_PD_WIDTH 1 /* DMICDAT2_PD */ #define java.lang.StringIndexOutOfBoundsException: Index 25 out of bounds for length 17#define WM2200_DMICDAT1_PD_MASK 0 x0004 /* DMICDAT1_PD */ #define WM2200_DMICDAT1_PD_SHIFT 2 /* DMICDAT1_PD */ #define WM2200_DMICDAT1_PD_WIDTH 1 /* DMICDAT1_PD */ #define java.lang.StringIndexOutOfBoundsException: Index 17 out of bounds for length 0#define WM2200_RSTB_PU_MASK 0 x0002 /* RSTB_PU */ #SOC_DAPM_ENUM ("Right " , sidetone2_enum);1 /* RSTB_PU */ #define static const charloopback_text[] = {#define WM2200_ADDR_PD_MASK 0 x0001 /* ADDR_PD */ #define WM2200_ADDR_PD_SHIFT 0 /* ADDR_PD */ #define WM2200_ADDR_PD_WIDTH 1 /* ADDR_PD */ /* #define WM2200_DSP_IRQ0_EINT0 x0080 * DSP_IRQ0_EINT */ #define WM2200_DSP_IRQ0_EINT_MASK 0 x0080 /* DSP_IRQ0_EINT */ const =#define WM2200_DSP_IRQ0_EINT_WIDTH 1 /* DSP_IRQ0_EINT */ 0 x0040 # WM2200_DSP_IRQ1_EINT_MASK0 x0040 /* DSP_IRQ1_EINT */ # WM2200_DSP_IRQ1_EINT_SHIFT /* DSP_IRQ1_EINT */ DSP_IRQ1_EINT*#define java.lang.StringIndexOutOfBoundsException: Index 21 out of bounds for length 2#define WM2200_DSP_IRQ2_EINT 0 x0020 /* DSP_IRQ2_EINT */ #define WM2200_DSP_IRQ2_EINT_MASK 0 x0020 /* DSP_IRQ2_EINT */ #define WM2200_DSP_IRQ2_EINT_SHIFT 5 /* DSP_IRQ2_EINT */ #define WM2200_DSP_IRQ2_EINT_WIDTH 1 /* DSP_IRQ2_EINT */ static const char *] java.lang.StringIndexOutOfBoundsException: Index 42 out of bounds for length 42#define WM2200_DSP_IRQ3_EINT 0 x0010 /* DSP_IRQ3_EINT */ #define WM2200_DSP_IRQ3_EINT_MASK 0 x0010 /* DSP_IRQ3_EINT */ #define WM2200_DSP_IRQ3_EINT_SHIFT 4 /* DSP_IRQ3_EINT */ # WM2200_GP4_EINT0 x0008/#define WM2200_GP4_EINT_MASK 0 static const struct snd_kcontrol_new aif2dacr_src_mux =#define WM2200_GP4_EINT_SHIFT 3 /* GP4_EINT */ #define WM2200_GP4_EINT_WIDTH 1 /* GP4_EINT */ #define WM2200_GP3_EINT 0 x0004 /* GP3_EINT */ # 0 x0004 * GP3_EINT */ #define WM2200_GP3_EINT_SHIFT 2 ("ate PGA" ,0 ,0 , tion: Index 72 out of bounds for length 72#define WM2200_GP3_EINT_WIDTH 1 /* GP3_EINT */ #define WM2200_GP2_EINT 0 x0002 /* GP2_EINT */ #define WM2200_GP2_EINT_MASK ("PKL" ,8 ,1 /* GP2_EINT */ #define WM2200_GP2_EINT_WIDTH 1 /* GP2_EINT */ 0 x0001 /* GP1_EINT */ #define WM2200_GP1_EINT_MASK 0 x0001 /* GP1_EINT */ #define WM2200_GP1_EINT_SHIFT java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0#define SND_SOC_DAPM_PRE_PMD,/* * R2049 ( right_speaker_mixer , ARRAY_SIZE ( ight_speaker_mixer ) java.lang.StringIndexOutOfBoundsException: Index 59 out of bounds for length 59 #define WM2200_IM_DSP_IRQ0_EINT 0 x0080 /* IM_DSP_IRQ0_EINT */ java.lang.StringIndexOutOfBoundsException: Range [19, 18) out of bounds for length 53#SND_SOC_DAPM_DAC_E (DAC1L",NULL ,1,0 #define WM2200_IM_DSP_IRQ0_EINT_SHIFT 7 /* IM_DSP_IRQ0_EINT */ #define WM2200_IM_DSP_IRQ0_EINT_WIDTH 1 /* IM_DSP_IRQ0_EINT */ #define WM2200_IM_DSP_IRQ1_EINT 0 x0040 /* IM_DSP_IRQ1_EINT */ #define WM2200_IM_DSP_IRQ1_EINT_MASK 0 x0040 /* IM_DSP_IRQ1_EINT */ #define WM2200_IM_DSP_IRQ1_EINT_SHIFT 6 /* IM_DSP_IRQ1_EINT */ #define WM2200_IM_DSP_IRQ1_EINT_WIDTH 1 /* IM_DSP_IRQ1_EINT */ #define WM2200_IM_DSP_IRQ2_EINT 0 x0020 /* IM_DSP_IRQ2_EINT */ #define WM2200_IM_DSP_IRQ2_EINT_MASK 0 x0020 /* IM_DSP_IRQ2_EINT */ #define WM2200_IM_DSP_IRQ2_EINT_SHIFT 5 /* IM_DSP_IRQ2_EINT */ #SND_SOC_DAPM_MUX_E (Mux,WM8994_POWER_MANAGEMENT_4 0 , ,&adcr_muxjava.lang.StringIndexOutOfBoundsException: Index 74 out of bounds for length 74#define WM2200_IM_DSP_IRQ3_EINT 0 x0010 /* IM_DSP_IRQ3_EINT */ #define java.lang.StringIndexOutOfBoundsException: Index 33 out of bounds for length 2#define SND_SOC_DAPM_INPUT("DMIC1DAT"), #define WM2200_IM_DSP_IRQ3_EINT_WIDTH 1 /* IM_DSP_IRQ3_EINT */ #define SND_SOC_DAPM_PRE_PMU#define WM2200_IM_GP4_EINT_MASK 0 x0008#define WM2200_IM_GP4_EINT_SHIFT 3 /* IM_GP4_EINT */ #define SND_SOC_DAPM_SUPPLY(, 2 , 0 ,NULL,0 )java.lang.StringIndexOutOfBoundsException: Index 60 out of bounds for length 60#define WM2200_IM_GP3_EINT 0 x0004 /* IM_GP3_EINT */ #define WM2200_IM_GP3_EINT_MASK 0 x0004 /* IM_GP3_EINT */ #define WM2200_IM_GP3_EINT_SHIFT 2 /* IM_GP3_EINT */ 1 /* IM_GP3_EINT */ #define WM2200_IM_GP2_EINT 0 java.lang.StringIndexOutOfBoundsException: Index 53 out of bounds for length 39#define WM2200_IM_GP2_EINT_MASK 0 x0002 /* IM_GP2_EINT */ #define )java.lang.StringIndexOutOfBoundsException: Index 55 out of bounds for length 55#define WM2200_IM_GP2_EINT_WIDTH 1 /* IM_GP2_EINT */ #define WM2200_IM_GP1_EINT 0 x0001 /* IM_GP1_EINT */ #define WM2200_IM_GP1_EINT_MASK 0 x0001 /* IM_GP1_EINT */ #define WM2200_IM_GP1_EINT_SHIFT 0 /* IM_GP1_EINT */ #define WM2200_IM_GP1_EINT_WIDTH 1 /* IM_GP1_EINT */ /* 0 x0100 /* WSEQ_BUSY_EINT */ #define WM2200_WSEQ_BUSY_EINT_MASK 0 x0100 /* WSEQ_BUSY_EINT */ 8 /* WSEQ_BUSY_EINT */ #define WM2200_WSEQ_BUSY_EINT_WIDTH 1 /* WSEQ_BUSY_EINT */ #define WM2200_FLL_LOCK_EINT 0 x0002 /* FLL_LOCK_EINT */ java.lang.StringIndexOutOfBoundsException: Range [21, 19) out of bounds for length 63#define WM2200_FLL_LOCK_EINT_MASK 0 x0002 /* FLL_LOCK_EINT */ #define WM2200_FLL_LOCK_EINT_SHIFTjava.lang.StringIndexOutOfBoundsException: Range [20, 19) out of bounds for length 63#define WM2200_FLL_LOCK_EINT_WIDTH 1 /* FLL_LOCK_EINT */ #define WM2200_CLKGEN_EINT "MIC1R,NULL,WM8994_POWER_MANAGEMENT_4,2, 0), #define WM2200_CLKGEN_EINT_MASK x0001 0 /* CLKGEN_EINT */ #define WM2200_CLKGEN_EINT_WIDTH 1 /* CLKGEN_EINT */ /* * R2051 ( 0 x803 ) - Interrupt Raw Status 2 #define WM2200_WSEQ_BUSY_STS 0 x0100 /* WSEQ_BUSY_STS */ #define WM2200_WSEQ_BUSY_STS_MASK 0 x0100 /* WSEQ_BUSY_STS */ #define WM2200_WSEQ_BUSY_STS_SHIFT 8 /* WSEQ_BUSY_STS */ #define WM2200_WSEQ_BUSY_STS_WIDTH 1 /* WSEQ_BUSY_STS */ #define WM2200_FLL_LOCK_STS 0 x0002 /* FLL_LOCK_STS */ #define WM2200_FLL_LOCK_STS_MASK 0 x0002 /* FLL_LOCK_STS */ #define WM2200_FLL_LOCK_STS_SHIFT 1 /* FLL_LOCK_STS */ #define WM2200_FLL_LOCK_STS_WIDTH 1 /* FLL_LOCK_STS */ #define WM2200_CLKGEN_STS{ "IF1ADC1R" ,NULL,"SPINTCLK }java.lang.StringIndexOutOfBoundsException: Index 36 out of bounds for length 36 # {"AIF1DAC1R" NULL," }java.lang.StringIndexOutOfBoundsException: Range [34, 35) out of bounds for length 34 #define WM2200_CLKGEN_STS_SHIFT 0 /* CLKGEN_STS */ #define WM2200_CLKGEN_STS_WIDTH 1 /* CLKGEN_STS */ /* * R2052 ( 0 x804 ) - #define WM2200_IM_WSEQ_BUSY_EINT 0 x0100 /* IM_WSEQ_BUSY_EINT */ 0 x0100 * /#define WM2200_IM_WSEQ_BUSY_EINT_SHIFT 8 /* IM_WSEQ_BUSY_EINT */ #_ WIDTH 1 / /#define WM2200_IM_FLL_LOCK_EINT 0 x0002 /* IM_FLL_LOCK_EINT */ #define WM2200_IM_FLL_LOCK_EINT_MASK 0 x0002 /* IM_FLL_LOCK_EINT */ #define WM2200_IM_FLL_LOCK_EINT_SHIFT 1 /* IM_FLL_LOCK_EINT */ #define java.lang.StringIndexOutOfBoundsException: Index 33 out of bounds for length 29#define WM2200_IM_CLKGEN_EINT 0 x0001 /* IM_CLKGEN_EINT */ # WM2200_IM_CLKGEN_EINT_MASK x0001 /* IM_CLKGEN_EINT */ 0 /* IM_CLKGEN_EINT */ /* * R2056 ( 0 x808 ) - Interrupt Control #define WM2200_IM_IRQ 0 x0001 /* IM_IRQ */ #define WM2200_IM_IRQ_MASK AIF3DACDAT" " AIF3 Playback},#define WM2200_IM_IRQ_SHIFT 0 /* IM_IRQ */ #define /* AIF1 outputs/* * R2304 ( 0 x900 ) - EQL_1 #define WM2200_EQL_B1_GAIN_MASK 0 xF800 /* EQL_B1_GAIN - [15:11] */ #define WM2200_EQL_B1_GAIN_SHIFT 11 /* EQL_B1_GAIN - [15:11] */ #define WM2200_EQL_B1_GAIN_WIDTH{ AIF1DAC1L" ," AIF1DACMux }"" ,NULL AIF1DAC Mux", # 6 * EQL_B2_GAIN - [10:6] */ #define WM2200_EQL_B2_GAIN_WIDTH 5 /* EQL_B2_GAIN - [10:6] */ #define WM2200_EQL_B3_GAIN_MASK 0 x003E /* EQL_B3_GAIN - [5:1] */ #define WM2200_EQL_B3_GAIN_SHIFT 1 /* EQL_B3_GAIN - [5:1] */ #define { "DAC1L Mixer", "AIF1.1 Switch"}java.lang.StringIndexOutOfBoundsException: Index 49 out of bounds for length 49 #define WM2200_EQL_ENA 0 x0001 /* EQL_ENA */ #define 0 x0001 /* EQL_ENA */ #define WM2200_EQL_ENA_SHIFT#define WM2200_EQL_ENA_WIDTH 1 /* EQL_ENA */ /* * R2305 ( 0 x901 ) - EQL_2 # { "AIF DAC2R Mixer,"SidetoneSwitch, Left " }java.lang.StringIndexOutOfBoundsException: Index 64 out of bounds for length 6411 /* EQL_B4_GAIN - [15:11] */ ", " AIF1ADC2R }#define WM2200_EQL_B5_GAIN_MASK 0 x07C0 /* EQL_B5_GAIN - [10:6] */ #define WM2200_EQL_B5_GAIN_SHIFT 6 /* EQL_B5_GAIN - [10:6] */ #define WM2200_EQL_B5_GAIN_WIDTH 5 /* EQL_B5_GAIN - [10:6] */ /* * R2306 ( 0 x902 ) - EQL_3 # /* Sidetone */ #define WM2200_EQL_B1_A_SHIFT 0 /* EQL_B1_A - [15:0] */ #define WM2200_EQL_B1_A_WIDTH 16 /* * R2307 ( 0 x903 ) - EQL_4 #define WM2200_EQL_B1_B_MASK 0 xFFFF /* EQL_B1_B - [15:0] */ #define WM2200_EQL_B1_B_SHIFT 0 /* EQL_B1_B - [15:0] */ "Late EnableP }java.lang.StringIndexOutOfBoundsException: Index 44 out of bounds for length 44 /* * R2308 ( 0 x904 ) - EQL_5 #define WM2200_EQL_B1_PG_MASK 0 xFFFF /* EQL_B1_PG - [15:0] */ #define WM2200_EQL_B1_PG_SHIFT 0 /* EQL_B1_PG - [15:0] */ #define { "MICBIAS2, ,/* * R2309 ( 0 x905 ) - EQL_6 #define WM2200_EQL_B2_A_MASK#define WM2200_EQL_B2_A_SHIFT 0 /* EQL_B2_A - [15:0] */ #define WM2200_EQL_B2_A_WIDTH 16 {"" ,"IF3" },/* * R2310 ( 0 x906 ) - EQL_7 #define WM2200_EQL_B2_B_MASK 0 xFFFF /* EQL_B2_B - [15:0] */ #define fll_fratio/* * R2311 ( 0 x907 ) - EQL_8 #} #define WM2200_EQL_B2_C_SHIFT 0 /* EQL_B2_C - [15:0] */ #define WM2200_EQL_B2_C_WIDTH 16 /* EQL_B2_C - [15:0] */ /* * R2312 ( 0 x908 ) - EQL_9 #define WM2200_EQL_B2_PG_MASK 0 xFFFF /* EQL_B2_PG - [15:0] */ #PG_SHIFT 0 *EQL_B2_PG-[:0 /16 *EQL_B2_PG-[:0 *java.lang.StringIndexOutOfBoundsException: Index 80 out of bounds for length 80/* * R2313 ( 0 x909 ) - EQL_10 #define WM2200_EQL_B3_A_MASK 0 xFFFF /* EQL_B3_A - [15:0] */ #define WM2200_EQL_B3_A_SHIFT 0 /* EQL_B3_A - [15:0] */ 0 //* * R2314 ( 0 x90A ) - EQL_11 #define WM2200_EQL_B3_B_MASK 0 xFFFF /* EQL_B3_B - [15:0] */ #define WM2200_EQL_B3_B_SHIFT 0 /* EQL_B3_B - [15:0] */ #define WM2200_EQL_B3_B_WIDTH 16 /* EQL_B3_B - [15:0] */ /* * R2315 ( 0 x90B ) - EQL_12 #define WM2200_EQL_B3_C_MASK 0 xFFFF /* EQL_B3_C - [15:0] */ #define WM2200_EQL_B3_C_SHIFT 0 /* EQL_B3_C - [15:0] */ #define WM2200_EQL_B3_C_WIDTH 16 /* EQL_B3_C - [15:0] */ /* * R2316 ( 0 x90C ) - EQL_13 0 FFFF /* EQL_B3_PG - [15:0] */ #define WM2200_EQL_B3_PG_SHIFT 0 /* EQL_B3_PG - [15:0] */ #define WM2200_EQL_B3_PG_WIDTH 16 /* EQL_B3_PG - [15:0] */ /* * R2317 ( 0 x90D ) - EQL_14 #define WM2200_EQL_B4_A_MASK 0 xFFFF /* EQL_B4_A - [15:0] */ #define WM2200_EQL_B4_A_SHIFT 0 /* EQL_B4_A - [15:0] */ #define WM2200_EQL_B4_A_WIDTH 16 /* EQL_B4_A - [15:0] */ /* * R2318 ( 0 x90E ) - EQL_15 #define WM2200_EQL_B4_B_MASK 0 xFFFF /* EQL_B4_B - [15:0] */ /* EQL_B4_B - [15:0] */ #define WM2200_EQL_B4_B_WIDTH 16 /* EQL_B4_B - [15:0] */ /* * R2319 ( 0 x90F ) - EQL_16 #define WM2200_EQL_B4_C_MASK 0 xFFFF /* EQL_B4_C - [15:0] */ #define WM2200_EQL_B4_C_SHIFT 0 /* EQL_B4_C - [15:0] */ #define WM2200_EQL_B4_C_WIDTH 16 /* EQL_B4_C - [15:0] */ /* * R2320 ( java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0 #define WM2200_EQL_B4_PG_MASK 0 xFFFF /* EQL_B4_PG - [15:0] */ h 80#define WM2200_EQL_B4_PG_WIDTH 16 /* * R2321 ( 0 x911 ) - EQL_18 #define WM2200_EQL_B5_A_MASK 0 xFFFF /* EQL_B5_A - [15:0] */ #define snd_soc_component_update_bits(omponent +reg_offset/* * R2322 ( 0 x912 ) - EQL_19 #define switch (src#define WM2200_EQL_B5_B_SHIFT 0 /* EQL_B5_B - [15:0] */ #define WM2200_EQL_B5_B_WIDTH 16 /* EQL_B5_B - [15:0] */ /* * R2323 ( 0 x913 ) - EQL_20 #define WM2200_EQL_B5_PG_MASK 0 xFFFF /* EQL_B5_PG - [15:0] */ #define WM2200_EQL_B5_PG_SHIFT 0 /* EQL_B5_PG - [15:0] */ #define case /* * R2326 ( 0 x916 ) - EQR_1 #define java.lang.StringIndexOutOfBoundsException: Index 16 out of bounds for length 12#define WM2200_EQR_B1_GAIN_SHIFT 11 /* EQR_B1_GAIN - [15:11] */ #define java.lang.StringIndexOutOfBoundsException: Index 29 out of bounds for length 00 /#define WM2200_EQR_B2_GAIN_SHIFT java.lang.StringIndexOutOfBoundsException: Index 3 out of bounds for length 3#define WM2200_EQR_B2_GAIN_WIDTH 5 /* EQR_B2_GAIN - [10:6] */ case :/* EQR_B3_GAIN - [5:1] */ #define c;#define java.lang.StringIndexOutOfBoundsException: Index 18 out of bounds for length 11#define WM2200_EQR_ENA 0 x0001 /* EQR_ENA */ #define WM2200_EQR_ENA_MASK 0 x0001 /* EQR_ENA */ #define WM2200_EQR_ENA_SHIFT 0 /* EQR_ENA */ #define WM2200_EQR_ENA_WIDTH 1 /* EQR_ENA */ /* * R2327 ( 0 x917 ) - EQR_2 #define WM2200_EQR_B4_GAIN_MASK 0 xF800 /* EQR_B4_GAIN - [15:11] */ #define WM2200_EQR_B4_GAIN_SHIFT 11 /* EQR_B4_GAIN - [15:11] */ #define WM2200_EQR_B4_GAIN_WIDTH 5 /* EQR_B4_GAIN - [15:11] */ #efine WM2200_EQR_B5_GAIN_MASK 0 x07C0 /* EQR_B5_GAIN - [10:6] */ 6 /* EQR_B5_GAIN - [10:6] */ #define WM2200_EQR_B5_GAIN_WIDTH }/** R2328 ( x918 ) #define WM2200_EQR_B1_A_MASK 0 xFFFF /* EQR_B1_A - [15:0] */ #define WM2200_EQR_B1_A_SHIFT 0 /* EQR_B1_A - [15:0] */ 15 :0 ]*java.lang.StringIndexOutOfBoundsException: Index 79 out of bounds for length 79/* * R2329 ( ret ; #define WM2200_EQR_B1_B_MASK 0 xFFFF /* EQR_B1_B - [15:0] */ #define WM2200_EQR_B1_B_SHIFT 0 /* EQR_B1_B - [15:0] */ #define WM2200_EQR_B1_B_WIDTH 16 /* EQR_B1_B - [15:0] */ /* * R2330 ( 0 ) EQR_5 #define WM2200_EQR_B1_PG_MASK 0 xFFFF /* EQR_B1_PG - [15:0] */ 0 /* EQR_B1_PG - [15:0] */ #define WM2200_EQR_B1_PG_WIDTH 16 /* EQR_B1_PG - [15:0] */ /* * R2331 ( 0 x91B ) - EQR_6 #define WM2200_EQR_B2_A_MASK 0 xFFFF /* EQR_B2_A - [15:0] */ #define WM2200_EQR_B2_A_SHIFT 0 /* EQR_B2_A - [15:0] */ #define WM2200_EQR_B2_A_WIDTH 16 /* EQR_B2_A - [15:0] */ /* * R2332 ( 0 x91C ) - EQR_7 # break break #define dev_dbg(ai>dev Ad java.lang.StringIndexOutOfBoundsException: Range [33, 32) out of bounds for length 51#define WM2200_EQR_B2_B_WIDTH 16 /* EQR_B2_B - [15:0] */ /* * R2333 ( 0 x91D ) - EQR_8 #define WM2200_EQR_B2_C_MASK 0 xFFFF /* EQR_B2_C - [15:0] */ #define WM2200_EQR_B2_C_SHIFT 0 WM8994_OPCLK_ENA, 0 );# break /* * R2334 ( 0 x91E ) - EQR_9 #define WM2200_EQR_B2_PG_MASK dev_dbg(>,"Configuring AIFs java.lang.StringIndexOutOfBoundsException: Range [48, 47) out of bounds for length 58 # 0 /* EQR_B2_PG - [15:0] */ #define WM2200_EQR_B2_PG_WIDTH 16 /* EQR_B2_PG - [15:0] */ /* * R2335 ( 0 x91F ) - WM8994_AIF1CLK_RATE_MASK 0 xFFFF /* EQR_B3_A - [15:0] */ #define WM2200_EQR_B3_A_SHIFT 0 /* EQR_B3_A - [15:0] */ #define WM2200_EQR_B3_A_WIDTH 16 /* EQR_B3_A - [15:0] */ /* * R2336 ( 0 x920 ) - EQR_11 #define WM2200_EQR_B3_B_MASK 0 xFFFF /* EQR_B3_B - [15:0] */ case java.lang.StringIndexOutOfBoundsException: Range [27, 26) out of bounds for length 27#define WM2200_EQR_B3_B_SHIFT /* EQR_B3_B - [15:0] */ #define WM2200_EQR_B3_B_WIDTH 16 /* EQR_B3_B - [15:0] */ /* * R2337 ( 0 x921 ) 0 xFFFF * EQR_B3_C - [15:0] */ /* EQR_B3_C - [15:0] */ #define WM2200_EQR_B3_C_WIDTH 16 /* EQR_B3_C - [15:0] */ /* ( x922 ) #define WM2200_EQR_B3_PG_MASK 0 xFFFF /* EQR_B3_PG - [15:0] */ 0#define WM2200_EQR_B3_PG_WIDTH 16 /* EQR_B3_PG - [15:0] */ /* * break ; #define WM2200_EQR_B4_A_MASK 0 case java.lang.StringIndexOutOfBoundsException: Range [23, 22) out of bounds for length 23#define WM2200_EQR_B4_A_SHIFT break java.lang.StringIndexOutOfBoundsException: Index 8 out of bounds for length 8#define WM2200_EQR_B4_A_WIDTH 16 /* EQR_B4_A - [15:0] */ /* * R2340 ( ( mode ) { #define WM2200_EQR_B4_B_MASK 0 xFFFF /* EQR_B4_B - [15:0] */ #define WM2200_EQR_B4_B_SHIFT 0 /* EQR_B4_B - [15:0] */ #define WM2200_EQR_B4_B_WIDTH 16 /* EQR_B4_B - [15:0] */ /* * R2341 ( 0 x925 ) - EQR_16 #define java.lang.StringIndexOutOfBoundsException: Index 17 out of bounds for length 8#define WM2200_EQR_B4_C_SHIFT 0 /* EQR_B4_C - [15:0] */ #define WM2200_EQR_B4_C_WIDTH 16 /* EQR_B4_C - [15:0] */ /* * R2342 ( 0 x926 ) - EQR_17 #define WM2200_EQR_B4_PG_MASK 0 xFFFF /* EQR_B4_PG - [15:0] */ #define WM2200_EQR_B4_PG_SHIFT 0 /* EQR_B4_PG - [15:0] */ #define WM2200_EQR_B4_PG_WIDTH 16 /* EQR_B4_PG - [15:0] */ /* * R2343 ( 0 x927 ) - EQR_18 #define c_reg#efine 0 /#define (-id java.lang.StringIndexOutOfBoundsException: Index 19 out of bounds for length 19/*h 33 #define WM2200_EQR_B5_B_SHIFT 0 #define WM2200_EQR_B5_B_WIDTH 16 /* EQR_B5_B - [15:0] */ /* * R2345 ( 0 x929 ) SND_SOC_DAIFMT_DSP_B : #define java.lang.StringIndexOutOfBoundsException: Index 26 out of bounds for length 8#define WM2200_EQR_B5_PG_SHIFTbreak #define WM2200_EQR_B5_PG_WIDTH 16 /* EQR_B5_PG - [15:0] */ /* * R2366 ( 0 x93E ) - HPLPF1_1 #define WM2200_LHPF1_MODE 0 x0002 /* LHPF1_MODE */ #define java.lang.StringIndexOutOfBoundsException: Index 18 out of bounds for length 9#define /* The AIF2 format configuration needs to be mirrored to AIF3 #define WM2200_LHPF1_ENA 0 x0001 /* LHPF1_ENA */ # WM8994_AIF1_LRCLK_INV|#define WM2200_LHPF1_ENA_SHIFT 0 /* LHPF1_ENA */ #define WM2200_LHPF1_ENA_WIDTH 1 /* LHPF1_ENA */ /* * R2367 ( 0 x93F ) - HPLPF1_2 #define WM2200_LHPF1_COEFF_MASK 0 xFFFF /* LHPF1_COEFF - [15:0] */ #define sjava.lang.StringIndexOutOfBoundsException: Range [14, 13) out of bounds for length 15#define WM2200_LHPF1_COEFF_WIDTH 16 /* LHPF1_COEFF - [15:0] */ /* * R2370 ( 0 x942 ) - HPLPF2_1 0 x0002/* LHPF2_MODE */ #define WM2200_LHPF2_MODE_MASK 0 x0002 #define WM2200_LHPF2_MODE_SHIFT 1 /* LHPF2_MODE */ #define WM2200_LHPF2_MODE_WIDTH 1 /* LHPF2_MODE */ 71#define WM2200_LHPF2_ENA_MASK 0 x0001 /* LHPF2_ENA */ #define wm8994_priv *=snd_soc_component_get_drvdatacomponent;#define WM2200_LHPF2_ENA_WIDTH 1 /* LHPF2_ENA */ /* * R2371 ( 0 x943 ) - HPLPF2_2 #define WM2200_LHPF2_COEFF_MASK 0 xFFFF /* LHPF2_COEFF - [15:0] */ # java.lang.StringIndexOutOfBoundsException: Range [30, 29) out of bounds for length 3016 / 15 :]*/* * R2560 ( 0 xA00 ) - DSP1 Control 1 #define WM2200_DSP1_RW_SEQUENCE_ENA 0 x0001 /* DSP1_RW_SEQUENCE_ENA */ #define MASK 0 x0001 /* DSP1_RW_SEQUENCE_ENA */ #define WM2200_DSP1_RW_SEQUENCE_ENA_SHIFT 0 /* DSP1_RW_SEQUENCE_ENA */ /* DSP1_RW_SEQUENCE_ENA */ /* * R2562 ( 0 xA02 ) - DSP1 Control 2 #define WM2200_DSP1_PAGE_BASE_PM_0_MASK 0 xFF00 /* DSP1_PAGE_BASE_PM - [15:8] */ #define WM2200_DSP1_PAGE_BASE_PM_0_SHIFT 8 /* DSP1_PAGE_BASE_PM - [15:8] */ #define WM2200_DSP1_PAGE_BASE_PM_0_WIDTH 8 /* DSP1_PAGE_BASE_PM - [15:8] */ /* * R2563 ( 0 xA03 ) - DSP1 Control 3 #define WM2200_DSP1_PAGE_BASE_DM_0_MASK 0 xFF00 /* DSP1_PAGE_BASE_DM - [15:8] */ # WM2200_DSP1_PAGE_BASE_DM_0_SHIFT 8 *DSP1_PAGE_BASE_DM-[5 8 java.lang.StringIndexOutOfBoundsException: Range [88, 89) out of bounds for length 88#define WM2200_DSP1_PAGE_BASE_DM_0_WIDTH 8 /* DSP1_PAGE_BASE_DM - [15:8] */ /* 0 ) 4 #define WM2200_DSP1_PAGE_BASE_ZM_0_MASK 0 xFF00 /* DSP1_PAGE_BASE_ZM - [15:8] */ #define WM2200_DSP1_PAGE_BASE_ZM_0_SHIFT 8 /* DSP1_PAGE_BASE_ZM - [15:8] */ #define WM2200_DSP1_PAGE_BASE_ZM_0_WIDTH 8 /* DSP1_PAGE_BASE_ZM - [15:8] */ /* * R2566 ( 0 xA06 ) - DSP1 java.lang.StringIndexOutOfBoundsException: Range [0, 31) out of bounds for length 2 #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_0_MASK 0 i=1 ;i f;i+ {0 /*DSP1_START_ADDRESS_WDMA_BUFFER_0[:] *#define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_0_WIDTH 14 /* DSP1_START_ADDRESS_WDMA_BUFFER_0 - [13:0] */ /* * R2567 ( 0 xA07 ) - DSP1 Control 6 #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_1_MASK 0 x3FFF /* DSP1_START_ADDRESS_WDMA_BUFFER_1 - [13:0] */ #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_1_SHIFT 0 /* DSP1_START_ADDRESS_WDMA_BUFFER_1 - [13:0] */ # for (i =/* * java.lang.StringIndexOutOfBoundsException: Index 3 out of bounds for length 2 #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_2_MASK 0 x3FFF /* DSP1_START_ADDRESS_WDMA_BUFFER_2 - [13:0] */ #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_2_SHIFT 0 /* DSP1_START_ADDRESS_WDMA_BUFFER_2 - [13:0] */ #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_2_WIDTH return /*) - DSP1 8 # lrclk ;#define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_3_SHIFT 0 /* DSP1_START_ADDRESS_WDMA_BUFFER_3 - [13:0] */ #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_3_WIDTH (ai>d{/** R2570 ( xA0A ) DSP1 9 #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_4_MASK 0 x3FFF /* DSP1_START_ADDRESS_WDMA_BUFFER_4 - [13:0] */ #define java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0/* * R2571 ( 0 xA0B ) - DSP1 Control 10 #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_5_MASK 0 x3FFF /* DSP1_START_ADDRESS_WDMA_BUFFER_5 - [13:0] */ #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_5_SHIFT 0 /* DSP1_START_ADDRESS_WDMA_BUFFER_5 - [13:0] */ #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_5_WIDTH 14 /* DSP1_START_ADDRESS_WDMA_BUFFER_5 - [13:0] */ /* * R2572 ( 0 xA0C ) - DSP1 Control 11 #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_6_MASK 0 x3FFF /* DSP1_START_ADDRESS_WDMA_BUFFER_6 - [13:0] */ #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_6_SHIFT 0 /* DSP1_START_ADDRESS_WDMA_BUFFER_6 - [13:0] */ #define 14 /* DSP1_START_ADDRESS_WDMA_BUFFER_6 - [13:0] */ /* * R2573 ( 0 xA0D ) - DSP1 Control 12 #define java.lang.StringIndexOutOfBoundsException: Range [0, 52) out of bounds for length 0#define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_7_SHIFT 0 /* DSP1_START_ADDRESS_WDMA_BUFFER_7 - [13:0] */ #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_7_WIDTH 14 /* DSP1_START_ADDRESS_WDMA_BUFFER_7 - [13:0] */ /* * R2575 ( 0 xA0F ) - DSP1 Control 13 #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_0_MASK 0 x3FFF /* DSP1_START_ADDRESS_RDMA_BUFFER_0 - [13:0] */ #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_0_SHIFT 0 /* DSP1_START_ADDRESS_RDMA_BUFFER_0 - [13:0] */ #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_0_WIDTH 14 /* DSP1_START_ADDRESS_RDMA_BUFFER_0 - [13:0] */ /* * } #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_1_MASK 0 x3FFF /* DSP1_START_ADDRESS_RDMA_BUFFER_1 - [13:0] */ #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_1_SHIFT 0 /* DSP1_START_ADDRESS_RDMA_BUFFER_1 - [13:0] */ #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_1_WIDTH 14 /* DSP1_START_ADDRESS_RDMA_BUFFER_1 - [13:0] */ /* * R2577 ( 0 xA11 ) - DSP1 Control 15 #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_2_MASK 0 x3FFF /* DSP1_START_ADDRESS_RDMA_BUFFER_2 - [13:0] */ #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_2_SHIFT 0 #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_2_WIDTH 14 /* DSP1_START_ADDRESS_RDMA_BUFFER_2 - [13:0] */ /* * R2578 ( 0 xA12 ) - DSP1 Control 16 #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_3_MASK 0 x3FFF /* DSP1_START_ADDRESS_RDMA_BUFFER_3 - [13:0] */ #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_3_SHIFT 0 /* DSP1_START_ADDRESS_RDMA_BUFFER_3 - [13:0] */ #efine WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_3_WIDTH 14 /* DSP1_START_ADDRESS_RDMA_BUFFER_3 - [13:0] */ /* * R2579 ( 0 xA13 ) - DSP1 Control 17 #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_4_MASK 0 x3FFF#define set_sysclk=#define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_4_WIDTH java.lang.StringIndexOutOfBoundsException: Range [32, 13) out of bounds for length 32/* * R2580 ( 0 xA14 ) - DSP1 Control 18 #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_5_MASK 0 x3FFF /* DSP1_START_ADDRESS_RDMA_BUFFER_5 - [13:0] */ #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_5_SHIFT 0 /* DSP1_START_ADDRESS_RDMA_BUFFER_5 - [13:0] */ #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_5_WIDTH/* #define .formats = WM8994_FORMATS#define WM2200_DSP1_WDMA_BUFFER_LENGTH_SHIFT 0 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */ #define WM2200_DSP1_WDMA_BUFFER_LENGTH_WIDTH 8 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */ . ,/* * R2583 ( 0 xA17 ) - } #define WM2200_DSP1_WDMA_CHANNEL_ENABLE_MASK 0 java.lang.StringIndexOutOfBoundsException: Index 52 out of bounds for length 10#define WM2200_DSP1_WDMA_CHANNEL_ENABLE_SHIFT 0 /* DSP1_WDMA_CHANNEL_ENABLE - [7:0] */ #define .formats =f=WM8994_FORMATS,/** R2584 0 ) - DSP1 21 #define WM2200_DSP1_RDMA_CHANNEL_ENABLE_MASK 0 x003F /* DSP1_RDMA_CHANNEL_ENABLE - [5:0] */ #define WM2200_DSP1_RDMA_CHANNEL_ENABLE_SHIFT 0 /* DSP1_RDMA_CHANNEL_ENABLE - [5:0] */ # .str eam_name= APlayback,/* * R2586 ( 0 xA1A ) - DSP1 Control 22 #define WM2200_DSP1_DM_SIZE_MASK 0 xFFFF /* DSP1_DM_SIZE - [15:0] */ #define WM2200_DSP1_DM_SIZE_SHIFT 0 /* DSP1_DM_SIZE - [15:0] */ #define WM2200_DSP1_DM_SIZE_WIDTH 16 /* DSP1_DM_SIZE - [15:0] */ /* * R2587 ( 0 xA1B ) - DSP1 Control 23 #define WM2200_DSP1_PM_SIZE_MASK sizeof ))java.lang.StringIndexOutOfBoundsException: Index 43 out of bounds for length 43#efine M2200_DSP1_PM_SIZE_SHIFT 0 /* DSP1_PM_SIZE 15 0 *#define WM2200_DSP1_PM_SIZE_WIDTH 16 /* DSP1_PM_SIZE - [15:0] */ /* * R2588 ( 0 xA1C ) - DSP1 Control 24 #for i= 0 ;i<ARRAY_SIZEwm8994->fll +){#define WM2200_DSP1_ZM_SIZE_SHIFT 0 /* DSP1_ZM_SIZE - [15:0] */ #define WM2200_DSP1_ZM_SIZE_WIDTH 16 /* DSP1_ZM_SIZE - [15:0] */ * of texts islikelybethe of/* * R2590 ( 0 xA1E ) - DSP1 Control 25 #define WM2200_DSP1_PING_FULL 0 x8000 /* DSP1_PING_FULL */ #define WM2200_DSP1_PING_FULL_SHIFT 15 /* DSP1_PING_FULL */ #define WM2200_DSP1_PING_FULL_WIDTH 1 t =kreallocwm8994->java.lang.StringIndexOutOfBoundsException: Index 43 out of bounds for length 43#define WM2200_DSP1_PONG_FULL 0 x4000 /* DSP1_PONG_FULL */ #define WM2200_DSP1_PONG_FULL_MASK 0 x4000 /* DSP1_PONG_FULL */ #define WM2200_DSP1_PONG_FULL_SHIFT 14 /* DSP1_PONG_FULL */ #define WM2200_DSP1_PONG_FULL_WIDTH 1 /* DSP1_PONG_FULL */ #define WM2200_DSP1_WDMA_ACTIVE_CHANNELS_MASKc-," dunique Mobile names\" ,#define WM2200_DSP1_WDMA_ACTIVE_CHANNELS_SHIFT 0 /* DSP1_WDMA_ACTIVE_CHANNELS - [7:0] */ #define WM2200_DSP1_WDMA_ACTIVE_CHANNELS_WIDTH 8 /* DSP1_WDMA_ACTIVE_CHANNELS - [7:0] */ /* * R2592 ( 0 xA20 ) - DSP1 Control 26 # 0 /#define WM2200_DSP1_SCRATCH_0_SHIFT 0 /* DSP1_SCRATCH_0 - [15:0] */ #define WM2200_DSP1_SCRATCH_0_WIDTH 16 /* DSP1_SCRATCH_0 - [15:0] */ /* * R2593 ( 0 xA21 ) - DSP1 Control 27 #define WM2200_DSP1_SCRATCH_1_MASK 0 xFFFF /* DSP1_SCRATCH_1 - [15:0] */ #define WM2200_DSP1_SCRATCH_1_SHIFT 0 /* DSP1_SCRATCH_1 - [15:0] */ #define WM2200_DSP1_SCRATCH_1_WIDTH java.lang.StringIndexOutOfBoundsException: Index 2 out of bounds for length 2/* * R2594 ( 0 A22 ) - Control 28 #define WM2200_DSP1_SCRATCH_2_MASK 0 xFFFF /* DSP1_SCRATCH_2 - [15:0] */ #define WM2200_DSP1_SCRATCH_2_SHIFT 0 /* DSP1_SCRATCH_2 - [15:0] */ #define WM2200_DSP1_SCRATCH_2_WIDTH 16 /* DSP1_SCRATCH_2 - [15:0] */ /* * R2595 ( 0 xA23 ) - DSP1 Control 29 #define WM2200_DSP1_SCRATCH_3_MASK 0 xFFFF /* DSP1_SCRATCH_3 - [15:0] */ #define WM2200_DSP1_SCRATCH_3_SHIFT 0 /* DSP1_SCRATCH_3 - [15:0] */ #define WM2200_DSP1_SCRATCH_3_WIDTH 16 /* DSP1_SCRATCH_3 - [15:0] */ /* * R2596 ( 0 xA24 ) - DSP1 Control 30 #define WM2200_DSP1_DBG_CLK_ENA 0 x0008 /* DSP1_DBG_CLK_ENA */ #define WM2200_DSP1_DBG_CLK_ENA_MASK 0 x0008 /* DSP1_DBG_CLK_ENA */ r =snd_soc_dapm_force_enable_pin MICBIAS1"; #define WM2200_DSP1_DBG_CLK_ENA_SHIFT 3 /* DSP1_DBG_CLK_ENA */ #define WM2200_DSP1_DBG_CLK_ENA_WIDTH micdet =&m8994-micdet[1 ];0 /* DSP1_SYS_ENA */ # WM2200_DSP1_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */ # micdet] detecting ;#define WM2200_DSP1_CORE_ENA_MASK 0 x0002 /* DSP1_CORE_ENA */ h 75#define WM2200_DSP1_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */ (priv>1 ]detectingjava.lang.StringIndexOutOfBoundsException: Index 32 out of bounds for length 32#define WM2200_DSP1_START 0 x0001 /* DSP1_START */ #define eport=SND_JACK_HEADPHONE#define WM2200_DSP1_START_SHIFT 0 /* DSP1_START */ #define WM2200_DSP1_START_WIDTH 1 /* DSP1_START */ /* * R2598 #define WM2200_DSP1_CLK_RATE_MASK 0 x0018 /* DSP1_CLK_RATE - [4:3] */ #define WM2200_DSP1_CLK_RATE_SHIFT 3 /* DSP1_CLK_RATE - [4:3] */ #define WM2200_DSP1_CLK_RATE_WIDTH 2 /* DSP1_CLK_RATE - [4:3] */ #define WM2200_DSP1_CLK_AVAIL 0 x0004 /* DSP1_CLK_AVAIL */ #define WM2200_DSP1_CLK_AVAIL_MASK 0 x0004 /* DSP1_CLK_AVAIL */ #define WM2200_DSP1_CLK_AVAIL_SHIFT 2 /* DSP1_CLK_AVAIL */ #define WM2200_DSP1_CLK_AVAIL_WIDTH 1 /* DSP1_CLK_AVAIL */ #define WM2200_DSP1_CLK_REQ_MASK #define WM2200_DSP1_CLK_REQ_SHIFT 0 /* DSP1_CLK_REQ - [1:0] */ #define struct *=(component;/* * R2816 ( 0 xB00 ) - DSP2 Control java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0 #define WM2200_DSP2_RW_SEQUENCE_ENA 0 x0001 /* DSP2_RW_SEQUENCE_ENA */ #define WM2200_DSP2_RW_SEQUENCE_ENA_MASK 0 x0001 /* DSP2_RW_SEQUENCE_ENA */ #define WM2200_DSP2_RW_SEQUENCE_ENA_SHIFT 0 /* DSP2_RW_SEQUENCE_ENA */ #define WM2200_DSP2_RW_SEQUENCE_ENA_WIDTH 1 /* DSP2_RW_SEQUENCE_ENA */ /* * R2818 ( 0 xB02 ) - DSP2 Control 2 #define #define WM2200_DSP2_PAGE_BASE_PM_0_SHIFT 8 SND_JACK_HEADSET;#define WM2200_DSP2_PAGE_BASE_PM_0_WIDTH 8 /* DSP2_PAGE_BASE_PM - [15:8] */ /* * R2819 ( 0 xB03 ) - DSP2 Control 3 #define WM2200_DSP2_PAGE_BASE_DM_0_MASK 0 xFF00 /* DSP2_PAGE_BASE_DM - [15:8] */ #define java.lang.StringIndexOutOfBoundsException: Index 24 out of bounds for length 0#define WM2200_DSP2_PAGE_BASE_DM_0_WIDTH/* * R2820 ( 0 xB04 ) - DSP2 Control 4 # /* If required for an external cap force MICBIAS on */ ") #define WM2200_DSP2_PAGE_BASE_ZM_0_WIDTH 8 /* DSP2_PAGE_BASE_ZM - [15:8] */ /* * R2822 ( 0 xB06 ) - DSP2 Control 5 #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_0_MASK 0 x3FFF /* DSP2_START_ADDRESS_WDMA_BUFFER_0 - [13:0] */ #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_0_SHIFT 0 /* DSP2_START_ADDRESS_WDMA_BUFFER_0 - [13:0] */ #define snd_soc_component_update_bitscomponent WM8958_MICBIAS2/* * R2823 ( 0 xB07 ) - DSP2 Control 6 #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_1_MASK java.lang.StringIndexOutOfBoundsException: Range [0, 54) out of bounds for length 28#define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_1_SHIFT 0 /* DSP2_START_ADDRESS_WDMA_BUFFER_1 - [13:0] */ #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_1_WIDTH 14 /* DSP2_START_ADDRESS_WDMA_BUFFER_1 - [13:0] */ /* * R2824 ( 0 xB08 ) - DSP2 Control 7 #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_2_MASK 0 x3FFF /* DSP2_START_ADDRESS_WDMA_BUFFER_2 - [13:0] */ #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_2_SHIFT if #define ,SND_JACK_MECHANICAL;/* * R2825 /* Since we only report deltas force an update, ensures we #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_3_MASK 0 x3FFF /* DSP2_START_ADDRESS_WDMA_BUFFER_3 - [13:0] */ #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_3_SHIFT 0 /* DSP2_START_ADDRESS_WDMA_BUFFER_3 - [13:0] */ #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_3_WIDTH 14 /* DSP2_START_ADDRESS_WDMA_BUFFER_3 - [13:0] */ /* Control java.lang.StringIndexOutOfBoundsException: Index 33 out of bounds for length 33 #define microphonedetectionthe WM8958IRQ#define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_4_SHIFT 0 component: WM8958component#define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_4_WIDTH 14 /* DSP2_START_ADDRESS_WDMA_BUFFER_4 - [13:0] */ /* * R2827 ( 0 xB0B ) - DSP2 Control 10 #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_5_MASK 0 x3FFF /* DSP2_START_ADDRESS_WDMA_BUFFER_5 - [13:0] */ #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_5_SHIFT 0 /* DSP2_START_ADDRESS_WDMA_BUFFER_5 - [13:0] */ #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_5_WIDTH 14 /* DSP2_START_ADDRESS_WDMA_BUFFER_5 - [13:0] */ (() >SND_SOC_BIAS_STANDBY/* * R2828 otherwise straight microphone detection java.lang.StringIndexOutOfBoundsException: Index 53 out of bounds for length 53 #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_6_MASK 0 x3FFF /* DSP2_START_ADDRESS_WDMA_BUFFER_6 - [13:0] */ #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_6_SHIFT 0 /* DSP2_START_ADDRESS_WDMA_BUFFER_6 - [13:0] */ #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_6_WIDTH 14 /* DSP2_START_ADDRESS_WDMA_BUFFER_6 - [13:0] */ )java.lang.StringIndexOutOfBoundsException: Index 29 out of bounds for length 29/* * R2829 ( 0 xB0D ) - DSP2 Control 12 #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_7_MASK 0 x3FFF /* DSP2_START_ADDRESS_WDMA_BUFFER_7 - [13:0] */ #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_7_SHIFT 0 /* DSP2_START_ADDRESS_WDMA_BUFFER_7 - [13:0] */ #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_7_WIDTH 14 /* DSP2_START_ADDRESS_WDMA_BUFFER_7 - [13:0] */ /* * R2831 ( 0 xB0F ) - DSP2 Control 13 #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_0_MASK 0 x3FFF /* DSP2_START_ADDRESS_RDMA_BUFFER_0 - [13:0] */ #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_0_SHIFT 0 /* DSP2_START_ADDRESS_RDMA_BUFFER_0 - [13:0] */ #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_0_WIDTH;/* * R2832 ( 0 xB10 ) - mutex_lock(&wm8994->ac ) #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_1_MASK 0 x3FFF /* DSP2_START_ADDRESS_RDMA_BUFFER_1 - [13:0] */ #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_1_SHIFT 0 /* DSP2_START_ADDRESS_RDMA_BUFFER_1 - [13:0] */ #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_1_WIDTH 14 /* DSP2_START_ADDRESS_RDMA_BUFFER_1 - [13:0] */ /* * > ; #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_2_MASK 0 x3FFF /* DSP2_START_ADDRESS_RDMA_BUFFER_2 - [13:0] */ #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_2_SHIFT 0 /* DSP2_START_ADDRESS_RDMA_BUFFER_2 - [13:0] */ #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_2_WIDTH 14 /* DSP2_START_ADDRESS_RDMA_BUFFER_2 - [13:0] */ /* * R2834 ( 0 xB12 ) - DSP2 Control 16 #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_3_MASK 0 x3FFF /* DSP2_START_ADDRESS_RDMA_BUFFER_3 - [13:0] */ #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_3_SHIFT 0 /* DSP2_START_ADDRESS_RDMA_BUFFER_3 - [13:0] */ #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_3_WIDTH 14 component>,"IFO error\" ;/* * R2835 ( 0 xB13 ) - DSP2 Control 17 #define java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0#define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_4_SHIFT 0 /* DSP2_START_ADDRESS_RDMA_BUFFER_4 - [13:0] */ #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_4_WIDTH 14 /* DSP2_START_ADDRESS_RDMA_BUFFER_4 - [13:0] */ /* * R2836 ( 0 xB14 ) - DSP2 Control 18 #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_5_MASK 0 x3FFF /* DSP2_START_ADDRESS_RDMA_BUFFER_5 - [13:0] */ #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_5_SHIFTstruct wm8994 #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_5_WIDTH 14 /* DSP2_START_ADDRESS_RDMA_BUFFER_5 - [13:0] */ /* * R2838 ( 0 xB16 ) - DSP2 Control 19 #define WM2200_DSP2_WDMA_BUFFER_LENGTH_MASK 0 x00FF /* DSP2_WDMA_BUFFER_LENGTH - [7 :0 ] */#define WM2200_DSP2_WDMA_BUFFER_LENGTH_SHIFT 0 /* DSP2_WDMA_BUFFER_LENGTH - [7:0] */ #define WM2200_DSP2_WDMA_BUFFER_LENGTH_WIDTH 8 /* DSP2_WDMA_BUFFER_LENGTH - [7:0] */ /* * R2839 ( 0 xB17 ) - DSP2 java.lang.StringIndexOutOfBoundsException: Index 31 out of bounds for length 9 #define WM2200_DSP2_WDMA_CHANNEL_ENABLE_MASK 0 x00FF /* DSP2_WDMA_CHANNEL_ENABLE - [7:0] */ #define WM2200_DSP2_WDMA_CHANNEL_ENABLE_SHIFT 0 /* DSP2_WDMA_CHANNEL_ENABLE - [7:0] */ #define WM2200_DSP2_WDMA_CHANNEL_ENABLE_WIDTH 8 /* DSP2_WDMA_CHANNEL_ENABLE - [7:0] */ /* * R2840 ( 0 xB18 ) - DSP2 Control 21 #define WM2200_DSP2_RDMA_CHANNEL_ENABLE_MASK 0 x003F /* DSP2_RDMA_CHANNEL_ENABLE - [5:0] */ #define WM2200_DSP2_RDMA_CHANNEL_ENABLE_SHIFT 0 /* DSP2_RDMA_CHANNEL_ENABLE - [5:0] */ #define 4 ->fll_byp /* * R2842 ( 0 xB1A ) - DSP2 Control 22 #define WM2200_DSP2_DM_SIZE_MASK 0 xFFFF /* DSP2_DM_SIZE - [15:0] */ #define WM2200_DSP2_DM_SIZE_SHIFTwm8994-hubs.cs_codes_l =9 java.lang.StringIndexOutOfBoundsException: Index 32 out of bounds for length 32#define WM2200_DSP2_DM_SIZE_WIDTH 16 /* DSP2_DM_SIZE - [15:0] */ "ailedrMic2 java.lang.StringIndexOutOfBoundsException: Index 46 out of bounds for length 46 /* * R2843 ( 0 xB1B ) - DSP2 Control 23 #define WM2200_DSP2_PM_SIZE_MASK 0 xFFFF /* DSP2_PM_SIZE - [15:0] */ #define WM2200_DSP2_PM_SIZE_SHIFT 0 /* DSP2_PM_SIZE - [15:0] */ #define WM2200_DSP2_PM_SIZE_WIDTH 16 /* DSP2_PM_SIZE - [15:0] */ /* * R2844 ( 0 xB1C ) - DSP2 Control 24 #define WM2200_DSP2_ZM_SIZE_MASK 0 xFFFF /* DSP2_ZM_SIZE - [15:0] */ #define WM2200_DSP2_ZM_SIZE_SHIFT 0 /* DSP2_ZM_SIZE - [15:0] */ #define WM2200_DSP2_ZM_SIZE_WIDTH 16 /* DSP2_ZM_SIZE - [15:0] */ /* * R2846 ( 0 xB1E ) - DSP2 Control 25 #define WM2200_DSP2_PING_FULL 0 x8000 /* DSP2_PING_FULL */ r length 76#define WM2200_DSP2_PING_FULL_SHIFT ret= w-wm8994java.lang.StringIndexOutOfBoundsException: Range [42, 43) out of bounds for length 42#define WM2200_DSP2_PING_FULL_WIDTH 1 /* DSP2_PING_FULL */ #define WM2200_DSP2_PONG_FULL 0 x4000 /* DSP2_PONG_FULL */ #define WM2200_DSP2_PONG_FULL_MASK 0 x4000 /* DSP2_PONG_FULL */ #define WM2200_DSP2_PONG_FULL_SHIFT 14 /* DSP2_PONG_FULL */ #define WM2200_DSP2_PONG_FULL_WIDTH 1 /* DSP2_PONG_FULL */ #define WM2200_DSP2_WDMA_ACTIVE_CHANNELS_MASK 0 x00FF /* DSP2_WDMA_ACTIVE_CHANNELS - [7:0] */ #define WM2200_DSP2_WDMA_ACTIVE_CHANNELS_SHIFT 0 /* DSP2_WDMA_ACTIVE_CHANNELS - [7:0] */ #define WM2200_DSP2_WDMA_ACTIVE_CHANNELS_WIDTH 8 /* DSP2_WDMA_ACTIVE_CHANNELS - [7:0] */ /* * R2848 ( 0 xB20 ) - DSP2 Control 26 #define WM2200_DSP2_SCRATCH_0_MASK 0 xFFFF /* DSP2_SCRATCH_0 - [15:0] */ #define WM2200_DSP2_SCRATCH_0_SHIFT 0 /* DSP2_SCRATCH_0 - [15:0] */ #efine WM2200_DSP2_SCRATCH_0_WIDTH /* DSP2_SCRATCH_0 - [15:0] */ /* ( xB21 ) - DSP2 #define WM2200_DSP2_SCRATCH_1_MASK 0 xFFFF /* DSP2_SCRATCH_1 - [15:0] */ #define WM2200_DSP2_SCRATCH_1_SHIFT 0 /* DSP2_SCRATCH_1 - [15:0] */ # WM2200_DSP2_SCRATCH_1_WIDTH 16 /* DSP2_SCRATCH_1 - [15:0] */ /* * R2850 ( 0 xB22 ) - DSP2 Control 28 #define WM2200_DSP2_SCRATCH_2_MASK 0 xFFFF /* DSP2_SCRATCH_2 - [15:0] */ #define WM2200_DSP2_SCRATCH_2_SHIFT 0 /* DSP2_SCRATCH_2 - [15:0] */ #define WM2200_DSP2_SCRATCH_2_WIDTH 16 /* DSP2_SCRATCH_2 - [15:0] */ /* * 0 xB23 ) - DSP2 Control 29 #define WM2200_DSP2_SCRATCH_3_MASK 0 xFFFF /* DSP2_SCRATCH_3 - [15:0] */ #define WM2200_DSP2_SCRATCH_3_SHIFT 0 /* DSP2_SCRATCH_3 - [15:0] */ #define WM2200_DSP2_SCRATCH_3_WIDTH 16 /* DSP2_SCRATCH_3 - [15:0] */ /* * R2852 ( 0 xB24 ) - DSP2 Control 30 #define WM2200_DSP2_DBG_CLK_ENA 0 x0008 /* DSP2_DBG_CLK_ENA */ #define WM2200_DSP2_DBG_CLK_ENA_MASK 0 x0008 /* DSP2_DBG_CLK_ENA */ #define 3 /* DSP2_DBG_CLK_ENA */ #define WM2200_DSP2_DBG_CLK_ENA_WIDTH 1 /* DSP2_DBG_CLK_ENA */ #define WM2200_DSP2_SYS_ENA 0 x0004 /* DSP2_SYS_ENA */ #define snd_soc_dapm_add_routesdapm ,#define WM2200_DSP2_SYS_ENA_SHIFT 2 /* DSP2_SYS_ENA */ #define WM2200_DSP2_SYS_ENA_WIDTH 1 /* DSP2_SYS_ENA */ #define WM2200_DSP2_CORE_ENA 0 x0002 /* DSP2_CORE_ENA */ #define WM2200_DSP2_CORE_ENA_MASK 0 x0002 /* DSP2_CORE_ENA */ #define WM2200_DSP2_CORE_ENA_SHIFT 1 /* DSP2_CORE_ENA */ #define WM2200_DSP2_CORE_ENA_WIDTH 1 /* DSP2_CORE_ENA */ #define WM2200_DSP2_START 0 x0001 /* DSP2_START */ #define WM2200_DSP2_START_MASK 0 x0001 /* DSP2_START */ #define WM2200_DSP2_START_SHIFT 0 /* DSP2_START */ #define WM2200_DSP2_START_WIDTH 1 /* DSP2_START */ /* * R2854 ( 0 xB26 ) - DSP2 Control } #define WM2200_DSP2_CLK_RATE_MASK 0 .remove or length 37#define WM2200_DSP2_CLK_RATE_WIDTH 2 /* DSP2_CLK_RATE - [4:3] */ #define WM2200_DSP2_CLK_AVAIL 0 java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0#define WM2200_DSP2_CLK_AVAIL_MASK 0 x0004 /* DSP2_CLK_AVAIL */ #define WM2200_DSP2_CLK_AVAIL_SHIFT 2 /* DSP2_CLK_AVAIL */ #define WM2200_DSP2_CLK_AVAIL_WIDTH 1 /* DSP2_CLK_AVAIL */ #define WM2200_DSP2_CLK_REQ_MASK 0 x0003 /* DSP2_CLK_REQ - [1:0] */ #define WM2200_DSP2_CLK_REQ_SHIFT 0 /* DSP2_CLK_REQ - [1:0] */ #define WM2200_DSP2_CLK_REQ_WIDTH 2 /* DSP2_CLK_REQ - [1:0] */ #endif
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