// SPDX-License-Identifier: GPL-2.0 /* * ARMv7 Cortex - A8 and Cortex - A9 Performance Events handling code . * * ARMv7 support : Jean Pihet < jpihet @ mvista . com > * 2010 ( c ) MontaVista Software , LLC . * * Copied from ARMv6 code , with the low level code inspired * by the ARMv7 Oprofile code . * * Cortex - A8 has up to 4 configurable performance counters and * a single cycle counter . * Cortex - A9 has up to 31 configurable performance counters and * a single cycle counter . * * All counters can be enabled / disabled and IRQ masked separately . The cycle * counter and all 4 performance counters together can be reset separately . #include <asm /cp15.h>#include <asm /cputype.h>#include <asm /irq_regs.h>#include <asm /vfp.h>#include "../vfp/vfpinstr.h" #include <linux/of.h>#include <linux/perf/arm_pmu.h>#include <linux/platform_device.h>/* * Common ARMv7 event types * * Note : An implementation may not be able to count all of these events * but the encodings are considered to be ` reserved ' in the case that * they are not available . #define ARMV7_PERFCTR_PMNC_SW_INCR 0 x00#define ARMV7_PERFCTR_L1_ICACHE_REFILL 0 x01#define ARMV7_PERFCTR_ITLB_REFILL 0 x02#define ARMV7_PERFCTR_L1_DCACHE_REFILL 0 x03#define ARMV7_PERFCTR_L1_DCACHE_ACCESS 0 x04#define ARMV7_PERFCTR_DTLB_REFILL 0 x05#define ARMV7_PERFCTR_MEM_READ 0 x06#define ARMV7_PERFCTR_MEM_WRITE 0 x07#define ARMV7_PERFCTR_INSTR_EXECUTED 0 x08#define ARMV7_PERFCTR_EXC_TAKEN 0 x09#define ARMV7_PERFCTR_EXC_EXECUTED 0 x0A#define ARMV7_PERFCTR_CID_WRITE 0 x0B/* * ARMV7_PERFCTR_PC_WRITE is equivalent to HW_BRANCH_INSTRUCTIONS . * It counts : * - all ( taken ) branch instructions , * - instructions that explicitly write the PC , * - exception generating instructions . #define ARMV7_PERFCTR_PC_WRITE 0 x0C#define ARMV7_PERFCTR_PC_IMM_BRANCH 0 x0D#define ARMV7_PERFCTR_PC_PROC_RETURN 0 x0E#define ARMV7_PERFCTR_MEM_UNALIGNED_ACCESS 0 x0F#define ARMV7_PERFCTR_PC_BRANCH_MIS_PRED 0 x10#define ARMV7_PERFCTR_CLOCK_CYCLES 0 x11#define ARMV7_PERFCTR_PC_BRANCH_PRED 0 x12/* These events are defined by the PMUv2 supplement (ARM DDI 0457A). */ #define ARMV7_PERFCTR_MEM_ACCESS 0 x13#define ARMV7_PERFCTR_L1_ICACHE_ACCESS 0 x14#define ARMV7_PERFCTR_L1_DCACHE_WB 0 x15#define ARMV7_PERFCTR_L2_CACHE_ACCESS 0 x16#define ARMV7_PERFCTR_L2_CACHE_REFILL 0 x17#define ARMV7_PERFCTR_L2_CACHE_WB 0 x18#define ARMV7_PERFCTR_BUS_ACCESS 0 x19#define ARMV7_PERFCTR_MEM_ERROR 0 x1A#define ARMV7_PERFCTR_INSTR_SPEC 0 x1B#define ARMV7_PERFCTR_TTBR_WRITE 0 x1C#define ARMV7_PERFCTR_BUS_CYCLES 0 x1D#define ARMV7_PERFCTR_CPU_CYCLES 0 xFF/* ARMv7 Cortex-A8 specific event types */ #define ARMV7_A8_PERFCTR_L2_CACHE_ACCESS 0 x43#define ARMV7_A8_PERFCTR_L2_CACHE_REFILL 0 x44#define ARMV7_A8_PERFCTR_L1_ICACHE_ACCESS 0 x50#define ARMV7_A8_PERFCTR_STALL_ISIDE 0 x56/* ARMv7 Cortex-A9 specific event types */ #define ARMV7_A9_PERFCTR_INSTR_CORE_RENAME 0 x68#define ARMV7_A9_PERFCTR_STALL_ICACHE 0 x60#define ARMV7_A9_PERFCTR_STALL_DISPATCH 0 x66/* ARMv7 Cortex-A5 specific event types */ #define ARMV7_A5_PERFCTR_PREFETCH_LINEFILL 0 xc2#define ARMV7_A5_PERFCTR_PREFETCH_LINEFILL_DROP 0 xc3/* ARMv7 Cortex-A15 specific event types */ #define ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_READ 0 x40#define ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_WRITE 0 x41#define ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_READ 0 x42#define ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_WRITE 0 x43#define ARMV7_A15_PERFCTR_DTLB_REFILL_L1_READ 0 x4C#define ARMV7_A15_PERFCTR_DTLB_REFILL_L1_WRITE 0 x4D#define ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_READ 0 x50#define ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_WRITE 0 x51#define ARMV7_A15_PERFCTR_L2_CACHE_REFILL_READ 0 x52#define ARMV7_A15_PERFCTR_L2_CACHE_REFILL_WRITE 0 x53#define ARMV7_A15_PERFCTR_PC_WRITE_SPEC 0 x76/* ARMv7 Cortex-A12 specific event types */ #define ARMV7_A12_PERFCTR_L1_DCACHE_ACCESS_READ 0 x40#define ARMV7_A12_PERFCTR_L1_DCACHE_ACCESS_WRITE 0 x41#define ARMV7_A12_PERFCTR_L2_CACHE_ACCESS_READ 0 x50#define ARMV7_A12_PERFCTR_L2_CACHE_ACCESS_WRITE 0 x51#define ARMV7_A12_PERFCTR_PC_WRITE_SPEC 0 x76#define ARMV7_A12_PERFCTR_PF_TLB_REFILL 0 xe7/* ARMv7 Krait specific event types */ #define KRAIT_PMRESR0_GROUP0 0 xcc#define KRAIT_PMRESR1_GROUP0 0 xd0#define KRAIT_PMRESR2_GROUP0 0 xd4#define KRAIT_VPMRESR0_GROUP0 0 xd8#define KRAIT_PERFCTR_L1_ICACHE_ACCESS 0 x10011#define KRAIT_PERFCTR_L1_ICACHE_MISS 0 x10010#define KRAIT_PERFCTR_L1_ITLB_ACCESS 0 x12222#define KRAIT_PERFCTR_L1_DTLB_ACCESS 0 x12210/* ARMv7 Scorpion specific event types */ #define SCORPION_LPM0_GROUP0 0 x4c#define SCORPION_LPM1_GROUP0 0 x50#define SCORPION_LPM2_GROUP0 0 x54#define SCORPION_L2LPM_GROUP0 0 x58#define SCORPION_VLPM_GROUP0 0 x5c#define SCORPION_ICACHE_ACCESS 0 x10053#define SCORPION_ICACHE_MISS 0 x10052#define SCORPION_DTLB_ACCESS 0 x12013#define SCORPION_DTLB_MISS 0 x12012#define SCORPION_ITLB_MISS 0 x12021/* * Cortex - A8 HW events mapping * * The hardware events that we support . We do support cache operations but * we have harvard caches and no way to combine instruction and data * accesses / misses in hardware . static const unsigned armv7_a8_perf_map[PERF_COUNT_HW_MAX] = {static const unsigned armv7_a8_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]/* * The performance counters don ' t differentiate between read and write * accesses / misses so this isn ' t strictly correct , but it ' s the best we * can do . Writes and reads get combined . /* * Cortex - A9 HW events mapping static const unsigned armv7_a9_perf_map[PERF_COUNT_HW_MAX] = {static const unsigned armv7_a9_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]/* * The performance counters don ' t differentiate between read and write * accesses / misses so this isn ' t strictly correct , but it ' s the best we * can do . Writes and reads get combined . /* * Cortex - A5 HW events mapping static const unsigned armv7_a5_perf_map[PERF_COUNT_HW_MAX] = {static const unsigned armv7_a5_perf_cache_map[PERF_COUNT_HW_CACHE_MAX],/* * The prefetch counters don ' t differentiate between the I side and the * D side . ,/* * Cortex - A15 HW events mapping static const unsigned armv7_a15_perf_map[PERF_COUNT_HW_MAX] = {static const unsigned armv7_a15_perf_cache_map[PERF_COUNT_HW_CACHE_MAX],/* * Not all performance counters differentiate between read and write * accesses / misses so we ' re not always strictly correct , but it ' s the * best we can do . Writes and reads get combined in these cases . /* * Cortex - A7 HW events mapping static const unsigned armv7_a7_perf_map[PERF_COUNT_HW_MAX] = {static const unsigned armv7_a7_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]/* * The performance counters don ' t differentiate between read and write * accesses / misses so this isn ' t strictly correct , but it ' s the best we * can do . Writes and reads get combined . /* * Cortex - A12 HW events mapping static const unsigned armv7_a12_perf_map[PERF_COUNT_HW_MAX] = {static const unsigned armv7_a12_perf_cache_map[PERF_COUNT_HW_CACHE_MAX],/* * Not all performance counters differentiate between read and write * accesses / misses so we ' re not always strictly correct , but it ' s the * best we can do . Writes and reads get combined in these cases . /* * Krait HW events mapping static const unsigned krait_perf_map[PERF_COUNT_HW_MAX] = {static const unsigned krait_perf_map_no_branch[PERF_COUNT_HW_MAX] = {static const unsigned krait_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]/* * The performance counters don ' t differentiate between read and write * accesses / misses so this isn ' t strictly correct , but it ' s the best we * can do . Writes and reads get combined . /* * Scorpion HW events mapping static const unsigned scorpion_perf_map[PERF_COUNT_HW_MAX] = {static const unsigned scorpion_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]/* * The performance counters don ' t differentiate between read and write * accesses / misses so this isn ' t strictly correct , but it ' s the best we * can do . Writes and reads get combined . /* * Only ITLB misses and DTLB refills are supported . If users want the * DTLB refills misses a raw counter must be used . "config:0-7" );static struct attribute *armv7_pmu_format_attrs[] = {static struct attribute_group armv7_pmu_format_attr_group = {"format" ,#define ARMV7_EVENT_ATTR_RESOLVE(m) #m #define ARMV7_EVENT_ATTR(name, config) \## name, \"event=" ARMV7_EVENT_ATTR_RESOLVE(config))static struct attribute *armv7_pmuv1_event_attrs[] = {static struct attribute_group armv7_pmuv1_events_attr_group = {"events" ,static struct attribute *armv7_pmuv2_event_attrs[] = {static struct attribute_group armv7_pmuv2_events_attr_group = {"events" ,/* * Perf Events ' indices #define ARMV7_IDX_CYCLE_COUNTER 31 #define ARMV7_IDX_COUNTER_MAX 31 /* * ARMv7 low level PMNC access /* * Per - CPU PMNC : config reg #define ARMV7_PMNC_E (1 << 0 ) /* Enable all counters */ #define ARMV7_PMNC_P (1 << 1 ) /* Reset all counters */ #define ARMV7_PMNC_C (1 << 2 ) /* Cycle counter reset */ #define ARMV7_PMNC_D (1 << 3 ) /* CCNT counts every 64th cpu cycle */ #define ARMV7_PMNC_X (1 << 4 ) /* Export to ETM */ #define ARMV7_PMNC_DP (1 << 5 ) /* Disable CCNT if non-invasive debug*/ #define ARMV7_PMNC_N_SHIFT 11 /* Number of counters supported */ #define ARMV7_PMNC_N_MASK 0 x1f#define ARMV7_PMNC_MASK 0 x3f /* Mask for writable bits */ /* * FLAG : counters overflow flag status reg #define ARMV7_FLAG_MASK 0 xffffffff /* Mask for writable bits */ #define ARMV7_OVERFLOWED_MASK ARMV7_FLAG_MASK/* * PMXEVTYPER : Event selection reg #define ARMV7_EVTYPE_MASK 0 xc80000ff /* Mask for writable bits */ #define ARMV7_EVTYPE_EVENT 0 xff /* Mask for EVENT bits */ /* * Event filters for PMUv2 #define ARMV7_EXCLUDE_PL1 BIT(31 )#define ARMV7_EXCLUDE_USER BIT(30 )#define ARMV7_INCLUDE_HYP BIT(27 )/* * Secure debug enable reg #define ARMV7_SDER_SUNIDEN BIT(1 ) /* Permit non-invasive debug */ static inline u32 armv7_pmnc_read(void )asm volatile ("mrc p15, 0, %0, c9, c12, 0" : "=r" (val));return val;static inline void armv7_pmnc_write(u32 val)asm volatile ("mcr p15, 0, %0, c9, c12, 0" : : "r" (val));static inline int armv7_pmnc_has_overflowed(u32 pmnc)return pmnc & ARMV7_OVERFLOWED_MASK;static inline int armv7_pmnc_counter_valid(struct arm_pmu *cpu_pmu, int idx)return test_bit(idx, cpu_pmu->cntr_mask);static inline int armv7_pmnc_counter_has_overflowed(u32 pmnc, int idx)return pmnc & BIT(idx);static inline void armv7_pmnc_select_counter(int idx)asm volatile ("mcr p15, 0, %0, c9, c12, 5" : : "r" (idx));static inline u64 armv7pmu_read_counter(struct perf_event *event)struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);struct hw_perf_event *hwc = &event->hw;int idx = hwc->idx;0 ;if (!armv7_pmnc_counter_valid(cpu_pmu, idx)) {"CPU%u reading wrong counter %d\n" ,else if (idx == ARMV7_IDX_CYCLE_COUNTER) {asm volatile ("mrc p15, 0, %0, c9, c13, 0" : "=r" (value));else {asm volatile ("mrc p15, 0, %0, c9, c13, 2" : "=r" (value));return value;static inline void armv7pmu_write_counter(struct perf_event *event, u64 value)struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);struct hw_perf_event *hwc = &event->hw;int idx = hwc->idx;if (!armv7_pmnc_counter_valid(cpu_pmu, idx)) {"CPU%u writing wrong counter %d\n" ,else if (idx == ARMV7_IDX_CYCLE_COUNTER) {asm volatile ("mcr p15, 0, %0, c9, c13, 0" : : "r" ((u32)value));else {asm volatile ("mcr p15, 0, %0, c9, c13, 2" : : "r" ((u32)value));static inline void armv7_pmnc_write_evtsel(int idx, u32 val)asm volatile ("mcr p15, 0, %0, c9, c13, 1" : : "r" (val));static inline void armv7_pmnc_enable_counter(int idx)asm volatile ("mcr p15, 0, %0, c9, c12, 1" : : "r" (BIT(idx)));static inline void armv7_pmnc_disable_counter(int idx)asm volatile ("mcr p15, 0, %0, c9, c12, 2" : : "r" (BIT(idx)));static inline void armv7_pmnc_enable_intens(int idx)asm volatile ("mcr p15, 0, %0, c9, c14, 1" : : "r" (BIT(idx)));static inline void armv7_pmnc_disable_intens(int idx)asm volatile ("mcr p15, 0, %0, c9, c14, 2" : : "r" (BIT(idx)));/* Clear the overflow flag in case an interrupt is pending. */ asm volatile ("mcr p15, 0, %0, c9, c12, 3" : : "r" (BIT(idx)));static inline u32 armv7_pmnc_getreset_flags(void )/* Read */ asm volatile ("mrc p15, 0, %0, c9, c12, 3" : "=r" (val));/* Write to clear flags */ asm volatile ("mcr p15, 0, %0, c9, c12, 3" : : "r" (val));return val;#ifdef DEBUGstatic void armv7_pmnc_dump_regs(struct arm_pmu *cpu_pmu)unsigned int cnt;"PMNC registers dump:\n" );asm volatile ("mrc p15, 0, %0, c9, c12, 0" : "=r" (val));"PMNC =0x%08x\n" , val);asm volatile ("mrc p15, 0, %0, c9, c12, 1" : "=r" (val));"CNTENS=0x%08x\n" , val);asm volatile ("mrc p15, 0, %0, c9, c14, 1" : "=r" (val));"INTENS=0x%08x\n" , val);asm volatile ("mrc p15, 0, %0, c9, c12, 3" : "=r" (val));"FLAGS =0x%08x\n" , val);asm volatile ("mrc p15, 0, %0, c9, c12, 5" : "=r" (val));"SELECT=0x%08x\n" , val);asm volatile ("mrc p15, 0, %0, c9, c13, 0" : "=r" (val));"CCNT =0x%08x\n" , val);asm volatile ("mrc p15, 0, %0, c9, c13, 2" : "=r" (val));"CNT[%d] count =0x%08x\n" , cnt, val);asm volatile ("mrc p15, 0, %0, c9, c13, 1" : "=r" (val));"CNT[%d] evtsel=0x%08x\n" , cnt, val);#endif static void armv7pmu_enable_event(struct perf_event *event)struct hw_perf_event *hwc = &event->hw;struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);int idx = hwc->idx;if (!armv7_pmnc_counter_valid(cpu_pmu, idx)) {"CPU%u enabling wrong PMNC counter IRQ enable %d\n" ,return ;/* * Set event ( if destined for PMNx counters ) * We only need to set the event for the cycle counter if we * have the ability to perform event filtering . if (cpu_pmu->set_event_filter || idx != ARMV7_IDX_CYCLE_COUNTER)static void armv7pmu_disable_event(struct perf_event *event)struct hw_perf_event *hwc = &event->hw;struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);int idx = hwc->idx;if (!armv7_pmnc_counter_valid(cpu_pmu, idx)) {"CPU%u disabling wrong PMNC counter IRQ enable %d\n" ,return ;static irqreturn_t armv7pmu_handle_irq(struct arm_pmu *cpu_pmu)struct perf_sample_data data;struct pmu_hw_events *cpuc = this_cpu_ptr(cpu_pmu->hw_events);struct pt_regs *regs;int idx;/* * Get and reset the IRQ flags /* * Did an overflow occur ? if (!armv7_pmnc_has_overflowed(pmnc))return IRQ_NONE;/* * Handle the counter ( s ) overflow ( s ) struct perf_event *event = cpuc->events[idx];struct hw_perf_event *hwc;/* Ignore if we don't have an event. */ if (!event)continue ;/* * We have a single interrupt for all counters . Check that * each counter has overflowed before we process it . if (!armv7_pmnc_counter_has_overflowed(pmnc, idx))continue ;0 , hwc->last_period);if (!armpmu_event_set_period(event))continue ;/* * Handle the pending perf events . * * Note : this call * must * be run with interrupts disabled . For * platforms that can have the PMU interrupts raised as an NMI , this * will not work . return IRQ_HANDLED;static void armv7pmu_start(struct arm_pmu *cpu_pmu)/* Enable all counters */ static void armv7pmu_stop(struct arm_pmu *cpu_pmu)/* Disable all counters */ static int armv7pmu_get_event_idx(struct pmu_hw_events *cpuc,struct perf_event *event)int idx;struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);struct hw_perf_event *hwc = &event->hw;unsigned long evtype = hwc->config_base & ARMV7_EVTYPE_EVENT;/* Always place a cycle counter into the cycle counter. */ if (evtype == ARMV7_PERFCTR_CPU_CYCLES) {if (test_and_set_bit(ARMV7_IDX_CYCLE_COUNTER, cpuc->used_mask))return -EAGAIN;return ARMV7_IDX_CYCLE_COUNTER;/* * For anything other than a cycle counter , try and use * the events counters if (!test_and_set_bit(idx, cpuc->used_mask))return idx;/* The counters are all in use. */ return -EAGAIN;static void armv7pmu_clear_event_idx(struct pmu_hw_events *cpuc,struct perf_event *event)/* * Add an event filter to a given event . This will only work for PMUv2 PMUs . static int armv7pmu_set_event_filter(struct hw_perf_event *event,struct perf_event_attr *attr)unsigned long config_base = 0 ;if (attr->exclude_idle) {"ARM performance counters do not support mode exclusion\n" );return -EOPNOTSUPP;if (attr->exclude_user)if (attr->exclude_kernel)if (!attr->exclude_hv)/* * Install the filter into config_base as this is used to * construct the event type . return 0 ;static void armv7pmu_reset(void *info)struct arm_pmu *cpu_pmu = (struct arm_pmu *)info;if (cpu_pmu->secure_access) {asm volatile ("mrc p15, 0, %0, c1, c1, 1" : "=r" (val));asm volatile ("mcr p15, 0, %0, c1, c1, 1" : : "r" (val));/* The counter and interrupt enable registers are unknown at reset. */ /* Initialize & Reset PMNC: C and P bits */ static int armv7_a8_map_event(struct perf_event *event)return armpmu_map_event(event, &armv7_a8_perf_map,0 xFF);static int armv7_a9_map_event(struct perf_event *event)return armpmu_map_event(event, &armv7_a9_perf_map,0 xFF);static int armv7_a5_map_event(struct perf_event *event)return armpmu_map_event(event, &armv7_a5_perf_map,0 xFF);static int armv7_a15_map_event(struct perf_event *event)return armpmu_map_event(event, &armv7_a15_perf_map,0 xFF);static int armv7_a7_map_event(struct perf_event *event)return armpmu_map_event(event, &armv7_a7_perf_map,0 xFF);static int armv7_a12_map_event(struct perf_event *event)return armpmu_map_event(event, &armv7_a12_perf_map,0 xFF);static int krait_map_event(struct perf_event *event)return armpmu_map_event(event, &krait_perf_map,0 xFFFFF);static int krait_map_event_no_branch(struct perf_event *event)return armpmu_map_event(event, &krait_perf_map_no_branch,0 xFFFFF);static int scorpion_map_event(struct perf_event *event)return armpmu_map_event(event, &scorpion_perf_map,0 xFFFFF);static void armv7pmu_init(struct arm_pmu *cpu_pmu)static void armv7_read_num_pmnc_events(void *info)int nb_cnt;struct arm_pmu *cpu_pmu = info;/* Read the nb of CNTx counters supported from PMNC */ 0 , nb_cnt);/* Add the CPU cycles counter */ static int armv7_probe_num_events(struct arm_pmu *arm_pmu)return smp_call_function_any(&arm_pmu->supported_cpus,1 );static int armv7_a8_pmu_init(struct arm_pmu *cpu_pmu)"armv7_cortex_a8" ;return armv7_probe_num_events(cpu_pmu);static int armv7_a9_pmu_init(struct arm_pmu *cpu_pmu)"armv7_cortex_a9" ;return armv7_probe_num_events(cpu_pmu);static int armv7_a5_pmu_init(struct arm_pmu *cpu_pmu)"armv7_cortex_a5" ;return armv7_probe_num_events(cpu_pmu);static int armv7_a15_pmu_init(struct arm_pmu *cpu_pmu)"armv7_cortex_a15" ;return armv7_probe_num_events(cpu_pmu);static int armv7_a7_pmu_init(struct arm_pmu *cpu_pmu)"armv7_cortex_a7" ;return armv7_probe_num_events(cpu_pmu);static int armv7_a12_pmu_init(struct arm_pmu *cpu_pmu)"armv7_cortex_a12" ;return armv7_probe_num_events(cpu_pmu);static int armv7_a17_pmu_init(struct arm_pmu *cpu_pmu)int ret = armv7_a12_pmu_init(cpu_pmu);"armv7_cortex_a17" ;return ret;/* * Krait Performance Monitor Region Event Selection Register ( PMRESRn ) * * 31 30 24 16 8 0 * + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + * PMRESR0 | EN | CC | CC | CC | CC | N = 1 , R = 0 * + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + * PMRESR1 | EN | CC | CC | CC | CC | N = 1 , R = 1 * + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + * PMRESR2 | EN | CC | CC | CC | CC | N = 1 , R = 2 * + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + * VPMRESR0 | EN | CC | CC | CC | CC | N = 2 , R = ? * + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + * EN | G = 3 | G = 2 | G = 1 | G = 0 * * Event Encoding : * * hwc - > config_base = 0 xNRCCG * * N = prefix , 1 for Krait CPU ( PMRESRn ) , 2 for Venum VFP ( VPMRESR ) * R = region register * CC = class of events the group G is choosing from * G = group or particular event * * Example : 0 x12021 is a Krait CPU event in PMRESR2 ' s group 1 with code 2 * * A region ( R ) corresponds to a piece of the CPU ( execution unit , instruction * unit , etc . ) while the event code ( CC ) corresponds to a particular class of * events ( interrupts for example ) . An event code is broken down into * groups ( G ) that can be mapped into the PMU ( irq , fiqs , and irq + fiqs for * example ) . #define KRAIT_EVENT (1 << 16 )#define VENUM_EVENT (2 << 16 )#define KRAIT_EVENT_MASK (KRAIT_EVENT | VENUM_EVENT)#define PMRESRn_EN BIT(31 )#define EVENT_REGION(event) (((event) >> 12 ) & 0 xf) /* R */ #define EVENT_GROUP(event) ((event) & 0 xf) /* G */ #define EVENT_CODE(event) (((event) >> 4 ) & 0 xff) /* CC */ #define EVENT_VENUM(event) (!!(event & VENUM_EVENT)) /* N=2 */ #define EVENT_CPU(event) (!!(event & KRAIT_EVENT)) /* N=1 */ static u32 krait_read_pmresrn(int n)switch (n) {case 0 :asm volatile ("mrc p15, 1, %0, c9, c15, 0" : "=r" (val));break ;case 1 :asm volatile ("mrc p15, 1, %0, c9, c15, 1" : "=r" (val));break ;case 2 :asm volatile ("mrc p15, 1, %0, c9, c15, 2" : "=r" (val));break ;default :/* Should be validated in krait_pmu_get_event_idx() */ return val;static void krait_write_pmresrn(int n, u32 val)switch (n) {case 0 :asm volatile ("mcr p15, 1, %0, c9, c15, 0" : : "r" (val));break ;case 1 :asm volatile ("mcr p15, 1, %0, c9, c15, 1" : : "r" (val));break ;case 2 :asm volatile ("mcr p15, 1, %0, c9, c15, 2" : : "r" (val));break ;default :/* Should be validated in krait_pmu_get_event_idx() */ static u32 venum_read_pmresr(void )asm volatile ("mrc p10, 7, %0, c11, c0, 0" : "=r" (val));return val;static void venum_write_pmresr(u32 val)asm volatile ("mcr p10, 7, %0, c11, c0, 0" : : "r" (val));static void venum_pre_pmresr(u32 *venum_orig_val, u32 *fp_orig_val)/* CPACR Enable CP10 and CP11 access */ 10 ) | CPACC_SVC(11 );/* Enable FPEXC */ static void venum_post_pmresr(u32 venum_orig_val, u32 fp_orig_val)/* Restore FPEXC */ /* Restore CPACR */ static u32 krait_get_pmresrn_event(unsigned int region)static const u32 pmresrn_table[] = { KRAIT_PMRESR0_GROUP0,return pmresrn_table[region];static void krait_evt_setup(int idx, u32 config_base)unsigned int region = EVENT_REGION(config_base);unsigned int group = EVENT_GROUP(config_base);unsigned int code = EVENT_CODE(config_base);unsigned int group_shift;bool venum_event = EVENT_VENUM(config_base);8 ;0 xff << group_shift;/* Configure evtsel for the region and group */ if (venum_event)else /* Mix in mode-exclusion bits */ if (venum_event) {else {static u32 clear_pmresrn_group(u32 val, int group)int group_shift;8 ;0 xff << group_shift;/* Don't clear enable bit if entire region isn't disabled */ if (val & ~PMRESRn_EN)return val |= PMRESRn_EN;return 0 ;static void krait_clearpmu(u32 config_base)unsigned int region = EVENT_REGION(config_base);unsigned int group = EVENT_GROUP(config_base);bool venum_event = EVENT_VENUM(config_base);if (venum_event) {else {static void krait_pmu_disable_event(struct perf_event *event)struct hw_perf_event *hwc = &event->hw;int idx = hwc->idx;/* Disable counter and interrupt */ /* Disable counter */ /* * Clear pmresr code ( if destined for PMNx counters ) if (hwc->config_base & KRAIT_EVENT_MASK)/* Disable interrupt for this counter */ static void krait_pmu_enable_event(struct perf_event *event)struct hw_perf_event *hwc = &event->hw;int idx = hwc->idx;/* * Set event ( if destined for PMNx counters ) * We set the event for the cycle counter because we * have the ability to perform event filtering . if (hwc->config_base & KRAIT_EVENT_MASK)else static void krait_pmu_reset(void *info)struct arm_pmu *cpu_pmu = info;/* Clear all pmresrs */ 0 , 0 );1 , 0 );2 , 0 );0 );/* Reset PMxEVNCTCR to sane default */ asm volatile ("mcr p15, 0, %0, c9, c15, 0" : : "r" (0 ));static int krait_event_to_bit(struct perf_event *event, unsigned int region,unsigned int group)int bit;struct hw_perf_event *hwc = &event->hw;struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);if (hwc->config_base & VENUM_EVENT)else 0 );/* * Lower bits are reserved for use by the counters ( see * armv7pmu_get_event_idx ( ) for more info ) return bit;/* * We check for column exclusion constraints here . * Two events cant use the same group within a pmresr register . static int krait_pmu_get_event_idx(struct pmu_hw_events *cpuc,struct perf_event *event)int idx;int bit = -1 ;struct hw_perf_event *hwc = &event->hw;unsigned int region = EVENT_REGION(hwc->config_base);unsigned int code = EVENT_CODE(hwc->config_base);unsigned int group = EVENT_GROUP(hwc->config_base);bool venum_event = EVENT_VENUM(hwc->config_base);bool krait_event = EVENT_CPU(hwc->config_base);if (venum_event || krait_event) {/* Ignore invalid events */ if (group > 3 || region > 2 )return -EINVAL;if (venum_event && (code & 0 xe0))return -EINVAL;if (test_and_set_bit(bit, cpuc->used_mask))return -EAGAIN;if (idx < 0 && bit >= 0 )return idx;static void krait_pmu_clear_event_idx(struct pmu_hw_events *cpuc,struct perf_event *event)int bit;struct hw_perf_event *hwc = &event->hw;unsigned int region = EVENT_REGION(hwc->config_base);unsigned int group = EVENT_GROUP(hwc->config_base);bool venum_event = EVENT_VENUM(hwc->config_base);bool krait_event = EVENT_CPU(hwc->config_base);if (venum_event || krait_event) {static int krait_pmu_init(struct arm_pmu *cpu_pmu)"armv7_krait" ;/* Some early versions of Krait don't support PC write events */ if (of_property_read_bool(cpu_pmu->plat_device->dev.of_node,"qcom,no-pc-write" ))else return armv7_probe_num_events(cpu_pmu);/* * Scorpion Local Performance Monitor Register ( LPMn ) * * 31 30 24 16 8 0 * + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + * LPM0 | EN | CC | CC | CC | CC | N = 1 , R = 0 * + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + * LPM1 | EN | CC | CC | CC | CC | N = 1 , R = 1 * + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + * LPM2 | EN | CC | CC | CC | CC | N = 1 , R = 2 * + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + * L2LPM | EN | CC | CC | CC | CC | N = 1 , R = 3 * + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + * VLPM | EN | CC | CC | CC | CC | N = 2 , R = ? * + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + * EN | G = 3 | G = 2 | G = 1 | G = 0 * * * Event Encoding : * * hwc - > config_base = 0 xNRCCG * * N = prefix , 1 for Scorpion CPU ( LPMn / L2LPM ) , 2 for Venum VFP ( VLPM ) * R = region register * CC = class of events the group G is choosing from * G = group or particular event * * Example : 0 x12021 is a Scorpion CPU event in LPM2 ' s group 1 with code 2 * * A region ( R ) corresponds to a piece of the CPU ( execution unit , instruction * unit , etc . ) while the event code ( CC ) corresponds to a particular class of * events ( interrupts for example ) . An event code is broken down into * groups ( G ) that can be mapped into the PMU ( irq , fiqs , and irq + fiqs for * example ) . static u32 scorpion_read_pmresrn(int n)switch (n) {case 0 :asm volatile ("mrc p15, 0, %0, c15, c0, 0" : "=r" (val));break ;case 1 :asm volatile ("mrc p15, 1, %0, c15, c0, 0" : "=r" (val));break ;case 2 :asm volatile ("mrc p15, 2, %0, c15, c0, 0" : "=r" (val));break ;case 3 :asm volatile ("mrc p15, 3, %0, c15, c2, 0" : "=r" (val));break ;default :/* Should be validated in scorpion_pmu_get_event_idx() */ return val;static void scorpion_write_pmresrn(int n, u32 val)switch (n) {case 0 :asm volatile ("mcr p15, 0, %0, c15, c0, 0" : : "r" (val));break ;case 1 :asm volatile ("mcr p15, 1, %0, c15, c0, 0" : : "r" (val));break ;case 2 :asm volatile ("mcr p15, 2, %0, c15, c0, 0" : : "r" (val));break ;case 3 :asm volatile ("mcr p15, 3, %0, c15, c2, 0" : : "r" (val));break ;default :/* Should be validated in scorpion_pmu_get_event_idx() */ static u32 scorpion_get_pmresrn_event(unsigned int region)static const u32 pmresrn_table[] = { SCORPION_LPM0_GROUP0,return pmresrn_table[region];static void scorpion_evt_setup(int idx, u32 config_base)unsigned int region = EVENT_REGION(config_base);unsigned int group = EVENT_GROUP(config_base);unsigned int code = EVENT_CODE(config_base);unsigned int group_shift;bool venum_event = EVENT_VENUM(config_base);8 ;0 xff << group_shift;/* Configure evtsel for the region and group */ if (venum_event)else /* Mix in mode-exclusion bits */ asm volatile ("mcr p15, 0, %0, c9, c15, 0" : : "r" (0 ));if (venum_event) {else {static void scorpion_clearpmu(u32 config_base)unsigned int region = EVENT_REGION(config_base);unsigned int group = EVENT_GROUP(config_base);bool venum_event = EVENT_VENUM(config_base);if (venum_event) {else {static void scorpion_pmu_disable_event(struct perf_event *event)struct hw_perf_event *hwc = &event->hw;int idx = hwc->idx;/* Disable counter and interrupt */ /* Disable counter */ /* * Clear pmresr code ( if destined for PMNx counters ) if (hwc->config_base & KRAIT_EVENT_MASK)/* Disable interrupt for this counter */ static void scorpion_pmu_enable_event(struct perf_event *event)struct hw_perf_event *hwc = &event->hw;int idx = hwc->idx;/* * Set event ( if destined for PMNx counters ) * We don ' t set the event for the cycle counter because we * don ' t have the ability to perform event filtering . if (hwc->config_base & KRAIT_EVENT_MASK)else if (idx != ARMV7_IDX_CYCLE_COUNTER)static void scorpion_pmu_reset(void *info)struct arm_pmu *cpu_pmu = info;/* Clear all pmresrs */ 0 , 0 );1 , 0 );2 , 0 );3 , 0 );0 );/* Reset PMxEVNCTCR to sane default */ asm volatile ("mcr p15, 0, %0, c9, c15, 0" : : "r" (0 ));static int scorpion_event_to_bit(struct perf_event *event, unsigned int region,unsigned int group)int bit;struct hw_perf_event *hwc = &event->hw;struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);if (hwc->config_base & VENUM_EVENT)else 0 );/* * Lower bits are reserved for use by the counters ( see * armv7pmu_get_event_idx ( ) for more info ) return bit;/* * We check for column exclusion constraints here . * Two events cant use the same group within a pmresr register . static int scorpion_pmu_get_event_idx(struct pmu_hw_events *cpuc,struct perf_event *event)int idx;int bit = -1 ;struct hw_perf_event *hwc = &event->hw;unsigned int region = EVENT_REGION(hwc->config_base);unsigned int group = EVENT_GROUP(hwc->config_base);bool venum_event = EVENT_VENUM(hwc->config_base);bool scorpion_event = EVENT_CPU(hwc->config_base);if (venum_event || scorpion_event) {/* Ignore invalid events */ if (group > 3 || region > 3 )return -EINVAL;if (test_and_set_bit(bit, cpuc->used_mask))return -EAGAIN;if (idx < 0 && bit >= 0 )return idx;static void scorpion_pmu_clear_event_idx(struct pmu_hw_events *cpuc,struct perf_event *event)int bit;struct hw_perf_event *hwc = &event->hw;unsigned int region = EVENT_REGION(hwc->config_base);unsigned int group = EVENT_GROUP(hwc->config_base);bool venum_event = EVENT_VENUM(hwc->config_base);bool scorpion_event = EVENT_CPU(hwc->config_base);if (venum_event || scorpion_event) {static int scorpion_pmu_init(struct arm_pmu *cpu_pmu)"armv7_scorpion" ;return armv7_probe_num_events(cpu_pmu);static int scorpion_mp_pmu_init(struct arm_pmu *cpu_pmu)"armv7_scorpion_mp" ;return armv7_probe_num_events(cpu_pmu);static const struct of_device_id armv7_pmu_of_device_ids[] = {"arm,cortex-a17-pmu" , .data = armv7_a17_pmu_init},"arm,cortex-a15-pmu" , .data = armv7_a15_pmu_init},"arm,cortex-a12-pmu" , .data = armv7_a12_pmu_init},"arm,cortex-a9-pmu" , .data = armv7_a9_pmu_init},"arm,cortex-a8-pmu" , .data = armv7_a8_pmu_init},"arm,cortex-a7-pmu" , .data = armv7_a7_pmu_init},"arm,cortex-a5-pmu" , .data = armv7_a5_pmu_init},"qcom,krait-pmu" , .data = krait_pmu_init},"qcom,scorpion-pmu" , .data = scorpion_pmu_init},"qcom,scorpion-mp-pmu" , .data = scorpion_mp_pmu_init},static int armv7_pmu_device_probe(struct platform_device *pdev)return arm_pmu_device_probe(pdev, armv7_pmu_of_device_ids, NULL);static struct platform_driver armv7_pmu_driver = {"armv7-pmu" ,true ,
Messung V0.5 in Prozent C=95 H=88 G=91
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(vorverarbeitet am 2026-09-27)
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