Quellcode-Bibliothek habanalabs_accel.h
Sprache: C
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note * * Copyright 2016 - 2023 HabanaLabs , Ltd . * All Rights Reserved . * #ifndef HABANALABS_H_#define HABANALABS_H_#include <drm/drm.h>/* * Defines that are asic - specific but constitutes as ABI between kernel driver * and userspace #define GOYA_KMD_SRAM_RESERVED_SIZE_FROM_START 0 x8000 /* 32KB */ #define GAUDI_DRIVER_SRAM_RESERVED_SIZE_FROM_START 0 x80 /* 128 bytes */ /* * 128 SOBs reserved for collective wait * 16 SOBs reserved for sync stream #define GAUDI_FIRST_AVAILABLE_W_S_SYNC_OBJECT 144 /* * 64 monitors reserved for collective wait * 8 monitors reserved for sync stream #define GAUDI_FIRST_AVAILABLE_W_S_MONITOR 72 /* Max number of elements in timestamps registration buffers */ #define TS_MAX_ELEMENTS_NUM (1 << 20 ) /* 1MB */ /* * Goya queue Numbering * * The external queues ( PCI DMA channels ) MUST be before the internal queues * and each group ( PCI DMA channels and internal ) must be contiguous inside * itself but there can be a gap between the two groups ( although not * recommended ) enum goya_queue_id {0 ,1 ,2 ,3 ,4 ,5 ,6 , /* Internal queues start here */ 7 ,8 ,9 ,10 ,11 ,12 ,13 ,14 ,/* * Gaudi queue Numbering * External queues ( PCI DMA channels ) are DMA_0_ * , DMA_1_ * and DMA_5_ * . * Except one CPU queue , all the rest are internal queues . enum gaudi_queue_id {0 , /* external */ 1 , /* external */ 2 , /* external */ 3 , /* external */ 4 , /* external */ 5 , /* external */ 6 , /* external */ 7 , /* external */ 8 , /* CPU */ 9 , /* internal */ 10 , /* internal */ 11 , /* internal */ 12 , /* internal */ 13 , /* internal */ 14 , /* internal */ 15 , /* internal */ 16 , /* internal */ 17 , /* internal */ 18 , /* internal */ 19 , /* internal */ 20 , /* internal */ 21 , /* internal */ 22 , /* internal */ 23 , /* internal */ 24 , /* internal */ 25 , /* internal */ 26 , /* internal */ 27 , /* internal */ 28 , /* internal */ 29 , /* internal */ 30 , /* internal */ 31 , /* internal */ 32 , /* internal */ 33 , /* internal */ 34 , /* internal */ 35 , /* internal */ 36 , /* internal */ 37 , /* internal */ 38 , /* internal */ 39 , /* internal */ 40 , /* internal */ 41 , /* internal */ 42 , /* internal */ 43 , /* internal */ 44 , /* internal */ 45 , /* internal */ 46 , /* internal */ 47 , /* internal */ 48 , /* internal */ 49 , /* internal */ 50 , /* internal */ 51 , /* internal */ 52 , /* internal */ 53 , /* internal */ 54 , /* internal */ 55 , /* internal */ 56 , /* internal */ 57 , /* internal */ 58 , /* internal */ 59 , /* internal */ 60 , /* internal */ 61 , /* internal */ 62 , /* internal */ 63 , /* internal */ 64 , /* internal */ 65 , /* internal */ 66 , /* internal */ 67 , /* internal */ 68 , /* internal */ 69 , /* internal */ 70 , /* internal */ 71 , /* internal */ 72 , /* internal */ 73 , /* internal */ 74 , /* internal */ 75 , /* internal */ 76 , /* internal */ 77 , /* internal */ 78 , /* internal */ 79 , /* internal */ 80 , /* internal */ 81 , /* internal */ 82 , /* internal */ 83 , /* internal */ 84 , /* internal */ 85 , /* internal */ 86 , /* internal */ 87 , /* internal */ 88 , /* internal */ 89 , /* internal */ 90 , /* internal */ 91 , /* internal */ 92 , /* internal */ 93 , /* internal */ 94 , /* internal */ 95 , /* internal */ 96 , /* internal */ 97 , /* internal */ 98 , /* internal */ 99 , /* internal */ 100 , /* internal */ 101 , /* internal */ 102 , /* internal */ 103 , /* internal */ 104 , /* internal */ 105 , /* internal */ 106 , /* internal */ 107 , /* internal */ 108 , /* internal */ 109 , /* internal */ 110 , /* internal */ 111 , /* internal */ 112 , /* internal */ /* * In GAUDI2 we have two modes of operation in regard to queues : * 1 . Legacy mode , where each QMAN exposes 4 streams to the user * 2 . F / W mode , where we use F / W to schedule the JOBS to the different queues . * * When in legacy mode , the user sends the queue id per JOB according to * enum gaudi2_queue_id below . * * When in F / W mode , the user sends a stream id per Command Submission . The * stream id is a running number from 0 up to ( N - 1 ) , where N is the number * of streams the F / W exposes and is passed to the user in * struct hl_info_hw_ip_info enum gaudi2_queue_id {0 ,1 ,2 ,3 ,4 ,5 ,6 ,7 ,8 ,9 ,10 ,11 ,12 ,13 ,14 ,15 ,16 ,17 ,18 ,19 ,20 ,21 ,22 ,23 ,24 ,25 ,26 ,27 ,28 ,29 ,30 ,31 ,32 ,33 ,34 ,35 ,36 ,37 ,38 ,39 ,40 ,41 ,42 ,43 ,44 ,45 ,46 ,47 ,48 ,49 ,50 ,51 ,52 ,53 ,54 ,55 ,56 ,57 ,58 ,59 ,60 ,61 ,62 ,63 ,64 ,65 ,66 ,67 ,68 ,69 ,70 ,71 ,72 ,73 ,74 ,75 ,76 ,77 ,78 ,79 ,80 ,81 ,82 ,83 ,84 ,85 ,86 ,87 ,88 ,89 ,90 ,91 ,92 ,93 ,94 ,95 ,96 ,97 ,98 ,99 ,100 ,101 ,102 ,103 ,104 ,105 ,106 ,107 ,108 ,109 ,110 ,111 ,112 ,113 ,114 ,115 ,116 ,117 ,118 ,119 ,120 ,121 ,122 ,123 ,124 ,125 ,126 ,127 ,128 ,129 ,130 ,131 ,132 ,133 ,134 ,135 ,136 ,137 ,138 ,139 ,140 ,141 ,142 ,143 ,144 ,145 ,146 ,147 ,148 ,149 ,150 ,151 ,152 ,153 ,154 ,155 ,156 ,157 ,158 ,159 ,160 ,161 ,162 ,163 ,164 ,165 ,166 ,167 ,168 ,169 ,170 ,171 ,172 ,173 ,174 ,175 ,176 ,177 ,178 ,179 ,180 ,181 ,182 ,183 ,184 ,185 ,186 ,187 ,188 ,189 ,190 ,191 ,192 ,193 ,194 ,195 ,196 ,197 ,198 ,199 ,200 ,201 ,202 ,203 ,204 ,205 ,206 ,207 ,208 ,209 ,210 ,211 ,212 ,213 ,214 ,215 ,216 ,217 ,218 ,219 ,220 ,221 ,222 ,223 ,224 ,225 ,226 ,227 ,228 ,229 ,230 ,231 ,232 ,233 ,234 ,235 ,236 ,237 ,238 ,239 ,240 ,241 ,242 ,243 ,244 ,245 ,246 ,247 ,248 ,249 ,250 ,251 ,252 ,253 ,254 ,255 ,256 ,257 ,258 ,259 ,260 ,/* * Engine Numbering * * Used in the " busy_engines_mask " field in ` struct hl_info_hw_idle ' enum goya_engine_id {0 ,enum gaudi_engine_id {0 ,enum gaudi2_engine_id {0 ,/* * ASIC specific PLL index * * Used to retrieve in frequency info of different IPs via HL_INFO_PLL_FREQUENCY under * DRM_IOCTL_HL_INFO IOCTL . * The enums need to be used as an index in struct hl_pll_frequency_info . enum hl_goya_pll_index {0 ,enum hl_gaudi_pll_index {0 ,enum hl_gaudi2_pll_index {0 ,/** * enum hl_goya_dma_direction - Direction of DMA operation inside a LIN_DMA packet that is * submitted to the GOYA ' s DMA QMAN . This attribute is not relevant * to the H / W but the kernel driver use it to parse the packet ' s * addresses and patch / validate them . * @ HL_DMA_HOST_TO_DRAM : DMA operation from Host memory to GOYA ' s DDR . * @ HL_DMA_HOST_TO_SRAM : DMA operation from Host memory to GOYA ' s SRAM . * @ HL_DMA_DRAM_TO_SRAM : DMA operation from GOYA ' s DDR to GOYA ' s SRAM . * @ HL_DMA_SRAM_TO_DRAM : DMA operation from GOYA ' s SRAM to GOYA ' s DDR . * @ HL_DMA_SRAM_TO_HOST : DMA operation from GOYA ' s SRAM to Host memory . * @ HL_DMA_DRAM_TO_HOST : DMA operation from GOYA ' s DDR to Host memory . * @ HL_DMA_DRAM_TO_DRAM : DMA operation from GOYA ' s DDR to GOYA ' s DDR . * @ HL_DMA_SRAM_TO_SRAM : DMA operation from GOYA ' s SRAM to GOYA ' s SRAM . * @ HL_DMA_ENUM_MAX : number of values in enum enum hl_goya_dma_direction {/** * enum hl_device_status - Device status information . * @ HL_DEVICE_STATUS_OPERATIONAL : Device is operational . * @ HL_DEVICE_STATUS_IN_RESET : Device is currently during reset . * @ HL_DEVICE_STATUS_MALFUNCTION : Device is unusable . * @ HL_DEVICE_STATUS_NEEDS_RESET : Device needs reset because auto reset was disabled . * @ HL_DEVICE_STATUS_IN_DEVICE_CREATION : Device is operational but its creation is still in * progress . * @ HL_DEVICE_STATUS_IN_RESET_AFTER_DEVICE_RELEASE : Device is currently during reset that was * triggered because the user released the device * @ HL_DEVICE_STATUS_LAST : Last status . enum hl_device_status {enum hl_server_type {0 ,1 ,2 ,3 ,4 ,5 ,7 /* * Notifier event values - for the notification mechanism and the HL_INFO_GET_EVENTS command * * HL_NOTIFIER_EVENT_TPC_ASSERT - Indicates TPC assert event * HL_NOTIFIER_EVENT_UNDEFINED_OPCODE - Indicates undefined operation code * HL_NOTIFIER_EVENT_DEVICE_RESET - Indicates device requires a reset * HL_NOTIFIER_EVENT_CS_TIMEOUT - Indicates CS timeout error * HL_NOTIFIER_EVENT_DEVICE_UNAVAILABLE - Indicates device is unavailable * HL_NOTIFIER_EVENT_USER_ENGINE_ERR - Indicates device engine in error state * HL_NOTIFIER_EVENT_GENERAL_HW_ERR - Indicates device HW error * HL_NOTIFIER_EVENT_RAZWI - Indicates razwi happened * HL_NOTIFIER_EVENT_PAGE_FAULT - Indicates page fault happened * HL_NOTIFIER_EVENT_CRITICAL_HW_ERR - Indicates a HW error that requires SW abort and * HW reset * HL_NOTIFIER_EVENT_CRITICAL_FW_ERR - Indicates a FW error that requires SW abort and * HW reset #define HL_NOTIFIER_EVENT_TPC_ASSERT (1 ULL << 0 )#define HL_NOTIFIER_EVENT_UNDEFINED_OPCODE (1 ULL << 1 )#define HL_NOTIFIER_EVENT_DEVICE_RESET (1 ULL << 2 )#define HL_NOTIFIER_EVENT_CS_TIMEOUT (1 ULL << 3 )#define HL_NOTIFIER_EVENT_DEVICE_UNAVAILABLE (1 ULL << 4 )#define HL_NOTIFIER_EVENT_USER_ENGINE_ERR (1 ULL << 5 )#define HL_NOTIFIER_EVENT_GENERAL_HW_ERR (1 ULL << 6 )#define HL_NOTIFIER_EVENT_RAZWI (1 ULL << 7 )#define HL_NOTIFIER_EVENT_PAGE_FAULT (1 ULL << 8 )#define HL_NOTIFIER_EVENT_CRITICL_HW_ERR (1 ULL << 9 )#define HL_NOTIFIER_EVENT_CRITICL_FW_ERR (1 ULL << 10 )/* Opcode for management ioctl * * HW_IP_INFO - Receive information about different IP blocks in the * device . * HL_INFO_HW_EVENTS - Receive an array describing how many times each event * occurred since the last hard reset . * HL_INFO_DRAM_USAGE - Retrieve the dram usage inside the device and of the * specific context . This is relevant only for devices * where the dram is managed by the kernel driver * HL_INFO_HW_IDLE - Retrieve information about the idle status of each * internal engine . * HL_INFO_DEVICE_STATUS - Retrieve the device ' s status . This opcode doesn ' t * require an open context . * HL_INFO_DEVICE_UTILIZATION - Retrieve the total utilization of the device * over the last period specified by the user . * The period can be between 100 ms to 1 s , in * resolution of 100 ms . The return value is a * percentage of the utilization rate . * HL_INFO_HW_EVENTS_AGGREGATE - Receive an array describing how many times each * event occurred since the driver was loaded . * HL_INFO_CLK_RATE - Retrieve the current and maximum clock rate * of the device in MHz . The maximum clock rate is * configurable via sysfs parameter * HL_INFO_RESET_COUNT - Retrieve the counts of the soft and hard reset * operations performed on the device since the last * time the driver was loaded . * HL_INFO_TIME_SYNC - Retrieve the device ' s time alongside the host ' s time * for synchronization . * HL_INFO_CS_COUNTERS - Retrieve command submission counters * HL_INFO_PCI_COUNTERS - Retrieve PCI counters * HL_INFO_CLK_THROTTLE_REASON - Retrieve clock throttling reason * HL_INFO_SYNC_MANAGER - Retrieve sync manager info per dcore * HL_INFO_TOTAL_ENERGY - Retrieve total energy consumption * HL_INFO_PLL_FREQUENCY - Retrieve PLL frequency * HL_INFO_POWER - Retrieve power information * HL_INFO_OPEN_STATS - Retrieve info regarding recent device open calls * HL_INFO_DRAM_REPLACED_ROWS - Retrieve DRAM replaced rows info * HL_INFO_DRAM_PENDING_ROWS - Retrieve DRAM pending rows num * HL_INFO_LAST_ERR_OPEN_DEV_TIME - Retrieve timestamp of the last time the device was opened * and CS timeout or razwi error occurred . * HL_INFO_CS_TIMEOUT_EVENT - Retrieve CS timeout timestamp and its related CS sequence number . * HL_INFO_RAZWI_EVENT - Retrieve parameters of razwi : * Timestamp of razwi . * The address which accessing it caused the razwi . * Razwi initiator . * Razwi cause , was it a page fault or MMU access error . * May return 0 even though no new data is available , in that case * timestamp will be 0 . * HL_INFO_DEV_MEM_ALLOC_PAGE_SIZES - Retrieve valid page sizes for device memory allocation * HL_INFO_SECURED_ATTESTATION - Retrieve attestation report of the boot . * HL_INFO_REGISTER_EVENTFD - Register eventfd for event notifications . * HL_INFO_UNREGISTER_EVENTFD - Unregister eventfd * HL_INFO_GET_EVENTS - Retrieve the last occurred events * HL_INFO_UNDEFINED_OPCODE_EVENT - Retrieve last undefined opcode error information . * May return 0 even though no new data is available , in that case * timestamp will be 0 . * HL_INFO_ENGINE_STATUS - Retrieve the status of all the h / w engines in the asic . * HL_INFO_PAGE_FAULT_EVENT - Retrieve parameters of captured page fault . * May return 0 even though no new data is available , in that case * timestamp will be 0 . * HL_INFO_USER_MAPPINGS - Retrieve user mappings , captured after page fault event . * HL_INFO_FW_GENERIC_REQ - Send generic request to FW . * HL_INFO_HW_ERR_EVENT - Retrieve information on the reported HW error . * May return 0 even though no new data is available , in that case * timestamp will be 0 . * HL_INFO_FW_ERR_EVENT - Retrieve information on the reported FW error . * May return 0 even though no new data is available , in that case * timestamp will be 0 . * HL_INFO_USER_ENGINE_ERR_EVENT - Retrieve the last engine id that reported an error . #define HL_INFO_HW_IP_INFO 0 #define HL_INFO_HW_EVENTS 1 #define HL_INFO_DRAM_USAGE 2 #define HL_INFO_HW_IDLE 3 #define HL_INFO_DEVICE_STATUS 4 #define HL_INFO_DEVICE_UTILIZATION 6 #define HL_INFO_HW_EVENTS_AGGREGATE 7 #define HL_INFO_CLK_RATE 8 #define HL_INFO_RESET_COUNT 9 #define HL_INFO_TIME_SYNC 10 #define HL_INFO_CS_COUNTERS 11 #define HL_INFO_PCI_COUNTERS 12 #define HL_INFO_CLK_THROTTLE_REASON 13 #define HL_INFO_SYNC_MANAGER 14 #define HL_INFO_TOTAL_ENERGY 15 #define HL_INFO_PLL_FREQUENCY 16 #define HL_INFO_POWER 17 #define HL_INFO_OPEN_STATS 18 #define HL_INFO_DRAM_REPLACED_ROWS 21 #define HL_INFO_DRAM_PENDING_ROWS 22 #define HL_INFO_LAST_ERR_OPEN_DEV_TIME 23 #define HL_INFO_CS_TIMEOUT_EVENT 24 #define HL_INFO_RAZWI_EVENT 25 #define HL_INFO_DEV_MEM_ALLOC_PAGE_SIZES 26 #define HL_INFO_SECURED_ATTESTATION 27 #define HL_INFO_REGISTER_EVENTFD 28 #define HL_INFO_UNREGISTER_EVENTFD 29 #define HL_INFO_GET_EVENTS 30 #define HL_INFO_UNDEFINED_OPCODE_EVENT 31 #define HL_INFO_ENGINE_STATUS 32 #define HL_INFO_PAGE_FAULT_EVENT 33 #define HL_INFO_USER_MAPPINGS 34 #define HL_INFO_FW_GENERIC_REQ 35 #define HL_INFO_HW_ERR_EVENT 36 #define HL_INFO_FW_ERR_EVENT 37 #define HL_INFO_USER_ENGINE_ERR_EVENT 38 #define HL_INFO_DEV_SIGNED 40 #define HL_INFO_VERSION_MAX_LEN 128 #define HL_INFO_CARD_NAME_MAX_LEN 16 /* Maximum buffer size for retrieving engines status */ #define HL_ENGINES_DATA_MAX_SIZE SZ_1M/** * struct hl_info_hw_ip_info - hardware information on various IPs in the ASIC * @ sram_base_address : The first SRAM physical base address that is free to be * used by the user . * @ dram_base_address : The first DRAM virtual or physical base address that is * free to be used by the user . * @ dram_size : The DRAM size that is available to the user . * @ sram_size : The SRAM size that is available to the user . * @ num_of_events : The number of events that can be received from the f / w . This * is needed so the user can what is the size of the h / w events * array he needs to pass to the kernel when he wants to fetch * the event counters . * @ device_id : PCI device ID of the ASIC . * @ module_id : Module ID of the ASIC for mezzanine cards in servers * ( From OCP spec ) . * @ decoder_enabled_mask : Bit - mask that represents which decoders are enabled . * @ first_available_interrupt_id : The first available interrupt ID for the user * to be used when it works with user interrupts . * Relevant for Gaudi2 and later . * @ server_type : Server type that the Gaudi ASIC is currently installed in . * The value is according to enum hl_server_type * @ cpld_version : CPLD version on the board . * @ psoc_pci_pll_nr : PCI PLL NR value . Needed by the profiler in some ASICs . * @ psoc_pci_pll_nf : PCI PLL NF value . Needed by the profiler in some ASICs . * @ psoc_pci_pll_od : PCI PLL OD value . Needed by the profiler in some ASICs . * @ psoc_pci_pll_div_factor : PCI PLL DIV factor value . Needed by the profiler * in some ASICs . * @ tpc_enabled_mask : Bit - mask that represents which TPCs are enabled . Relevant * for Goya / Gaudi only . * @ dram_enabled : Whether the DRAM is enabled . * @ security_enabled : Whether security is enabled on device . * @ mme_master_slave_mode : Indicate whether the MME is working in master / slave * configuration . Relevant for Gaudi2 and later . * @ cpucp_version : The CPUCP f / w version . * @ card_name : The card name as passed by the f / w . * @ tpc_enabled_mask_ext : Bit - mask that represents which TPCs are enabled . * Relevant for Gaudi2 and later . * @ dram_page_size : The DRAM physical page size . * @ edma_enabled_mask : Bit - mask that represents which EDMAs are enabled . * Relevant for Gaudi2 and later . * @ number_of_user_interrupts : The number of interrupts that are available to the userspace * application to use . Relevant for Gaudi2 and later . * @ device_mem_alloc_default_page_size : default page size used in device memory allocation . * @ revision_id : PCI revision ID of the ASIC . * @ tpc_interrupt_id : interrupt id for TPC to use in order to raise events towards the host . * @ rotator_enabled_mask : Bit - mask that represents which rotators are enabled . * Relevant for Gaudi3 and later . * @ engine_core_interrupt_reg_addr : interrupt register address for engine core to use * in order to raise events toward FW . * @ reserved_dram_size : DRAM size reserved for driver and firmware . struct hl_info_hw_ip_info {struct hl_info_dram_usage {#define HL_BUSY_ENGINES_MASK_EXT_SIZE 4 struct hl_info_hw_idle {/* * Bitmask of busy engines . * Bits definition is according to ` enum < chip > _ engine_id ' . /* * Extended Bitmask of busy engines . * Bits definition is according to ` enum < chip > _ engine_id ' . struct hl_info_device_status {struct hl_info_device_utilization {struct hl_info_clk_rate {struct hl_info_reset_count {struct hl_info_time_sync {/** * struct hl_info_pci_counters - pci counters * @ rx_throughput : PCI rx throughput KBps * @ tx_throughput : PCI tx throughput KBps * @ replay_cnt : PCI replay counter struct hl_info_pci_counters {enum hl_clk_throttling_type {/* clk_throttling_reason masks */ #define HL_CLK_THROTTLE_POWER (1 << HL_CLK_THROTTLE_TYPE_POWER)#define HL_CLK_THROTTLE_THERMAL (1 << HL_CLK_THROTTLE_TYPE_THERMAL)/** * struct hl_info_clk_throttle - clock throttling reason * @ clk_throttling_reason : each bit represents a clk throttling reason * @ clk_throttling_timestamp_us : represents CPU timestamp in microseconds of the start - event * @ clk_throttling_duration_ns : the clock throttle time in nanosec struct hl_info_clk_throttle {/** * struct hl_info_energy - device energy information * @ total_energy_consumption : total device energy consumption struct hl_info_energy {#define HL_PLL_NUM_OUTPUTS 4 struct hl_pll_frequency_info {/** * struct hl_open_stats_info - device open statistics information * @ open_counter : ever growing counter , increased on each successful dev open * @ last_open_period_ms : duration ( ms ) device was open last time * @ is_compute_ctx_active : Whether there is an active compute context executing * @ compute_ctx_in_release : true if the current compute context is being released struct hl_open_stats_info {6 ];/** * struct hl_power_info - power information * @ power : power consumption struct hl_power_info {/** * struct hl_info_sync_manager - sync manager information * @ first_available_sync_object : first available sob * @ first_available_monitor : first available monitor * @ first_available_cq : first available cq struct hl_info_sync_manager {/** * struct hl_info_cs_counters - command submission counters * @ total_out_of_mem_drop_cnt : total dropped due to memory allocation issue * @ ctx_out_of_mem_drop_cnt : context dropped due to memory allocation issue * @ total_parsing_drop_cnt : total dropped due to error in packet parsing * @ ctx_parsing_drop_cnt : context dropped due to error in packet parsing * @ total_queue_full_drop_cnt : total dropped due to queue full * @ ctx_queue_full_drop_cnt : context dropped due to queue full * @ total_device_in_reset_drop_cnt : total dropped due to device in reset * @ ctx_device_in_reset_drop_cnt : context dropped due to device in reset * @ total_max_cs_in_flight_drop_cnt : total dropped due to maximum CS in - flight * @ ctx_max_cs_in_flight_drop_cnt : context dropped due to maximum CS in - flight * @ total_validation_drop_cnt : total dropped due to validation error * @ ctx_validation_drop_cnt : context dropped due to validation error struct hl_info_cs_counters {/** * struct hl_info_last_err_open_dev_time - last error boot information . * @ timestamp : timestamp of last time the device was opened and error occurred . struct hl_info_last_err_open_dev_time {/** * struct hl_info_cs_timeout_event - last CS timeout information . * @ timestamp : timestamp when last CS timeout event occurred . * @ seq : sequence number of last CS timeout event . struct hl_info_cs_timeout_event {#define HL_RAZWI_NA_ENG_ID U16_MAX#define HL_RAZWI_MAX_NUM_OF_ENGINES_PER_RTR 128 #define HL_RAZWI_READ BIT(0 )#define HL_RAZWI_WRITE BIT(1 )#define HL_RAZWI_LBW BIT(2 )#define HL_RAZWI_HBW BIT(3 )#define HL_RAZWI_RR BIT(4 )#define HL_RAZWI_ADDR_DEC BIT(5 )/** * struct hl_info_razwi_event - razwi information . * @ timestamp : timestamp of razwi . * @ addr : address which accessing it caused razwi . * @ engine_id : engine id of the razwi initiator , if it was initiated by engine that does not * have engine id it will be set to HL_RAZWI_NA_ENG_ID . If there are several possible * engines which caused the razwi , it will hold all of them . * @ num_of_possible_engines : contains number of possible engine ids . In some asics , razwi indication * might be common for several engines and there is no way to get the * exact engine . In this way , engine_id array will be filled with all * possible engines caused this razwi . Also , there might be possibility * in gaudi , where we don ' t indication on specific engine , in that case * the value of this parameter will be zero . * @ flags : bitmask for additional data : HL_RAZWI_READ - razwi caused by read operation * HL_RAZWI_WRITE - razwi caused by write operation * HL_RAZWI_LBW - razwi caused by lbw fabric transaction * HL_RAZWI_HBW - razwi caused by hbw fabric transaction * HL_RAZWI_RR - razwi caused by range register * HL_RAZWI_ADDR_DEC - razwi caused by address decode error * Note : this data is not supported by all asics , in that case the relevant bits will not * be set . struct hl_info_razwi_event {5 ];#define MAX_QMAN_STREAMS_INFO 4 #define OPCODE_INFO_MAX_ADDR_SIZE 8 /** * struct hl_info_undefined_opcode_event - info about last undefined opcode error * @ timestamp : timestamp of the undefined opcode error * @ cb_addr_streams : CB addresses ( per stream ) that are currently exists in the PQ * entries . In case all streams array entries are * filled with values , it means the execution was in Lower - CP . * @ cq_addr : the address of the current handled command buffer * @ cq_size : the size of the current handled command buffer * @ cb_addr_streams_len : num of streams - actual len of cb_addr_streams array . * should be equal to 1 in case of undefined opcode * in Upper - CP ( specific stream ) and equal to 4 incase * of undefined opcode in Lower - CP . * @ engine_id : engine - id that the error occurred on * @ stream_id : the stream id the error occurred on . In case the stream equals to * MAX_QMAN_STREAMS_INFO it means the error occurred on a Lower - CP . struct hl_info_undefined_opcode_event {/** * struct hl_info_hw_err_event - info about HW error * @ timestamp : timestamp of error occurrence * @ event_id : The async event ID ( specific to each device type ) . * @ pad : size padding for u64 granularity . struct hl_info_hw_err_event {3 ];/* FW error definition for event_type in struct hl_info_fw_err_event */ enum hl_info_fw_err_type {/** * struct hl_info_fw_err_event - info about FW error * @ timestamp : time - stamp of error occurrence * @ err_type : The type of event as defined in hl_info_fw_err_type . * @ event_id : The async event ID ( specific to each device type , applicable only when event type is * HL_INFO_FW_REPORTED_ERR ) . * @ pad : size padding for u64 granularity . struct hl_info_fw_err_event {/** * struct hl_info_engine_err_event - engine error info * @ timestamp : time - stamp of error occurrence * @ engine_id : engine id who reported the error . * @ error_count : Amount of errors reported . * @ pad : size padding for u64 granularity . struct hl_info_engine_err_event {/** * struct hl_info_dev_memalloc_page_sizes - valid page sizes in device mem alloc information . * @ page_order_bitmask : bitmap in which a set bit represents the order of the supported page size * ( e . g . 0 x2100000 means that 1 MB and 32 MB pages are supported ) . struct hl_info_dev_memalloc_page_sizes {#define SEC_PCR_DATA_BUF_SZ 256 #define SEC_PCR_QUOTE_BUF_SZ 510 /* (512 - 2) 2 bytes used for size */ #define SEC_SIGNATURE_BUF_SZ 255 /* (256 - 1) 1 byte used for size */ #define SEC_PUB_DATA_BUF_SZ 510 /* (512 - 2) 2 bytes used for size */ #define SEC_CERTIFICATE_BUF_SZ 2046 /* (2048 - 2) 2 bytes used for size */ #define SEC_DEV_INFO_BUF_SZ 5120 /* * struct hl_info_sec_attest - attestation report of the boot * @ nonce : number only used once . random number provided by host . this also passed to the quote * command as a qualifying data . * @ pcr_quote_len : length of the attestation quote data ( bytes ) * @ pub_data_len : length of the public data ( bytes ) * @ certificate_len : length of the certificate ( bytes ) * @ pcr_num_reg : number of PCR registers in the pcr_data array * @ pcr_reg_len : length of each PCR register in the pcr_data array ( bytes ) * @ quote_sig_len : length of the attestation report signature ( bytes ) * @ pcr_data : raw values of the PCR registers * @ pcr_quote : attestation report data structure * @ quote_sig : signature structure of the attestation report * @ public_data : public key for the signed attestation * ( outPublic + name + qualifiedName ) * @ certificate : certificate for the attestation signing key struct hl_info_sec_attest {2 ];/* * struct hl_info_signed - device information signed by a secured device . * @ nonce : number only used once . random number provided by host . this also passed to the quote * command as a qualifying data . * @ pub_data_len : length of the public data ( bytes ) * @ certificate_len : length of the certificate ( bytes ) * @ info_sig_len : length of the attestation signature ( bytes ) * @ public_data : public key info signed info data ( outPublic + name + qualifiedName ) * @ certificate : certificate for the signing key * @ info_sig : signature of the info + nonce data . * @ dev_info_len : length of device info ( bytes ) * @ dev_info : device info as byte array . struct hl_info_signed {2 ];/** * struct hl_page_fault_info - page fault information . * @ timestamp : timestamp of page fault . * @ addr : address which accessing it caused page fault . * @ engine_id : engine id which caused the page fault , supported only in gaudi3 . struct hl_page_fault_info {6 ];/** * struct hl_user_mapping - user mapping information . * @ dev_va : device virtual address . * @ size : virtual address mapping size . struct hl_user_mapping {enum gaudi_dcores {/** * struct hl_info_args - Main structure to retrieve device related information . * @ return_pointer : User space address of the relevant structure related to HL_INFO_ * operation * mentioned in @ op . * @ return_size : Size of the structure used in @ return_pointer , just like " size " in " snprintf " , it * limits how many bytes the kernel can write . For hw_events array , the size should be * hl_info_hw_ip_info . num_of_events * sizeof ( _ _ u32 ) . * @ op : Defines which type of information to be retrieved . Refer HL_INFO_ * for details . * @ dcore_id : DCORE id for which the information is relevant ( for Gaudi refer to enum gaudi_dcores ) . * @ ctx_id : Context ID of the user . Currently not in use . * @ period_ms : Period value , in milliseconds , for utilization rate in range 100 ms - 1000 ms in 100 ms * resolution . Currently not in use . * @ pll_index : Index as defined in hl_ < asic type > _ pll_index enumeration . * @ eventfd : event file descriptor for event notifications . * @ user_buffer_actual_size : Actual data size which was copied to user allocated buffer by the * driver . It is possible for the user to allocate buffer larger than * needed , hence updating this variable so user will know the exact amount * of bytes copied by the kernel to the buffer . * @ sec_attest_nonce : Nonce number used for attestation report . * @ array_size : Number of array members copied to user buffer . * Relevant for HL_INFO_USER_MAPPINGS info ioctl . * @ fw_sub_opcode : generic requests sub opcodes . * @ pad : Padding to 64 bit . struct hl_info_args {union {/* Opcode to create a new command buffer */ #define HL_CB_OP_CREATE 0 /* Opcode to destroy previously created command buffer */ #define HL_CB_OP_DESTROY 1 /* Opcode to retrieve information about a command buffer */ #define HL_CB_OP_INFO 2 /* 2MB minus 32 bytes for 2xMSG_PROT */ #define HL_MAX_CB_SIZE (0 x200000 - 32 )/* Indicates whether the command buffer should be mapped to the device's MMU */ #define HL_CB_FLAGS_MAP 0 x1/* Used with HL_CB_OP_INFO opcode to get the device va address for kernel mapped CB */ #define HL_CB_FLAGS_GET_DEVICE_VA 0 x2struct hl_cb_in {/* Handle of CB or 0 if we want to create one */ /* HL_CB_OP_* */ /* Size of CB. Maximum size is HL_MAX_CB_SIZE. The minimum size that * will be allocated , regardless of this parameter ' s value , is PAGE_SIZE /* Context ID - Currently not in use */ /* HL_CB_FLAGS_* */ struct hl_cb_out {union {/* Handle of CB */ union {/* Information about CB */ struct {/* Usage count of CB */ /* CB mapped address to device MMU */ union hl_cb_args {struct hl_cb_in in;struct hl_cb_out out;/* HL_CS_CHUNK_FLAGS_ values * * HL_CS_CHUNK_FLAGS_USER_ALLOC_CB : * Indicates if the CB was allocated and mapped by userspace * ( relevant to Gaudi2 and later ) . User allocated CB is a command buffer , * allocated by the user , via malloc ( or similar ) . After allocating the * CB , the user invokes - “ memory ioctl ” to map the user memory into a * device virtual address . The user provides this address via the * cb_handle field . The interface provides the ability to create a * large CBs , Which aren ’ t limited to “ HL_MAX_CB_SIZE ” . Therefore , it * increases the PCI - DMA queues throughput . This CB allocation method * also reduces the use of Linux DMA - able memory pool . Which are limited * and used by other Linux sub - systems . #define HL_CS_CHUNK_FLAGS_USER_ALLOC_CB 0 x1/* * This structure size must always be fixed to 64 - bytes for backward * compatibility struct hl_cs_chunk {union {/* Goya/Gaudi: * For external queue , this represents a Handle of CB on the * Host . * For internal queue in Goya , this represents an SRAM or * a DRAM address of the internal CB . In Gaudi , this might also * represent a mapped host address of the CB . * * Gaudi2 onwards : * For H / W queue , this represents either a Handle of CB on the * Host , or an SRAM , a DRAM , or a mapped host address of the CB . * * A mapped host address is in the device address space , after * a host address was mapped by the device MMU . /* Relevant only when HL_CS_FLAGS_WAIT or * HL_CS_FLAGS_COLLECTIVE_WAIT is set * This holds address of array of u64 values that contain * signal CS sequence numbers . The wait described by * this job will listen on all those signals * ( wait event per signal ) /* * Relevant only when HL_CS_FLAGS_WAIT or * HL_CS_FLAGS_COLLECTIVE_WAIT is set * along with HL_CS_FLAGS_ENCAP_SIGNALS . * This is the CS sequence which has the encapsulated signals . /* Index of queue to put the CB on */ union {/* * Size of command buffer with valid packets * Can be smaller then actual CB size /* Relevant only when HL_CS_FLAGS_WAIT or * HL_CS_FLAGS_COLLECTIVE_WAIT is set . * Number of entries in signal_seq_arr /* Relevant only when HL_CS_FLAGS_WAIT or * HL_CS_FLAGS_COLLECTIVE_WAIT is set along * with HL_CS_FLAGS_ENCAP_SIGNALS * This set the signals range that the user want to wait for * out of the whole reserved signals range . * e . g if the signals range is 20 , and user don ' t want * to wait for signal 8 , so he set this offset to 7 , then * he call the API again with 9 and so on till 20 . /* HL_CS_CHUNK_FLAGS_* */ /* Relevant only when HL_CS_FLAGS_COLLECTIVE_WAIT is set. * This holds the collective engine ID . The wait described by this job * will sync with this engine and with all NICs before completion . /* Align structure to 64 bytes */ 10 ];/* SIGNAL/WAIT/COLLECTIVE_WAIT flags are mutually exclusive */ #define HL_CS_FLAGS_FORCE_RESTORE 0 x1#define HL_CS_FLAGS_SIGNAL 0 x2#define HL_CS_FLAGS_WAIT 0 x4#define HL_CS_FLAGS_COLLECTIVE_WAIT 0 x8#define HL_CS_FLAGS_TIMESTAMP 0 x20#define HL_CS_FLAGS_STAGED_SUBMISSION 0 x40#define HL_CS_FLAGS_STAGED_SUBMISSION_FIRST 0 x80#define HL_CS_FLAGS_STAGED_SUBMISSION_LAST 0 x100#define HL_CS_FLAGS_CUSTOM_TIMEOUT 0 x200#define HL_CS_FLAGS_SKIP_RESET_ON_TIMEOUT 0 x400/* * The encapsulated signals CS is merged into the existing CS ioctls . * In order to use this feature need to follow the below procedure : * 1 . Reserve signals , set the CS type to HL_CS_FLAGS_RESERVE_SIGNALS_ONLY * the output of this API will be the SOB offset from CFG_BASE . * this address will be used to patch CB cmds to do the signaling for this * SOB by incrementing it ' s value . * for reverting the reservation use HL_CS_FLAGS_UNRESERVE_SIGNALS_ONLY * CS type , note that this might fail if out - of - sync happened to the SOB * value , in case other signaling request to the same SOB occurred between * reserve - unreserve calls . * 2 . Use the staged CS to do the encapsulated signaling jobs . * use HL_CS_FLAGS_STAGED_SUBMISSION and HL_CS_FLAGS_STAGED_SUBMISSION_FIRST * along with HL_CS_FLAGS_ENCAP_SIGNALS flag , and set encaps_signal_offset * field . This offset allows app to wait on part of the reserved signals . * 3 . Use WAIT / COLLECTIVE WAIT CS along with HL_CS_FLAGS_ENCAP_SIGNALS flag * to wait for the encapsulated signals . #define HL_CS_FLAGS_ENCAP_SIGNALS 0 x800#define HL_CS_FLAGS_RESERVE_SIGNALS_ONLY 0 x1000#define HL_CS_FLAGS_UNRESERVE_SIGNALS_ONLY 0 x2000/* * The engine cores CS is merged into the existing CS ioctls . * Use it to control the engine cores mode . #define HL_CS_FLAGS_ENGINE_CORE_COMMAND 0 x4000/* * The flush HBW PCI writes is merged into the existing CS ioctls . * Used to flush all HBW PCI writes . * This is a blocking operation and for this reason the user shall not use * the return sequence number ( which will be invalid anyway ) #define HL_CS_FLAGS_FLUSH_PCI_HBW_WRITES 0 x8000/* * The engines CS is merged into the existing CS ioctls . * Use it to control engines modes . #define HL_CS_FLAGS_ENGINES_COMMAND 0 x10000#define HL_CS_STATUS_SUCCESS 0 #define HL_MAX_JOBS_PER_CS 512 /* * enum hl_engine_command - engine command * * @ HL_ENGINE_CORE_HALT : engine core halt * @ HL_ENGINE_CORE_RUN : engine core run * @ HL_ENGINE_STALL : user engine / s stall * @ HL_ENGINE_RESUME : user engine / s resume enum hl_engine_command {1 ,2 ,3 ,4 ,struct hl_cs_in {union {struct {/* this holds address of array of hl_cs_chunk for restore phase */ /* holds address of array of hl_cs_chunk for execution phase */ /* Valid only when HL_CS_FLAGS_ENGINE_CORE_COMMAND is set */ struct {/* this holds address of array of uint32 for engine_cores */ /* number of engine cores in engine_cores array */ /* the core command to be sent towards engine cores */ /* Valid only when HL_CS_FLAGS_ENGINES_COMMAND is set */ struct {/* this holds address of array of uint32 for engines */ /* number of engines in engines array */ /* the engine command to be sent towards engines */ union {/* * Sequence number of a staged submission CS * valid only if HL_CS_FLAGS_STAGED_SUBMISSION is set and * HL_CS_FLAGS_STAGED_SUBMISSION_FIRST is unset . /* * Encapsulated signals handle id * Valid for two flows : * 1 . CS with encapsulated signals : * when HL_CS_FLAGS_STAGED_SUBMISSION and * HL_CS_FLAGS_STAGED_SUBMISSION_FIRST * and HL_CS_FLAGS_ENCAP_SIGNALS are set . * 2 . unreserve signals : * valid when HL_CS_FLAGS_UNRESERVE_SIGNALS_ONLY is set . /* Valid only when HL_CS_FLAGS_RESERVE_SIGNALS_ONLY is set */ struct {/* Encapsulated signals number */ /* Encapsulated signals queue index (stream) */ /* Number of chunks in restore phase array. Maximum number is * HL_MAX_JOBS_PER_CS /* Number of chunks in execution array. Maximum number is * HL_MAX_JOBS_PER_CS /* timeout in seconds - valid only if HL_CS_FLAGS_CUSTOM_TIMEOUT * is set /* HL_CS_FLAGS_* */ /* Context ID - Currently not in use */ 4 ];struct hl_cs_out {union {/* * seq holds the sequence number of the CS to pass to wait * ioctl . All values are valid except for 0 and ULLONG_MAX /* Valid only when HL_CS_FLAGS_RESERVE_SIGNALS_ONLY is set */ struct {/* This is the reserved signal handle id */ /* This is the signals count */ /* HL_CS_STATUS */ /* * SOB base address offset * Valid only when HL_CS_FLAGS_RESERVE_SIGNALS_ONLY or HL_CS_FLAGS_SIGNAL is set /* * Count of completed signals in SOB before current signal submission . * Valid only when ( HL_CS_FLAGS_ENCAP_SIGNALS & HL_CS_FLAGS_STAGED_SUBMISSION ) * or HL_CS_FLAGS_SIGNAL is set 3 ];union hl_cs_args {struct hl_cs_in in;struct hl_cs_out out;#define HL_WAIT_CS_FLAGS_INTERRUPT 0 x2#define HL_WAIT_CS_FLAGS_INTERRUPT_MASK 0 xFFF00000#define HL_WAIT_CS_FLAGS_ANY_CQ_INTERRUPT 0 xFFF00000#define HL_WAIT_CS_FLAGS_ANY_DEC_INTERRUPT 0 xFFE00000#define HL_WAIT_CS_FLAGS_MULTI_CS 0 x4#define HL_WAIT_CS_FLAGS_INTERRUPT_KERNEL_CQ 0 x10#define HL_WAIT_CS_FLAGS_REGISTER_INTERRUPT 0 x20#define HL_WAIT_MULTI_CS_LIST_MAX_LEN 32 struct hl_wait_cs_in {union {struct {/* * In case of wait_cs holds the CS sequence number . * In case of wait for multi CS hold a user pointer to * an array of CS sequence numbers /* Absolute timeout to wait for command submission * in microseconds struct {union {/* User address for completion comparison. * upon interrupt , driver will compare the value pointed * by this address with the supplied target value . * in order not to perform any comparison , set address * to all 1 s . * Relevant only when HL_WAIT_CS_FLAGS_INTERRUPT is set /* cq_counters_handle to a kernel mapped cb which contains * cq counters . * Relevant only when HL_WAIT_CS_FLAGS_INTERRUPT_KERNEL_CQ is set /* Target value for completion comparison */ /* Context ID - Currently not in use */ /* HL_WAIT_CS_FLAGS_* * If HL_WAIT_CS_FLAGS_INTERRUPT is set , this field should include * interrupt id according to HL_WAIT_CS_FLAGS_INTERRUPT_MASK * * in order to wait for any CQ interrupt , set interrupt value to * HL_WAIT_CS_FLAGS_ANY_CQ_INTERRUPT . * * in order to wait for any decoder interrupt , set interrupt value to * HL_WAIT_CS_FLAGS_ANY_DEC_INTERRUPT . union {struct {/* Multi CS API info- valid entries in multi-CS array */ 7 ];/* Absolute timeout to wait for an interrupt in microseconds. * Relevant only when HL_WAIT_CS_FLAGS_INTERRUPT is set /* * cq counter offset inside the counters cb pointed by cq_counters_handle above . * upon interrupt , driver will compare the value pointed * by this address ( cq_counters_handle + cq_counters_offset ) * with the supplied target value . * relevant only when HL_WAIT_CS_FLAGS_INTERRUPT_KERNEL_CQ is set /* * Timestamp_handle timestamps buffer handle . * relevant only when HL_WAIT_CS_FLAGS_REGISTER_INTERRUPT is set /* * Timestamp_offset is offset inside the timestamp buffer pointed by timestamp_handle above . * upon interrupt , if the cq reached the target value then driver will write * timestamp to this offset . * relevant only when HL_WAIT_CS_FLAGS_REGISTER_INTERRUPT is set #define HL_WAIT_CS_STATUS_COMPLETED 0 #define HL_WAIT_CS_STATUS_BUSY 1 #define HL_WAIT_CS_STATUS_TIMEDOUT 2 #define HL_WAIT_CS_STATUS_ABORTED 3 #define HL_WAIT_CS_STATUS_FLAG_GONE 0 x1#define HL_WAIT_CS_STATUS_FLAG_TIMESTAMP_VLD 0 x2struct hl_wait_cs_out {/* HL_WAIT_CS_STATUS_* */ /* HL_WAIT_CS_STATUS_FLAG* */ /* * valid only if HL_WAIT_CS_STATUS_FLAG_TIMESTAMP_VLD is set * for wait_cs : timestamp of CS completion * for wait_multi_cs : timestamp of FIRST CS completion /* multi CS completion bitmap */ union hl_wait_cs_args {struct hl_wait_cs_in in;struct hl_wait_cs_out out;/* Opcode to allocate device memory */ #define HL_MEM_OP_ALLOC 0 /* Opcode to free previously allocated device memory */ #define HL_MEM_OP_FREE 1 /* Opcode to map host and device memory */ #define HL_MEM_OP_MAP 2 /* Opcode to unmap previously mapped host and device memory */ #define HL_MEM_OP_UNMAP 3 /* Opcode to map a hw block */ #define HL_MEM_OP_MAP_BLOCK 4 /* Opcode to create DMA-BUF object for an existing device memory allocation * and to export an FD of that DMA - BUF back to the caller #define HL_MEM_OP_EXPORT_DMABUF_FD 5 /* Opcode to create timestamps pool for user interrupts registration support * The memory will be allocated by the kernel driver , A timestamp buffer which the user * will get handle to it for mmap , and another internal buffer used by the * driver for registration management * The memory will be freed when the user closes the file descriptor ( ctx close ) #define HL_MEM_OP_TS_ALLOC 6 /* Memory flags */ #define HL_MEM_CONTIGUOUS 0 x1#define HL_MEM_SHARED 0 x2#define HL_MEM_USERPTR 0 x4#define HL_MEM_FORCE_HINT 0 x8#define HL_MEM_PREFETCH 0 x40/** * structure hl_mem_in - structure that handle input args for memory IOCTL * @ union arg : union of structures to be used based on the input operation * @ op : specify the requested memory operation ( one of the HL_MEM_OP_ * definitions ) . * @ flags : flags for the memory operation ( one of the HL_MEM_ * definitions ) . * For the HL_MEM_OP_EXPORT_DMABUF_FD opcode , this field holds the DMA - BUF file / FD flags . * @ ctx_id : context ID - currently not in use . * @ num_of_elements : number of timestamp elements used only with HL_MEM_OP_TS_ALLOC opcode . struct hl_mem_in {union {/** * structure for device memory allocation ( used with the HL_MEM_OP_ALLOC op ) * @ mem_size : memory size to allocate * @ page_size : page size to use on allocation . when the value is 0 the default page * size will be taken . struct {/** * structure for free - ing device memory ( used with the HL_MEM_OP_FREE op ) * @ handle : handle returned from HL_MEM_OP_ALLOC struct {/** * structure for mapping device memory ( used with the HL_MEM_OP_MAP op ) * @ hint_addr : requested virtual address of mapped memory . * the driver will try to map the requested region to this hint * address , as long as the address is valid and not already mapped . * the user should check the returned address of the IOCTL to make * sure he got the hint address . * passing 0 here means that the driver will choose the address itself . * @ handle : handle returned from HL_MEM_OP_ALLOC . struct {/** * structure for mapping host memory ( used with the HL_MEM_OP_MAP op ) * @ host_virt_addr : address of allocated host memory . * @ hint_addr : requested virtual address of mapped memory . * the driver will try to map the requested region to this hint * address , as long as the address is valid and not already mapped . * the user should check the returned address of the IOCTL to make * sure he got the hint address . * passing 0 here means that the driver will choose the address itself . * @ size : size of allocated host memory . struct {/** * structure for mapping hw block ( used with the HL_MEM_OP_MAP_BLOCK op ) * @ block_addr : HW block address to map , a handle and size will be returned * to the user and will be used to mmap the relevant block . * only addresses from configuration space are allowed . struct {/** * structure for unmapping host memory ( used with the HL_MEM_OP_UNMAP op ) * @ device_virt_addr : virtual address returned from HL_MEM_OP_MAP struct {/** * structure for exporting DMABUF object ( used with * the HL_MEM_OP_EXPORT_DMABUF_FD op ) * @ addr : for Gaudi1 , the driver expects a physical address * inside the device ' s DRAM . this is because in Gaudi1 * we don ' t have MMU that covers the device ' s DRAM . * for all other ASICs , the driver expects a device * virtual address that represents the start address of * a mapped DRAM memory area inside the device . * the address must be the same as was received from the * driver during a previous HL_MEM_OP_MAP operation . * @ mem_size : size of memory to export . * @ offset : for Gaudi1 , this value must be 0 . For all other ASICs , * the driver expects an offset inside of the memory area * describe by addr . the offset represents the start * address of that the exported dma - buf object describes . struct {struct hl_mem_out {union {/* * Used for HL_MEM_OP_MAP as the virtual address that was * assigned in the device VA space . * A value of 0 means the requested operation failed . /* * Used in HL_MEM_OP_ALLOC * This is the assigned handle for the allocated memory struct {/* * Used in HL_MEM_OP_MAP_BLOCK . * This is the assigned handle for the mapped block /* * Used in HL_MEM_OP_MAP_BLOCK * This is the size of the mapped block /* Returned in HL_MEM_OP_EXPORT_DMABUF_FD. Represents the * DMA - BUF object that was created to describe a memory * allocation on the device ' s memory space . The FD should be * passed to the importer driver union hl_mem_args {struct hl_mem_in in;struct hl_mem_out out;#define HL_DEBUG_MAX_AUX_VALUES 10 struct hl_debug_params_etr {/* Address in memory to allocate buffer */ /* Size of buffer to allocate */ /* Sink operation mode: SW fifo, HW fifo, Circular buffer */ struct hl_debug_params_etf {/* Address in memory to allocate buffer */ /* Size of buffer to allocate */ /* Sink operation mode: SW fifo, HW fifo, Circular buffer */ struct hl_debug_params_stm {/* Two bit masks for HW event and Stimulus Port */ /* Trace source ID */ /* Frequency for the timestamp register */ struct hl_debug_params_bmon {/* Two address ranges that the user can request to filter */ /* Capture window configuration */ /* Trace source ID */ /* Control register */ /* Two more address ranges that the user can request to filter */ struct hl_debug_params_spmu {/* Event types selection */ /* Number of event types selection */ /* TRC configuration register values */ /* Opcode for ETR component */ #define HL_DEBUG_OP_ETR 0 /* Opcode for ETF component */ #define HL_DEBUG_OP_ETF 1 /* Opcode for STM component */ #define HL_DEBUG_OP_STM 2 /* Opcode for FUNNEL component */ #define HL_DEBUG_OP_FUNNEL 3 /* Opcode for BMON component */ #define HL_DEBUG_OP_BMON 4 /* Opcode for SPMU component */ #define HL_DEBUG_OP_SPMU 5 /* Opcode for timestamp (deprecated) */ #define HL_DEBUG_OP_TIMESTAMP 6 /* Opcode for setting the device into or out of debug mode. The enable * variable should be 1 for enabling debug mode and 0 for disabling it #define HL_DEBUG_OP_SET_MODE 7 struct hl_debug_args {/* * Pointer to user input structure . * This field is relevant to specific opcodes . /* Pointer to user output structure */ /* Size of user input structure */ /* Size of user output structure */ /* HL_DEBUG_OP_* */ /* * Register index in the component , taken from the debug_regs_index enum * in the various ASIC header files /* Enable/disable */ /* Context ID - Currently not in use */ #define HL_IOCTL_INFO 0 x00#define HL_IOCTL_CB 0 x01#define HL_IOCTL_CS 0 x02#define HL_IOCTL_WAIT_CS 0 x03#define HL_IOCTL_MEMORY 0 x04#define HL_IOCTL_DEBUG 0 x05/* * Various information operations such as : * - H / W IP information * - Current dram usage * * The user calls this IOCTL with an opcode that describes the required * information . The user should supply a pointer to a user - allocated memory * chunk , which will be filled by the driver with the requested information . * * The user supplies the maximum amount of size to copy into the user ' s memory , * in order to prevent data corruption in case of differences between the * definitions of structures in kernel and userspace , e . g . in case of old * userspace and new kernel driver #define DRM_IOCTL_HL_INFO DRM_IOWR(DRM_COMMAND_BASE + HL_IOCTL_INFO, struct hl_info_args)/* * Command Buffer * - Request a Command Buffer * - Destroy a Command Buffer * * The command buffers are memory blocks that reside in DMA - able address * space and are physically contiguous so they can be accessed by the device * directly . They are allocated using the coherent DMA API . * * When creating a new CB , the IOCTL returns a handle of it , and the user - space * process needs to use that handle to mmap the buffer so it can access them . * * In some instances , the device must access the command buffer through the * device ' s MMU , and thus its memory should be mapped . In these cases , user can * indicate the driver that such a mapping is required . * The resulting device virtual address will be used internally by the driver , * and won ' t be returned to user . * #define DRM_IOCTL_HL_CB DRM_IOWR(DRM_COMMAND_BASE + HL_IOCTL_CB, union hl_cb_args)/* * Command Submission * * To submit work to the device , the user need to call this IOCTL with a set * of JOBS . That set of JOBS constitutes a CS object . * Each JOB will be enqueued on a specific queue , according to the user ' s input . * There can be more then one JOB per queue . * * The CS IOCTL will receive two sets of JOBS . One set is for " restore " phase * and a second set is for " execution " phase . * The JOBS on the " restore " phase are enqueued only after context - switch * ( or if its the first CS for this context ) . The user can also order the * driver to run the " restore " phase explicitly * * Goya / Gaudi : * There are two types of queues - external and internal . External queues * are DMA queues which transfer data from / to the Host . All other queues are * internal . The driver will get completion notifications from the device only * on JOBS which are enqueued in the external queues . * * Gaudi2 onwards : * There is a single type of queue for all types of engines , either DMA engines * for transfers from / to the host or inside the device , or compute engines . * The driver will get completion notifications from the device for all queues . * * For jobs on external queues , the user needs to create command buffers * through the CB ioctl and give the CB ' s handle to the CS ioctl . For jobs on * internal queues , the user needs to prepare a " command buffer " with packets * on either the device SRAM / DRAM or the host , and give the device address of * that buffer to the CS ioctl . * For jobs on H / W queues both options of command buffers are valid . * * This IOCTL is asynchronous in regard to the actual execution of the CS . This * means it returns immediately after ALL the JOBS were enqueued on their * relevant queues . Therefore , the user mustn ' t assume the CS has been completed * or has even started to execute . * * Upon successful enqueue , the IOCTL returns a sequence number which the user * can use with the " Wait for CS " IOCTL to check whether the handle ' s CS * non - internal JOBS have been completed . Note that if the CS has internal JOBS * which can execute AFTER the external JOBS have finished , the driver might * report that the CS has finished executing BEFORE the internal JOBS have * actually finished executing . * * Even though the sequence number increments per CS , the user can NOT * automatically assume that if CS with sequence number N finished , then CS * with sequence number N - 1 also finished . The user can make this assumption if * and only if CS N and CS N - 1 are exactly the same ( same CBs for the same * queues ) . #define DRM_IOCTL_HL_CS DRM_IOWR(DRM_COMMAND_BASE + HL_IOCTL_CS, union hl_cs_args)/* * Wait for Command Submission * * The user can call this IOCTL with a handle it received from the CS IOCTL * to wait until the handle ' s CS has finished executing . The user will wait * inside the kernel until the CS has finished or until the user - requested * timeout has expired . * * If the timeout value is 0 , the driver won ' t sleep at all . It will check * the status of the CS and return immediately * * The return value of the IOCTL is a standard Linux error code . The possible * values are : * * EINTR - Kernel waiting has been interrupted , e . g . due to OS signal * that the user process received * ETIMEDOUT - The CS has caused a timeout on the device * EIO - The CS was aborted ( usually because the device was reset ) * ENODEV - The device wants to do hard - reset ( so user need to close FD ) * * The driver also returns a custom define in case the IOCTL call returned 0 . * The define can be one of the following : * * HL_WAIT_CS_STATUS_COMPLETED - The CS has been completed successfully ( 0 ) * HL_WAIT_CS_STATUS_BUSY - The CS is still executing ( 0 ) * HL_WAIT_CS_STATUS_TIMEDOUT - The CS has caused a timeout on the device * ( ETIMEDOUT ) * HL_WAIT_CS_STATUS_ABORTED - The CS was aborted , usually because the * device was reset ( EIO ) #define DRM_IOCTL_HL_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + HL_IOCTL_WAIT_CS, union hl_wait_cs_args)/* * Memory * - Map host memory to device MMU * - Unmap host memory from device MMU * * This IOCTL allows the user to map host memory to the device MMU * * For host memory , the IOCTL doesn ' t allocate memory . The user is supposed * to allocate the memory in user - space ( malloc / new ) . The driver pins the * physical pages ( up to the allowed limit by the OS ) , assigns a virtual * address in the device VA space and initializes the device MMU . * * There is an option for the user to specify the requested virtual address . * #define DRM_IOCTL_HL_MEMORY DRM_IOWR(DRM_COMMAND_BASE + HL_IOCTL_MEMORY, union hl_mem_args)/* * Debug * - Enable / disable the ETR / ETF / FUNNEL / STM / BMON / SPMU debug traces * * This IOCTL allows the user to get debug traces from the chip . * * Before the user can send configuration requests of the various * debug / profile engines , it needs to set the device into debug mode . * This is because the debug / profile infrastructure is shared component in the * device and we can ' t allow multiple users to access it at the same time . * * Once a user set the device into debug mode , the driver won ' t allow other * users to " work " with the device , i . e . open a FD . If there are multiple users * opened on the device , the driver won ' t allow any user to debug the device . * * For each configuration request , the user needs to provide the register index * and essential data such as buffer address and size . * * Once the user has finished using the debug / profile engines , he should * set the device into non - debug mode , i . e . disable debug mode . * * The driver can decide to " kick out " the user if he abuses this interface . * #define DRM_IOCTL_HL_DEBUG DRM_IOWR(DRM_COMMAND_BASE + HL_IOCTL_DEBUG, struct hl_debug_args)#define HL_COMMAND_START (DRM_COMMAND_BASE + HL_IOCTL_INFO)#define HL_COMMAND_END (DRM_COMMAND_BASE + HL_IOCTL_DEBUG + 1 )#endif /* HABANALABS_H_ */
Messung V0.5 in Prozent C=88 H=100 G=94
¤ Dauer der Verarbeitung: 0.165 Sekunden
(vorverarbeitet am 2026-10-01)
¤ *© Formatika GbR, Deutschland
2026-10-10
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