/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Copyright 2016-2023 Broadcom Inc. All rights reserved. #ifndef MPI30_IOC_H#define MPI30_IOC_H 1 struct mpi3_ioc_init_request {union mpi3_version_union mpi_version;#define MPI3_IOCINIT_MSGFLAGS_WRITESAMEDIVERT_SUPPORTED (0 x08)#define MPI3_IOCINIT_MSGFLAGS_SCSIIOSTATUSREPLY_SUPPORTED (0 x04)#define MPI3_IOCINIT_MSGFLAGS_HOSTMETADATA_MASK (0 x03)#define MPI3_IOCINIT_MSGFLAGS_HOSTMETADATA_SHIFT (0 )#define MPI3_IOCINIT_MSGFLAGS_HOSTMETADATA_NOT_USED (0 x00)#define MPI3_IOCINIT_MSGFLAGS_HOSTMETADATA_SEPARATED (0 x01)#define MPI3_IOCINIT_MSGFLAGS_HOSTMETADATA_INLINE (0 x02)#define MPI3_IOCINIT_MSGFLAGS_HOSTMETADATA_BOTH (0 x03)#define MPI3_WHOINIT_NOT_INITIALIZED (0 x00)#define MPI3_WHOINIT_ROM_BIOS (0 x02)#define MPI3_WHOINIT_HOST_DRIVER (0 x03)#define MPI3_WHOINIT_MANUFACTURER (0 x04)#define MPI3_IOCINIT_DRIVERCAP_OSEXPOSURE_MASK (0 x00000003)#define MPI3_IOCINIT_DRIVERCAP_OSEXPOSURE_SHIFT (0 )#define MPI3_IOCINIT_DRIVERCAP_OSEXPOSURE_NO_GUIDANCE (0 x00000000)#define MPI3_IOCINIT_DRIVERCAP_OSEXPOSURE_NO_SPECIAL (0 x00000001)#define MPI3_IOCINIT_DRIVERCAP_OSEXPOSURE_REPORT_AS_HDD (0 x00000002)#define MPI3_IOCINIT_DRIVERCAP_OSEXPOSURE_REPORT_AS_SSD (0 x00000003)struct mpi3_ioc_facts_request {union mpi3_sge_union sgl;struct mpi3_ioc_facts_data {union mpi3_version_union mpi_version;struct mpi3_comp_image_version fw_version;#define MPI3_IOCFACTS_CAPABILITY_NON_SUPERVISOR_MASK (0 x80000000)#define MPI3_IOCFACTS_CAPABILITY_NON_SUPERVISOR_SHIFT (31 )#define MPI3_IOCFACTS_CAPABILITY_SUPERVISOR_IOC (0 x00000000)#define MPI3_IOCFACTS_CAPABILITY_NON_SUPERVISOR_IOC (0 x80000000)#define MPI3_IOCFACTS_CAPABILITY_INT_COALESCE_MASK (0 x00000600)#define MPI3_IOCFACTS_CAPABILITY_INT_COALESCE_SHIFT (9 )#define MPI3_IOCFACTS_CAPABILITY_INT_COALESCE_FIXED_THRESHOLD (0 x00000000)#define MPI3_IOCFACTS_CAPABILITY_INT_COALESCE_OUTSTANDING_IO (0 x00000200)#define MPI3_IOCFACTS_CAPABILITY_COMPLETE_RESET_SUPPORTED (0 x00000100)#define MPI3_IOCFACTS_CAPABILITY_SEG_DIAG_TRACE_SUPPORTED (0 x00000080)#define MPI3_IOCFACTS_CAPABILITY_SEG_DIAG_FW_SUPPORTED (0 x00000040)#define MPI3_IOCFACTS_CAPABILITY_SEG_DIAG_DRIVER_SUPPORTED (0 x00000020)#define MPI3_IOCFACTS_CAPABILITY_ADVANCED_HOST_PD_SUPPORTED (0 x00000010)#define MPI3_IOCFACTS_CAPABILITY_RAID_SUPPORTED (0 x00000008)#define MPI3_IOCFACTS_CAPABILITY_MULTIPATH_SUPPORTED (0 x00000002)#define MPI3_IOCFACTS_CAPABILITY_COALESCE_CTRL_SUPPORTED (0 x00000001)#define MPI3_IOCFACTS_PID_TYPE_MASK (0 xf000)#define MPI3_IOCFACTS_PID_TYPE_SHIFT (12 )#define MPI3_IOCFACTS_PID_PRODUCT_MASK (0 x0f00)#define MPI3_IOCFACTS_PID_PRODUCT_SHIFT (8 )#define MPI3_IOCFACTS_PID_FAMILY_MASK (0 x00ff)#define MPI3_IOCFACTS_PID_FAMILY_SHIFT (0 )#define MPI3_IOCFACTS_EXCEPT_SECURITY_REKEY (0 x2000)#define MPI3_IOCFACTS_EXCEPT_SAS_DISABLED (0 x1000)#define MPI3_IOCFACTS_EXCEPT_SAFE_MODE (0 x0800)#define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_MASK (0 x0700)#define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_SHIFT (8 )#define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_NONE (0 x0000)#define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_LOCAL_VIA_MGMT (0 x0100)#define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_EXT_VIA_MGMT (0 x0200)#define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_DRIVE_EXT_VIA_MGMT (0 x0300)#define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_LOCAL_VIA_OOB (0 x0400)#define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_EXT_VIA_OOB (0 x0500)#define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_DRIVE_EXT_VIA_OOB (0 x0600)#define MPI3_IOCFACTS_EXCEPT_PCIE_DISABLED (0 x0080)#define MPI3_IOCFACTS_EXCEPT_PARTIAL_MEMORY_FAILURE (0 x0040)#define MPI3_IOCFACTS_EXCEPT_MANUFACT_CHECKSUM_FAIL (0 x0020)#define MPI3_IOCFACTS_EXCEPT_FW_CHECKSUM_FAIL (0 x0010)#define MPI3_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL (0 x0008)#define MPI3_IOCFACTS_EXCEPT_BLOCKING_BOOT_EVENT (0 x0004)#define MPI3_IOCFACTS_EXCEPT_SECURITY_SELFTEST_FAILURE (0 x0002)#define MPI3_IOCFACTS_EXCEPT_BOOTSTAT_MASK (0 x0001)#define MPI3_IOCFACTS_EXCEPT_BOOTSTAT_SHIFT (0 )#define MPI3_IOCFACTS_EXCEPT_BOOTSTAT_PRIMARY (0 x0000)#define MPI3_IOCFACTS_EXCEPT_BOOTSTAT_SECONDARY (0 x0001)#define MPI3_IOCFACTS_PROTOCOL_SAS (0 x0010)#define MPI3_IOCFACTS_PROTOCOL_SATA (0 x0008)#define MPI3_IOCFACTS_PROTOCOL_NVME (0 x0004)#define MPI3_IOCFACTS_PROTOCOL_SCSI_INITIATOR (0 x0002)#define MPI3_IOCFACTS_PROTOCOL_SCSI_TARGET (0 x0001)#define MPI3_IOCFACTS_MAX_DATA_LENGTH_NOT_REPORTED (0 x0000)#define MPI3_IOCFACTS_FLAGS_SIGNED_NVDATA_REQUIRED (0 x00010000)#define MPI3_IOCFACTS_FLAGS_DMA_ADDRESS_WIDTH_MASK (0 x0000ff00)#define MPI3_IOCFACTS_FLAGS_DMA_ADDRESS_WIDTH_SHIFT (8 )#define MPI3_IOCFACTS_FLAGS_INITIAL_PORT_ENABLE_MASK (0 x00000030)#define MPI3_IOCFACTS_FLAGS_INITIAL_PORT_ENABLE_SHIFT (4 )#define MPI3_IOCFACTS_FLAGS_INITIAL_PORT_ENABLE_NOT_STARTED (0 x00000000)#define MPI3_IOCFACTS_FLAGS_INITIAL_PORT_ENABLE_IN_PROGRESS (0 x00000010)#define MPI3_IOCFACTS_FLAGS_INITIAL_PORT_ENABLE_COMPLETE (0 x00000020)#define MPI3_IOCFACTS_FLAGS_PERSONALITY_MASK (0 x0000000f)#define MPI3_IOCFACTS_FLAGS_PERSONALITY_SHIFT (0 )#define MPI3_IOCFACTS_FLAGS_PERSONALITY_EHBA (0 x00000000)#define MPI3_IOCFACTS_FLAGS_PERSONALITY_RAID_DDR (0 x00000002)#define MPI3_IOCFACTS_IO_THROTTLE_DATA_LENGTH_NOT_REQUIRED (0 x0000)#define MPI3_IOCFACTS_MAX_IO_THROTTLE_GROUP_NOT_REQUIRED (0 x0000)#define MPI3_IOCFACTS_DIAGFDLSIZE_NOT_SUPPORTED (0 x00000000)#define MPI3_IOCFACTS_DIAGTTYSIZE_NOT_SUPPORTED (0 x00000000)struct mpi3_mgmt_passthrough_request {5 ];union mpi3_sge_union command_sgl;union mpi3_sge_union response_sgl;struct mpi3_create_request_queue_request {#define MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_MASK (0 x80)#define MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_SHIFT (7 )#define MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_SEGMENTED (0 x80)#define MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_CONTIGUOUS (0 x00)#define MPI3_CREATE_REQUEST_QUEUE_SIZE_MINIMUM (2 )struct mpi3_delete_request_queue_request {struct mpi3_create_reply_queue_request {#define MPI3_CREATE_REPLY_QUEUE_FLAGS_SEGMENTED_MASK (0 x80)#define MPI3_CREATE_REPLY_QUEUE_FLAGS_SEGMENTED_SHIFT (7 )#define MPI3_CREATE_REPLY_QUEUE_FLAGS_SEGMENTED_SEGMENTED (0 x80)#define MPI3_CREATE_REPLY_QUEUE_FLAGS_SEGMENTED_CONTIGUOUS (0 x00)#define MPI3_CREATE_REPLY_QUEUE_FLAGS_COALESCE_DISABLE (0 x02)#define MPI3_CREATE_REPLY_QUEUE_FLAGS_INT_ENABLE_MASK (0 x01)#define MPI3_CREATE_REPLY_QUEUE_FLAGS_INT_ENABLE_SHIFT (0 )#define MPI3_CREATE_REPLY_QUEUE_FLAGS_INT_ENABLE_DISABLE (0 x00)#define MPI3_CREATE_REPLY_QUEUE_FLAGS_INT_ENABLE_ENABLE (0 x01)#define MPI3_CREATE_REPLY_QUEUE_SIZE_MINIMUM (2 )struct mpi3_delete_reply_queue_request {struct mpi3_port_enable_request {#define MPI3_EVENT_LOG_DATA (0 x01)#define MPI3_EVENT_CHANGE (0 x02)#define MPI3_EVENT_GPIO_INTERRUPT (0 x04)#define MPI3_EVENT_CABLE_MGMT (0 x06)#define MPI3_EVENT_DEVICE_ADDED (0 x07)#define MPI3_EVENT_DEVICE_INFO_CHANGED (0 x08)#define MPI3_EVENT_PREPARE_FOR_RESET (0 x09)#define MPI3_EVENT_COMP_IMAGE_ACT_START (0 x0a)#define MPI3_EVENT_ENCL_DEVICE_ADDED (0 x0b)#define MPI3_EVENT_ENCL_DEVICE_STATUS_CHANGE (0 x0c)#define MPI3_EVENT_DEVICE_STATUS_CHANGE (0 x0d)#define MPI3_EVENT_ENERGY_PACK_CHANGE (0 x0e)#define MPI3_EVENT_SAS_DISCOVERY (0 x11)#define MPI3_EVENT_SAS_BROADCAST_PRIMITIVE (0 x12)#define MPI3_EVENT_SAS_NOTIFY_PRIMITIVE (0 x13)#define MPI3_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE (0 x14)#define MPI3_EVENT_SAS_INIT_TABLE_OVERFLOW (0 x15)#define MPI3_EVENT_SAS_TOPOLOGY_CHANGE_LIST (0 x16)#define MPI3_EVENT_SAS_PHY_COUNTER (0 x18)#define MPI3_EVENT_SAS_DEVICE_DISCOVERY_ERROR (0 x19)#define MPI3_EVENT_PCIE_TOPOLOGY_CHANGE_LIST (0 x20)#define MPI3_EVENT_PCIE_ENUMERATION (0 x22)#define MPI3_EVENT_PCIE_ERROR_THRESHOLD (0 x23)#define MPI3_EVENT_HARD_RESET_RECEIVED (0 x40)#define MPI3_EVENT_DIAGNOSTIC_BUFFER_STATUS_CHANGE (0 x50)#define MPI3_EVENT_MIN_PRODUCT_SPECIFIC (0 x60)#define MPI3_EVENT_MAX_PRODUCT_SPECIFIC (0 x7f)#define MPI3_EVENT_NOTIFY_EVENTMASK_WORDS (4 )struct mpi3_event_notification_request {struct mpi3_event_notification_reply {1 ];#define MPI3_EVENT_NOTIFY_MSGFLAGS_ACK_MASK (0 x01)#define MPI3_EVENT_NOTIFY_MSGFLAGS_ACK_SHIFT (0 )#define MPI3_EVENT_NOTIFY_MSGFLAGS_ACK_REQUIRED (0 x01)#define MPI3_EVENT_NOTIFY_MSGFLAGS_ACK_NOT_REQUIRED (0 x00)#define MPI3_EVENT_NOTIFY_MSGFLAGS_EVENT_ORIGINALITY_MASK (0 x02)#define MPI3_EVENT_NOTIFY_MSGFLAGS_EVENT_ORIGINALITY_SHIFT (1 )#define MPI3_EVENT_NOTIFY_MSGFLAGS_EVENT_ORIGINALITY_ORIGINAL (0 x00)#define MPI3_EVENT_NOTIFY_MSGFLAGS_EVENT_ORIGINALITY_REPLAY (0 x02)struct mpi3_event_data_gpio_interrupt {3 ];struct mpi3_event_data_cable_management {#define MPI3_EVENT_CABLE_MGMT_ACT_CABLE_PWR_INVALID (0 xffffffff)#define MPI3_EVENT_CABLE_MGMT_STATUS_INSUFFICIENT_POWER (0 x00)#define MPI3_EVENT_CABLE_MGMT_STATUS_PRESENT (0 x01)#define MPI3_EVENT_CABLE_MGMT_STATUS_DEGRADED (0 x02)struct mpi3_event_ack_request {3 ];struct mpi3_event_data_prepare_for_reset {#define MPI3_EVENT_PREPARE_RESET_RC_START (0 x01)#define MPI3_EVENT_PREPARE_RESET_RC_ABORT (0 x02)struct mpi3_event_data_comp_image_activation {struct mpi3_event_data_device_status_change {8 ];#define MPI3_EVENT_DEV_STAT_RC_MOVED (0 x01)#define MPI3_EVENT_DEV_STAT_RC_HIDDEN (0 x02)#define MPI3_EVENT_DEV_STAT_RC_NOT_HIDDEN (0 x03)#define MPI3_EVENT_DEV_STAT_RC_ASYNC_NOTIFICATION (0 x04)#define MPI3_EVENT_DEV_STAT_RC_INT_DEVICE_RESET_STRT (0 x20)#define MPI3_EVENT_DEV_STAT_RC_INT_DEVICE_RESET_CMP (0 x21)#define MPI3_EVENT_DEV_STAT_RC_INT_TASK_ABORT_STRT (0 x22)#define MPI3_EVENT_DEV_STAT_RC_INT_TASK_ABORT_CMP (0 x23)#define MPI3_EVENT_DEV_STAT_RC_INT_IT_NEXUS_RESET_STRT (0 x24)#define MPI3_EVENT_DEV_STAT_RC_INT_IT_NEXUS_RESET_CMP (0 x25)#define MPI3_EVENT_DEV_STAT_RC_PCIE_HOT_RESET_FAILED (0 x30)#define MPI3_EVENT_DEV_STAT_RC_EXPANDER_REDUCED_FUNC_STRT (0 x40)#define MPI3_EVENT_DEV_STAT_RC_EXPANDER_REDUCED_FUNC_CMP (0 x41)#define MPI3_EVENT_DEV_STAT_RC_VD_NOT_RESPONDING (0 x50)struct mpi3_event_data_energy_pack_change {struct mpi3_event_data_sas_discovery {#define MPI3_EVENT_SAS_DISC_FLAGS_DEVICE_CHANGE (0 x02)#define MPI3_EVENT_SAS_DISC_FLAGS_IN_PROGRESS (0 x01)#define MPI3_EVENT_SAS_DISC_RC_STARTED (0 x01)#define MPI3_EVENT_SAS_DISC_RC_COMPLETED (0 x02)#define MPI3_SAS_DISC_STATUS_MAX_ENCLOSURES_EXCEED (0 x80000000)#define MPI3_SAS_DISC_STATUS_MAX_EXPANDERS_EXCEED (0 x40000000)#define MPI3_SAS_DISC_STATUS_MAX_DEVICES_EXCEED (0 x20000000)#define MPI3_SAS_DISC_STATUS_MAX_TOPO_PHYS_EXCEED (0 x10000000)#define MPI3_SAS_DISC_STATUS_INVALID_CEI (0 x00010000)#define MPI3_SAS_DISC_STATUS_FECEI_MISMATCH (0 x00008000)#define MPI3_SAS_DISC_STATUS_MULTIPLE_DEVICES_IN_SLOT (0 x00004000)#define MPI3_SAS_DISC_STATUS_NECEI_MISMATCH (0 x00002000)#define MPI3_SAS_DISC_STATUS_TOO_MANY_SLOTS (0 x00001000)#define MPI3_SAS_DISC_STATUS_EXP_MULTI_SUBTRACTIVE (0 x00000800)#define MPI3_SAS_DISC_STATUS_MULTI_PORT_DOMAIN (0 x00000400)#define MPI3_SAS_DISC_STATUS_TABLE_TO_SUBTRACTIVE_LINK (0 x00000200)#define MPI3_SAS_DISC_STATUS_UNSUPPORTED_DEVICE (0 x00000100)#define MPI3_SAS_DISC_STATUS_TABLE_LINK (0 x00000080)#define MPI3_SAS_DISC_STATUS_SUBTRACTIVE_LINK (0 x00000040)#define MPI3_SAS_DISC_STATUS_SMP_CRC_ERROR (0 x00000020)#define MPI3_SAS_DISC_STATUS_SMP_FUNCTION_FAILED (0 x00000010)#define MPI3_SAS_DISC_STATUS_SMP_TIMEOUT (0 x00000008)#define MPI3_SAS_DISC_STATUS_MULTIPLE_PORTS (0 x00000004)#define MPI3_SAS_DISC_STATUS_INVALID_SAS_ADDRESS (0 x00000002)#define MPI3_SAS_DISC_STATUS_LOOP_DETECTED (0 x00000001)struct mpi3_event_data_sas_broadcast_primitive {#define MPI3_EVENT_BROADCAST_PRIMITIVE_CHANGE (0 x01)#define MPI3_EVENT_BROADCAST_PRIMITIVE_SES (0 x02)#define MPI3_EVENT_BROADCAST_PRIMITIVE_EXPANDER (0 x03)#define MPI3_EVENT_BROADCAST_PRIMITIVE_ASYNCHRONOUS_EVENT (0 x04)#define MPI3_EVENT_BROADCAST_PRIMITIVE_RESERVED3 (0 x05)#define MPI3_EVENT_BROADCAST_PRIMITIVE_RESERVED4 (0 x06)#define MPI3_EVENT_BROADCAST_PRIMITIVE_CHANGE0_RESERVED (0 x07)#define MPI3_EVENT_BROADCAST_PRIMITIVE_CHANGE1_RESERVED (0 x08)struct mpi3_event_data_sas_notify_primitive {#define MPI3_EVENT_NOTIFY_PRIMITIVE_ENABLE_SPINUP (0 x01)#define MPI3_EVENT_NOTIFY_PRIMITIVE_POWER_LOSS_EXPECTED (0 x02)#define MPI3_EVENT_NOTIFY_PRIMITIVE_RESERVED1 (0 x03)#define MPI3_EVENT_NOTIFY_PRIMITIVE_RESERVED2 (0 x04)struct mpi3_event_sas_topo_phy_entry {#define MPI3_EVENT_SAS_TOPO_LR_CURRENT_MASK (0 xf0)#define MPI3_EVENT_SAS_TOPO_LR_CURRENT_SHIFT (4 )#define MPI3_EVENT_SAS_TOPO_LR_PREV_MASK (0 x0f)#define MPI3_EVENT_SAS_TOPO_LR_PREV_SHIFT (0 )#define MPI3_EVENT_SAS_TOPO_LR_UNKNOWN_LINK_RATE (0 x00)#define MPI3_EVENT_SAS_TOPO_LR_PHY_DISABLED (0 x01)#define MPI3_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED (0 x02)#define MPI3_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE (0 x03)#define MPI3_EVENT_SAS_TOPO_LR_PORT_SELECTOR (0 x04)#define MPI3_EVENT_SAS_TOPO_LR_SMP_RESET_IN_PROGRESS (0 x05)#define MPI3_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY (0 x06)#define MPI3_EVENT_SAS_TOPO_LR_RATE_6_0 (0 x0a)#define MPI3_EVENT_SAS_TOPO_LR_RATE_12_0 (0 x0b)#define MPI3_EVENT_SAS_TOPO_LR_RATE_22_5 (0 x0c)#define MPI3_EVENT_SAS_TOPO_PHY_STATUS_MASK (0 xc0)#define MPI3_EVENT_SAS_TOPO_PHY_STATUS_SHIFT (6 )#define MPI3_EVENT_SAS_TOPO_PHY_STATUS_ACCESSIBLE (0 x00)#define MPI3_EVENT_SAS_TOPO_PHY_STATUS_NO_EXIST (0 x40)#define MPI3_EVENT_SAS_TOPO_PHY_STATUS_VACANT (0 x80)#define MPI3_EVENT_SAS_TOPO_PHY_RC_MASK (0 x0f)#define MPI3_EVENT_SAS_TOPO_PHY_RC_SHIFT (0 )#define MPI3_EVENT_SAS_TOPO_PHY_RC_TARG_NOT_RESPONDING (0 x02)#define MPI3_EVENT_SAS_TOPO_PHY_RC_PHY_CHANGED (0 x03)#define MPI3_EVENT_SAS_TOPO_PHY_RC_NO_CHANGE (0 x04)#define MPI3_EVENT_SAS_TOPO_PHY_RC_DELAY_NOT_RESPONDING (0 x05)#define MPI3_EVENT_SAS_TOPO_PHY_RC_RESPONDING (0 x06)struct mpi3_event_data_sas_topology_change_list {3 ];struct mpi3_event_sas_topo_phy_entry phy_entry[] __counted_by(num_entries);#define MPI3_EVENT_SAS_TOPO_ES_NO_EXPANDER (0 x00)#define MPI3_EVENT_SAS_TOPO_ES_NOT_RESPONDING (0 x02)#define MPI3_EVENT_SAS_TOPO_ES_RESPONDING (0 x03)#define MPI3_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING (0 x04)struct mpi3_event_data_sas_phy_counter {struct mpi3_event_data_sas_device_disc_err {#define MPI3_EVENT_SAS_DISC_ERR_RC_SMP_FAILED (0 x01)#define MPI3_EVENT_SAS_DISC_ERR_RC_SMP_TIMEOUT (0 x02)struct mpi3_event_data_pcie_enumeration {#define MPI3_EVENT_PCIE_ENUM_FLAGS_DEVICE_CHANGE (0 x02)#define MPI3_EVENT_PCIE_ENUM_FLAGS_IN_PROGRESS (0 x01)#define MPI3_EVENT_PCIE_ENUM_RC_STARTED (0 x01)#define MPI3_EVENT_PCIE_ENUM_RC_COMPLETED (0 x02)#define MPI3_EVENT_PCIE_ENUM_ES_MAX_SWITCH_DEPTH_EXCEED (0 x80000000)#define MPI3_EVENT_PCIE_ENUM_ES_MAX_SWITCHES_EXCEED (0 x40000000)#define MPI3_EVENT_PCIE_ENUM_ES_MAX_DEVICES_EXCEED (0 x20000000)#define MPI3_EVENT_PCIE_ENUM_ES_RESOURCES_EXHAUSTED (0 x10000000)struct mpi3_event_pcie_topo_port_entry {#define MPI3_EVENT_PCIE_TOPO_PS_NOT_RESPONDING (0 x02)#define MPI3_EVENT_PCIE_TOPO_PS_PORT_CHANGED (0 x03)#define MPI3_EVENT_PCIE_TOPO_PS_NO_CHANGE (0 x04)#define MPI3_EVENT_PCIE_TOPO_PS_DELAY_NOT_RESPONDING (0 x05)#define MPI3_EVENT_PCIE_TOPO_PS_RESPONDING (0 x06)#define MPI3_EVENT_PCIE_TOPO_PI_LANES_MASK (0 xf0)#define MPI3_EVENT_PCIE_TOPO_PI_LANES_SHIFT (4 )#define MPI3_EVENT_PCIE_TOPO_PI_LANES_UNKNOWN (0 x00)#define MPI3_EVENT_PCIE_TOPO_PI_LANES_1 (0 x10)#define MPI3_EVENT_PCIE_TOPO_PI_LANES_2 (0 x20)#define MPI3_EVENT_PCIE_TOPO_PI_LANES_4 (0 x30)#define MPI3_EVENT_PCIE_TOPO_PI_LANES_8 (0 x40)#define MPI3_EVENT_PCIE_TOPO_PI_LANES_16 (0 x50)#define MPI3_EVENT_PCIE_TOPO_PI_RATE_MASK (0 x0f)#define MPI3_EVENT_PCIE_TOPO_PI_RATE_SHIFT (0 )#define MPI3_EVENT_PCIE_TOPO_PI_RATE_UNKNOWN (0 x00)#define MPI3_EVENT_PCIE_TOPO_PI_RATE_DISABLED (0 x01)#define MPI3_EVENT_PCIE_TOPO_PI_RATE_2_5 (0 x02)#define MPI3_EVENT_PCIE_TOPO_PI_RATE_5_0 (0 x03)#define MPI3_EVENT_PCIE_TOPO_PI_RATE_8_0 (0 x04)#define MPI3_EVENT_PCIE_TOPO_PI_RATE_16_0 (0 x05)#define MPI3_EVENT_PCIE_TOPO_PI_RATE_32_0 (0 x06)struct mpi3_event_data_pcie_topology_change_list {3 ];struct mpi3_event_pcie_topo_port_entry port_entry[] __counted_by(num_entries);#define MPI3_EVENT_PCIE_TOPO_SS_NO_PCIE_SWITCH (0 x00)#define MPI3_EVENT_PCIE_TOPO_SS_NOT_RESPONDING (0 x02)#define MPI3_EVENT_PCIE_TOPO_SS_RESPONDING (0 x03)#define MPI3_EVENT_PCIE_TOPO_SS_DELAY_NOT_RESPONDING (0 x04)struct mpi3_event_data_pcie_error_threshold {#define MPI3_EVENT_PCI_ERROR_RC_THRESHOLD_EXCEEDED (0 x00)#define MPI3_EVENT_PCI_ERROR_RC_ESCALATION (0 x01)struct mpi3_event_data_sas_init_dev_status_change {#define MPI3_EVENT_SAS_INIT_RC_ADDED (0 x01)#define MPI3_EVENT_SAS_INIT_RC_NOT_RESPONDING (0 x02)struct mpi3_event_data_sas_init_table_overflow {struct mpi3_event_data_hard_reset_received {struct mpi3_event_data_diag_buffer_status_change {#define MPI3_EVENT_DIAG_BUFFER_STATUS_CHANGE_RC_RELEASED (0 x01)#define MPI3_EVENT_DIAG_BUFFER_STATUS_CHANGE_RC_PAUSED (0 x02)#define MPI3_EVENT_DIAG_BUFFER_STATUS_CHANGE_RC_RESUMED (0 x03)#define MPI3_PEL_LOCALE_FLAGS_NON_BLOCKING_BOOT_EVENT (0 x0200)#define MPI3_PEL_LOCALE_FLAGS_BLOCKING_BOOT_EVENT (0 x0100)#define MPI3_PEL_LOCALE_FLAGS_PCIE (0 x0080)#define MPI3_PEL_LOCALE_FLAGS_CONFIGURATION (0 x0040)#define MPI3_PEL_LOCALE_FLAGS_CONTROLER (0 x0020)#define MPI3_PEL_LOCALE_FLAGS_SAS (0 x0010)#define MPI3_PEL_LOCALE_FLAGS_EPACK (0 x0008)#define MPI3_PEL_LOCALE_FLAGS_ENCLOSURE (0 x0004)#define MPI3_PEL_LOCALE_FLAGS_PD (0 x0002)#define MPI3_PEL_LOCALE_FLAGS_VD (0 x0001)#define MPI3_PEL_CLASS_DEBUG (0 x00)#define MPI3_PEL_CLASS_PROGRESS (0 x01)#define MPI3_PEL_CLASS_INFORMATIONAL (0 x02)#define MPI3_PEL_CLASS_WARNING (0 x03)#define MPI3_PEL_CLASS_CRITICAL (0 x04)#define MPI3_PEL_CLASS_FATAL (0 x05)#define MPI3_PEL_CLASS_FAULT (0 x06)#define MPI3_PEL_CLEARTYPE_CLEAR (0 x00)#define MPI3_PEL_WAITTIME_INFINITE_WAIT (0 x00)#define MPI3_PEL_ACTION_GET_SEQNUM (0 x01)#define MPI3_PEL_ACTION_MARK_CLEAR (0 x02)#define MPI3_PEL_ACTION_GET_LOG (0 x03)#define MPI3_PEL_ACTION_GET_COUNT (0 x04)#define MPI3_PEL_ACTION_WAIT (0 x05)#define MPI3_PEL_ACTION_ABORT (0 x06)#define MPI3_PEL_ACTION_GET_PRINT_STRINGS (0 x07)#define MPI3_PEL_ACTION_ACKNOWLEDGE (0 x08)#define MPI3_PEL_STATUS_SUCCESS (0 x00)#define MPI3_PEL_STATUS_NOT_FOUND (0 x01)#define MPI3_PEL_STATUS_ABORTED (0 x02)#define MPI3_PEL_STATUS_NOT_READY (0 x03)struct mpi3_pel_seq {struct mpi3_pel_entry {class ;2 ];24 ];#define MPI3_PEL_FLAGS_COMPLETE_RESET_NEEDED (0 x02)#define MPI3_PEL_FLAGS_ACK_NEEDED (0 x01)struct mpi3_pel_list {struct mpi3_pel_entry entry[1 ];struct mpi3_pel_arg_map {#define MPI3_PEL_ARG_MAP_ARG_TYPE_APPEND_STRING (0 x00)#define MPI3_PEL_ARG_MAP_ARG_TYPE_INTEGER (0 x01)#define MPI3_PEL_ARG_MAP_ARG_TYPE_STRING (0 x02)#define MPI3_PEL_ARG_MAP_ARG_TYPE_BIT_FIELD (0 x03)struct mpi3_pel_print_string {3 ];struct mpi3_pel_arg_map arg_map[1 ];struct mpi3_pel_print_string_list {2 ];struct mpi3_pel_print_string print_string[1 ];#ifndef MPI3_PEL_ACTION_SPECIFIC_MAX#define MPI3_PEL_ACTION_SPECIFIC_MAX (1 )#endif struct mpi3_pel_request {struct mpi3_pel_req_action_get_sequence_numbers {5 ];union mpi3_sge_union sgl;struct mpi3_pel_req_action_clear_log_marker {3 ];struct mpi3_pel_req_action_get_log {class ;3 ];union mpi3_sge_union sgl;struct mpi3_pel_req_action_get_count {class ;3 ];union mpi3_sge_union sgl;struct mpi3_pel_req_action_wait {class ;2 ];struct mpi3_pel_req_action_abort {struct mpi3_pel_req_action_get_print_strings {3 ];union mpi3_sge_union sgl;struct mpi3_pel_req_action_acknowledge {#define MPI3_PELACKNOWLEDGE_MSGFLAGS_SAFE_MODE_EXIT_MASK (0 x03)#define MPI3_PELACKNOWLEDGE_MSGFLAGS_SAFE_MODE_EXIT_SHIFT (0 )#define MPI3_PELACKNOWLEDGE_MSGFLAGS_SAFE_MODE_EXIT_NO_GUIDANCE (0 x00)#define MPI3_PELACKNOWLEDGE_MSGFLAGS_SAFE_MODE_EXIT_CONTINUE_OP (0 x01)#define MPI3_PELACKNOWLEDGE_MSGFLAGS_SAFE_MODE_EXIT_TRANSITION_TO_FAULT (0 x02)struct mpi3_pel_reply {struct mpi3_ci_download_request {union mpi3_sge_union sgl;#define MPI3_CI_DOWNLOAD_MSGFLAGS_LAST_SEGMENT (0 x80)#define MPI3_CI_DOWNLOAD_MSGFLAGS_FORCE_FMC_ENABLE (0 x40)#define MPI3_CI_DOWNLOAD_MSGFLAGS_SIGNED_NVDATA (0 x20)#define MPI3_CI_DOWNLOAD_MSGFLAGS_WRITE_CACHE_FLUSH_MASK (0 x03)#define MPI3_CI_DOWNLOAD_MSGFLAGS_WRITE_CACHE_FLUSH_SHIFT (0 )#define MPI3_CI_DOWNLOAD_MSGFLAGS_WRITE_CACHE_FLUSH_FAST (0 x00)#define MPI3_CI_DOWNLOAD_MSGFLAGS_WRITE_CACHE_FLUSH_MEDIUM (0 x01)#define MPI3_CI_DOWNLOAD_MSGFLAGS_WRITE_CACHE_FLUSH_SLOW (0 x02)#define MPI3_CI_DOWNLOAD_ACTION_DOWNLOAD (0 x01)#define MPI3_CI_DOWNLOAD_ACTION_ONLINE_ACTIVATION (0 x02)#define MPI3_CI_DOWNLOAD_ACTION_OFFLINE_ACTIVATION (0 x03)#define MPI3_CI_DOWNLOAD_ACTION_GET_STATUS (0 x04)#define MPI3_CI_DOWNLOAD_ACTION_CANCEL_OFFLINE_ACTIVATION (0 x05)struct mpi3_ci_download_reply {#define MPI3_CI_DOWNLOAD_FLAGS_DOWNLOAD_IN_PROGRESS (0 x80)#define MPI3_CI_DOWNLOAD_FLAGS_ACTIVATION_FAILURE (0 x40)#define MPI3_CI_DOWNLOAD_FLAGS_OFFLINE_ACTIVATION_REQUIRED (0 x20)#define MPI3_CI_DOWNLOAD_FLAGS_KEY_UPDATE_PENDING (0 x10)#define MPI3_CI_DOWNLOAD_FLAGS_ACTIVATION_STATUS_MASK (0 x0e)#define MPI3_CI_DOWNLOAD_FLAGS_ACTIVATION_STATUS_SHIFT (1 )#define MPI3_CI_DOWNLOAD_FLAGS_ACTIVATION_STATUS_NOT_NEEDED (0 x00)#define MPI3_CI_DOWNLOAD_FLAGS_ACTIVATION_STATUS_AWAITING (0 x02)#define MPI3_CI_DOWNLOAD_FLAGS_ACTIVATION_STATUS_ONLINE_PENDING (0 x04)#define MPI3_CI_DOWNLOAD_FLAGS_ACTIVATION_STATUS_OFFLINE_PENDING (0 x06)#define MPI3_CI_DOWNLOAD_FLAGS_COMPATIBLE (0 x01)struct mpi3_ci_upload_request {union mpi3_sge_union sgl;#define MPI3_CI_UPLOAD_MSGFLAGS_LOCATION_MASK (0 x01)#define MPI3_CI_UPLOAD_MSGFLAGS_LOCATION_SHIFT (0 )#define MPI3_CI_UPLOAD_MSGFLAGS_LOCATION_PRIMARY (0 x00)#define MPI3_CI_UPLOAD_MSGFLAGS_LOCATION_SECONDARY (0 x01)#define MPI3_CI_UPLOAD_MSGFLAGS_FORMAT_MASK (0 x02)#define MPI3_CI_UPLOAD_MSGFLAGS_FORMAT_SHIFT (1 )#define MPI3_CI_UPLOAD_MSGFLAGS_FORMAT_FLASH (0 x00)#define MPI3_CI_UPLOAD_MSGFLAGS_FORMAT_EXECUTABLE (0 x02)#define MPI3_CTRL_OP_FORCE_FULL_DISCOVERY (0 x01)#define MPI3_CTRL_OP_LOOKUP_MAPPING (0 x02)#define MPI3_CTRL_OP_UPDATE_TIMESTAMP (0 x04)#define MPI3_CTRL_OP_GET_TIMESTAMP (0 x05)#define MPI3_CTRL_OP_GET_IOC_CHANGE_COUNT (0 x06)#define MPI3_CTRL_OP_CHANGE_PROFILE (0 x07)#define MPI3_CTRL_OP_REMOVE_DEVICE (0 x10)#define MPI3_CTRL_OP_CLOSE_PERSISTENT_CONNECTION (0 x11)#define MPI3_CTRL_OP_HIDDEN_ACK (0 x12)#define MPI3_CTRL_OP_CLEAR_DEVICE_COUNTERS (0 x13)#define MPI3_CTRL_OP_SEND_SAS_PRIMITIVE (0 x20)#define MPI3_CTRL_OP_SAS_PHY_CONTROL (0 x21)#define MPI3_CTRL_OP_READ_INTERNAL_BUS (0 x23)#define MPI3_CTRL_OP_WRITE_INTERNAL_BUS (0 x24)#define MPI3_CTRL_OP_PCIE_LINK_CONTROL (0 x30)#define MPI3_CTRL_OP_LOOKUP_MAPPING_PARAM8_LOOKUP_METHOD_INDEX (0 x00)#define MPI3_CTRL_OP_UPDATE_TIMESTAMP_PARAM64_TIMESTAMP_INDEX (0 x00)#define MPI3_CTRL_OP_CHANGE_PROFILE_PARAM8_PROFILE_ID_INDEX (0 x00)#define MPI3_CTRL_OP_REMOVE_DEVICE_PARAM16_DEVHANDLE_INDEX (0 x00)#define MPI3_CTRL_OP_CLOSE_PERSIST_CONN_PARAM16_DEVHANDLE_INDEX (0 x00)#define MPI3_CTRL_OP_HIDDEN_ACK_PARAM16_DEVHANDLE_INDEX (0 x00)#define MPI3_CTRL_OP_CLEAR_DEVICE_COUNTERS_PARAM16_DEVHANDLE_INDEX (0 x00)#define MPI3_CTRL_OP_SEND_SAS_PRIM_PARAM8_PHY_INDEX (0 x00)#define MPI3_CTRL_OP_SEND_SAS_PRIM_PARAM8_PRIMSEQ_INDEX (0 x01)#define MPI3_CTRL_OP_SEND_SAS_PRIM_PARAM32_PRIMITIVE_INDEX (0 x00)#define MPI3_CTRL_OP_SAS_PHY_CONTROL_PARAM8_ACTION_INDEX (0 x00)#define MPI3_CTRL_OP_SAS_PHY_CONTROL_PARAM8_PHY_INDEX (0 x01)#define MPI3_CTRL_OP_READ_INTERNAL_BUS_PARAM64_ADDRESS_INDEX (0 x00)#define MPI3_CTRL_OP_WRITE_INTERNAL_BUS_PARAM64_ADDRESS_INDEX (0 x00)#define MPI3_CTRL_OP_WRITE_INTERNAL_BUS_PARAM32_VALUE_INDEX (0 x00)#define MPI3_CTRL_OP_PCIE_LINK_CONTROL_PARAM8_ACTION_INDEX (0 x00)#define MPI3_CTRL_OP_PCIE_LINK_CONTROL_PARAM8_LINK_INDEX (0 x01)#define MPI3_CTRL_LOOKUP_METHOD_WWID_ADDRESS (0 x01)#define MPI3_CTRL_LOOKUP_METHOD_ENCLOSURE_SLOT (0 x02)#define MPI3_CTRL_LOOKUP_METHOD_SAS_DEVICE_NAME (0 x03)#define MPI3_CTRL_LOOKUP_METHOD_PERSISTENT_ID (0 x04)#define MPI3_CTRL_LOOKUP_METHOD_WWIDADDR_PARAM16_DEVH_INDEX (0 )#define MPI3_CTRL_LOOKUP_METHOD_WWIDADDR_PARAM64_WWID_INDEX (0 )#define MPI3_CTRL_LOOKUP_METHOD_ENCLSLOT_PARAM16_SLOTNUM_INDEX (0 )#define MPI3_CTRL_LOOKUP_METHOD_ENCLSLOT_PARAM64_ENCLOSURELID_INDEX (0 )#define MPI3_CTRL_LOOKUP_METHOD_SASDEVNAME_PARAM16_DEVH_INDEX (0 )#define MPI3_CTRL_LOOKUP_METHOD_SASDEVNAME_PARAM64_DEVNAME_INDEX (0 )#define MPI3_CTRL_LOOKUP_METHOD_PERSISTID_PARAM16_DEVH_INDEX (0 )#define MPI3_CTRL_LOOKUP_METHOD_PERSISTID_PARAM16_PERSISTENT_ID_INDEX (1 )#define MPI3_CTRL_LOOKUP_METHOD_VALUE16_DEVH_INDEX (0 )#define MPI3_CTRL_GET_TIMESTAMP_VALUE64_TIMESTAMP_INDEX (0 )#define MPI3_CTRL_GET_IOC_CHANGE_COUNT_VALUE16_CHANGECOUNT_INDEX (0 )#define MPI3_CTRL_READ_INTERNAL_BUS_VALUE32_VALUE_INDEX (0 )#define MPI3_CTRL_PRIMFLAGS_SINGLE (0 x01)#define MPI3_CTRL_PRIMFLAGS_TRIPLE (0 x03)#define MPI3_CTRL_PRIMFLAGS_REDUNDANT (0 x06)#define MPI3_CTRL_ACTION_NOP (0 x00)#define MPI3_CTRL_ACTION_LINK_RESET (0 x01)#define MPI3_CTRL_ACTION_HARD_RESET (0 x02)#define MPI3_CTRL_ACTION_CLEAR_ERROR_LOG (0 x05)struct mpi3_iounit_control_request {2 ];4 ];4 ];8 ];struct mpi3_iounit_control_reply {2 ];4 ];4 ];8 ];#endif
Messung V0.5 in Prozent C=93 H=94 G=93
¤ Dauer der Verarbeitung: 0.16 Sekunden
(vorverarbeitet am 2026-06-08)
¤ *© Formatika GbR, Deutschland
