// SPDX-License-Identifier: GPL-2.0-only // Copyright (C) 2014-2017 Broadcom /* * Broadcom Cygnus IOMUX driver * * This file contains the Cygnus IOMUX driver that supports group based PINMUX * configuration. Although PINMUX configuration is mainly group based, the * Cygnus IOMUX controller allows certain pins to be individually muxed to GPIO * function, and therefore be controlled by the Cygnus ASIU GPIO controller #include <linux/err.h>#include <linux/io.h>#include <linux/of.h>#include <linux/platform_device.h>#include <linux/seq_file.h>#include <linux/slab.h>#include <linux/pinctrl/pinconf-generic.h>#include <linux/pinctrl/pinconf.h>#include <linux/pinctrl/pinctrl.h>#include <linux/pinctrl/pinmux.h>#include "../core.h" #include "../pinctrl-utils.h" #define CYGNUS_NUM_IOMUX_REGS 8 #define CYGNUS_NUM_MUX_PER_REG 8 #define CYGNUS_NUM_IOMUX (CYGNUS_NUM_IOMUX_REGS * \/* * Cygnus IOMUX register description * * @offset: register offset for mux configuration of a group * @shift: bit shift for mux configuration of a group * @alt: alternate function to set to struct cygnus_mux {unsigned int offset;unsigned int shift;unsigned int alt;/* * Keep track of Cygnus IOMUX configuration and prevent double configuration * * @cygnus_mux: Cygnus IOMUX register description * @is_configured: flag to indicate whether a mux setting has already been * configured struct cygnus_mux_log {struct cygnus_mux mux;bool is_configured;/* * Group based IOMUX configuration * * @name: name of the group * @pins: array of pins used by this group * @num_pins: total number of pins used by this group * @mux: Cygnus group based IOMUX configuration struct cygnus_pin_group {const char *name;const unsigned *pins;unsigned num_pins;struct cygnus_mux mux;/* * Cygnus mux function and supported pin groups * * @name: name of the function * @groups: array of groups that can be supported by this function * @num_groups: total number of groups that can be supported by this function struct cygnus_pin_function {const char *name;const char * const *groups;unsigned num_groups;/* * Cygnus IOMUX pinctrl core * * @pctl: pointer to pinctrl_dev * @dev: pointer to device * @base0: first I/O register base of the Cygnus IOMUX controller * @base1: second I/O register base * @groups: pointer to array of groups * @num_groups: total number of groups * @functions: pointer to array of functions * @num_functions: total number of functions * @mux_log: pointer to the array of mux logs * @lock: lock to protect register access struct cygnus_pinctrl {struct pinctrl_dev *pctl;struct device *dev;void __iomem *base0;void __iomem *base1;const struct cygnus_pin_group *groups;unsigned num_groups;const struct cygnus_pin_function *functions;unsigned num_functions;struct cygnus_mux_log *mux_log;/* * Certain pins can be individually muxed to GPIO function * * @is_supported: flag to indicate GPIO mux is supported for this pin * @offset: register offset for GPIO mux override of a pin * @shift: bit shift for GPIO mux override of a pin struct cygnus_gpio_mux {int is_supported;unsigned int offset;unsigned int shift;/* * Description of a pin in Cygnus * * @pin: pin number * @name: pin name * @gpio_mux: GPIO override related information struct cygnus_pin {unsigned pin;char *name;struct cygnus_gpio_mux gpio_mux;#define CYGNUS_PIN_DESC(p, n, i, o, s) \/* * List of pins in Cygnus static struct cygnus_pin cygnus_pins[] = {0 , "ext_device_reset_n" , 0 , 0 , 0 ),1 , "chip_mode0" , 0 , 0 , 0 ),2 , "chip_mode1" , 0 , 0 , 0 ),3 , "chip_mode2" , 0 , 0 , 0 ),4 , "chip_mode3" , 0 , 0 , 0 ),5 , "chip_mode4" , 0 , 0 , 0 ),6 , "bsc0_scl" , 0 , 0 , 0 ),7 , "bsc0_sda" , 0 , 0 , 0 ),8 , "bsc1_scl" , 0 , 0 , 0 ),9 , "bsc1_sda" , 0 , 0 , 0 ),10 , "d1w_dq" , 1 , 0 x28, 0 ),11 , "d1wowstz_l" , 1 , 0 x4, 28 ),12 , "gpio0" , 0 , 0 , 0 ),13 , "gpio1" , 0 , 0 , 0 ),14 , "gpio2" , 0 , 0 , 0 ),15 , "gpio3" , 0 , 0 , 0 ),16 , "gpio4" , 0 , 0 , 0 ),17 , "gpio5" , 0 , 0 , 0 ),18 , "gpio6" , 0 , 0 , 0 ),19 , "gpio7" , 0 , 0 , 0 ),20 , "gpio8" , 0 , 0 , 0 ),21 , "gpio9" , 0 , 0 , 0 ),22 , "gpio10" , 0 , 0 , 0 ),23 , "gpio11" , 0 , 0 , 0 ),24 , "gpio12" , 0 , 0 , 0 ),25 , "gpio13" , 0 , 0 , 0 ),26 , "gpio14" , 0 , 0 , 0 ),27 , "gpio15" , 0 , 0 , 0 ),28 , "gpio16" , 0 , 0 , 0 ),29 , "gpio17" , 0 , 0 , 0 ),30 , "gpio18" , 0 , 0 , 0 ),31 , "gpio19" , 0 , 0 , 0 ),32 , "gpio20" , 0 , 0 , 0 ),33 , "gpio21" , 0 , 0 , 0 ),34 , "gpio22" , 0 , 0 , 0 ),35 , "gpio23" , 0 , 0 , 0 ),36 , "mdc" , 0 , 0 , 0 ),37 , "mdio" , 0 , 0 , 0 ),38 , "pwm0" , 1 , 0 x10, 30 ),39 , "pwm1" , 1 , 0 x10, 28 ),40 , "pwm2" , 1 , 0 x10, 26 ),41 , "pwm3" , 1 , 0 x10, 24 ),42 , "sc0_clk" , 1 , 0 x10, 22 ),43 , "sc0_cmdvcc_l" , 1 , 0 x10, 20 ),44 , "sc0_detect" , 1 , 0 x10, 18 ),45 , "sc0_fcb" , 1 , 0 x10, 16 ),46 , "sc0_io" , 1 , 0 x10, 14 ),47 , "sc0_rst_l" , 1 , 0 x10, 12 ),48 , "sc1_clk" , 1 , 0 x10, 10 ),49 , "sc1_cmdvcc_l" , 1 , 0 x10, 8 ),50 , "sc1_detect" , 1 , 0 x10, 6 ),51 , "sc1_fcb" , 1 , 0 x10, 4 ),52 , "sc1_io" , 1 , 0 x10, 2 ),53 , "sc1_rst_l" , 1 , 0 x10, 0 ),54 , "spi0_clk" , 1 , 0 x18, 10 ),55 , "spi0_mosi" , 1 , 0 x18, 6 ),56 , "spi0_miso" , 1 , 0 x18, 8 ),57 , "spi0_ss" , 1 , 0 x18, 4 ),58 , "spi1_clk" , 1 , 0 x18, 2 ),59 , "spi1_mosi" , 1 , 0 x1c, 30 ),60 , "spi1_miso" , 1 , 0 x18, 0 ),61 , "spi1_ss" , 1 , 0 x1c, 28 ),62 , "spi2_clk" , 1 , 0 x1c, 26 ),63 , "spi2_mosi" , 1 , 0 x1c, 22 ),64 , "spi2_miso" , 1 , 0 x1c, 24 ),65 , "spi2_ss" , 1 , 0 x1c, 20 ),66 , "spi3_clk" , 1 , 0 x1c, 18 ),67 , "spi3_mosi" , 1 , 0 x1c, 14 ),68 , "spi3_miso" , 1 , 0 x1c, 16 ),69 , "spi3_ss" , 1 , 0 x1c, 12 ),70 , "uart0_cts" , 1 , 0 x1c, 10 ),71 , "uart0_rts" , 1 , 0 x1c, 8 ),72 , "uart0_rx" , 1 , 0 x1c, 6 ),73 , "uart0_tx" , 1 , 0 x1c, 4 ),74 , "uart1_cts" , 1 , 0 x1c, 2 ),75 , "uart1_dcd" , 1 , 0 x1c, 0 ),76 , "uart1_dsr" , 1 , 0 x20, 14 ),77 , "uart1_dtr" , 1 , 0 x20, 12 ),78 , "uart1_ri" , 1 , 0 x20, 10 ),79 , "uart1_rts" , 1 , 0 x20, 8 ),80 , "uart1_rx" , 1 , 0 x20, 6 ),81 , "uart1_tx" , 1 , 0 x20, 4 ),82 , "uart3_rx" , 1 , 0 x20, 2 ),83 , "uart3_tx" , 1 , 0 x20, 0 ),84 , "sdio1_clk_sdcard" , 1 , 0 x14, 6 ),85 , "sdio1_cmd" , 1 , 0 x14, 4 ),86 , "sdio1_data0" , 1 , 0 x14, 2 ),87 , "sdio1_data1" , 1 , 0 x14, 0 ),88 , "sdio1_data2" , 1 , 0 x18, 30 ),89 , "sdio1_data3" , 1 , 0 x18, 28 ),90 , "sdio1_wp_n" , 1 , 0 x18, 24 ),91 , "sdio1_card_rst" , 1 , 0 x14, 10 ),92 , "sdio1_led_on" , 1 , 0 x18, 26 ),93 , "sdio1_cd" , 1 , 0 x14, 8 ),94 , "sdio0_clk_sdcard" , 1 , 0 x14, 26 ),95 , "sdio0_cmd" , 1 , 0 x14, 24 ),96 , "sdio0_data0" , 1 , 0 x14, 22 ),97 , "sdio0_data1" , 1 , 0 x14, 20 ),98 , "sdio0_data2" , 1 , 0 x14, 18 ),99 , "sdio0_data3" , 1 , 0 x14, 16 ),100 , "sdio0_wp_n" , 1 , 0 x14, 12 ),101 , "sdio0_card_rst" , 1 , 0 x14, 30 ),102 , "sdio0_led_on" , 1 , 0 x14, 14 ),103 , "sdio0_cd" , 1 , 0 x14, 28 ),104 , "sflash_clk" , 1 , 0 x18, 22 ),105 , "sflash_cs_l" , 1 , 0 x18, 20 ),106 , "sflash_mosi" , 1 , 0 x18, 14 ),107 , "sflash_miso" , 1 , 0 x18, 16 ),108 , "sflash_wp_n" , 1 , 0 x18, 12 ),109 , "sflash_hold_n" , 1 , 0 x18, 18 ),110 , "nand_ale" , 1 , 0 xc, 30 ),111 , "nand_ce0_l" , 1 , 0 xc, 28 ),112 , "nand_ce1_l" , 1 , 0 xc, 26 ),113 , "nand_cle" , 1 , 0 xc, 24 ),114 , "nand_dq0" , 1 , 0 xc, 22 ),115 , "nand_dq1" , 1 , 0 xc, 20 ),116 , "nand_dq2" , 1 , 0 xc, 18 ),117 , "nand_dq3" , 1 , 0 xc, 16 ),118 , "nand_dq4" , 1 , 0 xc, 14 ),119 , "nand_dq5" , 1 , 0 xc, 12 ),120 , "nand_dq6" , 1 , 0 xc, 10 ),121 , "nand_dq7" , 1 , 0 xc, 8 ),122 , "nand_rb_l" , 1 , 0 xc, 6 ),123 , "nand_re_l" , 1 , 0 xc, 4 ),124 , "nand_we_l" , 1 , 0 xc, 2 ),125 , "nand_wp_l" , 1 , 0 xc, 0 ),126 , "lcd_clac" , 1 , 0 x4, 26 ),127 , "lcd_clcp" , 1 , 0 x4, 24 ),128 , "lcd_cld0" , 1 , 0 x4, 22 ),129 , "lcd_cld1" , 1 , 0 x4, 0 ),130 , "lcd_cld10" , 1 , 0 x4, 20 ),131 , "lcd_cld11" , 1 , 0 x4, 18 ),132 , "lcd_cld12" , 1 , 0 x4, 16 ),133 , "lcd_cld13" , 1 , 0 x4, 14 ),134 , "lcd_cld14" , 1 , 0 x4, 12 ),135 , "lcd_cld15" , 1 , 0 x4, 10 ),136 , "lcd_cld16" , 1 , 0 x4, 8 ),137 , "lcd_cld17" , 1 , 0 x4, 6 ),138 , "lcd_cld18" , 1 , 0 x4, 4 ),139 , "lcd_cld19" , 1 , 0 x4, 2 ),140 , "lcd_cld2" , 1 , 0 x8, 22 ),141 , "lcd_cld20" , 1 , 0 x8, 30 ),142 , "lcd_cld21" , 1 , 0 x8, 28 ),143 , "lcd_cld22" , 1 , 0 x8, 26 ),144 , "lcd_cld23" , 1 , 0 x8, 24 ),145 , "lcd_cld3" , 1 , 0 x8, 20 ),146 , "lcd_cld4" , 1 , 0 x8, 18 ),147 , "lcd_cld5" , 1 , 0 x8, 16 ),148 , "lcd_cld6" , 1 , 0 x8, 14 ),149 , "lcd_cld7" , 1 , 0 x8, 12 ),150 , "lcd_cld8" , 1 , 0 x8, 10 ),151 , "lcd_cld9" , 1 , 0 x8, 8 ),152 , "lcd_clfp" , 1 , 0 x8, 6 ),153 , "lcd_clle" , 1 , 0 x8, 4 ),154 , "lcd_cllp" , 1 , 0 x8, 2 ),155 , "lcd_clpower" , 1 , 0 x8, 0 ),156 , "camera_vsync" , 1 , 0 x4, 30 ),157 , "camera_trigger" , 1 , 0 x0, 0 ),158 , "camera_strobe" , 1 , 0 x0, 2 ),159 , "camera_standby" , 1 , 0 x0, 4 ),160 , "camera_reset_n" , 1 , 0 x0, 6 ),161 , "camera_pixdata9" , 1 , 0 x0, 8 ),162 , "camera_pixdata8" , 1 , 0 x0, 10 ),163 , "camera_pixdata7" , 1 , 0 x0, 12 ),164 , "camera_pixdata6" , 1 , 0 x0, 14 ),165 , "camera_pixdata5" , 1 , 0 x0, 16 ),166 , "camera_pixdata4" , 1 , 0 x0, 18 ),167 , "camera_pixdata3" , 1 , 0 x0, 20 ),168 , "camera_pixdata2" , 1 , 0 x0, 22 ),169 , "camera_pixdata1" , 1 , 0 x0, 24 ),170 , "camera_pixdata0" , 1 , 0 x0, 26 ),171 , "camera_pixclk" , 1 , 0 x0, 28 ),172 , "camera_hsync" , 1 , 0 x0, 30 ),173 , "camera_pll_ref_clk" , 0 , 0 , 0 ),174 , "usb_id_indication" , 0 , 0 , 0 ),175 , "usb_vbus_indication" , 0 , 0 , 0 ),176 , "gpio0_3p3" , 0 , 0 , 0 ),177 , "gpio1_3p3" , 0 , 0 , 0 ),178 , "gpio2_3p3" , 0 , 0 , 0 ),179 , "gpio3_3p3" , 0 , 0 , 0 ),/* * List of groups of pins static const unsigned bsc1_pins[] = { 8 , 9 };static const unsigned pcie_clkreq_pins[] = { 8 , 9 };static const unsigned i2s2_0_pins[] = { 12 };static const unsigned i2s2_1_pins[] = { 13 };static const unsigned i2s2_2_pins[] = { 14 };static const unsigned i2s2_3_pins[] = { 15 };static const unsigned i2s2_4_pins[] = { 16 };static const unsigned pwm4_pins[] = { 17 };static const unsigned pwm5_pins[] = { 18 };static const unsigned key0_pins[] = { 20 };static const unsigned key1_pins[] = { 21 };static const unsigned key2_pins[] = { 22 };static const unsigned key3_pins[] = { 23 };static const unsigned key4_pins[] = { 24 };static const unsigned key5_pins[] = { 25 };static const unsigned key6_pins[] = { 26 };static const unsigned audio_dte0_pins[] = { 26 };static const unsigned key7_pins[] = { 27 };static const unsigned audio_dte1_pins[] = { 27 };static const unsigned key8_pins[] = { 28 };static const unsigned key9_pins[] = { 29 };static const unsigned key10_pins[] = { 30 };static const unsigned key11_pins[] = { 31 };static const unsigned key12_pins[] = { 32 };static const unsigned key13_pins[] = { 33 };static const unsigned key14_pins[] = { 34 };static const unsigned audio_dte2_pins[] = { 34 };static const unsigned key15_pins[] = { 35 };static const unsigned audio_dte3_pins[] = { 35 };static const unsigned pwm0_pins[] = { 38 };static const unsigned pwm1_pins[] = { 39 };static const unsigned pwm2_pins[] = { 40 };static const unsigned pwm3_pins[] = { 41 };static const unsigned sdio0_pins[] = { 94 , 95 , 96 , 97 , 98 , 99 };static const unsigned smart_card0_pins[] = { 42 , 43 , 44 , 46 , 47 };static const unsigned i2s0_0_pins[] = { 42 , 43 , 44 , 46 };static const unsigned spdif_pins[] = { 47 };static const unsigned smart_card1_pins[] = { 48 , 49 , 50 , 52 , 53 };static const unsigned i2s1_0_pins[] = { 48 , 49 , 50 , 52 };static const unsigned spi0_pins[] = { 54 , 55 , 56 , 57 };static const unsigned spi1_pins[] = { 58 , 59 , 60 , 61 };static const unsigned spi2_pins[] = { 62 , 63 , 64 , 65 };static const unsigned spi3_pins[] = { 66 , 67 , 68 , 69 };static const unsigned sw_led0_0_pins[] = { 66 , 67 , 68 , 69 };static const unsigned d1w_pins[] = { 10 , 11 };static const unsigned uart4_pins[] = { 10 , 11 };static const unsigned sw_led2_0_pins[] = { 10 , 11 };static const unsigned lcd_pins[] = { 126 , 127 , 128 , 129 , 130 , 131 , 132 , 133 ,134 , 135 , 136 , 137 , 138 , 139 , 140 , 141 , 142 , 143 , 144 , 145 , 146 , 147 ,148 , 149 , 150 , 151 , 152 , 153 , 154 , 155 };static const unsigned sram_0_pins[] = { 126 , 127 , 128 , 129 , 130 , 131 , 132 , 133 ,134 , 135 , 136 , 137 , 138 , 139 , 140 , 141 , 142 , 143 , 144 , 145 , 146 , 147 ,148 , 149 , 150 , 151 , 152 , 153 , 154 , 155 };static const unsigned spi5_pins[] = { 141 , 142 , 143 , 144 };static const unsigned uart0_pins[] = { 70 , 71 , 72 , 73 };static const unsigned sw_led0_1_pins[] = { 70 , 71 , 72 , 73 };static const unsigned uart1_dte_pins[] = { 75 , 76 , 77 , 78 };static const unsigned uart2_pins[] = { 75 , 76 , 77 , 78 };static const unsigned uart1_pins[] = { 74 , 79 , 80 , 81 };static const unsigned uart3_pins[] = { 82 , 83 };static const unsigned qspi_0_pins[] = { 104 , 105 , 106 , 107 };static const unsigned nand_pins[] = { 110 , 111 , 112 , 113 , 114 , 115 , 116 , 117 ,118 , 119 , 120 , 121 , 122 , 123 , 124 , 125 };static const unsigned sdio0_cd_pins[] = { 103 };static const unsigned sdio0_mmc_pins[] = { 100 , 101 , 102 };static const unsigned sdio1_data_0_pins[] = { 86 , 87 };static const unsigned can0_pins[] = { 86 , 87 };static const unsigned spi4_0_pins[] = { 86 , 87 };static const unsigned sdio1_data_1_pins[] = { 88 , 89 };static const unsigned can1_pins[] = { 88 , 89 };static const unsigned spi4_1_pins[] = { 88 , 89 };static const unsigned sdio1_cd_pins[] = { 93 };static const unsigned sdio1_led_pins[] = { 84 , 85 };static const unsigned sw_led2_1_pins[] = { 84 , 85 };static const unsigned sdio1_mmc_pins[] = { 90 , 91 , 92 };static const unsigned cam_led_pins[] = { 156 , 157 , 158 , 159 , 160 };static const unsigned sw_led1_pins[] = { 156 , 157 , 158 , 159 };static const unsigned cam_0_pins[] = { 169 , 170 , 171 , 169 , 170 };static const unsigned cam_1_pins[] = { 161 , 162 , 163 , 164 , 165 , 166 , 167 ,168 };static const unsigned sram_1_pins[] = { 161 , 162 , 163 , 164 , 165 , 166 , 167 ,168 };static const unsigned qspi_1_pins[] = { 108 , 109 };static const unsigned smart_card0_fcb_pins[] = { 45 };static const unsigned i2s0_1_pins[] = { 45 };static const unsigned smart_card1_fcb_pins[] = { 51 };static const unsigned i2s1_1_pins[] = { 51 };static const unsigned gpio0_3p3_pins[] = { 176 };static const unsigned usb0_oc_pins[] = { 176 };static const unsigned gpio1_3p3_pins[] = { 177 };static const unsigned usb1_oc_pins[] = { 177 };static const unsigned gpio2_3p3_pins[] = { 178 };static const unsigned usb2_oc_pins[] = { 178 };#define CYGNUS_PIN_GROUP(group_name, off, sh, al) \"_grp" , \## _pins, \## _pins), \/* * List of Cygnus pin groups static const struct cygnus_pin_group cygnus_pin_groups[] = {0 x0, 0 , 2 ),0 x0, 4 , 2 ),0 x0, 8 , 2 ),0 x0, 12 , 2 ),0 x0, 16 , 2 ),0 x0, 20 , 0 ),0 x0, 24 , 2 ),0 x4, 0 , 1 ),0 x4, 4 , 1 ),0 x4, 8 , 1 ),0 x4, 12 , 1 ),0 x4, 16 , 1 ),0 x4, 20 , 1 ),0 x4, 24 , 1 ),0 x4, 24 , 2 ),0 x4, 28 , 1 ),0 x4, 28 , 2 ),0 x8, 0 , 1 ),0 x8, 4 , 1 ),0 x8, 8 , 1 ),0 x8, 12 , 1 ),0 x8, 16 , 1 ),0 x8, 20 , 1 ),0 x8, 24 , 1 ),0 x8, 24 , 2 ),0 x8, 28 , 1 ),0 x8, 28 , 2 ),0 xc, 0 , 0 ),0 xc, 4 , 0 ),0 xc, 8 , 0 ),0 xc, 12 , 0 ),0 xc, 16 , 0 ),0 xc, 20 , 0 ),0 xc, 20 , 1 ),0 xc, 20 , 1 ),0 xc, 24 , 0 ),0 xc, 24 , 1 ),0 x10, 0 , 0 ),0 x10, 4 , 0 ),0 x10, 8 , 0 ),0 x10, 12 , 0 ),0 x10, 12 , 2 ),0 x10, 16 , 0 ),0 x10, 16 , 1 ),0 x10, 16 , 2 ),0 x10, 20 , 0 ),0 x10, 20 , 1 ),0 x10, 20 , 2 ),0 x14, 0 , 0 ),0 x14, 0 , 2 ),0 x14, 4 , 0 ),0 x14, 4 , 1 ),0 x14, 8 , 0 ),0 x14, 12 , 0 ),0 x14, 16 , 0 ),0 x14, 20 , 0 ),0 x18, 0 , 0 ),0 x18, 4 , 0 ),0 x18, 8 , 0 ),0 x18, 8 , 1 ),0 x18, 8 , 2 ),0 x18, 12 , 0 ),0 x18, 12 , 1 ),0 x18, 12 , 2 ),0 x18, 16 , 0 ),0 x18, 20 , 0 ),0 x18, 20 , 2 ),0 x18, 24 , 0 ),0 x1c, 0 , 0 ),0 x1c, 0 , 1 ),0 x1c, 4 , 0 ),0 x1c, 8 , 0 ),0 x1c, 8 , 1 ),0 x1c, 12 , 0 ),0 x1c, 16 , 0 ),0 x1c, 16 , 1 ),0 x20, 0 , 0 ),0 x20, 0 , 1 ),0 x20, 4 , 0 ),0 x20, 4 , 1 ),0 x28, 0 , 0 ),0 x28, 0 , 1 ),0 x28, 4 , 0 ),0 x28, 4 , 1 ),0 x28, 8 , 0 ),0 x28, 8 , 1 ),/* * List of groups supported by functions static const char * const i2s0_grps[] = { "i2s0_0_grp" , "i2s0_1_grp" };static const char * const i2s1_grps[] = { "i2s1_0_grp" , "i2s1_1_grp" };static const char * const i2s2_grps[] = { "i2s2_0_grp" , "i2s2_1_grp" ,"i2s2_2_grp" , "i2s2_3_grp" , "i2s2_4_grp" };static const char * const spdif_grps[] = { "spdif_grp" };static const char * const pwm0_grps[] = { "pwm0_grp" };static const char * const pwm1_grps[] = { "pwm1_grp" };static const char * const pwm2_grps[] = { "pwm2_grp" };static const char * const pwm3_grps[] = { "pwm3_grp" };static const char * const pwm4_grps[] = { "pwm4_grp" };static const char * const pwm5_grps[] = { "pwm5_grp" };static const char * const key_grps[] = { "key0_grp" , "key1_grp" , "key2_grp" ,"key3_grp" , "key4_grp" , "key5_grp" , "key6_grp" , "key7_grp" , "key8_grp" ,"key9_grp" , "key10_grp" , "key11_grp" , "key12_grp" , "key13_grp" ,"key14_grp" , "key15_grp" };static const char * const audio_dte_grps[] = { "audio_dte0_grp" ,"audio_dte1_grp" , "audio_dte2_grp" , "audio_dte3_grp" };static const char * const smart_card0_grps[] = { "smart_card0_grp" ,"smart_card0_fcb_grp" };static const char * const smart_card1_grps[] = { "smart_card1_grp" ,"smart_card1_fcb_grp" };static const char * const spi0_grps[] = { "spi0_grp" };static const char * const spi1_grps[] = { "spi1_grp" };static const char * const spi2_grps[] = { "spi2_grp" };static const char * const spi3_grps[] = { "spi3_grp" };static const char * const spi4_grps[] = { "spi4_0_grp" , "spi4_1_grp" };static const char * const spi5_grps[] = { "spi5_grp" };static const char * const sw_led0_grps[] = { "sw_led0_0_grp" ,"sw_led0_1_grp" };static const char * const sw_led1_grps[] = { "sw_led1_grp" };static const char * const sw_led2_grps[] = { "sw_led2_0_grp" ,"sw_led2_1_grp" };static const char * const d1w_grps[] = { "d1w_grp" };static const char * const lcd_grps[] = { "lcd_grp" };static const char * const sram_grps[] = { "sram_0_grp" , "sram_1_grp" };static const char * const uart0_grps[] = { "uart0_grp" };static const char * const uart1_grps[] = { "uart1_grp" , "uart1_dte_grp" };static const char * const uart2_grps[] = { "uart2_grp" };static const char * const uart3_grps[] = { "uart3_grp" };static const char * const uart4_grps[] = { "uart4_grp" };static const char * const qspi_grps[] = { "qspi_0_grp" , "qspi_1_grp" };static const char * const nand_grps[] = { "nand_grp" };static const char * const sdio0_grps[] = { "sdio0_grp" , "sdio0_cd_grp" ,"sdio0_mmc_grp" };static const char * const sdio1_grps[] = { "sdio1_data_0_grp" ,"sdio1_data_1_grp" , "sdio1_cd_grp" , "sdio1_led_grp" , "sdio1_mmc_grp" };static const char * const can0_grps[] = { "can0_grp" };static const char * const can1_grps[] = { "can1_grp" };static const char * const cam_grps[] = { "cam_led_grp" , "cam_0_grp" ,"cam_1_grp" };static const char * const bsc1_grps[] = { "bsc1_grp" };static const char * const pcie_clkreq_grps[] = { "pcie_clkreq_grp" };static const char * const usb0_oc_grps[] = { "usb0_oc_grp" };static const char * const usb1_oc_grps[] = { "usb1_oc_grp" };static const char * const usb2_oc_grps[] = { "usb2_oc_grp" };#define CYGNUS_PIN_FUNCTION(func) \#func , \## _grps, \## _grps), \/* * List of supported functions in Cygnus static const struct cygnus_pin_function cygnus_pin_functions[] = {static int cygnus_get_groups_count(struct pinctrl_dev *pctrl_dev)struct cygnus_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);return pinctrl->num_groups;static const char *cygnus_get_group_name(struct pinctrl_dev *pctrl_dev,unsigned selector)struct cygnus_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);return pinctrl->groups[selector].name;static int cygnus_get_group_pins(struct pinctrl_dev *pctrl_dev,unsigned selector, const unsigned **pins,unsigned *num_pins)struct cygnus_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);return 0 ;static void cygnus_pin_dbg_show(struct pinctrl_dev *pctrl_dev,struct seq_file *s, unsigned offset)" %s" , dev_name(pctrl_dev->dev));static const struct pinctrl_ops cygnus_pinctrl_ops = {static int cygnus_get_functions_count(struct pinctrl_dev *pctrl_dev)struct cygnus_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);return pinctrl->num_functions;static const char *cygnus_get_function_name(struct pinctrl_dev *pctrl_dev,unsigned selector)struct cygnus_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);return pinctrl->functions[selector].name;static int cygnus_get_function_groups(struct pinctrl_dev *pctrl_dev,unsigned selector,const char * const **groups,unsigned * const num_groups)struct cygnus_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);return 0 ;static int cygnus_pinmux_set(struct cygnus_pinctrl *pinctrl,const struct cygnus_pin_function *func,const struct cygnus_pin_group *grp,struct cygnus_mux_log *mux_log)const struct cygnus_mux *mux = &grp->mux;int i;0 x7;unsigned long flags;for (i = 0 ; i < CYGNUS_NUM_IOMUX; i++) {if (mux->offset != mux_log[i].mux.offset ||continue ;/* match found if we reach here */ /* if this is a new configuration, just do it! */ if (!mux_log[i].is_configured)break ;/* * IOMUX has been configured previously and one is trying to * configure it to a different function if (mux_log[i].mux.alt != mux->alt) {"double configuration error detected!\n" );"func:%s grp:%s\n" ,return -EINVAL;else {/* * One tries to configure it to the same function. * Just quit and don't bother return 0 ;true ;return 0 ;static int cygnus_pinmux_set_mux(struct pinctrl_dev *pctrl_dev,unsigned func_select, unsigned grp_select)struct cygnus_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);const struct cygnus_pin_function *func =const struct cygnus_pin_group *grp = &pinctrl->groups[grp_select];"func:%u name:%s grp:%u name:%s\n" ,"offset:0x%08x shift:%u alt:%u\n" ,return cygnus_pinmux_set(pinctrl, func, grp, pinctrl->mux_log);static int cygnus_gpio_request_enable(struct pinctrl_dev *pctrl_dev,struct pinctrl_gpio_range *range,unsigned pin)struct cygnus_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);const struct cygnus_gpio_mux *mux = pctrl_dev->desc->pins[pin].drv_data;unsigned long flags;/* not all pins support GPIO pinmux override */ if (!mux->is_supported)return -ENOTSUPP;0 x3 << mux->shift;"gpio request enable pin=%u offset=0x%x shift=%u\n" ,return 0 ;static void cygnus_gpio_disable_free(struct pinctrl_dev *pctrl_dev,struct pinctrl_gpio_range *range,unsigned pin)struct cygnus_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);struct cygnus_gpio_mux *mux = pctrl_dev->desc->pins[pin].drv_data;unsigned long flags;if (!mux->is_supported)return ;0 x3 << mux->shift);"gpio disable free pin=%u offset=0x%x shift=%u\n" ,static const struct pinmux_ops cygnus_pinmux_ops = {static struct pinctrl_desc cygnus_pinctrl_desc = {"cygnus-pinmux" ,static int cygnus_mux_log_init(struct cygnus_pinctrl *pinctrl)struct cygnus_mux_log *log;unsigned int i, j;sizeof (struct cygnus_mux_log),if (!pinctrl->mux_log)return -ENOMEM;for (i = 0 ; i < CYGNUS_NUM_IOMUX_REGS; i++) {for (j = 0 ; j < CYGNUS_NUM_MUX_PER_REG; j++) {4 ;4 ;0 ;false ;return 0 ;static int cygnus_pinmux_probe(struct platform_device *pdev)struct cygnus_pinctrl *pinctrl;int i, ret;struct pinctrl_pin_desc *pins;sizeof (*pinctrl), GFP_KERNEL);if (!pinctrl)return -ENOMEM;0 );if (IS_ERR(pinctrl->base0)) {"unable to map I/O space\n" );return PTR_ERR(pinctrl->base0);1 );if (IS_ERR(pinctrl->base1)) {"unable to map I/O space\n" );return PTR_ERR(pinctrl->base1);if (ret) {"unable to initialize IOMUX log\n" );return ret;sizeof (*pins),if (!pins)return -ENOMEM;for (i = 0 ; i < ARRAY_SIZE(cygnus_pins); i++) {if (IS_ERR(pinctrl->pctl)) {"unable to register Cygnus IOMUX pinctrl\n" );return PTR_ERR(pinctrl->pctl);return 0 ;static const struct of_device_id cygnus_pinmux_of_match[] = {"brcm,cygnus-pinmux" },static struct platform_driver cygnus_pinmux_driver = {"cygnus-pinmux" ,true ,static int __init cygnus_pinmux_init(void )return platform_driver_register(&cygnus_pinmux_driver);
Messung V0.5 in Prozent C=97 H=94 G=95
¤ Dauer der Verarbeitung: 0.18 Sekunden
(vorverarbeitet am 2026-06-06)
¤ *© Formatika GbR, Deutschland
