// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Rockchip MIPI Synopsys DPHY RX0 driver * * Copyright ( C ) 2019 Collabora , Ltd . * * Based on : * * drivers / media / platform / rockchip / isp1 / mipi_dphy_sy . c * in https : //chromium.googlesource.com/chromiumos/third_party/kernel, * chromeos - 4 . 4 branch . * * Copyright ( C ) 2017 Fuzhou Rockchip Electronics Co . , Ltd . * Jacob Chen < jacob2 . chen @ rock - chips . com > * Shunqian Zheng < zhengsq @ rock - chips . com > #include <linux/clk.h>#include <linux/delay.h>#include <linux/io.h>#include <linux/mfd/syscon.h>#include <linux/module.h>#include <linux/of.h>#include <linux/phy/phy.h>#include <linux/phy/phy-mipi-dphy.h>#include <linux/platform_device.h>#include <linux/regmap.h>#define RK3399_GRF_SOC_CON9 0 x6224#define RK3399_GRF_SOC_CON21 0 x6254#define RK3399_GRF_SOC_CON22 0 x6258#define RK3399_GRF_SOC_CON23 0 x625c#define RK3399_GRF_SOC_CON24 0 x6260#define RK3399_GRF_SOC_CON25 0 x6264#define RK3399_GRF_SOC_STATUS1 0 xe2a4#define CLOCK_LANE_HS_RX_CONTROL 0 x34#define LANE0_HS_RX_CONTROL 0 x44#define LANE1_HS_RX_CONTROL 0 x54#define LANE2_HS_RX_CONTROL 0 x84#define LANE3_HS_RX_CONTROL 0 x94#define LANES_THS_SETTLE_CONTROL 0 x75#define THS_SETTLE_COUNTER_THRESHOLD 0 x04struct hsfreq_range {static const struct hsfreq_range rk3399_mipidphy_hsfreq_ranges[] = {89 , 0 x00 }, { 99 , 0 x10 }, { 109 , 0 x20 }, { 129 , 0 x01 },139 , 0 x11 }, { 149 , 0 x21 }, { 169 , 0 x02 }, { 179 , 0 x12 },199 , 0 x22 }, { 219 , 0 x03 }, { 239 , 0 x13 }, { 249 , 0 x23 },269 , 0 x04 }, { 299 , 0 x14 }, { 329 , 0 x05 }, { 359 , 0 x15 },399 , 0 x25 }, { 449 , 0 x06 }, { 499 , 0 x16 }, { 549 , 0 x07 },599 , 0 x17 }, { 649 , 0 x08 }, { 699 , 0 x18 }, { 749 , 0 x09 },799 , 0 x19 }, { 849 , 0 x29 }, { 899 , 0 x39 }, { 949 , 0 x0a },999 , 0 x1a }, { 1049 , 0 x2a }, { 1099 , 0 x3a }, { 1149 , 0 x0b },1199 , 0 x1b }, { 1249 , 0 x2b }, { 1299 , 0 x3b }, { 1349 , 0 x0c },1399 , 0 x1c }, { 1449 , 0 x2c }, { 1500 , 0 x3c }static const char * const rk3399_mipidphy_clks[] = {"dphy-ref" ,"dphy-cfg" ,"grf" ,enum dphy_reg_id {0 ,/* rk3288 only */ /* below is for rk3399 only */ struct dphy_reg {#define PHY_REG(_offset, _width, _shift) \1 , .shift = _shift, }static const struct dphy_reg rk3399_grf_dphy_regs[] = {4 , 0 ),1 , 10 ),1 , 11 ),4 , 0 ),4 , 4 ),4 , 8 ),4 , 12 ),4 , 0 ),4 , 4 ),4 , 8 ),4 , 12 ),4 , 0 ),4 , 4 ),4 , 8 ),4 , 12 ),4 , 0 ),1 , 4 ),1 , 5 ),1 , 6 ),1 , 7 ),8 , 0 ),1 , 8 ),1 , 9 ),1 , 10 ),8 , 0 ),struct rk_dphy_drv_data {const char * const *clks;unsigned int num_clks;const struct hsfreq_range *hsfreq_ranges;unsigned int num_hsfreq_ranges;const struct dphy_reg *regs;struct rk_dphy {struct device *dev;struct regmap *grf;struct clk_bulk_data *clks;const struct rk_dphy_drv_data *drv_data;struct phy_configure_opts_mipi_dphy config;static inline void rk_dphy_write_grf(struct rk_dphy *priv,unsigned int index, u8 value)const struct dphy_reg *reg = &priv->drv_data->regs[index];/* Update high word */ unsigned int val = (value << reg->shift) |16 ));if (WARN_ON(!reg->offset))return ;static void rk_dphy_write(struct rk_dphy *priv, u8 test_code, u8 test_data)1 );/* * With the falling edge on TESTCLK , the TESTDIN [ 7 : 0 ] signal content * is latched internally as the current test code . Test data is * programmed internally by rising edge on TESTCLK . * This code assumes that TESTCLK is already 1 . 0 );0 );1 );static void rk_dphy_enable(struct rk_dphy *priv)0 );0 );/* Disable lane turn around, which is ignored in receive mode */ 0 );0 xf);1 , 0 ));/* dphy start */ 1 );1 );100 , 150 );0 );100 , 150 );/* set clock lane */ /* HS hsfreq_range & lane 0 settle bypass */ 0 );/* HS RX Control of lane0 */ 1 );/* HS RX Control of lane1 */ 1 );/* HS RX Control of lane2 */ 1 );/* HS RX Control of lane3 */ 1 );/* HS RX Data Lanes Settle State Time Control */ /* Normal operation */ 0 x0, 0 );static int rk_dphy_configure(struct phy *phy, union phy_configure_opts *opts)struct rk_dphy *priv = phy_get_drvdata(phy);const struct rk_dphy_drv_data *drv_data = priv->drv_data;struct phy_configure_opts_mipi_dphy *config = &opts->mipi_dphy;unsigned int hsfreq = 0 ;unsigned int i;int ret;/* pass with phy_mipi_dphy_get_default_config (with pixel rate?) */ if (ret)return ret;1000 * 1000 );"lanes %d - data_rate_mbps %llu\n" ,for (i = 0 ; i < drv_data->num_hsfreq_ranges; i++) {if (drv_data->hsfreq_ranges[i].range_h >= data_rate_mbps) {break ;if (!hsfreq)return -EINVAL;return 0 ;static int rk_dphy_power_on(struct phy *phy)struct rk_dphy *priv = phy_get_drvdata(phy);int ret;if (ret)return ret;return 0 ;static int rk_dphy_power_off(struct phy *phy)struct rk_dphy *priv = phy_get_drvdata(phy);0 );return 0 ;static int rk_dphy_init(struct phy *phy)struct rk_dphy *priv = phy_get_drvdata(phy);return clk_bulk_prepare(priv->drv_data->num_clks, priv->clks);static int rk_dphy_exit(struct phy *phy)struct rk_dphy *priv = phy_get_drvdata(phy);return 0 ;static const struct phy_ops rk_dphy_ops = {exit = rk_dphy_exit,static const struct rk_dphy_drv_data rk3399_mipidphy_drv_data = {static const struct of_device_id rk_dphy_dt_ids[] = {"rockchip,rk3399-mipi-dphy-rx0" ,static int rk_dphy_probe(struct platform_device *pdev)struct device *dev = &pdev->dev;struct device_node *np = dev->of_node;const struct rk_dphy_drv_data *drv_data;struct phy_provider *phy_provider;struct rk_dphy *priv;struct phy *phy;unsigned int i;int ret;if (!dev->parent || !dev->parent->of_node)return -ENODEV;sizeof (*priv), GFP_KERNEL);if (!priv)return -ENOMEM;if (IS_ERR(priv->grf)) {"Can't find GRF syscon\n" );return -ENODEV;sizeof (*priv->clks), GFP_KERNEL);if (!priv->clks)return -ENOMEM;for (i = 0 ; i < drv_data->num_clks; i++)if (ret)return ret;if (IS_ERR(phy)) {"failed to create phy\n" );return PTR_ERR(phy);return PTR_ERR_OR_ZERO(phy_provider);static struct platform_driver rk_dphy_driver = {"rockchip-mipi-dphy-rx0" ,"Ezequiel Garcia <ezequiel@collabora.com>" );"Rockchip MIPI Synopsys DPHY RX0 driver" );"Dual MIT/GPL" );
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