/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2023, Linaro Limited
*/
#ifndef QCOM_PHY_QMP_QSERDES_COM_V7_H_
#define QCOM_PHY_QMP_QSERDES_COM_V7_H_
/* Only for QMP V7 PHY - QSERDES COM registers */
#define QSERDES_V7_COM_SSC_STEP_SIZE1_MODE1 0 x00
#define QSERDES_V7_COM_SSC_STEP_SIZE2_MODE1 0 x04
#define QSERDES_V7_COM_CP_CTRL_MODE1 0 x10
#define QSERDES_V7_COM_PLL_RCTRL_MODE1 0 x14
#define QSERDES_V7_COM_PLL_CCTRL_MODE1 0 x18
#define QSERDES_V7_COM_CORECLK_DIV_MODE1 0 x1c
#define QSERDES_V7_COM_LOCK_CMP1_MODE1 0 x20
#define QSERDES_V7_COM_LOCK_CMP2_MODE1 0 x24
#define QSERDES_V7_COM_DEC_START_MODE1 0 x28
#define QSERDES_V7_COM_DEC_START_MSB_MODE1 0 x2c
#define QSERDES_V7_COM_DIV_FRAC_START1_MODE1 0 x30
#define QSERDES_V7_COM_DIV_FRAC_START2_MODE1 0 x34
#define QSERDES_V7_COM_DIV_FRAC_START3_MODE1 0 x38
#define QSERDES_V7_COM_HSCLK_SEL_1 0 x3c
#define QSERDES_V7_COM_INTEGLOOP_GAIN0_MODE1 0 x40
#define QSERDES_V7_COM_INTEGLOOP_GAIN1_MODE1 0 x44
#define QSERDES_V7_COM_VCO_TUNE1_MODE1 0 x48
#define QSERDES_V7_COM_VCO_TUNE2_MODE1 0 x4c
#define QSERDES_V7_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0 x50
#define QSERDES_V7_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0 x54
#define QSERDES_V7_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0 x58
#define QSERDES_V7_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0 x5c
#define QSERDES_V7_COM_SSC_STEP_SIZE1_MODE0 0 x60
#define QSERDES_V7_COM_SSC_STEP_SIZE2_MODE0 0 x64
#define QSERDES_V7_COM_CP_CTRL_MODE0 0 x70
#define QSERDES_V7_COM_PLL_RCTRL_MODE0 0 x74
#define QSERDES_V7_COM_PLL_CCTRL_MODE0 0 x78
#define QSERDES_V7_COM_PLL_CORE_CLK_DIV_MODE0 0 x7c
#define QSERDES_V7_COM_LOCK_CMP1_MODE0 0 x80
#define QSERDES_V7_COM_LOCK_CMP2_MODE0 0 x84
#define QSERDES_V7_COM_DEC_START_MODE0 0 x88
#define QSERDES_V7_COM_DEC_START_MSB_MODE0 0 x8c
#define QSERDES_V7_COM_DIV_FRAC_START1_MODE0 0 x90
#define QSERDES_V7_COM_DIV_FRAC_START2_MODE0 0 x94
#define QSERDES_V7_COM_DIV_FRAC_START3_MODE0 0 x98
#define QSERDES_V7_COM_HSCLK_HS_SWITCH_SEL_1 0 x9c
#define QSERDES_V7_COM_INTEGLOOP_GAIN0_MODE0 0 xa0
#define QSERDES_V7_COM_INTEGLOOP_GAIN1_MODE0 0 xa4
#define QSERDES_V7_COM_VCO_TUNE1_MODE0 0 xa8
#define QSERDES_V7_COM_VCO_TUNE2_MODE0 0 xac
#define QSERDES_V7_COM_BG_TIMER 0 xbc
#define QSERDES_V7_COM_SSC_EN_CENTER 0 xc0
#define QSERDES_V7_COM_SSC_ADJ_PER1 0 xc4
#define QSERDES_V7_COM_SSC_PER1 0 xcc
#define QSERDES_V7_COM_SSC_PER2 0 xd0
#define QSERDES_V7_COM_PLL_POST_DIV_MUX 0 xd8
#define QSERDES_V7_COM_PLL_BIAS_EN_CLK_BUFLR_EN 0 xdc
#define QSERDES_V7_COM_CLK_ENABLE1 0 xe0
#define QSERDES_V7_COM_SYS_CLK_CTRL 0 xe4
#define QSERDES_V7_COM_SYSCLK_BUF_ENABLE 0 xe8
#define QSERDES_V7_COM_PLL_IVCO 0 xf4
#define QSERDES_V7_COM_PLL_IVCO_MODE1 0 xf8
#define QSERDES_V7_COM_SYSCLK_EN_SEL 0 x110
#define QSERDES_V7_COM_RESETSM_CNTRL 0 x118
#define QSERDES_V7_COM_LOCK_CMP_EN 0 x120
#define QSERDES_V7_COM_LOCK_CMP_CFG 0 x124
#define QSERDES_V7_COM_VCO_TUNE_CTRL 0 x13c
#define QSERDES_V7_COM_VCO_TUNE_MAP 0 x140
#define QSERDES_V7_COM_VCO_TUNE_INITVAL2 0 x148
#define QSERDES_V7_COM_VCO_TUNE_MAXVAL2 0 x158
#define QSERDES_V7_COM_CLK_SELECT 0 x164
#define QSERDES_V7_COM_CORE_CLK_EN 0 x170
#define QSERDES_V7_COM_CMN_CONFIG_1 0 x174
#define QSERDES_V7_COM_SVS_MODE_CLK_SEL 0 x17c
#define QSERDES_V7_COM_CMN_MISC_1 0 x184
#define QSERDES_V7_COM_CMN_MODE 0 x188
#define QSERDES_V7_COM_PLL_VCO_DC_LEVEL_CTRL 0 x198
#define QSERDES_V7_COM_AUTO_GAIN_ADJ_CTRL_1 0 x1a4
#define QSERDES_V7_COM_AUTO_GAIN_ADJ_CTRL_2 0 x1a8
#define QSERDES_V7_COM_AUTO_GAIN_ADJ_CTRL_3 0 x1ac
#define QSERDES_V7_COM_ADDITIONAL_MISC 0 x1b4
#define QSERDES_V7_COM_ADDITIONAL_MISC_2 0 x1b8
#define QSERDES_V7_COM_ADDITIONAL_MISC_3 0 x1bc
#define QSERDES_V7_COM_CMN_STATUS 0 x1d0
#define QSERDES_V7_COM_C_READY_STATUS 0 x1f8
#endif
Messung V0.5 in Prozent C=96 H=94 G=94
¤ Dauer der Verarbeitung: 0.0 Sekunden
(vorverarbeitet am 2026-06-07)
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