// SPDX-License-Identifier: GPL-2.0-or-later /* Microchip Sparx5 Switch SerDes driver * * Copyright ( c ) 2020 Microchip Technology Inc . and its subsidiaries . * * The Sparx5 Chip Register Model can be browsed at this location : * https : //github.com/microchip-ung/sparx-5_reginfo * and the datasheet is available here : * https : //ww1.microchip.com/downloads/en/DeviceDoc/SparX-5_Family_L2L3_Enterprise_10G_Ethernet_Switches_Datasheet_00003822B.pdf #include <linux/printk.h>#include <linux/module.h>#include <linux/device.h>#include <linux/netdevice.h>#include <linux/platform_device.h>#include <linux/of.h>#include <linux/io.h>#include <linux/clk.h>#include <linux/phy.h>#include <linux/phy/phy.h>#include "sparx5_serdes.h" #define SPX5_SERDES_10G_START 13 #define SPX5_SERDES_25G_START 25 #define SPX5_SERDES_6G10G_CNT SPX5_SERDES_25G_START#define LAN969X_SERDES_10G_CNT 10 /* Optimal power settings from GUC */ #define SPX5_SERDES_QUIET_MODE_VAL 0 x01ef4e0c/* Register target sizes */ const unsigned int sparx5_serdes_tsize[TSIZE_LAST] = {12 ,14 ,14 ,25 ,const unsigned int lan969x_serdes_tsize[TSIZE_LAST] = {10 ,6 ,6 ,10 ,/* Pointer to the register target size table */ const unsigned int *tsize;enum sparx5_sd25g28_mode_preset_type {enum sparx5_sd10g28_mode_preset_type {struct sparx5_serdes_io_resource {enum sparx5_serdes_target id;struct sparx5_sd25g28_mode_preset {bool txmargin;struct sparx5_sd25g28_media_preset {struct sparx5_sd25g28_args {/* UDL if-width: 10/16/20/32/64 */ bool skip_cmu_cfg:1 ; /* Enable/disable CMU cfg */ enum sparx5_10g28cmu_mode cmu_sel; /* Device/Mode serdes uses */ bool no_pwrcycle:1 ; /* Omit initial power-cycle */ bool txinvert:1 ; /* Enable inversion of output data */ bool rxinvert:1 ; /* Enable inversion of input data */ /* Set output level */ /* Rate of network interface */ /* Set output level to half/full */ bool mute:1 ; /* Mute Output Buffer */ bool reg_rst:1 ;struct sparx5_sd25g28_params {struct sparx5_sd10g28_media_preset {struct sparx5_sd10g28_mode_preset {/* interface width: 10/16/20/32/64 */ enum sparx5_10g28cmu_mode cmu_sel; /* Device/Mode serdes uses */ /* Rate of network interface */ /* Set output level to half/full */ struct sparx5_sd10g28_args {bool skip_cmu_cfg:1 ; /* Enable/disable CMU cfg */ bool no_pwrcycle:1 ; /* Omit initial power-cycle */ bool txinvert:1 ; /* Enable inversion of output data */ bool rxinvert:1 ; /* Enable inversion of input data */ bool txmargin:1 ; /* Set output level to half/full */ /* Set output level */ bool mute:1 ; /* Mute Output Buffer */ bool is_6g:1 ;bool reg_rst:1 ;struct sparx5_sd10g28_params {2 ];static struct sparx5_sd25g28_media_preset media_presets_25g[] = {/* ETH_MEDIA_DEFAULT */ 0 ,1 ,0 ,0 ,1 ,0 ,0 xf,4 ,12 ,7 ,/* ETH_MEDIA_SR */ 1 ,1 ,1 ,0 ,1 ,0 x10,0 xf,8 ,4 ,0 ,/* ETH_MEDIA_DAC */ 0 ,1 ,0 ,0 ,1 ,0 ,0 xf,8 ,0 xc,0 ,static struct sparx5_sd25g28_mode_preset mode_presets_25g[] = {/* SPX5_SD25G28_MODE_PRESET_25000 */ 40 ,0 ,0 ,1 ,0 ,15 ,3 ,0 ,0 ,0 x26 << 1 ),0 xf0,0 ,0 xcc,0 xfe,3 ,0 ,1 ,0 x1f,1 ,1 ,1 ,0 ,8 ,0 xc,/* SPX5_SD25G28_MODE_PRESET_10000 */ 64 ,0 ,2 ,0 ,1 ,9 ,0 ,0 ,1 ,0 x20 << 1 ),0 x40,0 ,0 x4c,0 x44,3 ,0 ,3 ,1 ,0 x1f,0 ,1 ,1 ,0 ,0 ,/* SPX5_SD25G28_MODE_PRESET_5000 */ 64 ,0 ,2 ,0 ,2 ,9 ,0 ,0 ,1 ,0 x20 << 1 ),0 ,0 ,0 xe,0 x80,0 ,0 ,6 ,0 ,0 ,0 ,0 ,/* SPX5_SD25G28_MODE_PRESET_SD_2G5 */ 10 ,0 ,0 ,0 ,1 ,6 ,3 ,2 ,1 ,0 x26 << 1 ),0 xf << 4 ),2 ,0 x8,0 x8a,0 ,0 ,1 << 2 ),0 ,0 ,0 ,0 ,/* SPX5_SD25G28_MODE_PRESET_1000BASEX */ 10 ,0 ,1 ,0 ,1 ,8 ,3 ,3 ,1 ,0 x26 << 1 ),0 xf0,0 ,0 x8,0 xce,0 ,0 ,0 ,0 ,0 ,0 ,0 ,static struct sparx5_sd10g28_media_preset media_presets_10g[] = {/* ETH_MEDIA_DEFAULT */ 0 ,1 ,0 ,0 ,1 ,0 ,5 ,0 ,0 xa,1 ,0 x8,0 x3,/* ETH_MEDIA_SR */ 1 ,1 ,1 ,0 ,1 ,0 xc,0 xa,0 x4,0 xa,1 ,0 xF,0 x3,/* ETH_MEDIA_DAC */ 1 ,1 ,1 ,12 ,1 ,8 ,0 xa,4 ,0 xa,1 ,0 xf,0 x0,static struct sparx5_sd10g28_mode_preset mode_presets_10g[] = {/* SPX5_SD10G28_MODE_PRESET_10000 */ 64 ,0 x0,1 ,0 x1f,0 x0,0 x2,/* SPX5_SD10G28_MODE_PRESET_SFI_5000_6G */ 16 ,0 x1,0 ,0 ,0 x5,0 x0,/* SPX5_SD10G28_MODE_PRESET_SFI_5000_10G */ 64 ,0 x1,0 ,0 ,0 x5,0 x0,/* SPX5_SD10G28_MODE_PRESET_QSGMII */ 20 ,0 x1,0 ,0 ,0 x5,0 x0,/* SPX5_SD10G28_MODE_PRESET_SD_2G5 */ 10 ,0 x2,0 ,0 ,0 x7,0 x0,/* SPX5_SD10G28_MODE_PRESET_1000BASEX */ 10 ,0 x3,0 ,0 ,0 x7,0 x0,/* map from SD25G28 interface width to configuration value */ static u8 sd25g28_get_iw_setting(struct device *dev, const u8 interface_width)switch (interface_width) {case 10 : return 0 ;case 16 : return 1 ;case 32 : return 3 ;case 40 : return 4 ;case 64 : return 5 ;default :"%s: Illegal value %d for interface width\n" ,return 0 ;/* map from SD10G28 interface width to configuration value */ static u8 sd10g28_get_iw_setting(struct device *dev, const u8 interface_width)switch (interface_width) {case 10 : return 0 ;case 16 : return 1 ;case 20 : return 2 ;case 32 : return 3 ;case 40 : return 4 ;case 64 : return 7 ;default :"%s: Illegal value %d for interface width\n" , __func__,return 0 ;static int sparx5_sd10g25_get_mode_preset(struct sparx5_serdes_macro *macro,struct sparx5_sd25g28_mode_preset *mode)switch (macro->serdesmode) {case SPX5_SD_MODE_SFI:if (macro->speed == SPEED_25000)else if (macro->speed == SPEED_10000)else if (macro->speed == SPEED_5000)break ;case SPX5_SD_MODE_2G5:break ;case SPX5_SD_MODE_1000BASEX:break ;case SPX5_SD_MODE_100FX:/* Not supported */ return -EINVAL;default :break ;return 0 ;static int sparx5_sd10g28_get_mode_preset(struct sparx5_serdes_macro *macro,struct sparx5_sd10g28_mode_preset *mode,struct sparx5_sd10g28_args *args)switch (macro->serdesmode) {case SPX5_SD_MODE_SFI:if (macro->speed == SPEED_10000) {else if (macro->speed == SPEED_5000) {if (args->is_6g)else else {"%s: Illegal speed: %02u, sidx: %02u, mode (%u)" ,return -EINVAL;break ;case SPX5_SD_MODE_QSGMII:break ;case SPX5_SD_MODE_2G5:break ;case SPX5_SD_MODE_100FX:case SPX5_SD_MODE_1000BASEX:break ;default :break ;return 0 ;static void sparx5_sd25g28_get_params(struct sparx5_serdes_macro *macro,struct sparx5_sd25g28_media_preset *media,struct sparx5_sd25g28_mode_preset *mode,struct sparx5_sd25g28_args *args,struct sparx5_sd25g28_params *params)struct sparx5_sd25g28_params init = {0 ,0 ,1 ,1 ? 0 : 1 ,1 ,0 ,1 ,1 ? 0 : 1 ,1 ,0 ,1 ,0 ,0 ,0 ,0 ,1 ,1 ,0 ,1 ,1 ,0 ,0 ,0 ,0 ,1 ,0 ,0 ,2 ,4 ,0 ,1 ,6 ,0 ,1 ,0 xbf,0 x61,0 ,0 ,0 ,1 ,1 ,1 ,1 ,1 ,6 ,9 ,6 ,0 ,1 ,1 ,1 ,1 ,0 ,0 ,0 ,0 ,static void sparx5_sd10g28_get_params(struct sparx5_serdes_macro *macro,struct sparx5_sd10g28_media_preset *media,struct sparx5_sd10g28_mode_preset *mode,struct sparx5_sd10g28_args *args,struct sparx5_sd10g28_params *params)struct sparx5_sd10g28_params init = {2 ) << 6 ,2 ),0 ,0 ,1 ,1 ) ? 0 : 1 ,1 ) ? 0 : 1 ,1 ,0 ,1 ,0 ,0 ,0 ,0 ,1 ,0 ,0 ,0 ,0 ,1 ,1 ,0 ,0 ,6 ),63 ),0 x1,0 x0,0 x0,1 << 5 ),0 << 6 ),1 << 7 ) + 9 ,1 ,1 ,1 ,1 ,4 ,3 ,0 ,1 ,3 ,0 ,0 ,2 ,2 ,2 ,0 ,1 ,0 ,0 ] = 0 ,1 ] = 1 ,0 ,15 ,32 ,6 ,1 ,0 ,0 ,0 ,0 ,static int sparx5_cmu_apply_cfg(struct sparx5_serdes_private *priv,void __iomem *cmu_tgt,void __iomem *cmu_cfg_tgt,void __iomem **regs = priv->regs;struct device *dev = priv->dev;int value;if (cmu_idx == 1 || cmu_idx == 4 || cmu_idx == 7 ||10 || cmu_idx == 13 ) {0 ;1 ),0 ),1 ),0 x1) |0 x1) |0 x1) |0 x1) |0 x0),0 ),0 ),0 x1),1 ),3 ),3 ),1 ),0 ),20 );0 ),1 ),20 );if (value) {"CMU PLL Loss of Lock: 0x%x\n" , value);return -EINVAL;0 ),return 0 ;static int sparx5_cmu_cfg(struct sparx5_serdes_private *priv, u32 cmu_idx)void __iomem *cmu_tgt, *cmu_cfg_tgt;1 ;if (cmu_idx == 1 || cmu_idx == 4 || cmu_idx == 7 ||10 || cmu_idx == 13 ) {0 ;return sparx5_cmu_apply_cfg(priv, cmu_idx, cmu_tgt, cmu_cfg_tgt, spd10g);/* Map of 6G/10G serdes mode and index to CMU index. */ static const int 2 , 2 , 2 , 2 , 2 ,2 , 2 , 2 , 5 , 5 ,5 , 5 , 5 , 5 , 5 ,5 , 8 , 11 , 11 , 11 ,11 , 11 , 11 , 11 , 11 },0 , 0 , 3 , 3 , 3 ,3 , 3 , 3 , 3 , 3 ,6 , 6 , 6 , 6 , 6 ,6 , 6 , 9 , 9 , 12 ,12 , 12 , 12 , 12 , 12 },1 , 1 , 1 , 1 , 4 ,4 , 4 , 4 , 4 , 4 ,4 , 4 , 7 , 7 , 7 ,7 , 7 , 10 , 10 , 10 ,10 , 13 , 13 , 13 , 13 },1 , 1 , 1 , 1 , 4 ,4 , 4 , 4 , 4 , 4 ,4 , 4 , 7 , 7 , 7 ,7 , 7 , 10 , 10 , 10 ,10 , 13 , 13 , 13 , 13 },/* Get the index of the CMU which provides the clock for the specified serdes * mode and index . static int sparx5_serdes_cmu_get(enum sparx5_10g28cmu_mode mode, int sd_index)return sparx5_serdes_cmu_map[mode][sd_index];/* Map of 6G/10G serdes mode and index to CMU index. */ static const int 2 , 2 , 2 , 2 , 2 ,2 , 2 , 2 , 5 , 5 },0 , 0 , 3 , 3 , 3 ,3 , 3 , 3 , 3 , 3 },1 , 1 , 1 , 1 , 4 ,4 , 4 , 4 , 4 , 4 },1 , 1 , 1 , 1 , 4 ,4 , 4 , 4 , 4 , 4 },static int lan969x_serdes_cmu_get(enum sparx5_10g28cmu_mode mode, int sd_index)return lan969x_serdes_cmu_map[mode][sd_index];static void sparx5_serdes_cmu_power_off(struct sparx5_serdes_private *priv)void __iomem *cmu_inst, *cmu_cfg_inst;int i;/* Power down each CMU */ for (i = 0 ; i < priv->data->consts.cmu_max; i++) {0 ),0 ));0 ),0 ));0 ),0 ));1 ),0 ));0 ),0 ));1 ),0 ));1 ) |1 ) |1 ),0 ));1 ),0 ));static void sparx5_sd25g28_reset(void __iomem *regs[],struct sparx5_sd25g28_params *params,if (params->reg_rst == 1 ) {1 ),1000 , 2000 );0 ),static int sparx5_sd25g28_apply_params(struct sparx5_serdes_macro *macro,struct sparx5_sd25g28_params *params)struct sparx5_serdes_private *priv = macro->priv;void __iomem **regs = priv->regs;struct device *dev = priv->dev;1 ),0 xFF),0 ),1 ),0 ),1 ),0 ),1 ),0 x00),0 ),1 ),0 ),0 ),1000 , 2000 );1 ),10000 , 20000 );0 xff),if (value) {"25G PLL Loss of Lock: 0x%x\n" , value);return -EINVAL;if (value != 0 x1) {"25G PMA Reset failed: 0x%x\n" , value);return -EINVAL;0 x1),0 x0),0 x0),0 ),0 ),0 ),return 0 ;static void sparx5_sd10g28_reset(void __iomem *regs[], u32 lane_index)/* Note: SerDes SD10G_LANE_1 is configured in 10G_LAN mode */ 1 ),1000 , 2000 );0 ),static int sparx5_sd10g28_apply_params(struct sparx5_serdes_macro *macro,struct sparx5_sd10g28_params *params)struct sparx5_serdes_private *priv = macro->priv;void __iomem **regs = priv->regs;struct device *dev = priv->dev;void __iomem *sd_inst;int err;/* Do not configure serdes if CMU is not to be configured too */ if (params->skip_cmu_cfg)return 0 ;if (err)return err;if (params->is_6g)else 1 ),0 x0) |0 x1) |0 x1) |0 x1) |0 x0),0 x1) |0 x1) |0 x1) |0 x1),0 x1),0 x0) |0 x0) |0 x1),0 ]),1 ]),0 ),1 ),1 ),3000 , 6000 );if (value != 1 ) {"10G PMA Reset failed: 0x%x\n" , value);return -EINVAL;0 x0),0 x0),return 0 ;static int sparx5_sd25g28_config(struct sparx5_serdes_macro *macro, bool reset)struct sparx5_sd25g28_media_preset media = media_presets_25g[macro->media];struct sparx5_sd25g28_mode_preset mode;struct sparx5_sd25g28_args args = {1 ,0 ,240 ,0 xf,struct sparx5_sd25g28_params params;int err;if (err)return err;return sparx5_sd25g28_apply_params(macro, ¶ms);static int sparx5_sd10g28_config(struct sparx5_serdes_macro *macro, bool reset)struct sparx5_sd10g28_media_preset media = media_presets_10g[macro->media];struct sparx5_sd10g28_mode_preset mode;struct sparx5_sd10g28_params params;struct sparx5_sd10g28_args args = {0 ,1 ,240 ,int err;if (err)return err;return sparx5_sd10g28_apply_params(macro, ¶ms);/* Power down serdes TX driver */ static int sparx5_serdes_power_save(struct sparx5_serdes_macro *macro, u32 pwdn)struct sparx5_serdes_private *priv = macro->priv;void __iomem *sd_inst, *sd_lane_inst;if (macro->serdestype == SPX5_SDT_6G)else if (macro->serdestype == SPX5_SDT_10G)else if (macro->serdestype == SPX5_SDT_25G) {/* Take serdes out of reset */ 0 ),0 ));/* Configure optimal settings for quiet mode */ L),0 ));0 ));else {/* 6G and 10G */ /* Take serdes out of reset */ 0 ),0 ));/* Configure optimal settings for quiet mode */ 0 ));0 ));return 0 ;static int sparx5_serdes_clock_config(struct sparx5_serdes_macro *macro)struct sparx5_serdes_private *priv = macro->priv;/* Clock is auto-detected in 100Base-FX mode on lan969x */ if (priv->data->type == SPX5_TARGET_LAN969X)return 0 ;if (macro->serdesmode == SPX5_SD_MODE_100FX) {250000000 ? 2 :500000000 ? 1 : 0 ;return 0 ;static int sparx5_serdes_get_serdesmode(phy_interface_t portmode, int speed)switch (portmode) {case PHY_INTERFACE_MODE_1000BASEX:case PHY_INTERFACE_MODE_2500BASEX:if (speed == SPEED_2500)return SPX5_SD_MODE_2G5;if (speed == SPEED_100)return SPX5_SD_MODE_100FX;return SPX5_SD_MODE_1000BASEX;case PHY_INTERFACE_MODE_SGMII:/* The same Serdes mode is used for both SGMII and 1000BaseX */ return SPX5_SD_MODE_1000BASEX;case PHY_INTERFACE_MODE_QSGMII:return SPX5_SD_MODE_QSGMII;case PHY_INTERFACE_MODE_10GBASER:return SPX5_SD_MODE_SFI;default :return -EINVAL;static int sparx5_serdes_config(struct sparx5_serdes_macro *macro)struct device *dev = macro->priv->dev;int serdesmode;int err;if (serdesmode < 0 ) {"SerDes %u, interface not supported: %s\n" ,return serdesmode;if (macro->serdestype == SPX5_SDT_25G)false );else false );if (err) {"SerDes %u, config error: %d\n" ,return err;static int sparx5_serdes_power_on(struct phy *phy)struct sparx5_serdes_macro *macro = phy_get_drvdata(phy);return sparx5_serdes_power_save(macro, false );static int sparx5_serdes_power_off(struct phy *phy)struct sparx5_serdes_macro *macro = phy_get_drvdata(phy);return sparx5_serdes_power_save(macro, true );static int sparx5_serdes_set_mode(struct phy *phy, enum phy_mode mode, int submode)struct sparx5_serdes_macro *macro;if (mode != PHY_MODE_ETHERNET)return -EINVAL;switch (submode) {case PHY_INTERFACE_MODE_1000BASEX:case PHY_INTERFACE_MODE_2500BASEX:case PHY_INTERFACE_MODE_SGMII:case PHY_INTERFACE_MODE_QSGMII:case PHY_INTERFACE_MODE_10GBASER:return 0 ;default :return -EINVAL;static int sparx5_serdes_set_media(struct phy *phy, enum phy_media media)struct sparx5_serdes_macro *macro = phy_get_drvdata(phy);if (media != macro->media) {if (macro->serdesmode != SPX5_SD_MODE_NONE)return 0 ;static int sparx5_serdes_set_speed(struct phy *phy, int speed)struct sparx5_serdes_macro *macro = phy_get_drvdata(phy);if (macro->priv->data->type == SPX5_TARGET_SPARX5) {if (macro->sidx < SPX5_SERDES_10G_START && speed > SPEED_5000)return -EINVAL;if (macro->sidx < SPX5_SERDES_25G_START && speed > SPEED_10000)return -EINVAL;if (speed != macro->speed) {if (macro->serdesmode != SPX5_SD_MODE_NONE)return 0 ;static int sparx5_serdes_reset(struct phy *phy)struct sparx5_serdes_macro *macro = phy_get_drvdata(phy);int err;if (macro->serdestype == SPX5_SDT_25G)true );else true );if (err) {"SerDes %u, reset error: %d\n" ,return err;static int sparx5_serdes_validate(struct phy *phy, enum phy_mode mode,int submode,union phy_configure_opts *opts)struct sparx5_serdes_macro *macro = phy_get_drvdata(phy);if (mode != PHY_MODE_ETHERNET)return -EINVAL;if (macro->speed == 0 )return -EINVAL;if (macro->priv->data->type == SPX5_TARGET_SPARX5) {if (macro->sidx < SPX5_SERDES_10G_START &&return -EINVAL;if (macro->sidx < SPX5_SERDES_25G_START &&return -EINVAL;switch (submode) {case PHY_INTERFACE_MODE_1000BASEX:if (macro->speed != SPEED_100 && /* This is for 100BASE-FX */ return -EINVAL;break ;case PHY_INTERFACE_MODE_SGMII:case PHY_INTERFACE_MODE_2500BASEX:case PHY_INTERFACE_MODE_QSGMII:if (macro->speed >= SPEED_5000)return -EINVAL;break ;case PHY_INTERFACE_MODE_10GBASER:if (macro->speed < SPEED_5000)return -EINVAL;break ;default :return -EINVAL;return 0 ;static const struct phy_ops sparx5_serdes_ops = {static void sparx5_serdes_type_set(struct sparx5_serdes_macro *macro, int sidx)if (sidx < SPX5_SERDES_10G_START) {else if (sidx < SPX5_SERDES_25G_START) {else {static void lan969x_serdes_type_set(struct sparx5_serdes_macro *macro, int sidx)static int sparx5_phy_create(struct sparx5_serdes_private *priv,int idx, struct phy **phy)struct sparx5_serdes_macro *macro;if (IS_ERR(*phy))return PTR_ERR(*phy);sizeof (*macro), GFP_KERNEL);if (!macro)return -ENOMEM;/* Power off serdes by default */ return 0 ;static struct sparx5_serdes_io_resource sparx5_serdes_iomap[] = {0 x0 }, /* 0x610808000: sd_cmu_0 */ 1 , 0 x8000 }, /* 0x610810000: sd_cmu_1 */ 2 , 0 x10000 }, /* 0x610818000: sd_cmu_2 */ 3 , 0 x18000 }, /* 0x610820000: sd_cmu_3 */ 4 , 0 x20000 }, /* 0x610828000: sd_cmu_4 */ 5 , 0 x28000 }, /* 0x610830000: sd_cmu_5 */ 6 , 0 x30000 }, /* 0x610838000: sd_cmu_6 */ 7 , 0 x38000 }, /* 0x610840000: sd_cmu_7 */ 8 , 0 x40000 }, /* 0x610848000: sd_cmu_8 */ 0 x48000 }, /* 0x610850000: sd_cmu_cfg_0 */ 1 , 0 x50000 }, /* 0x610858000: sd_cmu_cfg_1 */ 2 , 0 x58000 }, /* 0x610860000: sd_cmu_cfg_2 */ 3 , 0 x60000 }, /* 0x610868000: sd_cmu_cfg_3 */ 4 , 0 x68000 }, /* 0x610870000: sd_cmu_cfg_4 */ 5 , 0 x70000 }, /* 0x610878000: sd_cmu_cfg_5 */ 6 , 0 x78000 }, /* 0x610880000: sd_cmu_cfg_6 */ 7 , 0 x80000 }, /* 0x610888000: sd_cmu_cfg_7 */ 8 , 0 x88000 }, /* 0x610890000: sd_cmu_cfg_8 */ 0 x90000 }, /* 0x610898000: sd6g_lane_0 */ 1 , 0 x98000 }, /* 0x6108a0000: sd6g_lane_1 */ 2 , 0 xa0000 }, /* 0x6108a8000: sd6g_lane_2 */ 3 , 0 xa8000 }, /* 0x6108b0000: sd6g_lane_3 */ 4 , 0 xb0000 }, /* 0x6108b8000: sd6g_lane_4 */ 5 , 0 xb8000 }, /* 0x6108c0000: sd6g_lane_5 */ 6 , 0 xc0000 }, /* 0x6108c8000: sd6g_lane_6 */ 7 , 0 xc8000 }, /* 0x6108d0000: sd6g_lane_7 */ 8 , 0 xd0000 }, /* 0x6108d8000: sd6g_lane_8 */ 9 , 0 xd8000 }, /* 0x6108e0000: sd6g_lane_9 */ 10 , 0 xe0000 }, /* 0x6108e8000: sd6g_lane_10 */ 11 , 0 xe8000 }, /* 0x6108f0000: sd6g_lane_11 */ 12 , 0 xf0000 }, /* 0x6108f8000: sd6g_lane_12 */ 0 xf8000 }, /* 0x610900000: sd10g_lane_0 */ 1 , 0 x100000 }, /* 0x610908000: sd10g_lane_1 */ 2 , 0 x108000 }, /* 0x610910000: sd10g_lane_2 */ 3 , 0 x110000 }, /* 0x610918000: sd10g_lane_3 */ 0 x1a0000 }, /* 0x6109a8000: sd_lane_0 */ 1 , 0 x1a8000 }, /* 0x6109b0000: sd_lane_1 */ 2 , 0 x1b0000 }, /* 0x6109b8000: sd_lane_2 */ 3 , 0 x1b8000 }, /* 0x6109c0000: sd_lane_3 */ 4 , 0 x1c0000 }, /* 0x6109c8000: sd_lane_4 */ 5 , 0 x1c8000 }, /* 0x6109d0000: sd_lane_5 */ 6 , 0 x1d0000 }, /* 0x6109d8000: sd_lane_6 */ 7 , 0 x1d8000 }, /* 0x6109e0000: sd_lane_7 */ 8 , 0 x1e0000 }, /* 0x6109e8000: sd_lane_8 */ 9 , 0 x1e8000 }, /* 0x6109f0000: sd_lane_9 */ 10 , 0 x1f0000 }, /* 0x6109f8000: sd_lane_10 */ 11 , 0 x1f8000 }, /* 0x610a00000: sd_lane_11 */ 12 , 0 x200000 }, /* 0x610a08000: sd_lane_12 */ 13 , 0 x208000 }, /* 0x610a10000: sd_lane_13 */ 14 , 0 x210000 }, /* 0x610a18000: sd_lane_14 */ 15 , 0 x218000 }, /* 0x610a20000: sd_lane_15 */ 16 , 0 x220000 }, /* 0x610a28000: sd_lane_16 */ 9 , 0 x400000 }, /* 0x610c08000: sd_cmu_9 */ 10 , 0 x408000 }, /* 0x610c10000: sd_cmu_10 */ 11 , 0 x410000 }, /* 0x610c18000: sd_cmu_11 */ 12 , 0 x418000 }, /* 0x610c20000: sd_cmu_12 */ 13 , 0 x420000 }, /* 0x610c28000: sd_cmu_13 */ 9 , 0 x428000 }, /* 0x610c30000: sd_cmu_cfg_9 */ 10 , 0 x430000 }, /* 0x610c38000: sd_cmu_cfg_10 */ 11 , 0 x438000 }, /* 0x610c40000: sd_cmu_cfg_11 */ 12 , 0 x440000 }, /* 0x610c48000: sd_cmu_cfg_12 */ 13 , 0 x448000 }, /* 0x610c50000: sd_cmu_cfg_13 */ 4 , 0 x450000 }, /* 0x610c58000: sd10g_lane_4 */ 5 , 0 x458000 }, /* 0x610c60000: sd10g_lane_5 */ 6 , 0 x460000 }, /* 0x610c68000: sd10g_lane_6 */ 7 , 0 x468000 }, /* 0x610c70000: sd10g_lane_7 */ 8 , 0 x470000 }, /* 0x610c78000: sd10g_lane_8 */ 9 , 0 x478000 }, /* 0x610c80000: sd10g_lane_9 */ 10 , 0 x480000 }, /* 0x610c88000: sd10g_lane_10 */ 11 , 0 x488000 }, /* 0x610c90000: sd10g_lane_11 */ 0 x490000 }, /* 0x610c98000: sd25g_lane_0 */ 1 , 0 x498000 }, /* 0x610ca0000: sd25g_lane_1 */ 2 , 0 x4a0000 }, /* 0x610ca8000: sd25g_lane_2 */ 3 , 0 x4a8000 }, /* 0x610cb0000: sd25g_lane_3 */ 4 , 0 x4b0000 }, /* 0x610cb8000: sd25g_lane_4 */ 5 , 0 x4b8000 }, /* 0x610cc0000: sd25g_lane_5 */ 6 , 0 x4c0000 }, /* 0x610cc8000: sd25g_lane_6 */ 7 , 0 x4c8000 }, /* 0x610cd0000: sd25g_lane_7 */ 17 , 0 x550000 }, /* 0x610d58000: sd_lane_17 */ 18 , 0 x558000 }, /* 0x610d60000: sd_lane_18 */ 19 , 0 x560000 }, /* 0x610d68000: sd_lane_19 */ 20 , 0 x568000 }, /* 0x610d70000: sd_lane_20 */ 21 , 0 x570000 }, /* 0x610d78000: sd_lane_21 */ 22 , 0 x578000 }, /* 0x610d80000: sd_lane_22 */ 23 , 0 x580000 }, /* 0x610d88000: sd_lane_23 */ 24 , 0 x588000 }, /* 0x610d90000: sd_lane_24 */ 0 x590000 }, /* 0x610d98000: sd_lane_25g_25 */ 1 , 0 x598000 }, /* 0x610da0000: sd_lane_25g_26 */ 2 , 0 x5a0000 }, /* 0x610da8000: sd_lane_25g_27 */ 3 , 0 x5a8000 }, /* 0x610db0000: sd_lane_25g_28 */ 4 , 0 x5b0000 }, /* 0x610db8000: sd_lane_25g_29 */ 5 , 0 x5b8000 }, /* 0x610dc0000: sd_lane_25g_30 */ 6 , 0 x5c0000 }, /* 0x610dc8000: sd_lane_25g_31 */ 7 , 0 x5c8000 }, /* 0x610dd0000: sd_lane_25g_32 */ static const struct sparx5_serdes_io_resource lan969x_serdes_iomap[] = {0 x0 }, /* 0xe3410000 */ 1 , 0 x8000 }, /* 0xe3418000 */ 2 , 0 x10000 }, /* 0xe3420000 */ 3 , 0 x18000 }, /* 0xe3428000 */ 4 , 0 x20000 }, /* 0xe3430000 */ 5 , 0 x28000 }, /* 0xe3438000 */ 0 x30000 }, /* 0xe3440000 */ 1 , 0 x38000 }, /* 0xe3448000 */ 2 , 0 x40000 }, /* 0xe3450000 */ 3 , 0 x48000 }, /* 0xe3458000 */ 4 , 0 x50000 }, /* 0xe3460000 */ 5 , 0 x58000 }, /* 0xe3468000 */ 0 x60000 }, /* 0xe3470000 */ 1 , 0 x68000 }, /* 0xe3478000 */ 2 , 0 x70000 }, /* 0xe3480000 */ 3 , 0 x78000 }, /* 0xe3488000 */ 4 , 0 x80000 }, /* 0xe3490000 */ 5 , 0 x88000 }, /* 0xe3498000 */ 6 , 0 x90000 }, /* 0xe34a0000 */ 7 , 0 x98000 }, /* 0xe34a8000 */ 8 , 0 xa0000 }, /* 0xe34b0000 */ 9 , 0 xa8000 }, /* 0xe34b8000 */ 0 x100000 }, /* 0xe3510000 */ 1 , 0 x108000 }, /* 0xe3518000 */ 2 , 0 x110000 }, /* 0xe3520000 */ 3 , 0 x118000 }, /* 0xe3528000 */ 4 , 0 x120000 }, /* 0xe3530000 */ 5 , 0 x128000 }, /* 0xe3538000 */ 6 , 0 x130000 }, /* 0xe3540000 */ 7 , 0 x138000 }, /* 0xe3548000 */ 8 , 0 x140000 }, /* 0xe3550000 */ 9 , 0 x148000 }, /* 0xe3558000 */ static const struct sparx5_serdes_match_data sparx5_desc = {33 ,14 ,static const struct sparx5_serdes_match_data lan969x_desc = {10 ,6 ,/* Client lookup function, uses serdes index */ static struct phy *sparx5_serdes_xlate(struct device *dev,const struct of_phandle_args *args)struct sparx5_serdes_private *priv = dev_get_drvdata(dev);int idx;unsigned int sidx;if (args->args_count != 1 )return ERR_PTR(-EINVAL);0 ];/* Check validity: ERR_PTR(-ENODEV) if not valid */ for (idx = 0 ; idx < priv->data->consts.sd_max; idx++) {struct sparx5_serdes_macro *macro =if (sidx != macro->sidx)continue ;return priv->phys[idx];return ERR_PTR(-ENODEV);static int sparx5_serdes_probe(struct platform_device *pdev)struct device_node *np = pdev->dev.of_node;struct sparx5_serdes_private *priv;struct phy_provider *provider;struct resource *iores;void __iomem *iomem;unsigned long clock;struct clk *clk;int idx;int err;if (!np && !pdev->dev.platform_data)return -ENODEV;sizeof (*priv), GFP_KERNEL);if (!priv)return -ENOMEM;if (!priv->data)return -EINVAL;/* Get coreclock */ if (IS_ERR(clk)) {"Failed to get coreclock\n" );return PTR_ERR(clk);if (clock == 0 ) {"Invalid coreclock %lu\n" , clock);return -EINVAL;0 );if (!iores) {"Invalid resource\n" );return -EINVAL;if (!iomem) {"Unable to get serdes registers: %s\n" ,return -ENOMEM;for (idx = 0 ; idx < priv->data->iomap_size; idx++) {const struct sparx5_serdes_io_resource *iomap =for (idx = 0 ; idx < priv->data->consts.sd_max; idx++) {if (err)return err;/* Power down all CMU's by default */ if (priv->data->type == SPX5_TARGET_SPARX5)return PTR_ERR_OR_ZERO(provider);static const struct of_device_id sparx5_serdes_match[] = {"microchip,sparx5-serdes" , .data = &sparx5_desc },"microchip,lan9691-serdes" , .data = &lan969x_desc },static struct platform_driver sparx5_serdes_driver = {"sparx5-serdes" ,"Microchip Sparx5 switch serdes driver" );"Steen Hegelund <steen.hegelund@microchip.com>" );"GPL v2" );
Messung V0.5 in Prozent C=94 H=99 G=96
¤ Dauer der Verarbeitung: 0.33 Sekunden
(vorverarbeitet am 2026-09-28)
¤ *© Formatika GbR, Deutschland
