// SPDX-License-Identifier: GPL-2.0 /* * PCI detection and setup code #include <linux/kernel.h>#include <linux/delay.h>#include <linux/init.h>#include <linux/pci.h>#include <linux/msi.h>#include <linux/of_pci.h>#include <linux/of_platform.h>#include <linux/platform_device.h>#include <linux/pci_hotplug.h>#include <linux/slab.h>#include <linux/module.h>#include <linux/cpumask.h>#include <linux/aer.h>#include <linux/acpi.h>#include <linux/hypervisor.h>#include <linux/irqdomain.h>#include <linux/pm_runtime.h>#include <linux/bitfield.h>#include "pci.h" #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */ #define CARDBUS_RESERVE_BUSNR 3 static struct resource busn_resource = {"PCI busn" ,0 ,255 ,/* Ugh. Need to stop exporting this to modules. */ static LIST_HEAD(pci_domain_busn_res_list);struct pci_domain_busn_res {struct list_head list;struct resource res;int domain_nr;static struct resource *get_pci_domain_busn_res(int domain_nr)struct pci_domain_busn_res *r;if (r->domain_nr == domain_nr)return &r->res;sizeof (*r), GFP_KERNEL);if (!r)return NULL;0 ;0 xff;return &r->res;/* * Some device drivers need know if PCI is initiated . * Basically , we think PCI is not initiated when there * is no device to be found on the pci_bus_type . int no_pci_devices(void )struct device *dev;int no_devices;return no_devices;/* * PCI Bus Class static void release_pcibus_dev(struct device *dev)struct pci_bus *pci_bus = to_pci_bus(dev);static const struct class pcibus_class = {"pci_bus" ,static int __init pcibus_class_init(void )return class_register(&pcibus_class);static u64 pci_size(u64 base, u64 maxbase, u64 mask)/* Find the significant bits */ if (!size)return 0 ;/* * Get the lowest of them to find the decode size , and from that * the extent . 1 );/* * base = = maxbase can be valid only if the BAR has already been * programmed with all 1 s . if (base == maxbase && ((base | (size - 1 )) & mask) != mask)return 0 ;return size;static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar)unsigned long flags;if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {return flags;if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)switch (mem_type) {case PCI_BASE_ADDRESS_MEM_TYPE_32:break ;case PCI_BASE_ADDRESS_MEM_TYPE_1M:/* 1M mem BAR treated as 32-bit BAR */ break ;case PCI_BASE_ADDRESS_MEM_TYPE_64:break ;default :/* mem unknown type treated as 32-bit BAR */ break ;return flags;#define PCI_COMMAND_DECODE_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)/** * _ _ pci_size_bars - Read the raw BAR mask for a range of PCI BARs * @ dev : the PCI device * @ count : number of BARs to size * @ pos : starting config space position * @ sizes : array to store mask values * @ rom : indicate whether to use ROM mask , which avoids enabling ROM BARs * * Provided @ sizes array must be sufficiently sized to store results for * @ count u32 BARs . Caller is responsible for disabling decode to specified * BAR range around calling this function . This function is intended to avoid * disabling decode around sizing each BAR individually , which can result in * non - trivial overhead in virtualized environments with very large PCI BARs . static void __pci_size_bars(struct pci_dev *dev, int count,unsigned int pos, u32 *sizes, bool rom)0 ;int i;for (i = 0 ; i < count; i++, pos += 4 , sizes++) {void __pci_size_stdbars(struct pci_dev *dev, int count,unsigned int pos, u32 *sizes)false );static void __pci_size_rom(struct pci_dev *dev, unsigned int pos, u32 *sizes)1 , pos, sizes, true );/** * _ _ pci_read_base - Read a PCI BAR * @ dev : the PCI device * @ type : type of the BAR * @ res : resource buffer to be filled in * @ pos : BAR position in the config space * @ sizes : array of one or more pre - read BAR masks * * Returns 1 if the BAR is 64 - bit , or 0 if 32 - bit . int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,struct resource *res, unsigned int pos, u32 *sizes)0 , sz;struct pci_bus_region region, inverted_region;const char *res_name = pci_resource_name(dev, res - dev->resource);0 ];/* * All bits set in sz means the device isn ' t working properly . * If the BAR isn ' t implemented , all bits must be 0 . If it ' s a * memory BAR or a ROM , bit 0 must be clear ; if it ' s an io BAR , bit * 1 must be clear . if (PCI_POSSIBLE_ERROR(sz))0 ;/* * I don ' t know how l can have all bits set . Copied from old code . * Maybe it fixes a bug on some ancient platform . if (PCI_POSSIBLE_ERROR(l))0 ;if (type == pci_bar_unknown) {if (res->flags & IORESOURCE_IO) {else {else {if (l & PCI_ROM_ADDRESS_ENABLE)if (res->flags & IORESOURCE_MEM_64) {4 , &l);1 ];32 );32 );0 << 32 );if (!sz64)goto fail;if (!sz64) {"%s: invalid; can't size\n" , res_name);goto fail;if (res->flags & IORESOURCE_MEM_64) {if ((sizeof (pci_bus_addr_t) < 8 || sizeof (resource_size_t) < 8 )0 x100000000ULL) {0 ;0 ;"%s: can't handle BAR larger than 4GB (size %#010llx)\n" ,unsigned long long )sz64);goto out;if ((sizeof (pci_bus_addr_t) < 8 ) && l) {/* Above 32-bit boundary; try to reallocate */ 0 ;1 ;"%s: can't handle BAR above 4GB (bus address %#010llx)\n" ,unsigned long long )l64);goto out;1 ;/* * If " A " is a BAR value ( a bus address ) , " bus_to_resource ( A ) " is * the corresponding resource address ( the physical address used by * the CPU . Converting that resource address back to a bus address * should yield the original BAR value : * * resource_to_bus ( bus_to_resource ( A ) ) = = A * * If it doesn ' t , CPU accesses to " bus_to_resource ( A ) " will not * be claimed by the device . if (inverted_region.start != region.start) {0 ;"%s: initial BAR value %#010llx invalid\n" ,unsigned long long )region.start);goto out;0 ;if (res->flags)"%s %pR\n" , res_name, res);return (res->flags & IORESOURCE_MEM_64) ? 1 : 0 ;static __always_inline void pci_read_bases(struct pci_dev *dev,unsigned int howmany, int rom)unsigned int pos, reg;if (dev->non_compliant_bars)return ;/* Per PCIe r4.0, sec 9.3.4.1.11, the VF BARs are all RO Zero */ if (dev->is_virtfn)return ;/* No printks while decoding is disabled! */ if (!dev->mmio_always_on) {if (orig_cmd & PCI_COMMAND_DECODE_ENABLE) {if (rom)if (!dev->mmio_always_on &&for (pos = 0 ; pos < howmany; pos++) {struct resource *res = &dev->resource[pos];2 );if (rom) {struct resource *res = &dev->resource[PCI_ROM_RESOURCE];static void pci_read_bridge_io(struct pci_dev *dev, struct resource *res,bool log)unsigned long io_mask, io_granularity, base, limit;struct pci_bus_region region;0 x1000;if (dev->io_window_1k) {/* Support 1K I/O space granularity */ 0 x400;8 ;8 ;if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {unsigned long ) io_base_hi << 16 );unsigned long ) io_limit_hi << 16 );if (base <= limit) {1 ;if (log)" bridge window %pR\n" , res);static void pci_read_bridge_mmio(struct pci_dev *dev, struct resource *res,bool log)unsigned long base, limit;struct pci_bus_region region;unsigned long ) mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16 ;unsigned long ) mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16 ;if (base <= limit) {0 xfffff;if (log)" bridge window %pR\n" , res);static void pci_read_bridge_mmio_pref(struct pci_dev *dev, struct resource *res,bool log)struct pci_bus_region region;16 ;16 ;if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {/* * Some bridges set the base > limit by default , and some * ( broken ) BIOSes do not initialize them . If we find * this , just assume they are not being used . if (mem_base_hi <= mem_limit_hi) {32 ;32 ;if (base != base64) {"can't handle bridge window above 4GB (bus address %#010llx)\n" ,unsigned long long ) base64);return ;if (base <= limit) {if (res->flags & PCI_PREF_RANGE_TYPE_64)0 xfffff;if (log)" bridge window %pR\n" , res);static void pci_read_bridge_windows(struct pci_dev *bridge)struct resource res;8 ) & 0 xff;16 ) & 0 xff;"PCI bridge to %pR%s\n" , &res," (subtractive decode)" : "" );if (!io) {0 xe0f0);0 x0);if (io) {1 ;true );true );/* * DECchip 21050 pass 2 errata : the bridge may miss an address * disconnect boundary by one PCI data phase . Workaround : do not * use prefetching on this device . if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0 x0001)return ;if (!pmem) {0 xffe0fff0);0 x0);if (!pmem)return ;1 ;if ((pmem & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {/* * Bridge claims to have a 64 - bit prefetchable memory * window ; verify that the upper bits are actually * writable . 0 xffffffff);if (tmp)1 ;true );void pci_read_bridge_bases(struct pci_bus *child)struct pci_dev *dev = child->self;struct resource *res;int i;if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */ return ;"PCI bridge to %pR%s\n" ," (subtractive decode)" : "" );for (i = 0 ; i < PCI_BRIDGE_RESOURCE_NUM; i++)0 ], false );1 ], false );2 ], false );if (!dev->transparent)return ;if (!res || !res->flags)continue ;" bridge window %pR (subtractive decode)\n" , res);static struct pci_bus *pci_alloc_bus(struct pci_bus *parent)struct pci_bus *b;sizeof (*b), GFP_KERNEL);if (!b)return NULL;#ifdef CONFIG_PCI_DOMAINS_GENERICif (parent)#endif return b;static void pci_release_host_bridge_dev(struct device *dev)struct pci_host_bridge *bridge = to_pci_host_bridge(dev);if (bridge->release_fn)static void pci_init_host_bridge(struct pci_host_bridge *bridge)/* * We assume we can manage these PCIe features . Some systems may * reserve these for use by the platform itself , e . g . , an ACPI BIOS * may implement its own AER handling and use _ OSC to prevent the * OS from interfering . 1 ;1 ;1 ;1 ;1 ;1 ;1 ;struct pci_host_bridge *pci_alloc_host_bridge(size_t priv)struct pci_host_bridge *bridge;sizeof (*bridge) + priv, GFP_KERNEL);if (!bridge)return NULL;return bridge;static void devm_pci_alloc_host_bridge_release(void *data)struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev,int ret;struct pci_host_bridge *bridge;if (!bridge)return NULL;if (ret)return NULL;if (ret)return NULL;return bridge;void pci_free_host_bridge(struct pci_host_bridge *bridge)/* Indexed by PCI_X_SSTATUS_FREQ (secondary bus mode and frequency) */ static const unsigned char pcix_bus_speed[] = {/* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C */ /* D */ /* E */ /* F */ /* Indexed by PCI_EXP_LNKCAP_SLS, PCI_EXP_LNKSTA_CLS */ const unsigned char pcie_link_speed[] = {/* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C */ /* D */ /* E */ /* F */ const char *pci_speed_string(enum pci_bus_speed speed)/* Indexed by the pci_bus_speed enum */ static const char *speed_strings[] = {"33 MHz PCI" , /* 0x00 */ "66 MHz PCI" , /* 0x01 */ "66 MHz PCI-X" , /* 0x02 */ "100 MHz PCI-X" , /* 0x03 */ "133 MHz PCI-X" , /* 0x04 */ /* 0x05 */ /* 0x06 */ /* 0x07 */ /* 0x08 */ "66 MHz PCI-X 266" , /* 0x09 */ "100 MHz PCI-X 266" , /* 0x0a */ "133 MHz PCI-X 266" , /* 0x0b */ "Unknown AGP" , /* 0x0c */ "1x AGP" , /* 0x0d */ "2x AGP" , /* 0x0e */ "4x AGP" , /* 0x0f */ "8x AGP" , /* 0x10 */ "66 MHz PCI-X 533" , /* 0x11 */ "100 MHz PCI-X 533" , /* 0x12 */ "133 MHz PCI-X 533" , /* 0x13 */ "2.5 GT/s PCIe" , /* 0x14 */ "5.0 GT/s PCIe" , /* 0x15 */ "8.0 GT/s PCIe" , /* 0x16 */ "16.0 GT/s PCIe" , /* 0x17 */ "32.0 GT/s PCIe" , /* 0x18 */ "64.0 GT/s PCIe" , /* 0x19 */ if (speed < ARRAY_SIZE(speed_strings))return speed_strings[speed];return "Unknown" ;void pcie_update_link_speed(struct pci_bus *bus)struct pci_dev *bridge = bus->self;static unsigned char agp_speeds[] = {static enum pci_bus_speed agp_speed(int agp3, int agpstat)int index = 0 ;if (agpstat & 4 )3 ;else if (agpstat & 2 )2 ;else if (agpstat & 1 )1 ;else goto out;if (agp3) {2 ;if (index == 5 )0 ;return agp_speeds[index];static void pci_set_bus_speed(struct pci_bus *bus)struct pci_dev *bridge = bus->self;int pos;if (!pos)if (pos) {8 , agpstat & 7 );8 , agpcmd & 7 );if (pos) {enum pci_bus_speed max;if (status & PCI_X_SSTATUS_533MHZ) {else if (status & PCI_X_SSTATUS_266MHZ) {else if (status & PCI_X_SSTATUS_133MHZ) {if ((status & PCI_X_SSTATUS_VERS) == PCI_X_SSTATUS_V2)else else {return ;if (pci_is_pcie(bridge)) {static struct irq_domain *pci_host_bridge_msi_domain(struct pci_bus *bus)struct irq_domain *d;/* If the host bridge driver sets a MSI domain of the bridge, use it */ /* * Any firmware interface that can resolve the msi_domain * should be called from here . if (!d)if (!d)/* * If no IRQ domain was found via the OF tree , try looking it up * directly through the fwnode_handle . if (!d) {struct fwnode_handle *fwnode = pci_root_bus_fwnode(bus);if (fwnode)return d;static void pci_set_bus_msi_domain(struct pci_bus *bus)struct irq_domain *d;struct pci_bus *b;/* * The bus can be a root bus , a subordinate bus , or a virtual bus * created by an SR - IOV device . Walk up to the first bridge device * found or derive the domain from the host bridge . for (b = bus, d = NULL; !d && !pci_is_root_bus(b); b = b->parent) {if (b->self)if (!d)static bool pci_preserve_config(struct pci_host_bridge *host_bridge)if (pci_acpi_preserve_config(host_bridge))return true ;if (host_bridge->dev.parent && host_bridge->dev.parent->of_node)return of_pci_preserve_config(host_bridge->dev.parent->of_node);return false ;static int pci_register_host_bridge(struct pci_host_bridge *bridge)struct device *parent = bridge->dev.parent;struct resource_entry *window, *next, *n;struct pci_bus *bus, *b;struct resource *res, *next_res;bool bus_registered = false ;char addr[64 ], *fmt;const char *name;int err;if (!bus)return -ENOMEM;#ifdef CONFIG_PCI_DOMAINS_GENERICif (bridge->domain_nr == PCI_DOMAIN_NR_NOT_SET)else if (bus->domain_nr < 0 ) {goto free;#endif if (b) {/* Ignore it if we already got here via a different bridge */ "bus already known\n" );goto free;"pci%04x:%02x" , pci_domain_nr(bus),if (err)goto free;/* Temporarily move resources off the list */ if (err)goto free;if (bridge->msi_domain && !dev_get_msi_domain(&bus->dev) &&if (!parent)class = &pcibus_class;"%04x:%02x" , pci_domain_nr(bus), bus->number);true ;if (err)goto unregister;if (bus->ops->add_bus) {if (WARN_ON(err < 0 ))"failed to add bus: %d\n" , err);/* Create legacy_io and legacy_mem files for this bus */ if (parent)"PCI host bridge to bus %s\n" , name);else "PCI host bridge to bus %s\n" , name);if (nr_node_ids > 1 && pcibus_to_node(bus) == NUMA_NO_NODE)"Unknown NUMA node; performance will be reduced\n" );/* Check if the boot configuration by FW needs to be preserved */ /* Coalesce contiguous windows */ if (list_is_last(&window->node, &resources))break ;if (res->flags != next_res->flags || offset != next_offset)continue ;if (res->end + 1 == next_res->start) {0 ;/* Add initial resources to the bus */ if (!res->flags && !res->start && !res->end) {continue ;if (res->flags & IORESOURCE_BUS)else if (offset) {if (resource_type(res) == IORESOURCE_IO)" (bus address [%#06llx-%#06llx])" ;else " (bus address [%#010llx-%#010llx])" ;sizeof (addr), fmt,unsigned long long )(res->start - offset),unsigned long long )(res->end - offset));else 0 ] = '\0' ;"root bus resource %pR%s\n" , res, addr);return 0 ;#ifdef CONFIG_PCI_DOMAINS_GENERIC#endif if (bus_registered)else return err;static bool pci_bridge_child_ext_cfg_accessible(struct pci_dev *bridge)int pos;/* * If extended config space isn ' t accessible on a bridge ' s primary * bus , we certainly can ' t access it on the secondary bus . if (bridge->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG)return false ;/* * PCIe Root Ports and switch ports are PCIe on both sides , so if * extended config space is accessible on the primary , it ' s also * accessible on the secondary . if (pci_is_pcie(bridge) &&return true ;/* * For the other bridge types : * - PCI - to - PCI bridges * - PCIe - to - PCI / PCI - X forward bridges * - PCI / PCI - X - to - PCIe reverse bridges * extended config space on the secondary side is only accessible * if the bridge supports PCI - X Mode 2 . if (!pos)return false ;return status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ);static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,struct pci_dev *bridge, int busnr)struct pci_bus *child;struct pci_host_bridge *host;int i;int ret;/* Allocate a new bus and inherit stuff from the parent */ if (!child)return NULL;if (host->child_ops)else /* * Initialize some portions of the bus device , but don ' t register * it now as the parent is not properly set up yet . class = &pcibus_class;"%04x:%02x" , pci_domain_nr(child), busnr);/* Set up the primary, secondary and subordinate bus numbers */ 0 xff;if (!bridge) {goto add_dev;/* * Check whether extended config space is accessible on the child * bus . Note that we currently assume it is always accessible on * the root bus . if (!pci_bridge_child_ext_cfg_accessible(bridge)) {"extended config space not accessible\n" );/* Set up default resource pointers and names */ for (i = 0 ; i < PCI_BRIDGE_RESOURCE_NUM; i++) {if (WARN_ON(ret < 0 )) {return NULL;if (child->ops->add_bus) {if (WARN_ON(ret < 0 ))"failed to add bus: %d\n" , ret);/* Create legacy_io and legacy_mem files for this bus */ return child;struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,int busnr)struct pci_bus *child;if (child) {return child;static void pci_enable_rrs_sv(struct pci_dev *pdev)0 ;/* Enable Configuration RRS Software Visibility if supported */ if (root_cap & PCI_EXP_RTCAP_RRS_SV) {1 ;static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus,unsigned int available_buses);/** * pci_ea_fixed_busnrs ( ) - Read fixed Secondary and Subordinate bus * numbers from EA capability . * @ dev : Bridge * @ sec : updated with secondary bus number from EA * @ sub : updated with subordinate bus number from EA * * If @ dev is a bridge with EA capability that specifies valid secondary * and subordinate bus numbers , return true with the bus numbers in @ sec * and @ sub . Otherwise return false . static bool pci_ea_fixed_busnrs(struct pci_dev *dev, u8 *sec, u8 *sub)int ea, offset;if (dev->hdr_type != PCI_HEADER_TYPE_BRIDGE)return false ;/* find PCI EA capability in list */ if (!ea)return false ;if (ea_sec == 0 || ea_sub < ea_sec)return false ;return true ;/* * pci_scan_bridge_extend ( ) - Scan buses behind a bridge * @ bus : Parent bus the bridge is on * @ dev : Bridge itself * @ max : Starting subordinate number of buses behind this bridge * @ available_buses : Total number of buses available for this bridge and * the devices below . After the minimal bus space has * been allocated the remaining buses will be * distributed equally between hotplug - capable bridges . * @ pass : Either % 0 ( scan already configured bridges ) or % 1 ( scan bridges * that need to be reconfigured . * * If it ' s a bridge , configure it and scan the bus behind it . * For CardBus bridges , we don ' t scan behind as the devices will * be handled by the bridge driver itself . * * We need to process bridges in two passes - - first we scan those * already configured by the BIOS and after we are done with all of * them , we proceed to assigning numbers to the remaining buses in * order to avoid overlaps between old and new bus numbers . * * Return : New subordinate number covering all buses behind this bridge . static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev,int max, unsigned int available_buses,int pass)struct pci_bus *child;int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);0 ;int broken = 0 ;bool fixed_buses;int next_busnr;/* * Make sure the bridge is powered on to be able to access config * space of devices below it . 0 xFF;8 ) & 0 xFF;16 ) & 0 xFF;"scanning [bus %02x-%02x] behind bridge, pass %d\n" ,if (!primary && (primary != bus->number) && secondary && subordinate) {"Primary bus is hard wired to 0\n" );/* Check if setup is sensible at all */ if (!pass &&"bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n" ,1 ;/* * Disable Master - Abort Mode during probing to avoid reporting of * bus errors in some architectures . if ((secondary || subordinate) && !pcibios_assign_all_busses() &&unsigned int cmax, buses;/* * Bus already configured by firmware , process it in the * first pass and just note the configuration . if (pass)goto out;/* * The bus might already exist for two reasons : Either we * are rescanning the bus or the bus is reachable through * more than one bridge . The second case can happen with * the i450NX chipset . if (!child) {if (!child)goto out;if (cmax > subordinate)"bridge has subordinate %02x but max busn %02x\n" ,/* Subordinate should equal child->busn_res.end */ if (subordinate > max)else {/* * We need to assign a number to this bus which we always * do in the second pass . if (!pass) {if (pcibios_assign_all_busses() || broken || is_cardbus)/* * Temporarily disable forwarding of the * configuration cycles on all bridges in * this bus segment to avoid possible * conflicts in the second pass between two * bridges programmed with overlapping bus * ranges . 0 xffffff);goto out;/* Clear errors */ 0 xffff);/* Read bus numbers from EA Capability (if present) */ if (fixed_buses)else 1 ;/* * Prevent assigning a bus number that already exists . * This can happen when a bridge is hot - plugged , so in this * case we only re - scan this bus . if (!child) {if (!child)goto out;if (available_buses)0 xff000000)unsigned int )(child->primary) << 0 )unsigned int )(child->busn_res.start) << 8 )unsigned int )(child->busn_res.end) << 16 );/* * yenta . c forces a secondary latency timer of 176 . * Copy that behaviour here . if (is_cardbus) {0 xff000000;24 ;/* We need to blast all three values with a single write */ if (!is_cardbus) {else {/* * For CardBus bridges , we leave 4 bus numbers as * cards with a PCI - to - PCI bridge can be inserted * later . for (i = 0 ; i < CARDBUS_RESERVE_BUSNR; i++) {struct pci_bus *parent = bus;if (pci_find_bus(pci_domain_nr(bus),1 ))break ;while (parent->parent) {if ((!pcibios_assign_all_busses()) &&1 ;if (j) {/* * Often , there are two CardBus * bridges - - try to leave one * valid bus number for each one . 2 ;break ;/* * Set subordinate bus number to its real value . * If fixed subordinate bus number exists from EA * capability then use it . if (fixed_buses)"PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x" ),/* Check that all devices are accessible */ while (bus->parent) {if ((child->busn_res.end > bus->busn_res.end) ||"devices behind bridge are unusable because %pR cannot be assigned for them\n" ,break ;/* Clear errors in the Secondary Status Register */ 0 xffff);return max;/* * pci_scan_bridge ( ) - Scan buses behind a bridge * @ bus : Parent bus the bridge is on * @ dev : Bridge itself * @ max : Starting subordinate number of buses behind this bridge * @ pass : Either % 0 ( scan already configured bridges ) or % 1 ( scan bridges * that need to be reconfigured . * * If it ' s a bridge , configure it and scan the bus behind it . * For CardBus bridges , we don ' t scan behind as the devices will * be handled by the bridge driver itself . * * We need to process bridges in two passes - - first we scan those * already configured by the BIOS and after we are done with all of * them , we proceed to assigning numbers to the remaining buses in * order to avoid overlaps between old and new bus numbers . * * Return : New subordinate number covering all buses behind this bridge . int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)return pci_scan_bridge_extend(bus, dev, max, 0 , pass);/* * Read interrupt line and base address registers . * The architecture - dependent code can tweak these , of course . static void pci_read_irq(struct pci_dev *dev)unsigned char irq;/* VFs are not allowed to use INTx, so skip the config reads */ if (dev->is_virtfn) {0 ;0 ;return ;if (irq)void set_pcie_port_type(struct pci_dev *pdev)int pos;int type;struct pci_dev *parent;if (!pos)return ;if (type == PCI_EXP_TYPE_ROOT_PORT)if (reg32 & PCI_EXP_LNKCAP_DLLLARC)1 ;if (!parent)return ;/* * Some systems do not identify their upstream / downstream ports * correctly so detect impossible configurations here and correct * the port type accordingly . if (type == PCI_EXP_TYPE_DOWNSTREAM) {/* * If pdev claims to be downstream port but the parent * device is also downstream port assume pdev is actually * upstream port . if (pcie_downstream_port(parent)) {"claims to be downstream port but is acting as upstream port, correcting type\n" );else if (type == PCI_EXP_TYPE_UPSTREAM) {/* * If pdev claims to be upstream port but the parent * device is also upstream port assume pdev is actually * downstream port . if (pci_pcie_type(parent) == PCI_EXP_TYPE_UPSTREAM) {"claims to be upstream port but is acting as downstream port, correcting type\n" );void set_pcie_hotplug_bridge(struct pci_dev *pdev)if (reg32 & PCI_EXP_SLTCAP_HPC)1 ;static void set_pcie_thunderbolt(struct pci_dev *dev)/* Is the device part of a Thunderbolt controller? */ if (vsec)1 ;static void set_pcie_untrusted(struct pci_dev *dev)struct pci_dev *parent = pci_upstream_bridge(dev);if (!parent)return ;/* * If the upstream bridge is untrusted we treat this device as * untrusted as well . if (parent->untrusted) {true ;return ;if (arch_pci_dev_is_removable(dev)) {"marking as untrusted\n" );true ;static void pci_set_removable(struct pci_dev *dev)struct pci_dev *parent = pci_upstream_bridge(dev);if (!parent)return ;/* * We ( only ) consider everything tunneled below an external_facing * device to be removable by the user . We ' re mainly concerned with * consumer platforms with user accessible thunderbolt ports that are * vulnerable to DMA attacks , and we expect those ports to be marked by * the firmware as external_facing . Devices in traditional hotplug * slots can technically be removed , but the expectation is that unless * the port is marked with external_facing , such devices are less * accessible to user / may not be removed by end user , and thus not * exposed as " removable " to userspace . if (dev_is_removable(&parent->dev)) {return ;if (arch_pci_dev_is_removable(dev)) {"marking as removable\n" );/** * pci_ext_cfg_is_aliased - Is ext config space just an alias of std config ? * @ dev : PCI device * * PCI Express to PCI / PCI - X Bridge Specification , rev 1 . 0 , 4 . 1 . 4 says that * when forwarding a type1 configuration request the bridge must check that * the extended register address field is zero . The bridge is not permitted * to forward the transactions and must handle it as an Unsupported Request . * Some bridges do not follow this rule and simply drop the extended register * bits , resulting in the standard config space being aliased , every 256 * bytes across the entire configuration space . Test for this condition by * comparing the first dword of each potential alias to the vendor / device ID . * Known offenders : * ASM1083 / 1085 PCIe - to - PCI Reversible Bridge ( 1 b21 : 1080 , rev 01 & 03 ) * AMD / ATI SBx00 PCI to PCI Bridge ( 1002 : 4384 , rev 40 ) static bool pci_ext_cfg_is_aliased(struct pci_dev *dev)#ifdef CONFIG_PCI_QUIRKSint pos, ret;for (pos = PCI_CFG_SPACE_SIZE;if ((ret != PCIBIOS_SUCCESSFUL) || (header != tmp))return false ;return true ;#else return false ;#endif /** * pci_cfg_space_size_ext - Get the configuration space size of the PCI device * @ dev : PCI device * * Regular PCI devices have 256 bytes , but PCI - X 2 and PCI Express devices * have 4096 bytes . Even if the device is capable , that doesn ' t mean we can * access it . Maybe we don ' t have a way to generate extended config space * accesses , or the device is behind a reverse Express bridge . So we try * reading the dword at 0 x100 which must either be 0 or a valid extended * capability header . static int pci_cfg_space_size_ext(struct pci_dev *dev)int pos = PCI_CFG_SPACE_SIZE;if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)return PCI_CFG_SPACE_SIZE;if (PCI_POSSIBLE_ERROR(status) || pci_ext_cfg_is_aliased(dev))return PCI_CFG_SPACE_SIZE;return PCI_CFG_SPACE_EXP_SIZE;int pci_cfg_space_size(struct pci_dev *dev)int pos;class ;#ifdef CONFIG_PCI_IOV/* * Per the SR - IOV specification ( rev 1 . 1 , sec 3 . 5 ) , VFs are required to * implement a PCIe capability and therefore must implement extended * config space . We can skip the NO_EXTCFG test below and the * reachability / aliasing test in pci_cfg_space_size_ext ( ) by virtue of * the fact that the SR - IOV capability on the PF resides in extended * config space and must be accessible and non - aliased to have enabled * support for this VF . This is a micro performance optimization for * systems supporting many VFs . if (dev->is_virtfn)return PCI_CFG_SPACE_EXP_SIZE;#endif if (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG)return PCI_CFG_SPACE_SIZE;class = dev->class >> 8 ;if (class == PCI_CLASS_BRIDGE_HOST)return pci_cfg_space_size_ext(dev);if (pci_is_pcie(dev))return pci_cfg_space_size_ext(dev);if (!pos)return PCI_CFG_SPACE_SIZE;if (status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ))return pci_cfg_space_size_ext(dev);return PCI_CFG_SPACE_SIZE;static u32 pci_class(struct pci_dev *dev)class ;#ifdef CONFIG_PCI_IOVif (dev->is_virtfn)return dev->physfn->sriov->class ;#endif class );return class ;static void pci_subsystem_ids(struct pci_dev *dev, u16 *vendor, u16 *device)#ifdef CONFIG_PCI_IOVif (dev->is_virtfn) {return ;#endif static u8 pci_hdr_type(struct pci_dev *dev)#ifdef CONFIG_PCI_IOVif (dev->is_virtfn)return dev->physfn->sriov->hdr_type;#endif return hdr_type;#define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)/** * pci_intx_mask_broken - Test PCI_COMMAND_INTX_DISABLE writability * @ dev : PCI device * * Test whether PCI_COMMAND_INTX_DISABLE is writable for @ dev . Check this * at enumeration - time to avoid modifying PCI_COMMAND at run - time . static int pci_intx_mask_broken(struct pci_dev *dev)new ;new );/* * PCI_COMMAND_INTX_DISABLE was reserved and read - only prior to PCI * r2 . 3 , so strictly speaking , a device is not * broken * if it ' s not * writable . But we ' ll live with the misnomer for now . if (new != toggle)return 1 ;return 0 ;static void early_dump_pci_device(struct pci_dev *pdev)256 / 4 ];int i;"config space:\n" );for (i = 0 ; i < 256 ; i += 4 )4 ]);"" , DUMP_PREFIX_OFFSET, 16 , 1 ,256 , false );static const char *pci_type_str(struct pci_dev *dev)static const char * const str[] = {"PCIe Endpoint" ,"PCIe Legacy Endpoint" ,"PCIe unknown" ,"PCIe unknown" ,"PCIe Root Port" ,"PCIe Switch Upstream Port" ,"PCIe Switch Downstream Port" ,"PCIe to PCI/PCI-X bridge" ,"PCI/PCI-X to PCIe bridge" ,"PCIe Root Complex Integrated Endpoint" ,"PCIe Root Complex Event Collector" ,int type;if (pci_is_pcie(dev)) {if (type < ARRAY_SIZE(str))return str[type];return "PCIe unknown" ;switch (dev->hdr_type) {case PCI_HEADER_TYPE_NORMAL:return "conventional PCI endpoint" ;case PCI_HEADER_TYPE_BRIDGE:return "conventional PCI bridge" ;case PCI_HEADER_TYPE_CARDBUS:return "CardBus bridge" ;default :return "conventional PCI" ;/** * pci_setup_device - Fill in class and map information of a device * @ dev : the device structure to fill * * Initialize the device structure with information about the device ' s * vendor , class , memory and IO - space addresses , IRQ lines etc . * Called at initialisation of the PCI subsystem and by CardBus services . * Returns 0 on success and negative if unknown type of device ( not normal , * bridge or CardBus ) . int pci_setup_device(struct pci_dev *dev)class ;int err, pos = 0 ;struct pci_bus_region region;struct resource *res;0 x7f;0 x80);if (err)return err;/* * Assume 32 - bit PCI ; let 64 - bit PCI cards ( which are far rarer ) * set this higher , assuming the system even supports it . 0 xffffffff;"%04x:%02x:%02x.%d" , pci_domain_nr(dev->bus),class = pci_class(dev);class & 0 xff;class = class >> 8 ; /* upper 3 bytes */ if (pci_early_dump)/* Need to have dev->class ready */ /* Need to have dev->cfg_size ready */ if (pci_is_pcie(dev))/* "Unknown power state" */ /* Early fixups, before probing the BARs */ "[%04x:%04x] type %02x class %#08x %s\n" ,class ,/* Device class may be changed after fixup */ class = dev->class >> 8 ;if (dev->non_compliant_bars && !dev->mmio_always_on) {if (cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) {"device has non-compliant BARs; disabling IO/MEM decoding\n" );switch (dev->hdr_type) { /* header type */ case PCI_HEADER_TYPE_NORMAL: /* standard header */ if (class == PCI_CLASS_BRIDGE_PCI)goto bad;/* * Do the ugly legacy mode stuff here rather than broken chip * quirk code . Legacy mode ATA controllers have fixed * addresses . These are not always echoed in BAR0 - 3 , and * BAR0 - 3 in a few cases contain junk ! if (class == PCI_CLASS_STORAGE_IDE) {if ((progif & 1 ) == 0 ) {0 x1F0;0 x1F7;0 ];"BAR 0 %pR: legacy IDE quirk\n" ,0 x3F6;0 x3F6;1 ];"BAR 1 %pR: legacy IDE quirk\n" ,if ((progif & 4 ) == 0 ) {0 x170;0 x177;2 ];"BAR 2 %pR: legacy IDE quirk\n" ,0 x376;0 x376;3 ];"BAR 3 %pR: legacy IDE quirk\n" ,break ;case PCI_HEADER_TYPE_BRIDGE: /* bridge header */ /* * The PCI - to - PCI bridge spec requires that subtractive * decoding ( i . e . transparent ) bridge must have programming * interface code of 0 x01 . class & 0 xff) == 1 );2 , PCI_ROM_ADDRESS1);if (pos) {break ;case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */ if (class != PCI_CLASS_BRIDGE_CARDBUS)goto bad;1 , 0 );break ;default : /* unknown header */ "unknown header type %02x, ignoring device\n" ,return -EIO;"ignoring class %#08x (doesn't match header type %02x)\n" ,class , dev->hdr_type);class = PCI_CLASS_NOT_DEFINED << 8 ;/* We found a fine healthy device, go go go... */ return 0 ;static void pci_configure_mps(struct pci_dev *dev)struct pci_dev *bridge = pci_upstream_bridge(dev);int mps, mpss, p_mps, rc;if (!pci_is_pcie(dev))return ;/* MPS and MRRS fields are of type 'RsvdP' for VFs, short-circuit out */ if (dev->is_virtfn)return ;/* * For Root Complex Integrated Endpoints , program the maximum * supported value unless limited by the PCIE_BUS_PEER2PEER case . if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_END) {if (pcie_bus_config == PCIE_BUS_PEER2PEER)128 ;else 128 << dev->pcie_mpss;if (rc) {"can't set Max Payload Size to %d; if necessary, use \" pci=pcie_bus_safe\" and report a bug\n" ,return ;if (!bridge || !pci_is_pcie(bridge))return ;if (mps == p_mps)return ;if (pcie_bus_config == PCIE_BUS_TUNE_OFF) {"Max Payload Size %d, but upstream %s set to %d; if necessary, use \" pci=pcie_bus_safe\" and report a bug\n" ,return ;/* * Fancier MPS configuration is done later by * pcie_bus_configure_settings ( ) if (pcie_bus_config != PCIE_BUS_DEFAULT)return ;128 << dev->pcie_mpss;if (mpss < p_mps && pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT) {"Upstream bridge's Max Payload Size set to %d (was %d, max %d)\n" ,128 << bridge->pcie_mpss);if (rc) {"can't set Max Payload Size to %d; if necessary, use \" pci=pcie_bus_safe\" and report a bug\n" ,return ;"Max Payload Size set to %d (was %d, max %d)\n" ,int pci_configure_extended_tags(struct pci_dev *dev, void *ign)struct pci_host_bridge *host;int ret;if (!pci_is_pcie(dev))return 0 ;if (ret)return 0 ;if (!(cap & PCI_EXP_DEVCAP_EXT_TAG))return 0 ;if (ret)return 0 ;if (!host)return 0 ;/* * If some device in the hierarchy doesn ' t handle Extended Tags * correctly , make sure they ' re disabled . if (host->no_ext_tags) {if (ctl & PCI_EXP_DEVCTL_EXT_TAG) {"disabling Extended Tags\n" );return 0 ;if (!(ctl & PCI_EXP_DEVCTL_EXT_TAG)) {"enabling Extended Tags\n" );return 0 ;/** * pcie_relaxed_ordering_enabled - Probe for PCIe relaxed ordering enable * @ dev : PCI device to query * * Returns true if the device has enabled relaxed ordering attribute . bool pcie_relaxed_ordering_enabled(struct pci_dev *dev)return !!(v & PCI_EXP_DEVCTL_RELAX_EN);static void pci_configure_relaxed_ordering(struct pci_dev *dev)struct pci_dev *root;/* PCI_EXP_DEVCTL_RELAX_EN is RsvdP in VFs */ if (dev->is_virtfn)return ;if (!pcie_relaxed_ordering_enabled(dev))return ;/* * For now , we only deal with Relaxed Ordering issues with Root * Ports . Peer - to - Peer DMA is another can of worms . if (!root)return ;if (root->dev_flags & PCI_DEV_FLAGS_NO_RELAXED_ORDERING) {"Relaxed Ordering disabled because the Root Port didn't support it\n" );static void pci_configure_eetlp_prefix(struct pci_dev *dev)struct pci_dev *bridge;unsigned int eetlp_max;int pcie_type;if (!pci_is_pcie(dev))return ;if (!(cap & PCI_EXP_DEVCAP2_EE_PREFIX))return ;/* 00b means 4 */ 4 ;if (pcie_type == PCI_EXP_TYPE_ROOT_PORT ||else {if (bridge && bridge->eetlp_prefix_max)static void pci_configure_serr(struct pci_dev *dev)if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {/* * A bridge will not forward ERR_ messages coming from an * endpoint unless SERR # forwarding is enabled . if (!(control & PCI_BRIDGE_CTL_SERR)) {static void pci_configure_device(struct pci_dev *dev)static void pci_release_capabilities(struct pci_dev *dev)/** * pci_release_dev - Free a PCI device structure when all users of it are * finished * @ dev : device that ' s been disconnected * * Will be called only by the device core when all users of this PCI device are * done . static void pci_release_dev(struct device *dev)struct pci_dev *pci_dev;"device released\n" );static const struct device_type pci_dev_type = {struct pci_dev *pci_alloc_dev(struct pci_bus *bus)struct pci_dev *dev;sizeof (struct pci_dev), GFP_KERNEL);if (!dev)return NULL;struct resource) {"PCI Exclusive" ,0 ,1 ,#ifdef CONFIG_PCI_MSI#endif return dev;static bool pci_bus_wait_rrs(struct pci_bus *bus, int devfn, u32 *l,int timeout)int delay = 1 ;if (!pci_bus_rrs_vendor_id(*l))return true ; /* not a Configuration RRS completion */ if (!timeout)return false ; /* RRS, but caller doesn't want to wait */ /* * We got the reserved Vendor ID that indicates a completion with * Configuration Request Retry Status ( RRS ) . Retry until we get a * valid Vendor ID or we time out . while (pci_bus_rrs_vendor_id(*l)) {if (delay > timeout) {"pci %04x:%02x:%02x.%d: not ready after %dms; giving up\n" ,1 );return false ;if (delay >= 1000 )"pci %04x:%02x:%02x.%d: not ready after %dms; waiting\n" ,1 );2 ;if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))return false ;if (delay >= 1000 )"pci %04x:%02x:%02x.%d: ready after %dms\n" ,1 );return true ;bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,int timeout)if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))return false ;/* Some broken boards return 0 or ~0 (PCI_ERROR_RESPONSE) if a slot is empty: */ if (PCI_POSSIBLE_ERROR(*l) || *l == 0 x00000000 ||0 x0000ffff || *l == 0 xffff0000)return false ;if (pci_bus_rrs_vendor_id(*l))return pci_bus_wait_rrs(bus, devfn, l, timeout);return true ;bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,int timeout)#ifdef CONFIG_PCI_QUIRKSstruct pci_dev *bridge = bus->self;/* * Certain IDT switches have an issue where they improperly trigger * ACS Source Validation errors on completions for config reads . if (bridge && bridge->vendor == PCI_VENDOR_ID_IDT &&0 x80b5)return pci_idt_bus_quirk(bus, devfn, l, timeout);#endif return pci_bus_generic_read_dev_vendor_id(bus, devfn, l, timeout);#if IS_ENABLED(CONFIG_PCI_PWRCTRL)static struct platform_device *pci_pwrctrl_create_device(struct pci_bus *bus, int devfn)struct pci_host_bridge *host = pci_find_host_bridge(bus);struct platform_device *pdev;struct device_node *np;if (!np)return NULL;if (pdev) {goto err_put_of_node;/* * First check whether the pwrctrl device really needs to be created or * not . This is decided based on at least one of the power supplies * being defined in the devicetree node of the device . if (!of_pci_supply_present(np)) {"PCI/pwrctrl: Skipping OF node: %s\n" , np->name);goto err_put_of_node;/* Now create the pwrctrl device */ if (!pdev) {"PCI/pwrctrl: Failed to create pwrctrl device for node: %s\n" , np->name);goto err_put_of_node;return pdev;return NULL;#else static struct platform_device *pci_pwrctrl_create_device(struct pci_bus *bus, int devfn)return NULL;#endif /* * Read the config data for a PCI device , sanity - check it , * and fill in the dev structure . static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)struct pci_dev *dev;/* * Create pwrctrl device ( if required ) for the PCI device to handle the * power state . If the pwrctrl device is created , then skip scanning * further as the pwrctrl core will rescan the bus after powering on * the device . if (pci_pwrctrl_create_device(bus, devfn))return NULL;if (!pci_bus_read_dev_vendor_id(bus, devfn, &l, 60 *1000 ))return NULL;if (!dev)return NULL;0 xffff;16 ) & 0 xffff;if (pci_setup_device(dev)) {return NULL;return dev;void pcie_report_downtraining(struct pci_dev *dev)if (!pci_is_pcie(dev))return ;/* Look from the device up to avoid downstream ports with no devices */ if ((pci_pcie_type(dev) != PCI_EXP_TYPE_ENDPOINT) &&return ;/* Multi-function PCIe devices share the same link/status */ if (PCI_FUNC(dev->devfn) != 0 || dev->is_virtfn)return ;/* Print link status only if the device is constrained by the fabric */ false );static void pci_imm_ready_init(struct pci_dev *dev)if (status & PCI_STATUS_IMM_READY)1 ;static void pci_init_capabilities(struct pci_dev *dev)/* Enhanced Allocation */ /* Disable MSI */ /* Disable MSI-X */ /* Buffers for saving PCIe and PCI-X capabilities */ /* Immediate Readiness */ /* Power Management */ /* Vital Product Data */ /* Alternative Routing-ID Forwarding */ /* Single Root I/O Virtualization */ /* Address Translation Services */ /* Page Request Interface */ /* Process Address Space ID */ /* Access Control Services */ /* Precision Time Measurement */ /* Advanced Error Reporting */ /* Downstream Port Containment */ /* Root Complex Event Collector */ /* Data Object Exchange */ /* TLP Processing Hints */ /* Resizable BAR */ /* * This is the equivalent of pci_host_bridge_msi_domain ( ) that acts on * devices . Firmware interfaces that can select the MSI domain on a * per - device basis should be called from here . static struct irq_domain *pci_dev_msi_domain(struct pci_dev *dev)struct irq_domain *d;/* * If a domain has been set through the pcibios_device_add ( ) * callback , then this is the one ( platform code knows best ) . if (d)return d;/* * Let ' s see if we have a firmware interface able to provide * the domain . if (d)return d;return NULL;static void pci_set_msi_domain(struct pci_dev *dev)struct irq_domain *d;/* * If the platform or firmware interfaces cannot supply a * device - specific MSI domain , then inherit the default domain * from the host bridge itself . if (!d)void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)int ret;0 xffffffffull;65536 );0 xffffffff);/* Fix up broken headers */ false ;/* * Add the device to our list of discovered devices * and the bus list for fixup functions , etc . 0 );/* Set up MSI IRQ domain */ /* Notifier could use PCI capabilities */ 0 );struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn)struct pci_dev *dev;if (dev) {return dev;if (!dev)return NULL;return dev;static int next_ari_fn(struct pci_bus *bus, struct pci_dev *dev, int fn)int pos;0 ;unsigned int next_fn;if (!dev)return -ENODEV;if (!pos)return -ENODEV;if (next_fn <= fn)return -ENODEV; /* protect against malformed list */ return next_fn;static int next_fn(struct pci_bus *bus, struct pci_dev *dev, int fn)if (pci_ari_enabled(bus))return next_ari_fn(bus, dev, fn);if (fn >= 7 )return -ENODEV;/* only multifunction devices may have more functions */ if (dev && !dev->multifunction)return -ENODEV;return fn + 1 ;static int only_one_child(struct pci_bus *bus)struct pci_dev *bridge = bus->self;/* * Systems with unusual topologies set PCI_SCAN_ALL_PCIE_DEVS so * we scan for all possible devices , not just Device 0 . if (pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS))return 0 ;/* * A PCIe Downstream Port normally leads to a Link with only Device * 0 on it ( PCIe spec r3 . 1 , sec 7 . 3 . 1 ) . As an optimization , scan * only for Device 0 in that situation . if (bridge && pci_is_pcie(bridge) && pcie_downstream_port(bridge))return 1 ;return 0 ;/** * pci_scan_slot - Scan a PCI slot on a bus for devices * @ bus : PCI bus to scan * @ devfn : slot number to scan ( must have zero function ) * * Scan a PCI slot on the specified PCI bus for devices , adding * discovered devices to the @ bus - > devices list . New devices * will not have is_added set . * * Returns the number of new devices found . int pci_scan_slot(struct pci_bus *bus, int devfn)struct pci_dev *dev;int fn = 0 , nr = 0 ;if (only_one_child(bus) && (devfn > 0 ))return 0 ; /* Already scanned the entire slot */ do {if (dev) {if (!pci_dev_is_added(dev))if (fn > 0 )1 ;else if (fn == 0 ) {/* * Function 0 is required unless we are running on * a hypervisor that passes through individual PCI * functions . if (!hypervisor_isolated_pci_functions())break ;while (fn >= 0 );/* Only one slot has PCIe device */ if (bus->self && nr)return nr;static int pcie_find_smpss(struct pci_dev *dev, void *data)if (!pci_is_pcie(dev))return 0 ;/* * We don ' t have a way to change MPS settings on devices that have * drivers attached . A hot - added device might support only the minimum * MPS setting ( MPS = 128 ) . Therefore , if the fabric contains a bridge * where devices may be hot - added , we limit the fabric MPS to 128 so * hot - added devices will work correctly . * * However , if we hot - add a device to a slot directly below a Root * Port , it ' s impossible for there to be other existing devices below * the port . We don ' t limit the MPS in this case because we can * reconfigure MPS on both the Root Port and the hot - added device , * and there are no other devices involved . * * Note that this PCIE_BUS_SAFE path assumes no peer - to - peer DMA . if (dev->is_hotplug_bridge &&0 ;if (*smpss > dev->pcie_mpss)return 0 ;static void pcie_write_mps(struct pci_dev *dev, int mps)int rc;if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {128 << dev->pcie_mpss;if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT &&/* * For " Performance " , the assumption is made that * downstream communication will never be larger than * the MRRS . So , the MPS only needs to be configured * for the upstream communication . This being the case , * walk from the top down and set the MPS of the child * to that of the parent bus . * * Configure the device MPS with the smaller of the * device MPSS or the bridge MPS ( which is assumed to be * properly configured at this point to the largest * allowable MPS based on its parent bus ) . if (rc)"Failed attempting to set the MPS\n" );static void pcie_write_mrrs(struct pci_dev *dev)int rc, mrrs;/* * In the " safe " case , do not configure the MRRS . There appear to be * issues with setting MRRS to 0 on a number of devices . if (pcie_bus_config != PCIE_BUS_PERFORMANCE)return ;/* * For max performance , the MRRS must be set to the largest supported * value . However , it cannot be configured larger than the MPS the * device or the bus can support . This should already be properly * configured by a prior call to pcie_write_mps ( ) . /* * MRRS is a R / W register . Invalid values can be written , but a * subsequent read will verify if the value is acceptable or not . * If the MRRS value provided is not acceptable ( e . g . , too large ) , * shrink the value until it is acceptable to the HW . while (mrrs != pcie_get_readrq(dev) && mrrs >= 128 ) {if (!rc)break ;"Failed attempting to set the MRRS\n" );2 ;if (mrrs < 128 )"MRRS was unable to be configured with a safe value. If problems are experienced, try running with pci=pcie_bus_safe\n" );static int pcie_bus_configure_set(struct pci_dev *dev, void *data)int mps, orig_mps;if (!pci_is_pcie(dev))return 0 ;if (pcie_bus_config == PCIE_BUS_TUNE_OFF ||return 0 ;128 << *(u8 *)data;"Max Payload Size set to %4d/%4d (was %4d), Max Read Rq %4d\n" ,128 << dev->pcie_mpss,return 0 ;/* * pcie_bus_configure_settings ( ) requires that pci_walk_bus work in a top - down , * parents then children fashion . If this changes , then this code will not * work as designed . void pcie_bus_configure_settings(struct pci_bus *bus)0 ;if (!bus->self)return ;if (!pci_is_pcie(bus->self))return ;/* * FIXME - Peer to peer DMA is possible , though the endpoint would need * to be aware of the MPS of the destination . To work around this , * simply force the MPS of the entire system to the smallest possible . if (pcie_bus_config == PCIE_BUS_PEER2PEER)0 ;if (pcie_bus_config == PCIE_BUS_SAFE) {/* * Called after each bus is probed , but before its children are examined . This * is marked as _ _ weak because multiple architectures define it . void __weak pcibios_fixup_bus(struct pci_bus *bus)/* nothing to do, expected to be removed in the future */ /** * pci_scan_child_bus_extend ( ) - Scan devices below a bus * @ bus : Bus to scan for devices * @ available_buses : Total number of buses available ( % 0 does not try to * extend beyond the minimal ) * * Scans devices below @ bus including subordinate buses . Returns new * subordinate number including all the found devices . Passing * @ available_buses causes the remaining bus space to be distributed * equally between hotplug - capable bridges to allow future extension of the * hierarchy . static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus,unsigned int available_buses)unsigned int used_buses, normal_bridges = 0 , hotplug_bridges = 0 ;unsigned int start = bus->busn_res.start;unsigned int devfn, cmax, max = start;struct pci_dev *dev;"scanning bus\n" );/* Go find them, Rover! */ for (devfn = 0 ; devfn < 256 ; devfn += 8 )/* Reserve buses for SR-IOV capability */ /* * After performing arch - dependent fixup of the bus , look behind * all PCI - to - PCI bridges on this bus . if (!bus->is_added) {"fixups for bus\n" );1 ;/* * Calculate how many hotplug bridges and normal bridges there * are on this bus . We will distribute the additional available * buses between hotplug bridges . if (dev->is_hotplug_bridge)else /* * Scan bridges that are already configured . We don ' t touch them * unless they are misconfigured ( which will be done in the second * scan below ) . 0 , 0 );/* * Reserve one bus for each bridge now to avoid extending * hotplug bridges too much during the second scan below . if (max - cmax > 1 )1 ;/* Scan bridges that need to be reconfigured */ unsigned int buses = 0 ;if (!hotplug_bridges && normal_bridges == 1 ) {/* * There is only one bridge on the bus ( upstream * port ) so it gets all available buses which it * can then distribute to the possible hotplug * bridges below . else if (dev->is_hotplug_bridge) {/* * Distribute the extra buses between hotplug * bridges if any . 1 );1 );/* One bus is already accounted so don't add it again */ if (max - cmax > 1 )1 ;/* * Make sure a hotplug bridge has at least the minimum requested * number of buses but allow it to grow up to the maximum available * bus number if there is room . if (bus->self && bus->self->is_hotplug_bridge) {unsigned int , available_buses,1 );if (max - start < used_buses) {/* Do not allocate more buses than we have room left */ if (max > bus->busn_res.end)"%pR extended by %#02x\n" ,/* * We ' ve scanned the bus and so we know all about what ' s on * the other side of any bridges that may be on this bus plus * any devices . * * Return how far we ' ve got finding sub - buses . "bus scan returning with max=%02x\n" , max);return max;/** * pci_scan_child_bus ( ) - Scan devices below a bus * @ bus : Bus to scan for devices * * Scans devices below @ bus including subordinate buses . Returns new * subordinate number including all the found devices . unsigned int pci_scan_child_bus(struct pci_bus *bus)return pci_scan_child_bus_extend(bus, 0 );/** * pcibios_root_bridge_prepare - Platform - specific host bridge setup * @ bridge : Host bridge to set up * * Default empty implementation . Replace with an architecture - specific setup * routine , if necessary . int __weak pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)return 0 ;void __weak pcibios_add_bus(struct pci_bus *bus)void __weak pcibios_remove_bus(struct pci_bus *bus)struct pci_bus *pci_create_root_bus(struct device *parent, int bus,struct pci_ops *ops, void *sysdata, struct list_head *resources)int error;struct pci_host_bridge *bridge;0 );if (!bridge)return NULL;if (error < 0 )goto err_out;return bridge->bus;return NULL;int pci_host_probe(struct pci_host_bridge *bridge)struct pci_bus *bus, *child;int ret;if (ret < 0 ) {"Scanning root bridge failed" );return ret;/* If we must preserve the resource configuration, claim now */ if (bridge->preserve_config)/* * Assign whatever was left unassigned . If we didn ' t claim above , * this will reassign everything . /* * Ensure pm_runtime_enable ( ) is called for the controller drivers * before calling pci_host_probe ( ) . The PM framework expects that * if the parent device supports runtime PM , it will be enabled * before child runtime PM is enabled . return 0 ;int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int bus_max)struct resource *res = &b->busn_res;struct resource *parent_res, *conflict;if (!pci_is_root_bus(b))else {if (conflict)"busn_res: can not insert %pR under %s%pR (conflicts with %s %pR)\n" ,"domain " : "" ,return conflict == NULL;int pci_bus_update_busn_res_end(struct pci_bus *b, int bus_max)struct resource *res = &b->busn_res;struct resource old_res = *res;int ret;if (res->start > bus_max)return -EINVAL;1 ;"busn_res: %pR end %s updated to %02x\n" ,"can not be" : "is" , bus_max);if (!ret && !res->parent)return ret;void pci_bus_release_busn_res(struct pci_bus *b)struct resource *res = &b->busn_res;int ret;if (!res->flags || !res->parent)return ;"busn_res: %pR %s released\n" ,"can not be" : "is" );int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge)struct resource_entry *window;bool found = false ;struct pci_bus *b;int max, bus, ret;if (!bridge)return -EINVAL;if (window->res->flags & IORESOURCE_BUS) {true ;break ;if (ret < 0 )return ret;if (!found) {"No busn resource found for root bus, will use [bus %02x-ff]\n" ,255 );if (!found)return 0 ;struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,struct pci_ops *ops, void *sysdata, struct list_head *resources)struct resource_entry *window;bool found = false ;struct pci_bus *b;int max;if (window->res->flags & IORESOURCE_BUS) {true ;break ;if (!b)return NULL;if (!found) {"No busn resource found for root bus, will use [bus %02x-ff]\n" ,255 );if (!found)return b;struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops,void *sysdata)struct pci_bus *b;if (b) {else {return b;/** * pci_rescan_bus_bridge_resize - Scan a PCI bus for devices * @ bridge : PCI bridge for the bus to scan * * Scan a PCI bus and child buses for new devices , add them , * and enable them , resizing bridge mmio / io resource if necessary * and possible . The caller must ensure the child devices are already * removed for resizing to occur . * * Returns the max number of subordinate bus discovered . unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge)unsigned int max;struct pci_bus *bus = bridge->subordinate;return max;/** * pci_rescan_bus - Scan a PCI bus for devices * @ bus : PCI bus to scan * * Scan a PCI bus and child buses for new devices , add them , * and enable them . * * Returns the max number of subordinate bus discovered . unsigned int pci_rescan_bus(struct pci_bus *bus)unsigned int max;return max;/* * pci_rescan_bus ( ) , pci_rescan_bus_bridge_resize ( ) and PCI device removal * routines should always be executed under this mutex . static DEFINE_MUTEX(pci_rescan_remove_lock);void pci_lock_rescan_remove(void )void pci_unlock_rescan_remove(void )static int __init pci_sort_bf_cmp(const struct device *d_a,const struct device *d_b)const struct pci_dev *a = to_pci_dev(d_a);const struct pci_dev *b = to_pci_dev(d_b);if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1 ;else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1 ;if (a->bus->number < b->bus->number) return -1 ;else if (a->bus->number > b->bus->number) return 1 ;if (a->devfn < b->devfn) return -1 ;else if (a->devfn > b->devfn) return 1 ;return 0 ;void __init pci_sort_breadthfirst(void )int pci_hp_add_bridge(struct pci_dev *dev)struct pci_bus *parent = dev->bus;int busnr, start = parent->busn_res.start;unsigned int available_buses = 0 ;int end = parent->busn_res.end;for (busnr = start; busnr <= end; busnr++) {if (!pci_find_bus(pci_domain_nr(parent), busnr))break ;if (busnr-- > end) {"No bus number available for hot-added bridge\n" );return -1 ;/* Scan bridges that are already configured */ 0 );/* * Distribute the available bus numbers between hotplug - capable * bridges to make extending the chain later possible . /* Scan bridges that need to be reconfigured */ 1 );if (!dev->subordinate)return -1 ;return 0 ;
Messung V0.5 in Prozent C=94 H=94 G=93
¤ Die Informationen auf dieser Webseite wurden
nach bestem Wissen sorgfältig zusammengestellt. Es wird jedoch weder Vollständigkeit, noch Richtigkeit,
noch Qualität der bereit gestellten Informationen zugesichert.0.139Bemerkung:
(vorverarbeitet am 2026-09-29)
¤ *Bot Zugriff
