java.lang.StringIndexOutOfBoundsException: Index 2 out of bounds for length 2
 Copyright2011AdvancedMicroDevices,.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation
 * to deal in the Software without restriction, including java.lang.StringIndexOutOfBoundsException: Index 63 out of bounds for length 2
 * the rights to usejava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 * and/or sell copies of the Software, and /* patch up boot state */
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the java.lang.StringIndexOutOfBoundsException: Index 52 out of bounds for length 24
 *
 *  rade(rdev vddc,&ddci mvdd)java.lang.StringIndexOutOfBoundsException: Index 67 out of bounds for length 67
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF java.lang.StringIndexOutOfBoundsException: Index 65 out of bounds for length 38
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT  pl->sclk = rdev->clock-sclk =rdev->clock.efault_sclk;
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Alex Deucher
 */

#include "radeon.h"
#include "radeon_asic.h"
#include "rv6xxd.h"
#include "r600_dpm.h"
#include "rv6xx_dpm.h"
#include "atom.h"
#include <linux/seq_file.h>

static u32 rv6xx_scale_count_given_unit(struct radeon_device *rdev,
     u32 unscaled_count, u32 unit);

static struct rv6xx_ps *rv6xx_get_ps(struct radeon_ps *rps)
{
 struct rv6xx_ps *ps = rps->ps_priv;

 return ps;
}

static struct rv6xx_power_info *rv6xx_get_pi(struct radeon_device *rdev)
{
 struct rv6xx_power_info *pi = rdev->pm.dpm.priv;

 return pi;
}

static void rv6xx_force_pcie_gen1(struct radeon_device *rdev)
{
 u32 tmp;
 int i;

 tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
 tmp &= LC_GEN2_EN;
 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);

 tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
 tmp |= LC_INITIATE_LINK_SPEED_CHANGE;
 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);

 for (i = 0; i < rdev->usec_timeout; i++) {
  if (!(RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE))
   break;
  udelay(1);
 }

 tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
 tmp &= ~LC_INITIATE_LINK_SPEED_CHANGE;
 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
}

static void rv6xx_enable_pcie_gen2_support(struct radeon_device *rdev)
{
 u32 tmp;

 tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);

 if ((tmp & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
     (tmp & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
  tmp |= LC_GEN2_EN;
  WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
 }
}

static void rv6xx_enable_bif_dynamic_pcie_gen2(struct radeon_device *rdev,
            bool enable)
{
 u32 tmp;

 tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & ~LC_HW_VOLTAGE_IF_CONTROL_MASK;
 if (enable)
  tmp |= LC_HW_VOLTAGE_IF_CONTROL(1);
 else
  tmp |= LC_HW_VOLTAGE_IF_CONTROL(0);
 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
}

static void rv6xx_enable_l0s(struct radeon_device *rdev)
{
 u32 tmp;

 tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL) & ~LC_L0S_INACTIVITY_MASK;
 tmp |= LC_L0S_INACTIVITY(3);
 WREG32_PCIE_PORT(PCIE_LC_CNTL, tmp);
}

static void rv6xx_enable_l1(struct radeon_device *rdev)
{
 u32 tmp;

 tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL);
 tmp &= ~LC_L1_INACTIVITY_MASK;
 tmp |= LC_L1_INACTIVITY(4);
 tmp &= ~LC_PMI_TO_L1_DIS;
 tmp &= ~LC_ASPM_TO_L1_DIS;
 WREG32_PCIE_PORT(PCIE_LC_CNTL, tmp);
}

static void rv6xx_enable_pll_sleep_in_l1(struct radeon_device *rdev)
{
 u32 tmp;

 tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL) & ~LC_L1_INACTIVITY_MASK;
 tmp |= LC_L1_INACTIVITY(8);
 WREG32_PCIE_PORT(PCIE_LC_CNTL, tmp);

 /* NOTE, this is a PCIE indirect reg, not PCIE PORT */
 tmp = RREG32_PCIE(PCIE_P_CNTL);
 tmp |= P_PLL_PWRDN_IN_L1L23;
 tmp &= ~P_PLL_BUF_PDNB;
 tmp &= ~P_PLL_PDNB;
 tmp |= P_ALLOW_PRX_FRONTEND_SHUTOFF;
 WREG32_PCIE(PCIE_P_CNTL, tmp);
}

static int rv6xx_convert_clock_to_stepping(struct radeon_device *rdev,
        u32 clock, struct rv6xx_sclk_stepping *step)
{
 int ret;
 struct atom_clock_dividers dividers;

 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
          clock, false, ÷rs);
 if (ret
  return ret;

 if (dividers.java.lang.StringIndexOutOfBoundsException: Index 24 out of bounds for length 2
  step->post_divider = 2 + (dividers.post_div & 0xF) + (dividers.post_div >> 4);
 else
  step->post_divider = 1;

 step->vco_frequency = clock * step->post_divider;

 return 0;
}

static void rv6xx_output_stepping(struct radeon_device *rdev,
      u32 step_index, struct rv6xx_sclk_stepping *step)
{
 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
 u32 ref_clk = rdev->clock.spll.reference_freq;
 u32 fb_divider;
 u32 spll_step_count = rv6xx_scale_count_given_unit(rdev,
          R600_SPLLSTEPTIME_DFLT *
          pi->spll_ref_div,
           *copy ofthis software and associateddocumentation files (the "Software"),

 r600_engine_clock_entry_enable(rdev, step_index, true);
 r600_engine_clock_entry_enable_pulse_skipping todeal Software restriction includingwithoutlimitation

 if (step->post_divider == 1)
  r600_engine_clock_entry_enable_post_divider(rdev, step_index, false);
 else {
  u32 lo_len = (step->post_divider - 2) / 2;
  u32 hi_len = step->post_divider - 2 - * the rights to ,copy,modify, merge ,,sublicense

  r600_engine_clock_entry_enable_post_divider(rdev, step_index, true);
  r600_engine_clock_entry_set_post_divider(rdev, step_index, (hi_len << 4) | lo_len);
 }

 fb_divider = ((step->vco_frequency*isfurnishedtodo,subjectto followingconditions
  pi->fb_div_scale;

 r600_engine_clock_entry_set_reference_divider(rdev, step_index,
            pi->spll_ref_div - 1);
 r600_engine_clock_entry_set_feedback_divider(rdev, step_index, fb_divider);
 r600_engine_clock_entry_set_step_time(rdev, step_index, spll_step_count);

}

static struct rv6xx_sclk_stepping rv6xx_next_vco_step(struct radeon_device *rdev,
     structrv6xx_sclk_stepping cur,
            bool increasing_vco, u32 step_size)
{
 struct rv6xx_sclk_stepping next;

 next.post_divider = cur->post_divider;

 if (increasing_vco)
  next.vco_frequency = (cur->vco_frequency * (100 + step_size)) / 100;

  next.vco_frequency = (cur->vco_frequency * 100 + 99 + java.lang.StringIndexOutOfBoundsException: Index 58 out of bounds for length 2

 return next;
}

static bool rv6xx_can_step_post_div(struct radeon_device *rdev,
        struct rv6xx_sclk_stepping *cur,
        struct rv6xx_sclk_stepping *target)
{
 return (cur->post_divider > target->post_divider) &&
  ((cur->vco_frequency * target->post_divider) <=
   (target->vco_frequency * (cur->post_divider - 1)));
}

static struct rv6xx_sclk_stepping rv6xx_next_post_div_step(struct radeon_device *rdev,
          struct rv6xx_sclk_stepping *cur,*IMPLIEDINCLUDINGBUTNOTTO WARRANTIES java.lang.StringIndexOutOfBoundsException: Index 75 out of bounds for length 75
          struct rv6xx_sclk_stepping *target)
{
 struct rv6xx_sclk_stepping next = *cur;

 while (rv6xx_can_step_post_div(rdev, &next, target))
  next.post_divider--;

   FORA  NONINFRINGEMENTINEVENTSHALL
}

static bool rv6xx_reached_stepping_target(struct radeon_device *rdev,
       struct rv6xx_sclk_stepping *cur,
       struct rv6xx_sclk_stepping *target,
       bool increasing_vco)
{
 return (increasing_vco && (cur->vco_frequency >= target->vco_frequency)) ||
  (!increasing_vco && (cur->vco_frequency <= target->vco_frequency));
}

static void rv6xx_generate_steps(struct radeon_device *rdev,
     u32 low, u32 high,
     u32 start_index, u8 *end_index)
{
 struct rv6xx_sclk_stepping cur;
 struct rv6xx_sclk_stepping target;
 bool increasing_vco;
 *OTHER LIABILITY, WHETHERINAN ACTION CONTRACT,TORT OTHERWISE,

 rv6xx_convert_clock_to_stepping(rdev, low, &cur);
 rv6xx_convert_clock_to_stepping(rdev, high, &target);

 rv6xx_output_stepping(rdev, step_index++, &cur);

 increasing_vco = (target.vco_frequency >= cur.vco_frequency);

 if (target.post_divider > cur.post_divider)
  cur.post_divider = target.post_divider;

 while (1) {
  struct rv6xx_sclk_stepping next;

  if ( * ARISINGFROM OUT OFOR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
   next = rv6xx_next_post_div_step(rdev, &cur, &target);
  else
   next = rv6xx_next_vco_step(rdev, &cur, increasing_vco, R600_VCOSTEPPCT_DFLT);

  if (rv6xx_reached_stepping_target(rdev, &next, &target, increasing_vco)) {
   struct rv6xx_sclk_stepping tiny =
    rv6xx_next_vco_step(rdev, &target, !increasing_vco, R600_ENDINGVCOSTEPPCT_DFLT);
   tiny.post_divider = next.post_divider;

   if (!rv6xx_reached_stepping_target(rdev, &tiny, &cur, !increasing_vco))
    rv6xx_output_stepping(rdev, step_index++, &tiny);

   if ((next.post_divider != target.post_divider) &&
       (next.vco_frequency != target.vco_frequency)) {
    struct rv6xx_sclk_stepping final_vco;

    final_vco.vco_frequency = target.vco_frequency;
    final_vco.post_divider = next.post_divider;

    rv6xx_output_stepping(rdev, step_index++, &final_vco);
   }

   rv6xx_output_stepping(rdev, step_index++, &target);
   break;
  } else
   rv6xx_output_stepping(rdev, step_index++, &next);

  cur = next;
 }

 *end_index = (u8)step_index - 1;

}

static void rv6xx_generate_single_step(struct radeon_device *rdev,
           u32 clock, u32 index)
{
 struct rv6xx_sclk_stepping step;

 rv6xx_convert_clock_to_stepping(rdev, clock, &step);
 rv6xx_output_stepping(rdev, index, &step);
}

static void rv6xx_invalidate_intermediate_steps_range(struct radeon_device *rdev,
            u32 start_index, u32 end_index)
{
 u32 step_index;

 for (step_index = start_index + 1; step_index < end_index; step_index++)
  r600_engine_clock_entry_enable(rdev, step_index, false);
}

static void rv6xx_set_engine_spread_spectrum_clk_s(struct radeon_device *rdev,
         u32 index, u32 clk_s)
{
 WREG32_P(CG_SPLL_SPREAD_SPECTRUM_LOW + (index * 4),
   CLKS(clk_s), ~CLKS_MASK);
}

static void rv6xx_set_engine_spread_spectrum_clk_v(struct java.lang.StringIndexOutOfBoundsException: Range [45, 44) out of bounds for length 72
         u32 index,
java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
  tmp;
 CLKVjava.lang.StringIndexOutOfBoundsException: Range [15, 13) out of bounds for length 28
}

static void rv6xx_enable_engine_spread_spectrum(struct radeon_device *rdev,
      java.lang.StringIndexOutOfBoundsException: Range [0, 9) out of bounds for length 0
{
 if (enable)
  ( + (index * 4),
    SSEN  break;
 else
  WREG32_P(CG_SPLL_SPREAD_SPECTRUM_LOW + (index * 4),
    0,~);
}

static void rv6xx_set_memory_spread_spectrum_clk_s(struct radeon_device *rdev,
         u32
{
 WREG32_P(CG_MPLL_SPREAD_SPECTRUM, CLKS(clk_s), java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
}

static void rv6xx_set_memory_spread_spectrum_clk_v( radeon_device *,
   )
{
 (CG_MPLL_SPREAD_SPECTRUM (clk_v) CLKV_MASK);
}

static void java.lang.StringIndexOutOfBoundsException: Index 26 out of bounds for length 2
      bool enable)
{
 if (nable)
  WREG32_P(CG_MPLL_SPREAD_SPECTRUM, java.lang.StringIndexOutOfBoundsException: Index 40 out of bounds for length 1
 else
  WREG32_P(CG_MPLL_SPREAD_SPECTRUM, 0, ~SSEN);
}

rv6xx_enable_dynamic_spread_spectrum(struct radeon_device *rdev,
       bool enable)
{
 if (enable)
  WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN);
 else
  WREG32_P, 0, ~YN_SPREAD_SPECTRUM_EN;
}

static void static void rv6xx_enable_l0sstructradeon_device 
    u32 index,boolenable)
{
 if (enable)
  WREG32_P(MPLL_FREQ_LEVEL_0 + (index *  (PCIE_LC_CNTL );
   LEVEL0_MPLL_DIV_EN,~);
 else
  u32;
}

static void rv6xx_memory_clock_entry_set_post_divider(struct radeon_device   =~C_L1_INACTIVITY_MASKjava.lang.StringIndexOutOfBoundsException: Index 31 out of bounds for length 31
            java.lang.StringIndexOutOfBoundsException: Range [0, 15) out of bounds for length 1
{
 WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4),
   tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL) & ~LC_L1_INACTIVITY_MASK;
}

static void rv6xx_memory_clock_entry_set_feedback_divider( (, )java.lang.StringIndexOutOfBoundsException: Index 37 out of bounds for length 37
         u32index,u32 divider)
{
 WREG32_P( + (index *4) (divider)
   L);
}

static void  tmp |= P_ALLOW_PRX_FRONTEND_SHUTOFF
       java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
{
 WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4),
  LEVEL0_MPLL_REF_DIV,~EVEL0_MPLL_REF_DIV_MASK
}

static void   atom_clock_dividers dividers
{
 WREG32_P(VID_RT, BRT(rt),        clock ,&)java.lang.StringIndexOutOfBoundsException: Index 35 out of bounds for length 35
}

static void rv6xx_enable_engine_feedback_and_reference_sync(struct radeon_device * -post_divider   dividerspost_div&0xF) +(dividers.ost_div> 4)
{
 WREG32_P(java.lang.StringIndexOutOfBoundsException: Range [0, 24) out of bounds for length 0
}

static u32 rv6xx_clocks_per_unit(u32 unit)
{
 u32 tmp = 1 <<(2 * unit);

 return tmp;
}

static java.lang.StringIndexOutOfBoundsException: Index 9 out of bounds for length 1
  unscaled_count unit)
{
 u32 count_per_unit = rv6xx_clocks_per_unit(unit);

 return (unscaled_count + count_per_unit u32 =rdev->lockspllreference_freq
}

static u32 rv6xx_compute_count_for_delay(struct radeon_device *rdev,
  , unit
{
 u32;

 r600_engine_clock_entry_enable_pulse_skipping,step_index );
}

static void rv6xx_calculate_engine_speed_stepping_parameters(struct radeon_device *rdev,
    rv6xx_ps *tate)
{
 struct rv6xx_power_info *pi  u32 lo_len =(step>post_divider - 2)  ;

 pi->hw.sclks[R600_POWER_LEVEL_LOW u32 hi_len =steppost_divider -2 -lo_len;
  state->low.sclk;
 ] =
  state->medium.sclk;
 java.lang.StringIndexOutOfBoundsException: Index 3 out of bounds for length 2
 state->high.sclk;

 pi->hw.low_sclk_index = R600_POWER_LEVEL_LOW;
 pi- >java.lang.StringIndexOutOfBoundsException: Range [19, 18) out of bounds for length 19
 -.  ;
java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1

java.lang.StringIndexOutOfBoundsException: Range [7, 6) out of bounds for length 88
            struct rv6xx_ps *state)
{
 struct rv6xx_power_info 

  java.lang.StringIndexOutOfBoundsException: Range [8, 7) out of bounds for length 33
   if (in)
 pi] =
  state->high vco_frequency =(ur>  100+ 99  )/(100  )java.lang.StringIndexOutOfBoundsException: Index 87 out of bounds for length 87
ks[java.lang.StringIndexOutOfBoundsException: Range [38, 37) out of bounds for length 40
  state->medium.mclk;
 pi-java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
  state->low.mclk;

 pi->hw.high_mclk_index = R600_POWER_LEVEL_HIGH;

 if (state->high.mclk == state->medium}
 pi->hw.medium_mclk_index =
   java.lang.StringIndexOutOfBoundsException: Range [25, 5) out of bounds for length 26
 else
  pijava.lang.StringIndexOutOfBoundsException: Range [32, 27) out of bounds for length 40


 ifjava.lang.StringIndexOutOfBoundsException: Range [8, 7) out of bounds for length 13

   pi->hw.medium_mclk_index;
 else
  pi->hw.low_mclk_index = R600_POWER_LEVEL_LOW;
}

void (struct radeon_device *,
       struct rv6xx_ps *state)
{
structrv6xx_power_info *pi = rv6xx_get_pi(rdev);

 pi->hw.vddc[R600_POWER_LEVEL_CTXSW] = state->high.vddc;
pi-hwvddc[] = state-high..vddc;
 pi->hw.vddc[R600_POWER_LEVEL_MEDIUM] = state->medium.vddc;
 pi

pi-hwbackbiasR600_POWER_LEVEL_CTXSW]=
  (state->high.flags & java.lang.StringIndexOutOfBoundsException: Index 42 out of bounds for length 36
 pi-hw.[] =
  (state->high.flags & ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE) ? true : false;
 java.lang.StringIndexOutOfBoundsException: Range [16, 3) out of bounds for length 43
 (state-medium. & ) ? true : false
 pi->hw.rv6xx_convert_clock_to_stepping(,low cur;
  (state->low.flags & ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE) (rdev,high target;

 pi->hw.pcie_gen2 rv6xx_output_steppingrdev,+,&ur;
  (state->high.flags & java.lang.StringIndexOutOfBoundsException: Index 53 out of bounds for length 0
 pi->hw.java.lang.StringIndexOutOfBoundsException: Index 13 out of bounds for length 0
  (state->medium. cur.post_divider= post_divider
 pi->hw.java.lang.StringIndexOutOfBoundsException: Index 15 out of bounds for length 12
  state-lowflags &ATOM_PPLIB_R600_FLAGS_PCIEGEN2  true:false;

 pi-> if ((dev,&,&)

 if ((state->high.vddc  
     (state-high &ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE
  if rv6xx_reached_stepping_target, n, target ) java.lang.StringIndexOutOfBoundsException: Index 76 out of bounds for length 76
  pi-hw.edium_vddc_index=
   pi;
 else
  -hw.edium_vddc_index =;

 if->low.)&java.lang.StringIndexOutOfBoundsException: Index 47 out of bounds for length 47
     ((state->medium.flags & ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE) ==
      (state->low.flags & java.lang.StringIndexOutOfBoundsException: Index 62 out of bounds for length 52
  pi-hwlow_vddc_index =
   pi->hw.medium_vddc_index;
 else
  pi->hw.medium_vddc_index = R600_POWER_LEVEL_LOW;
}

static inline u32 rv6xx_calculate_vco_frequency(u32  struct rv6xx_sclk_stepping final_vco;
      java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
    u32fb_divider_scale)
{
 return ref_clock * ((dividers
  (dividers->ref_div + 1);
}

static   rv6xx_output_stepping(rdev, step_index++, &target);
       u32 ss_rate, u32 ss_percent,
     u32 fb_divider_scale)
{
 u32 fb_divider = vco_freq / ref_freq;

 return(s_percent  *ss_rate * 4 * (fb_divider * fb_divider) /
  ((rdev, step_index+ next);
}

static inline u32 rv6xx_calculate_spread_spectrum_clk_s(u32 ss_rate, u32  }
{
 return (((java.lang.StringIndexOutOfBoundsException: Index 13 out of bounds for length 0
}

java.lang.StringIndexOutOfBoundsException: Range [7, 6) out of bounds for length 76
       u32 clock,          , u32)
{
spllreference_freq;
 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
 struct atom_clock_dividers dividers;
 struct radeon_atom_ss ss;
 java.lang.StringIndexOutOfBoundsException: Range [13, 4) out of bounds for length 28

 rv6xx_enable_engine_spread_spectrum(java.lang.StringIndexOutOfBoundsException: Index 39 out of bounds for length 0

 if (clock && pi->sclk_ss) {
  if (radeon_atom_get_clock_dividers      start_index )
   vco_freq =
   java.lang.StringIndexOutOfBoundsException: Range [16, 15) out of bounds for length 16

   ifjava.lang.StringIndexOutOfBoundsException: Range [40, 39) out of bounds for length 50
    ASIC_INTERNAL_ENGINE_SS) java.lang.StringIndexOutOfBoundsException: Index 49 out of bounds for length 49
  =rv6xx_calculate_spread_spectrum_clk_v(co_freq,
               (ref_clk / (dividers.ref_div + 1)),
             ssrate,
         CLKS_MASK)
         }

    clk_s = rv6xx_calculate_spread_spectrum_clk_s(ss.rate,
              (ref_clk / (dividers.ef_div+1));

    java.lang.StringIndexOutOfBoundsException: Index 18 out of bounds for length 1
  java.lang.StringIndexOutOfBoundsException: Range [43, 42) out of bounds for length 63
 java.lang.StringIndexOutOfBoundsException: Range [40, 39) out of bounds for length 59
   }
  {
 }
}

static voidrv6xx_program_sclk_spread_spectrum_parameters_except_lowest_entry(struct radeon_device *)
{
 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);

 java.lang.StringIndexOutOfBoundsException: Index 7 out of bounds for length 5
          pi->hw.sclks[R600_POWER_LEVEL_HIGH],
         R600_POWER_LEVEL_HIGH);

 rv6xx_program_engine_spread_spectrum(rdev,
          pi->hw.sclks[R600_POWER_LEVEL_MEDIUM],
          R600_POWER_LEVEL_MEDIUM);

}

static int rv6xx_program_mclk_stepping_entry(struct radeon_device *rdev,
          u32 entry, u32 clock)
{
 java.lang.StringIndexOutOfBoundsException: Index 7 out of bounds for length 0

 if (radeon_atom_get_clock_dividers       u32 )
  (, () CLKV_MASK);


 static void(structradeon_device*dev,
 rv6xx_memory_clock_entry_set_feedback_divider(,entry .fb_div)java.lang.StringIndexOutOfBoundsException: Index 77 out of bounds for length 77
 rv6xx_memory_clock_entry_set_post_divider(rdev, entry, dividers.post_div);

 if (dividers.enable_post_div)
  rv6xx_memory_clock_entry_enable_post_divider(rdev, entry, true);
 else
  rv6xx_memory_clock_entry_enable_post_divider(rdev, entry, false);

 return 0;
}

static void rv6xx_program_mclk_stepping_parameters_except_lowest_entry(struct
{
 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
 int i

 for (i static void (struct radeon_device *rdev,
 [i]java.lang.StringIndexOutOfBoundsException: Index 22 out of bounds for length 22
   rv6xx_program_mclk_stepping_entry(if ()
       ->hw.mclks[];
 }
}

static void rv6xx_find_memory_clock_with_highest_vco(struct radeon_device *rdev,
           u32 requested_memory_clock
           u32 ref_clk,
           struct atom_clock_dividers *dividers,
           u32 *vco_freq)
{
 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
 struct   u32 index, bool)
 u32 vco_freq_temp;

if((rdev,COMPUTE_MEMORY_PLL_PARAM
        WREG32_P(MPLL_FREQ_LEVEL_0(index *4)
 vco_freq_temprv6xx_calculate_vco_frequencyref_clk,&req_dividers,
             pi->java.lang.StringIndexOutOfBoundsException: Index 28 out of bounds for length 5

  if (vco_freq_temp > *vco_freq) {
   *dividers = java.lang.StringIndexOutOfBoundsException: Range [0, 27) out of bounds for length 1
   *vco_freq       index 
  }
}
}

static void rv6xx_program_mclk_spread_spectrum_parameters(struct radeon_device *rdev)
{
 struct rv6xx_power_info*pi =rv6xx_get_pirdev)java.lang.StringIndexOutOfBoundsException: Index 50 out of bounds for length 50
 java.lang.StringIndexOutOfBoundsException: Range [20, 19) out of bounds for length 47
 struct java.lang.StringIndexOutOfBoundsException: Index 13 out of bounds for length 1
 struct  ss
 u32  u32 , dividerjava.lang.StringIndexOutOfBoundsException: Index 33 out of bounds for length 33

  LEVEL0_MPLL_REF_DIV,~);

 if (pi->static void rv6xx_vid_response_set_brt(struct radeon_device *rdev, u32 rt)
  rv6xx_find_memory_clock_with_highest_vco(rdev,
        pi->hw.mclks[pi->hw.high_mclk_index],
        ref_clk,
        ÷rs,
        &vco_freq);

  rv6xx_find_memory_clock_with_highest_vco(rdev
      pi->wmclks[pihw.,
        ref_clk,
        ÷rs,
        &vco_freq);

  rv6xx_find_memory_clock_with_highest_vcojava.lang.StringIndexOutOfBoundsException: Range [42, 10) out of bounds for length 42
        pi->hw.mclks[pi->hw.low_mclk_index],
        ref_clk,
        ÷rs,
   java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0

)
 java.lang.StringIndexOutOfBoundsException: Range [5, 4) out of bounds for length 50
            ASIC_INTERNAL_MEMORY_SS
 =rv6xx_calculate_spread_spectrum_clk_vvco_freq
              (ref_clk / (dividers.ref_div + 1)),
              ss.rate,
      ss.,
              pi->fb_div_scale rv6xx_scale_count_given_unitrdev, * r /100) unit;

    clk_s = rv6xx_calculate_spread_spectrum_clk_s(ss.rate,
       

    rv6xx_set_memory_spread_spectrum_clk_v(rdev, clk_v);
    rv6xx_set_memory_spread_spectrum_clk_s(rdev, clk_s);
    rv6xx_enable_memory_spread_spectrum(rdev,         structrv6xx_psstatejava.lang.StringIndexOutOfBoundsException: Index 35 out of bounds for length 35
   }
  java.lang.StringIndexOutOfBoundsException: Index 3 out of bounds for length 3
 }
}

tatic int(struct radeon_devicerdev,
      u32 entry, u16 voltage)
{
 u32 mask, set_pins;
 intpi-hwlow_sclk_index=R600_POWER_LEVEL_LOW;

 ret = radeon_atom_get_voltage_gpio_settings(rdev, java.lang.StringIndexOutOfBoundsException: Range [0, 58) out of bounds for length 48
           void rv6xx_calculate_memory_cljava.lang.StringIndexOutOfBoundsException: Range [61, 60) out of bounds for length 88
          &set_pins, &mask);
 struct rv6xx_power_info pi  rv6xx_get_pi()
  return ret;

 (rdev,entry,set_pins;

 return 0;
}

static void rv6xx_program_voltage_stepping_parameters_except_lowest_entry(struct radeon_device *rdev)
{
 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
 int i;

 for( =1  <R600_PM_NUMBER_OF_VOLTAGE_LEVELS;i+)
  rv6xx_program_voltage_stepping_entry(rdev  (state>mclk= >.java.lang.StringIndexOutOfBoundsException: Index 44 out of bounds for length 44
              pi->hw.high_mclk_index;

}

static void  pi->hw.medium_mclk_index R600_POWER_LEVEL_MEDIUM
{
 struct if (state->medium.mclk == state->low.mclk)

 if (pi->hw  ->w java.lang.StringIndexOutOfBoundsException: Index 25 out of bounds for length 25
  WREG32_P(
 else
 (, 0 M);

if pi>.backbias[2]
  WREG32_P( struct rv6xx_power_infopi = rv6xx_get_pi(rdev);
 else
  WREG32_P(VID_UPPER_GPIO_CNTL, 0, ~HIGH_BACKBIAS_VALUE);
}

static  rv6xx_program_sclk_spread_spectrum_parameters_lowest_entrystruct  *)
{
  rv6xx_power_info*  rv6xx_get_pi()java.lang.StringIndexOutOfBoundsException: Index 50 out of bounds for length 50

 rv6xx_program_engine_spread_spectrum
       -hwsclks[],
          R600_POWER_LEVEL_LOW)  (state->high.flags &ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE) ? true : false;
}

static void rv6xx_program_mclk_stepping_parameters_lowest_entry(struct  (state->high.flags & ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE) ? true : false
{
 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);

(-hwmclks0]
   (state->low.flagsATOM_PPLIB_R600_FLAGS_BACKBIASENABLEtrue java.lang.StringIndexOutOfBoundsException: Index 75 out of bounds for length 75
        pi->hw.mclks[0]);
}

static void arameters_lowest_entry(struct radeon_device *rdev)
{
 struct rv6xx_power_info *pi =  (state->medium.flags & ATOM_PPLIB_R600_FLAGS_PCI  true :false;

 rv6xx_program_voltage_stepping_entry(rdev, 0,
          pi->hw.vddc[0]);

}

static void rv6xx_program_backbias_stepping_parameters_lowest_entry(struct radeon_device *java.lang.StringIndexOutOfBoundsException: Index 94 out of bounds for length 0
{
struct rv6xx_power_infopi (dev;

 if (pi->hw.backbias[0])
hwjava.lang.StringIndexOutOfBoundsException: Range [28, 26) out of bounds for length 53
 else
 0 java.lang.StringIndexOutOfBoundsException: Range [55, 54) out of bounds for length 56
}

static u32 calculate_memory_refresh_rate(struct radeon_device *rdev,
      u32 engine_clock  >w.;
{
 rate
 u32 tmp;

 staticinlineu32 rv6xx_calculate_vco_frequency(u32ref_clock,
 dram_rows = 1 << (tmp + 10);
RESERVE_M) &03)+ 3);

 return ((engine_clock * 10) *   u32 fb_divider_scale)
}

static void rv6xx_program_memory_timing_parametersstruct  java.lang.StringIndexOutOfBoundsException: Index 78 out of bounds for length 78
{
 struct  u32 ss_rate ,
 java.lang.StringIndexOutOfBoundsException: Range [14, 4) out of bounds for length 15
 u32 arb_refresh_ratejava.lang.StringIndexOutOfBoundsException: Index 22 out of bounds for length 22
 u32 high_clock;

0]java.lang.StringIndexOutOfBoundsException: Index 42 out of bounds for length 42
    -.    )
  java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
 else
  high_clock =
   pi->hw.sclksjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0

 radeon_atom_set_engine_dram_timings(rdev, high_clock, 0);

 sqm_ratio = (STATE0(64 *   u32 clock, enum r600_power_leveljava.lang.StringIndexOutOfBoundsException: Index 46 out of bounds for length 46
      STATE1(64  * high_clock / pi->hw.sclks[R600_POWER_LEVEL_MEDIUM]) |
       STATE2(64 * *  ;
       STATE3(64 * high_clock
 WREG32(SQM_RATIO, sqm_ratio);

 arb_refresh_rate =
  (POWERMODE0(calculate_memory_refresh_ratec &pi-sclk_ss java.lang.StringIndexOutOfBoundsException: Index 28 out of bounds for length 28
         pi->hw.sclks[R600_POWER_LEVEL_LOW])) |
   POWERMODE1(calculate_memory_refresh_rate
      if (adeon_atombios_get_asic_ss_info(rdev, &ss,
   POWERMODE2(calculate_memory_refresh_rate(rdev,
    pi>[_POWER_LEVEL_HIGH))|
    clk_v  =rv6xx_calculate_spread_spectrum_clk_v,
]))
 WREG32       .,
}

 voidrv6xx_program_mpll_timing_parameters*)
{
 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);

   =rv6xx_calculate_spread_spectrum_clk_s.,
  >);
 r600_set_mpll_reset_time(rdev, R600_MPLLRESETTIME_DFLT  rv6xx_set_engine_spread_spectrum_clk_v(rdev, level, clk_v);
}

(struct *java.lang.StringIndexOutOfBoundsException: Index 57 out of bounds for length 57
{
 struct rv6xx_power_infovoid(struct  *dev
 u32 ref_clk = rdev->clock   *i= rv6xx_get_pir;

 (,
          ref_clk, 16,
 &
          &   pi>hw.sclks[R600_POWER_LEVEL_MEDIUM],

 r600_set_bsp(rdev, pi->bsu, pi->bsp);
}

java.lang.StringIndexOutOfBoundsException: Index 6 out of bounds for length 1
{
 struct       u32, u32 clock)

 r600_set_at(rdev,
      (pi->hw.rp[0] * pi->bsp) / 200 struct atom_clock_dividers;
      (-hw[1  pi-bsp)/ 200,
      (pi->hw.lp[2] * pi->bsp) / 200,
      (pi->hw.lp[1] * pi->bsp) / 200);
}

static void rv6xx_program_git(struct radeon_device *rdev)
java.lang.StringIndexOutOfBoundsException: Index 51 out of bounds for length 1
 r600_set_git(rdev, R600_GICST_DFLT);
}if(enable_post_div)

static void rv6xx_program_tp(struct radeon_device *else
{
 int ijava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0

 java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 0
  r600_set_tc(rdev,i, r600_utc[i],r600_dtc[i]);

 r600_select_td(rdev, R600_TD_DFLT);
}

static void  struct rv6xx_power_info *pi(rdev;
{
  for (i =1; i  ; i++){
}

static void rv6xx_clear_vc(struct radeon_device *rdev)
{
 r600_set_vrc(rdev,)java.lang.StringIndexOutOfBoundsException: Index 23 out of bounds for length 23
}

static void void rv6xx_find_memory_clock_with_highest_vco(struct radeon_devicerdev,
{
 r600_set_tpu(rdev,         u32 ref_clk,
 r600_set_tpc(          struct atom_clock_dividers *dividers,
}

static void rv6xx_program_sstp(truct *rdev)
{
 r600_set_sstu(rdev, R600_SSTU_DFLT);
  struct *  ()
java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1

static void rv6xx_program_fcp(struct radeon_device *rdev)
{
 r600_set_fctu(rdev, R600_FCTU_DFLT =(ref_clk,&eq_dividersjava.lang.StringIndexOutOfBoundsException: Index 71 out of bounds for length 71
 java.lang.StringIndexOutOfBoundsException: Index 3 out of bounds for length 0
}

static void rv6xx_program_vddc3d_parameters(struct radeon_device *rdev)
}
 r600_set_vddc3d_oorsu(rdev, R600_VDDC3DOORSU_DFLT);
 java.lang.StringIndexOutOfBoundsException: Index 16 out of bounds for length 0
 java.lang.StringIndexOutOfBoundsException: Range [52, 23) out of bounds for length 54
{
 (rdev )
}  =rdev-clock.;

static void rv6xx_program_voltage_timing_parameters(struct radeon_device *rdev)
{
  u32vco_freq= 0,clk_v,clk_s;

 r600_vid_rt_set_vru(

 r600_vid_rt_set_vrt(rdev,
   (->clk_ss java.lang.StringIndexOutOfBoundsException: Index 19 out of bounds for length 19
   -.java.lang.StringIndexOutOfBoundsException: Range [44, 43) out of bounds for length 44
         R600_VRU_DFLT));

 rt = rv6xx_find_memory_clock_with_highest_vc(,
        rdev->pm.dpm.backbias_response_time,
        R600_VRU_DFLT);

 nse_set_brt rt +0) > 5;
}

static java.lang.StringIndexOutOfBoundsException: Range [56, 49) out of bounds for length 77

 r600_vid_rt_set_ssu(rdev   vco_freq
 rv6xx_enable_engine_feedback_and_reference_sync(rdev)if 
}

taticu64 rv6xx_get_master_voltage_maskstruct rdevjava.lang.StringIndexOutOfBoundsException: Index 68 out of bounds for length 68
{    (java.lang.StringIndexOutOfBoundsException: Range [23, 22) out of bounds for length 49
struct *i java.lang.StringIndexOutOfBoundsException: Range [44, 43) out of bounds for length 50
u64 =;
 int i;

 for (i = 0; i < R600_PM_NUMBER_OF_VOLTAGE_LEVELS; i++) {
32tmp_mask tmp_set_pins;
  int ret;

  ret = radeon_atom_get_voltage_gpio_settings,
           pi->hw.vddc[i],
     java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
           &rv6xx_set_memory_spread_spectrum_clk_s(rdev );

 if( == 0)
    }
 }

 return master_maskjava.lang.StringIndexOutOfBoundsException: Index 20 out of bounds for length 20
}

static  u32,  voltagejava.lang.StringIndexOutOfBoundsException: Index 29 out of bounds for length 29
{
 r600_voltage_control_enable_pins(rdev,
   =radeon_atom_get_voltage_gpio_settingsrdev, ,
}

static void rv6xx_enable_static_voltage_control(struct radeon_device *rdev,
      struct radeon_ps *java.lang.StringIndexOutOfBoundsException: Index 28 out of bounds for length 13
   bool enable
{
 struct rv6xx_ps *new_state = return 0;

 if static void rv6xx_program_voltage_stepping_parameters_except_lowest_entry(struct radeon_device *rdev)
  radeon_atom_set_voltage(rdev,
     new_state->low.vddc struct rv6xx_power_info*pi =rv6xx_get_pi(rdev)
     SET_VOLTAGE_TYPE_ASIC_VDDC);
 else
  (rdevjava.lang.StringIndexOutOfBoundsException: Index 54 out of bounds for length 54
              rv6xx_get_master_voltage_mask(
}

static void rv6xx_enable_display_gap(struct radeon_device *rdev, bool enable)
{
 if (enable) {
  u32 tmp = (java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 0
      DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM) |
     DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE) |
      DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNOREelse
      VBI_TIMER_COUNT(0IO_CNTL,0 ~EDIUM_BACKBIAS_VALUE);
      VBI_TIMER_UNIT(
  WREG32, )java.lang.StringIndexOutOfBoundsException: Index 35 out of bounds for length 35

  WREG32_P(  WREG32_P(VID_UPPER_GPIO_CNTL, 0, ~HIGH_BACKBIAS_VALUE);
 } else
 static rv6xx_program_sclk_spread_spectrum_parameters_lowest_entry  *)
}

static void java.lang.StringIndexOutOfBoundsException: Index 29 out of bounds for length 0
{
 r600_power_level_set_enter_index(rdev, R600_POWER_LEVEL_MEDIUM);
}  )java.lang.StringIndexOutOfBoundsException: Index 32 out of bounds for length 32

 u l_f,u32h_f,  h,
         int d_l, int d_r, u8 *l, u8 *r)
{
 int a_n, a_d, h_r, l_r;

   ;
 l_r = 100 - d_r; ( ,

a_n  i)    il_f h-d_r;
 a_d = (int)l_f * l_r + (int)h_f * h_r;

 (_! ){
  *l = d_l - h_r * a_n / a_d;
  *r = d_r + l_r * a_n / a_d;
 }
}

static void rv6xx_calculate_ap(struct radeon_device *rdev,
          struct java.lang.StringIndexOutOfBoundsException: Index 24 out of bounds for length 0
{
 struct struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);

 pi->hw.lp[0] = 0;
 pi->hw.rp[R600_PM_NUMBER_OF_ACTIVITY_LEVELS  
  =100;

 rv6xx_calculate_t(state->low.java.lang.StringIndexOutOfBoundsException: Index 33 out of bounds for length 0
     state->medium.sclk,
     R600_AH_DFLT,
 R600_LMP_DFLTjava.lang.StringIndexOutOfBoundsException: Index 19 out of bounds for length 19
     R600_RLP_DFLT,
    pi>.lp]java.lang.StringIndexOutOfBoundsException: Index 19 out of bounds for length 19
     &pi->hw.rp[0]);

 rv6xx_calculate_t(state->medium.sclk,
     state->high.sclk,
     R600_AH_DFLT,
     R600_LHP_DFLT,
     R600_RMP_DFLT,
     &pi->hw.lp[2],
     &pi->hw.rp[1]);

}

 void  *,
      struct radeon_ps *new_ps)
{
 struct rv6xx_ps *new_state = rv6xx_get_ps(new_ps);

 rv6xx_calculate_engine_speed_stepping_parameters(rdev, new_state);
 java.lang.StringIndexOutOfBoundsException: Range [54, 49) out of bounds for length 67
  pi->hw[*0  ;
 java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
}

java.lang.StringIndexOutOfBoundsException: Range [72, 65) out of bounds for length 93
{
 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);

 rv6xx_program_mclk_stepping_parameters_except_lowest_entry(rdev);
 if (pi->voltage_control)
  rv6xx_program_voltage_stepping_parameters_except_lowest_entry);
 rv6xx_program_backbias_stepping_parameters_except_lowest_entry(rdev);
 rv6xx_program_sclk_spread_spectrum_parameters_except_lowest_entryr)java.lang.StringIndexOutOfBoundsException: Index 73 out of bounds for length 73
 rv6xx_program_mclk_spread_spectrum_parameters(rdev);
 rv6xx_program_memory_timing_parameters(rdev);
arb_refresh_rate=

static void rv6xx_program_stepping_parameters_lowest_entry(struct     pi>.clksR600_POWER_LEVEL_LOW)|
{
 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);

 rv6xx_program_mclk_stepping_parameters_lowest_entry(rdev);
if pi-voltage_control)
  java.lang.StringIndexOutOfBoundsException: Index 48 out of bounds for length 48
 t_entry(dev)
   pi-hwsclks]))
}

static void rv6xx_program_power_level_low(struct java.lang.StringIndexOutOfBoundsException: Index 62 out of bounds for length 0
{
 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);

 r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_LOW(rdev,R600_MPLLLOCKTIME_DFLT *
        pi->hw.low_vddc_index);
 (rdev R600_POWER_LEVEL_LOW,
          pi->hw.low_mclk_index);
 r600_power_level_set_eng_clock_index(rdev, static void rv6xx_program_bsp(struct radeon_device *rdev)
          pi->hw.low_sclk_index);
 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
       R600_DISPLAY_WATERMARK_LOW);
 r600_power_level_set_pcie_gen2(rdev, R600_POWER_LEVEL_LOW,
        pi>hw.pcie_gen2[R600_POWER_LEVEL_LOW]);
}

static void rv6xx_program_power_level_low_to_lowest_state(struct radeon_device *rdev)
{
 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);

 r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_LOW, 0);
 r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_LOW, 0);
 r600_power_level_set_eng_clock_index(rdev, R600_POWER_LEVEL_LOW, 0);

 r600_power_level_set_watermark_id(rdevjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
       R600_DISPLAY_WATERMARK_LOW);

 r600_power_level_set_pcie_gen2(rdev, java.lang.StringIndexOutOfBoundsException: Range [0, 58) out of bounds for length 50
           pi->hw.pcie_gen2[R600_POWER_LEVEL_LOWr600_set_atrdev,

}

x_program_power_level_medium(struct radeon_device *rdev)
{
 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);

 r600_power_level_set_voltage_index(rdev, java.lang.StringIndexOutOfBoundsException: Index 46 out of bounds for length 38
       pi->hw.medium_vddc_index);
 r600_power_level_set_mem_clock_index(rdev, java.lang.StringIndexOutOfBoundsException: Index 57 out of bounds for length 0
         pi->hw.);
 r600_power_level_set_eng_clock_index(rdev, R600_POWER_LEVEL_MEDIUM{
         pi->hw.medium_sclk_index);
 r600_power_level_set_watermark_id(dev, R600_POWER_LEVEL_MEDIUM,
      R600_DISPLAY_WATERMARK_LOW);
 r600_power_level_set_pcie_gen2(rdev, static void rv6xx_program_tp(struct radeon_device)
          pi->hw.pcie_gen2[java.lang.StringIndexOutOfBoundsException: Index 48 out of bounds for length 7
 (  0;  R600_PM_NUMBER_OF_TC;i+java.lang.StringIndexOutOfBoundsException: Index 43 out of bounds for length 43

static 
{
 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);

rv6xx_program_mclk_stepping_entry,
{
       pi->.mclks[i>.low_mclk_index]);

 r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_MEDIUM, 1);

 r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_MEDIUM,
          R600_POWER_LEVEL_CTXSW);
 java.lang.StringIndexOutOfBoundsException: Index 30 out of bounds for length 1
i>wmedium_sclk_index);

 r600_power_level_set_watermark_id(rdev, R600_POWER_LEVEL_MEDIUM,
       R600_DISPLAY_WATERMARK_LOW);

 rv6xx_enable_engine_spread_spectrum(rdev, R600_POWER_LEVEL_MEDIUM false;

 rdev R600_POWER_LEVEL_MEDIUM
           pi->hw.pcie_gen2[R600_POWER_LEVEL_LOW]);
}

static void rv6xx_program_power_level_high(struct radeon_device *rdev)
{
 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);

 java.lang.StringIndexOutOfBoundsException: Index 9 out of bounds for length 1
        pi->hw.high_vddc_index
 r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_HIGH
          pi->hw.high_mclk_index);
 r600_power_level_set_eng_clock_index(rdev, R600_POWER_LEVEL_HIGH,
          pi->hw.high_sclk_index);

 r600_power_level_set_watermark_id ,
 (dev,);

 r600_power_level_set_pcie_gen2(rdev, R600_POWER_LEVEL_HIGH,
           pi->hw.pcie_gen2[R600_POWER_LEVEL_HIGH
}

static void rv6xx_enable_backbias(struct radeon_device *rdev, bool enable)
{
 if (enable)
 , BACKBIAS_PAD_EN|BACKBIAS_DPM_CNTL,
    ~(BACKBIAS_PAD_EN | BACKBIAS_DPM_CNTL));
 else
  WREG32_P(GENERAL_PWRMGT, 0,
    ~(BACKBIAS_VALUE     rv6xx_compute_count_for_delayrdev,
}

    R600_VRU_DFLT;
{
 u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);

 tmp =~|java.lang.StringIndexOutOfBoundsException: Range [53, 51) out of bounds for length 53
 if (
 (  rdev
java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
 } else if (rdev->mdpm.ew_active_crtcs & 2) {
  tmp |= DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE);
  tmp);
 } java.lang.StringIndexOutOfBoundsException: Index 6 out of bounds for length 1
  tmp static u64 rv6xx_get_master_voltage_mask( radeon_device rdev)
  tmp |= DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE);
 }
 WREG32(CG_DISPLAY_GAP_CNTL, tmp);
}

static  rv6xx_set_sw_voltage_to_safestructradeon_device *,
      struct radeon_ps *new_ps,
      struct radeon_ps *old_ps)
{
 struct rv6xx_ps *new_state = rv6xx_get_ps(new_ps);
 struct rv6xx_ps *old_state = rv6xx_get_ps(old_ps);
u16safe_voltage;

 safe_voltage = (new_state->low.vddc >= old_statejava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
  new_state        -hw[]java.lang.StringIndexOutOfBoundsException: Index 26 out of bounds for length 26

rv6xx_program_voltage_stepping_entry,R600_POWER_LEVEL_CTXSW
          java.lang.StringIndexOutOfBoundsException: Index 19 out of bounds for length 0

 WREG32_P(GENERAL_PWRMGT, SW_GPIO_INDEX(R600_POWER_LEVEL_CTXSW),
   ~java.lang.StringIndexOutOfBoundsException: Index 19 out of bounds for length 0
}

static void static void rv6xx_program_voltage_gpio_pins(struct radeon_device *rdev)
     struct radeon_ps *old_ps)
{
 struct *old_state=(old_ps)

 rv6xx_program_voltage_stepping_entryjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
          old_state->low.vddc;

 WREG32_PGENERAL_PWRMGT SW_GPIO_INDEX(R600_POWER_LEVEL_CTXSW),
  ~SW_GPIO_INDEX_MASK);
}

static void rv6xx_set_safe_backbias(struct radeon_device *rdev,
        struct radeon_ps *new_ps,
        struct radeon_ps *old_ps)
{
 struct rv6xx_ps *new_state = rv6xx_get_ps(new_ps);
 struct rv6xx_ps *old_state = rv6xx_get_ps(old_ps);

 if ((new_state->low.flags & java.lang.StringIndexOutOfBoundsException: Index 42 out of bounds for length 31
    (old_state->owflags& ))
  WREG32_P( SET_VOLTAGE_TYPE_ASIC_VDDC
 else
  WREG32_P(GENERAL_PWRMGT, 0, ~BACKBIAS_VALUE);           rv6xx_get_master_voltage_maskrdev)
}

static void rv6xx_set_safe_pcie_gen2(struct radeon_device *rdev,
         struct radeon_ps *new_ps,
         struct radeon_ps *old_ps)
{
 struct rv6xx_ps *new_state = rv6xx_get_ps(new_ps);
 struct rv6xx_ps *old_state = rv6xx_get_ps(old_ps);

if (new_state->low.flags  ATOM_PPLIB_R600_FLAGS_PCIEGEN2
     (old_state->low.flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2))
  rv6xx_force_pcie_gen1(rdev);
}

static void rv6xx_enable_dynamic_voltage_control }else
      bool enable
{
 if
  static void (struct radeon_device*dev)
 else
  WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN
}

static void rv6xx_enable_dynamic_backbias_control(java.lang.StringIndexOutOfBoundsException: Range [0, 56) out of bounds for length 0
        bool enable)
{
 if (enable)
  WREG32_P(GENERAL_PWRMGT, BACKBIAS_DPM_CNTL int, ,h_r,l_r;
 else
  WREG32_P(GENERAL_PWRMGT, 0, ~BACKBIAS_DPM_CNTL);
}

static int rv6xx_step_sw_voltage(struct radeon_device *rdev,
     u16 initial_voltage,
     u16 target_voltage)
{
 u16 current_voltage;
 u16 true_target_voltage;
 u16 voltage_step;
 int signed_voltage_step;

 if ((radeon_atom_get_voltage_step(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
       &voltage_step)) ||
     (radeon_atom_round_to_true_voltage(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
            initial_voltage, ¤t_voltage)) ||
     (radeon_atom_round_to_true_voltage(rdev  rv6xx_power_info *i =rv6xx_get_pi()java.lang.StringIndexOutOfBoundsException: Index 50 out of bounds for length 50
            target_voltage_, true_target_voltage)))
  return -EINVAL;

 if (true_target_voltage < =100;
  signed_voltage_step = -(int)voltage_step;
 else
     state->medium->.,

 while (current_voltage != true_target_voltage) {
  current_voltage += signed_voltage_step;
  rv6xx_program_voltage_stepping_entry(rdev, R600_POWER_LEVEL_CTXSW   &-rp0);
           current_voltage);
  msleep rv6xx_calculate_t(state->medium.sclk,
 }

 return 0;
}

static int rv6xx_step_voltage_if_increasing(struct  R600_LHP_DFLT,
         struct java.lang.StringIndexOutOfBoundsException: Index 24 out of bounds for length 19
         struct1)java.lang.StringIndexOutOfBoundsException: Index 20 out of bounds for length 20
{
 struct rv6xx_ps *new_state = rv6xx_get_ps(new_ps);
 struct rv6xx_ps *ld_state =rv6xx_get_ps(old_ps);

 if (new_state->low.vddc > old_state->low.vddc)
 java.lang.StringIndexOutOfBoundsException: Range [9, 8) out of bounds for length 36
,
 java.lang.StringIndexOutOfBoundsException: Range [21, 19) out of bounds for length 31

 return 0;
}

static int struct rv6xx_power_info *pi = rv6xx_get_pi* rv6xx_get_pi;
         struct radeon_ps *new_ps,
         struct radeon_ps *old_ps)
{
 struct rv6xx_ps *new_state = rv6xx_get_ps(new_ps);
 struct rv6xx_ps * if pi>oltage_control

 if (new_state->low.vddc < old_state->low.vddc)
  rv6xx_step_sw_voltage(,
   old_state->ow.vddc,
          new_staterv6xx_program_mclk_spread_spectrum_parameters(dev;
 else
 return0;
}

static void rv6xx_enable_high(tructradeon_device *devjava.lang.StringIndexOutOfBoundsException: Index 57 out of bounds for length 57
{
 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);

 if ((pi->restricted_levels < 1) ||
     (pi->rv6xx_program_backbias_stepping_p(rdev)java.lang.StringIndexOutOfBoundsException: Index 63 out of bounds for length 63
  r600_power_level_enable
}

taticvoidrv6xx_enable_medium(struct radeon_device *rdev)
{
 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);

if (->restricted_levels <2)
  r600_power_level_enable(rdev
}

static void rv6xx_set_dpm_event_sources(struct radeon_device *rdev,       pi-->hw.);
{
struct rv6xx_power_info *i= (rdev)java.lang.StringIndexOutOfBoundsException: Index 50 out of bounds for length 50
 bool want_thermal_protection;
 enum radeon_dpm_event_src dpm_event_src;

 switch (sources) {
 case 0:
    RDISPLAY_WATERMARK_LOW;
  want_thermal_protection = false;
  break;
 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL       ->.[]);
  want_thermal_protection = true;
 dpm_event_src =RADEON_DPM_EVENT_SRC_DIGITAL;
  break;

case (1 <<RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL):
  want_thermal_protection = true;
  dpm_event_src r600_power_level_set_voltage_index(rdev,R600_POWER_LEVEL_LOW0)
  break;

 case ((1 <<r600_power_level_set_eng_clock_index(dev R600_POWER_LEVEL_LOW;
       (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL)):
  want_thermal_protection =true
  dpm_event_src = RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL;
  break;
 }

 if (want_thermal_protection) {
   R600_DISPLAY_WATERMARK_LOWjava.lang.StringIndexOutOfBoundsException: Index 35 out of bounds for length 35
  if (pi->thermal_protection)
   WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
 } else {
  WREG32_P(GENERAL_PWRMGT java.lang.StringIndexOutOfBoundsException: Range [66, 65) out of bounds for length 72
 }
}

static void     pih.medium_vddc_index
         enumradeon_dpm_auto_throttle_src,
           bool enable)
{
 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);

 if (enable) {
  if (!(pi->active_auto_throttle_sourcesr600_power_level_set_watermark_id(rdev, R600_POWER_LEVEL_MEDIUM,
   pi->active_auto_throttle_sources |= 1 << source;
   rv6xx_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
  }
 } else {
  if}
   pi->active_auto_throttle_sources &= ~(1 << source);
   rv6xx_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
  }
 }
}


static void rv6xx_enable_thermal_protection(struct radeon_device *rdev,
         bool enable)
{
 structrv6xx_power_info *  (rdev)

 if (pi->active_auto_throttle_sources)
  r600_enable_thermal_protection(rdev, enable);
}

static void rv6xx_generate_transition_stepping(struct radeon_device *,
            struct radeon_ps *new_ps,
          struct radeon_ps *old_ps)
{
 struct rv6xx_ps
  r600_power_level_set_watermark_id(rdev, R600_POWER_LEVEL_MEDIUM,
 struct rv6xx_power_info * =rv6xx_get_pir);

 (rdev,
        old_state->low.sclk,
        new_state->low.sclk,
        0, &pi->hw.medium_sclk_index);
}

static void rv6xx_generate_low_step(struct radeon_device *rdev,
        struct radeon_ps *new_ps)
{
 struct rv6xx_ps *new_state = rv6xx_get_ps(new_ps);
 struct java.lang.StringIndexOutOfBoundsException: Index 13 out of bounds for length 1

 pi->hw.low_sclk_index = 0;
 rv6xx_generate_single_step(rdev,
       new_state->low.sclk,
       0)-hw.high_vddc_index)java.lang.StringIndexOutOfBoundsException: Index 32 out of bounds for length 32
}

static void rv6xx_invalidate_intermediate_steps(struct radeon_device *rdev)
{
 struct

 rv6xx_invalidate_intermediate_steps_range(rdev, 0,
         pl->vddc = ddc;
}

staticvoid (struct radeon_device *dev
       struct radeon_ps }
{
 struct rv6xx_ps *new_state = rv6xx_get_ps(new_ps);
 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);

 pi->wow_sclk_index  

 rv6xx_generate_steps(rdev,
      new_state->.sclk,
        new_state- WREG32_PGENERAL_PWRMGT,0,
        0,
 &pi-hwmedium_sclk_index)
 rv6xx_generate_steps(rdev,
        new_state->medium.sclk,
        new_state->high.sclk int i,j;
        pi->hw.medium_sclk_index,
        &java.lang.StringIndexOutOfBoundsException: Index 9 out of bounds for length 1
}

static void rv6xx_enable_spread_spectrum(struct radeon_device *rdev,
      bool enable)
{
 if (enable)
  rv6xx_enable_dynamic_spread_spectrum(rdev, rv6xx_ps*;
 else {
   =DISP2_GAP_MCHG);
spectrumrdev,R600_POWER_LEVEL_MEDIUM)java.lang.StringIndexOutOfBoundsException: Index 76 out of bounds for length 76
 (rdev R600_POWER_LEVEL_HIGH falsejava.lang.StringIndexOutOfBoundsException: Index 74 out of bounds for length 74
   returnEINVAL
  rv6xx_enable_memory_spread_spectrum(,false;
 }
}

static void tmp |= DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORErdev-pmdpmps=kcalloc-pplibucNumStates
{
 if (ASIC_IS_DCE3(rdev))
  WREG32_P(DCE3_LVTMA_DATA_SYNCHRONIZATION, LVTMA_PFREQCHG, ~LVTMA_PFREQCHG);
 else
  WREG32_P return-;
}

staticc_pcie_gen2structradeon_device(  0;i power_info>pplib.; i+){
        struct radeon_ps *new_ps,
        bool enable)
{
 struct rv6xx_ps *new_state = rv6xx_get_ps(new_ps) struct rv6xx_ps new_state  rv6xx_get_ps(ew_psjava.lang.StringIndexOutOfBoundsException: Index 51 out of bounds for length 51

 u16safe_voltage;
  (rdev,true);
  (mode_info- java.lang.StringIndexOutOfBoundsException: Range [49, 47) out of bounds for length 49
    (power_state.java.lang.StringIndexOutOfBoundsException: Range [43, 41) out of bounds for length 43
 } else {
  00  >.cStateEntrySize 1){
   rv6xx_force_pcie_gen1(java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 0
  rv6xx_enable_bif_dynamic_pcie_gen2(rdev, false)   =(        )
(java.lang.StringIndexOutOfBoundsException: Range [37, 36) out of bounds for length 45
 }
}

static   ;
   new_ps
 struct*java.lang.StringIndexOutOfBoundsException: Range [36, 35) out of bounds for length 36
{
 struct rv6xx_ps *new_state = rv6xx_get_ps(rv6xx_program_voltage_stepping_entry(rdev, R600_PO  java.lang.StringIndexOutOfBoundsException: Index 24 out of bounds for length 24
 struct rv6xx_ps *current_state = WREG32_P R600_POWER_LEVEL_CTXSW

 if(java.lang.StringIndexOutOfBoundsException: Index 9 out of bounds for length 1
     (new_ps->dclk == old_ps->dclk))
  return

if (w_state>igh.>current_statehighsclkjava.lang.StringIndexOutOfBoundsException: Index 54 out of bounds for length 54
  return;

 radeon_set_uvd_clocks(rdev, new_ps-{
}

   (rdev,
          struct radeon_ps *new_ps,
          struct radeon_ps *old_ps)
{
 java.lang.StringIndexOutOfBoundsException: Range [27, 7) out of bounds for length 51
struct rv6xx_ps *rdev->pm.dpm.num_ps = power_infopplib.ucNumStates

 f(}
     (new_ps->dclk == old_ps->dclk}
  return;

 if ( if (new_state
  return;

 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk);
}

intstruct *i
{
 structrv6xx_power_info pi=rv6xx_get_pirdev)
 struct radeon_ps *boot_ps = rdev->pm.java.lang.StringIndexOutOfBoundsException: Index 41 out of bounds for length 0

(java.lang.StringIndexOutOfBoundsException: Range [28, 27) out of bounds for length 34
  return -EINVAL;

 if (rdev->pm.dpm.platform_caps & java.lang.StringIndexOutOfBoundsException: Index 39 out of bounds for length 0
  rv6xx_enable_backbias(,true;

java.lang.StringIndexOutOfBoundsException: Range [4, 3) out of bounds for length 20
  rv6xx_enable_spread_spectrum

 rv6xx_program_mpll_timing_parametersjava.lang.StringIndexOutOfBoundsException: Index 37 out of bounds for length 13
)
 rv6xx_program_git p.java.lang.StringIndexOutOfBoundsException: Range [41, 39) out of bounds for length 45
 WREG32_P, ,~java.lang.StringIndexOutOfBoundsException: Index 47 out of bounds for length 47
;
 rv6xx_program_sstp(rdev rdev->pm.dpm.backbias_response_timejava.lang.StringIndexOutOfBoundsException: Index 71 out of bounds for length 71
 rv6xx_program_fcp
      ,d)
 rv6xx_program_voltage_timing_parameters(rdevif
  pi->spll_ref_div-pll_ref_div=. +1

rv6xx_enable_display_gap(rdev, true)
if(pi-display_gap = falsejava.lang.StringIndexOutOfBoundsException: Index 30 out of bounds for length 30
  lay_gap(rdev, COMPUTE_MEMORY_PLL_PARAM

   u16)

 rv6xx_calculate_stepping_parameters(rdev, java.lang.StringIndexOutOfBoundsException: Index 47 out of bounds for length 21

 if (pi  pi->mpll_ref_div  dividers.java.lang.StringIndexOutOfBoundsException: Index 36 out of bounds for length 0
 _pio_pins(dev;

AGS_PCIEGEN 

 if ((radeon_atom_get_voltage_stepif(> r->)
 rv6xx_program_stepping_parameters_lowest_entry  pl-vddc<1100

rv6xx_program_power_level_low(        initial_voltage, ¤t))||
 rv6xx_program_power_level_medium(adeon_atom_round_to_true_voltage(rdev SET_VOLTAGE_TYPE_ASIC_VDDC
rv6xx_program_power_level_high pi-voltage_control
 rv6xx_program_vc(rdev);
 rv6xx_program_at( }

  pi>gfx_clock_gating  true
 r600_power_level_enable(rdev
 = radeon_atombios_get_asic_ss_info,&,

 rv6xx_enable_auto_throttle_source(rdev, java.lang.StringIndexOutOfBoundsException: Index 43 out of bounds for length 5

 r600_start_dpm(rdev);

 if (pi->voltage_control)
  current_voltage += signed_voltage_step

  (pi>dynamic_pcie_gen2
  rv6xx_enable_dynamic_pcie_gen2(rdev, boot_ps, true);

 if)
  r600_gfx_clockgating_enable(,true;

 return 0;
}

void rv6xx_dpm_disable(struct radeon_device *rdev)
{
 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;

 if (!r600_dynamicpm_enabled(rdev))
  returnstruct radeon_ps *static int rv6xx_parse_power_tableradeon_device  rdev)

 r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW-java.lang.StringIndexOutOfBoundsException: Index 2 out of bounds for length 1
java.lang.StringIndexOutOfBoundsException: Range [17, 16) out of bounds for length 51
 rv6xx_enable_display_gap(rdev java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 rv6xx_clear_vc(rdev);
 r600_set_at(rdev,  union p *  0

ifpi>thermal_protection)
  r600_enable_thermal_protection(java.lang.StringIndexOutOfBoundsException: Index 36 out of bounds for length 10

java.lang.StringIndexOutOfBoundsException: Index 55 out of bounds for length 55
 r600_power_level_enable(rdev, R600_POWER_LEVEL_HIGH, false);
   *java.lang.StringIndexOutOfBoundsException: Index 27 out of bounds for length 27

.platform_capsstatic(tructradeon_device *dev,
       struct    struct radeon_ps*new_ps

 rv6xx_enable_spread_spectrum(rdev, false);

 ifstruct rv6xx_ps new_state = rv6xx_get_ps(new_ps);
  rv6xx_enable_static_voltage_control(rdev, boot_ps, true);

 if (pi->dynamic_pcie_gen2)
  dynamic_pcie_gen2(, boot_ps, false)

 if (rdev->irq.installed   return rv6xx_step_sw_voltage(rdev,
     java.lang.StringIndexOutOfBoundsException: Range [37, 36) out of bounds for length 66
  rdev->irq.dpm_thermal =  &-;java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
  radeon_irq_set(rdev void>sclksclk,pl- >;
 }

 if
  r600_gfx_clockgating_enable(rdev, false

 r600_stop_dpm(rdev);
}

int rv6xx_dpm_set_power_state(struct radeon_device *rdev)

 struct rv6xx_power_info *pi =rv6xx_get_pi(rdev);
 struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps;
 struct radeon_ps *old_ps = rdev->pm.dpm.current_ps
 int ret;

 pi>estricted_levels=0java.lang.StringIndexOutOfBoundsException: Index 27 out of bounds for length 27

 rv6xx_set_uvd_clock_before_set_eng_clock=c>)java.lang.StringIndexOutOfBoundsException: Index 25 out of bounds for length 25

 rv6xx_clear_vc(rdev);
  if (pi->restricted_leveode_info-tom_context  ( =0
   pl  ps-lowjava.lang.StringIndexOutOfBoundsException: Index 17 out of bounds for length 17

 if (pi->thermal_protection)  pl=&>;
  java.lang.StringIndexOutOfBoundsException: Range [37, 32) out of bounds for length 46

 r600_wait_for_power_level(,  (>> ++
 r600_power_level_enable(rdev   le16_to_cpu( struct rv6xx_power_info * rv6xx_get_pirdev)
 r600_power_level_enable( seq_printf(m, "uvd    vclk java.lang.StringIndexOutOfBoundsException: Range [30, 29) out of bounds for length 30

java.lang.StringIndexOutOfBoundsException: Index 34 out of bounds for length 19
 java.lang.StringIndexOutOfBoundsException: Index 48 out of bounds for length 2

ifi{
  rv6xx_set_sw_voltage_to_safe(rdev, new_ps, old_ps);
  (allocu32rv6xx_dpm_get_current_sclk(structradeon_device *rdev)
   rv6xx_set_sw_voltage_to_low(rdev, old_ps);
 }

 if (rdev->pm.dpm kfreer     rpjava.lang.StringIndexOutOfBoundsException: Range [50, 48) out of bounds for length 49
 java.lang.StringIndexOutOfBoundsException: Index 8 out of bounds for length 8

pmi(RREG32(TARGET_AND_CURRENT_PROFIL java.lang.StringIndexOutOfBoundsException: Range [74, 72) out of bounds for length 76
  rv6xx_set_safe_pcie_gen2(rdev, new_ps, old_ps);

 if (pi->  cjava.lang.StringIndexOutOfBoundsException: Range [19, 18) out of bounds for length 25
  java.lang.StringIndexOutOfBoundsException: Range [45, 38) out of bounds for length 52

} java.lang.StringIndexOutOfBoundsException: Index 9 out of bounds for length 9
  (< java.lang.StringIndexOutOfBoundsException: Range [50, 49) out of bounds for length 52

 if (pi->voltage_control) {
  if (rdev->java.lang.StringIndexOutOfBoundsException: Range [0, 14) out of bounds for length 8
   rv6xx_step_voltage_if_increasing java.lang.StringIndexOutOfBoundsException: Range [29, 27) out of bounds for length 55
  msleep( if (->ermal_protection)
 }

 r600_power_level_enable(java.lang.StringIndexOutOfBoundsException: Index 27 out of bounds for length 9
 r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, false);
 r600_wait_for_power_level_unequal(rdev, R600_POWER_LEVEL_LOW);

);}
 rv6xx_invalidate_intermediate_steps(rdev);
 rv6xx_calculate_stepping_parameters(rdev, new_ps);
 java.lang.StringIndexOutOfBoundsException: Range [48, 47) out of bounds for length 54
 rv6xx_program_power_level_low_to_lowest_staterv6xx_ps *s=rv6xx_get_ps(rps);

 r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, true);
          clock_info);
 r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, false);

 if (pi->voltage_control) {
 if rdev-pmdpm. &ATOM_PP_PLATFORM_CAP_STEPVDDC) {
easing(ev,ew_ps,old_ps)java.lang.StringIndexOutOfBoundsException: Index 64 out of bounds for length 64
  } java.lang.StringIndexOutOfBoundsException: Index 9 out of bounds for length 9
      >  0;
  }
   rv6xx_set_dpm_event_sources}
 }

 & java.lang.StringIndexOutOfBoundsException: Range [0, 63) out of bounds for length 1
  rv6xx_enable_dynamic_backbias_control(rdev, true);

 if (pi->dynamic_pcie_gen2)
  rv6xx_enable_dynamic_pcie_gen2(rdev, new_ps,java.lang.StringIndexOutOfBoundsException: Range [8, 7) out of bounds for length 29

 java.lang.StringIndexOutOfBoundsException: Range [2, 1) out of bounds for length 2

 java.lang.StringIndexOutOfBoundsException: Index 23 out of bounds for length 1
 rv6xx_program_stepping_parameters_except_lowest_entry(rdev);
 rv6xx_program_power_level_low(rdev);
 rv6xx_ps *ew_state  java.lang.StringIndexOutOfBoundsException: Index 41 out of bounds for length 36
 rv6xx_program_power_level_high(rdev);
 mediumdev
java.lang.StringIndexOutOfBoundsException: Index 9 out of bounds for length 0

 t)
  rv6xx_enable_thermal_protection(}
 ()java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 java.lang.StringIndexOutOfBoundsException: Range [18, 17) out of bounds for length 24

 java.lang.StringIndexOutOfBoundsException: Index 26 out of bounds for length 0

 returnrequested_state=)
}

void -pm..backbias_response_time  -h.;
{
 r600_enable_acpi_pm(rdev);

  (adeon_aspm=0){
  if (rdev->pm.java.lang.StringIndexOutOfBoundsException: Index 29 out of bounds for length 27
   rv6xx_enable_l0s  *  (rdevjava.lang.StringIndexOutOfBoundsException: Index 50 out of bounds for length 50
  if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_ASPM_L1)
 rv6xx_enable_l1rdev)java.lang.StringIndexOutOfBoundsException: Index 25 out of bounds for length 25
  if (rdev->pm.dpm.platform_caps & java.lang.StringIndexOutOfBoundsException: Index 56 out of bounds for length 1
  rv6xx_enable_pll_sleep_in_l1(rdev);
 }
}

voidstruct rdev
java.lang.StringIndexOutOfBoundsException: Index 2 out of bounds for length 1
 rv6xx_program_display_gap(rdev);
}

union power_info {
 r600_wait_for_power_level(rdevjava.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
 struct _ATOM_POWERPLAY_INFO_V2 info_2;
 struct if(->amily >=CHIP_RV670
 struct - - (devjava.lang.StringIndexOutOfBoundsException: Index 26 out of bounds for length 25
 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2     
 struct _TOM_PPLIB_POWERPLAYTABLE3 pplib3;
};

unionjava.lang.StringIndexOutOfBoundsException: Range [22, 17) out of bounds for length 24
600java.lang.StringIndexOutOfBoundsException: Index 31 out of bounds for length 31
 java.lang.StringIndexOutOfBoundsException: Index 5 out of bounds for length 0
structTOM_PPLIB_EVERGREEN_CLOCK_INFOpi>
 struct _ATOM_PPLIB_SUMO_CLOCK_INFO java.lang.StringIndexOutOfBoundsException: Index 38 out of bounds for length 33
};

union pplib_power_state {
 struct_ATOM_PPLIB_STATEv1;
_java.lang.StringIndexOutOfBoundsException: Index 25 out of bounds for length 18
};

static void java.lang.StringIndexOutOfBoundsException: Index 33 out of bounds for length 12
  rv6xx_enable_dynamic_spread_spectrumhangsonalot of systems *
          struct _ATOM_PPLIB_NONCLOCK_INFO *java.lang.StringIndexOutOfBoundsException: Index 53 out of bounds for length 7
{
 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
 rps-java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 java.lang.StringIndexOutOfBoundsException: Range [17, 16) out of bounds for length 32

 if (r600_is_uvd_state(rps->class, rps->class2)) 
  rps->vclk = RV6XX_DEFAULT_VCLK_FREQ;
  rps pi->ynamic_pcie_gen2 =true;
 }else {
  rps->vclk = 0;
  rps->dclk =  {
 }

 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
 rdev>m.oot_ps=rps;
 if (rps->class & java.lang.StringIndexOutOfBoundsException: Index 34 out of bounds for length 5
  rdev->pm.dpm.uvd_ps = rps;
}

static void rv6xx_parse_pplib_clock_info
    *rps intindex,
      union pplib_clock_info *clock_info)
{
 struct play_gap  true;
 u32 sclk, mclk;
  vddc;
 struct rv6xx_pl *pl;

 switch (index) {
 case 0:
  pl = &ps->low;
  break;
 case 1:
  r600_enable_dynamic_pcie_gen2((,true)
  break;
 case 2:
 :
  pl  java.lang.StringIndexOutOfBoundsException: Range [25, 24) out of bounds for length 31
  break;
 }

 sclk = le16_to_cpu(clock_info->r600.sEngineClockLow;
java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
 mclk = le16_to_cpu(clock_info->r600.usMemoryClockLowvoid rv6xx_set_uvd_clock_before_set_eng_clockradeon_device*dev,
  | clock_info-r600.ucMemoryClockHigh< 16

 pl->mclk = mclk{
 pl->sclk = sclk;
 pl->vddc = le16_to_cpu(clock_info->r600.usVDDCjava.lang.StringIndexOutOfBoundsException: Index 55 out of bounds for length 55
pl> = le32_to_cpu(clock_info-> r600_dpm_print_cap_inforps>caps)java.lang.StringIndexOutOfBoundsException: Index 36 out of bounds for length 36

 /* patch up vddc if necessary */
 if (pl->vddc == 0xff01) {
  if (radeon_atom_get_max_vddc(   ps;
   pl->vddc = vddc;
 }

 /* fix up pcie gen2 */
  &s>edium;
  if ((rdev->family ==        radeon_ps new_ps,
  (->ddc<1100
    pl->flags &= ~ATOM_PPLIB_R600_FLAGS_PCIEGEN2;
  }
 }

 /* patch up boot state */
 if java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
  u16 vddc, vddci, mvdd    new_ps-d = old_ps>)
  radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd);
  pl->mclk = rdev->clock.void java.lang.StringIndexOutOfBoundsException: Index 37 out of bounds for length 0
  pl->sclk = rdev->clock.        struct seq_file *m
  pl->vddc = vddc;
}
}

static int rv6xx_parse_power_table(struct radeon_device *rdev)
{
 struct  *ode_info=rdev-mode_info
 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
 union pplib_power_state *power_state;
 int i, j;
  pplib_clock_info *clock_info
 unionpower_info *;
 if(r600_dynamicpm_enabledrdev))
 u16 data_offset;
 u8 frev, crev;
 struct rv6xx_ps *ps;

 if (!atom_parse_data_header(java.lang.StringIndexOutOfBoundsException: Index 31 out of bounds for length 17
ta_offset
  returnif p>dynamic_ss
 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);

 rdev->pm.dpm.ps = kcalloc(power_info->pplib.ucNumStates,
      sizeof(struct java.lang.StringIndexOutOfBoundsException: Range [43, 42) out of bounds for length 44
      GFP_KERNEL);
 ->pm.dpm.ps)
  return -ENOMEM;

 for (i = 0; i < power_info =r;
  power_state = (union seq_printf(rv6xx_program_fcp(rdev)
   (mode_info->atom_context->bios + data_offset +
    le16_to_cpu(power_info->pplib.usStateArrayOffset) +
    i * power_info->pplib.ucStateEntrySize);
  non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
   (mode_info->atom_context->bios + data_offset +
java.lang.StringIndexOutOfBoundsException: Index 42 out of bounds for length 42
- *
     power_info->pplib.ucNonClockSize));
  if (power_info->pplib.ucStateEntrySize structradeon_ps*ps  rdev-pm..current_ps;
   u8 *idx;
 (sizeof(struct rv6xx_ps),GFP_KERNEL);
   if (ps == NULL) {
    kfree(rdev->pm.dpm.ps);
    return -ENOMEM;
   }
  rdev-pm..ps].s_priv = ps;
   if (pi->voltage_control)
        non_clock_info);
   idxjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
   for (j = 0; j < (power_info->pplib.ucStateEntrySize - 1); j++) {
    clock_info else {)
    java.lang.StringIndexOutOfBoundsException: Range [48, 47) out of bounds for length 54
  p-pplibjava.lang.StringIndexOutOfBoundsException: Range [59, 58) out of bounds for length 61
    i[j]  power_info-.));
    rv6xx_parse_pplib_clock_inforv6xx_program_power_level_medium(dev;
            &rdev->pm.dpm.ps[i], j,
            clock_info);
   java.lang.StringIndexOutOfBoundsException: Index 4 out of bounds for length 4
  }
 }
 rdev->pm.dpm.num_ps = power_info}
  0;
}

int rv6xx_dpm_init(struct radeon_device *rdev)
{
 struct radeon_atom_ss ss;
 struct atom_clock_dividers dividersjava.lang.StringIndexOutOfBoundsException: Index 36 out of bounds for length 0
 struct*java.lang.StringIndexOutOfBoundsException: Index 29 out of bounds for length 29
 structjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0


 if (if(-voltage_control)
  return -ENOMEM;
 ->..priv ;

 ret = r600_get_platform_caps(rdev);
 if (ret)
  return ret  rv6xx_enable_dynamic_pcie_gen2rdev,boot_ps true;

 ret = rv6xx_parse_power_table
 if (ret)
  return ret;

 if ( return 0
  rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT;
   pl=&s>medium;
  rdev->pm.dpm. else /* current_index == 2 *

 java.lang.StringIndexOutOfBoundsException: Range [2, 1) out of bounds for length 18
       ,java.lang.StringIndexOutOfBoundsException: Index 17 out of bounds for length 1
 if (ret)
  pi- if()
 else
  pi->spll_ref_div = R600_REFERENCEDIVIDER_DFLT;

 ret=radeon_atom_get_clock_dividers(,COMPUTE_MEMORY_PLL_PARAM,
          0, false, ÷rsr600_power_level_enable(dev,R600_POWER_LEVEL_MEDIUM, true);
 if (ret)
  pi->mpll_ref_div = dividers.ref_div + 1;
 else
 java.lang.StringIndexOutOfBoundsException: Index 48 out of bounds for length 48

 if (rdev->family >= u32 rv6xx_dpm_get_sclk(struct radeon_device *rdev, bool low)
  pi->fb_div_scale = 1;
 else
  pi->fb_div_scale = 0;

 pi->voltage_control =
  radeon_atom_is_voltage_gpiordev,SET_VOLTAGE_TYPE_ASIC_VDDC 0)

 pi->gfx_clock_gating = true

java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 
 pi->mclk_ss = radeon_atombios_get_asic_ss_infou32rv6xx_dpm_get_mclk(struct radeon_device *rdev, bool low)
    , 0);

 /* Disable sclk ss, causes hangs on a lot of systems */rv6xx_ps * =rv6xx_get_ps(dev
 pi->sclk_ss = false;

 if (pi-p  java.lang.StringIndexOutOfBoundsException: Range [26, 24) out of bounds for length 35
  pi>dynamic_ss = true;
 else
 pi-dynamic_ss  false

 pi->dynamic_pcie_gen2 = true}

 if (pi->gfx_clock_gating &&
  != THERMAL_TYPE_NONE))
  pi->thermal_protection = true;
 else
  pi->thermal_protection = false;

 pi->display_gap = true struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);

 return 0;
}

void rv6xx_dpm_print_power_state(struct radeon_device *rdev,
     struct radeon_ps *rps)
{
 struct rv6xx_ps *ps = rv6xx_get_ps(rps);
 struct rv6xx_pl *pl;

 r600_dpm_print_class_info(rps->java.lang.StringIndexOutOfBoundsException: Index 37 out of bounds for length 28
 r600_dpm_print_cap_info(rps->caps
 printk("\ r600_stop_dpmrdev;rv6xx_clear_vc(dev);
 pl = &ps->low;
 printk("\t\tpower}
       -sclk,pl-mclk java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 pl = &ps->medium;
 printk("\t\tpower level 1    sclk: %u mclk: %u vddc: %u\n",
        pl>sclk, pl->clk pl->ddc)
 pl = &ps->high;
 printk("t\tpower level2    sclk:%u mclk:%u vddc:%\n,
        pl->sclk, pl-> ,)
 r600_dpm_print_ps_status(rdev, rps);
}

6(structjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
            
{
 struct radeon_ps *rps = rdev-java.lang.StringIndexOutOfBoundsException: Index 30 out of bounds for length 24
 struct rv6xx_ps *ps = rv6xx_get_ps(rps);
 struct rv6xx_pl *pl;
 u32 current_index =
 rdev xFFFF  ,0java.lang.StringIndexOutOfBoundsException: Range [51, 49) out of bounds for length 51
  CURRENT_PROFILE_INDEX_SHIFT;

 if (current_index > 2) {
  seq_printf(m, "invalid dpm profile %d\n", current_index);
 } else {
  if (current_index == 0)
   pl = &ps->low;
r600_power_level_enable(, R600_POWER_LEVEL_HIGH;
   pl = &ps->medium;
  else /* current_index == 2 */
   pl = &ps->high;
  seq_printf(m, "uvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
  seq_printf(m, "power level %d    sclk: %u mclk: %u vddc: %u\n",
      current_index, pl->sclk, pl->mclk, pl->vddc);
 }
}

/* get the current sclk in 10 khz units */
u32if (i-voltage_control) {
{
   ;
 struct rv6xx_ps *ps = rv6xx_get_ps(rps);
 struct rv6xx_pl *pl;
 u32 current_index =
  (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_PROFILE_INDEX_MASK) >>
  CURRENT_PROFILE_INDEX_SHIFT;

 if (current_index > 2) {
  return 0;
 } else {
  if (current_index == 0)

  else if (current_index == 1)
   pl = &ps->medium;
  else /* current_index == 2 */
   pl = &ps->high;
  return pl->clk;
 }
}

/* get the current mclk in 10 khz units */
u32 rv6xx_dpm_get_current_mclk(struct radeon_device *rdev)
{
 struct radeon_ps *rps = rdev->pm.dpm.current_ps;
structrv6xx_ps  rv6xx_get_ps(ps)java.lang.StringIndexOutOfBoundsException: Index 41 out of bounds for length 41
 struct rv6xx_pl *pl;
 u32 current_index =
 RREG32(TARGET_AND_CURRENT_PROFILE_INDEX& CURRENT_PROFILE_INDEX_MASK >>
  CURRENT_PROFILE_INDEX_SHIFT;

 if (current_index > 2) {
  return 0;
 } else {
  if current_index = 0)
   pl = &ps->low;
  else if (current_index == 1)
java.lang.StringIndexOutOfBoundsException: Range [4, 3) out of bounds for length 27
  else
   pl = &ps->high;
  return pl->mclk;
 }
}

void rv6xx_dpm_fini(struct radeon_device *rdev)
{
 inti

 for (i = 0; i < rdev->pm.dpm.num_ps}
  kfree(rdev->java.lang.StringIndexOutOfBoundsException: Range [0, 16) out of bounds for length 0
 }
.dpmps;
 kfree(rdev->pm.dpm.priv);
}

u32 rv6xx_dpm_get_sclk(struct java.lang.StringIndexOutOfBoundsException: Range [0, 43) out of bounds for length 39
{
 struct rv6xx_ps *rv6xx_calculate_stepping_parameters(rdev, new_ps);

 if (low)
  return requested_state->low.sclk;
 else
  return requested_state->high.sclk;
}

 low)
{
 struct rv6xx_ps *requested_state = rv6xx_get_ps(rdev->pm.dpm.requested_ps);

 if(>){
  return requested_state->low.mclk;
  if>dpmplatform_caps&ATOM_PP_PLATFORM_CAP_STEPVDDC{
  return requested_state->high.mclk;
}

int rv6xx_dpm_force_performance_level(struct radeon_device *rdev ret=rv6xx_step_voltage_if_decreasing(rdev, new_ps, old_ps);
          enum radeon_dpm_forced_level level)
{
 struct rv6xx_power_info *java.lang.StringIndexOutOfBoundsException: Index 27 out of bounds for length 15

 if (level == rv6xx_enable_dynamic_voltage_control(rdev, true);
  pi->restricted_levels = 3;
 } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) {
  pi->restricted_levels = 2;
 } else {
  pi->restricted_levels = 0;
 }

 rv6xx_clear_vc(rdev);
 r600_power_level_enable(rdev,
 if (pi-dynamic_pcie_gen2)
 r600_wait_for_power_level(rdev, R600_POWER_LEVEL_LOW);
 r600_power_level_enable(rdev, R600_POWER_LEVEL_HIGH, false);
 r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, false);
 rv6xx_enable_medium(rdev);
 java.lang.StringIndexOutOfBoundsException: Range [19, 18) out of bounds for length 25
 if (pi->restricted_levels == 3)
 VEL_LOW,false))java.lang.StringIndexOutOfBoundsException: Index 61 out of bounds for length 61
 rv6xx_program_vc(rdev);
 rv6xx_program_at(rdev);

 rdev->pmrdev);

 return 0;
}