Quelle htt.h
Sprache: C
/* SPDX-License-Identifier: ISC */ /* * Copyright ( c ) 2005 - 2011 Atheros Communications Inc . * Copyright ( c ) 2011 - 2017 Qualcomm Atheros , Inc . * Copyright ( c ) 2018 , The Linux Foundation . All rights reserved . * Copyright ( c ) 2021 , 2023 - 2024 Qualcomm Innovation Center , Inc . All rights reserved . #ifndef _HTT_H_#define _HTT_H_#include <linux/bug.h>#include <linux/interrupt.h>#include <linux/dmapool.h>#include <linux/hashtable.h>#include <linux/kfifo.h>#include <net/mac80211.h>#include "htc.h" #include "hw.h" #include "rx_desc.h" enum htt_dbg_stats_type {1 << 0 ,1 << 1 ,1 << 2 ,1 << 3 ,1 << 4 ,/* bits 5-23 currently reserved */ /* keep this last */ enum htt_h2t_msg_type { /* host-to-target */ 0 ,1 ,2 ,3 ,4 ,5 ,6 ,/* This command is used for sending management frames in HTT < 3.0. * HTT > = 3 . 0 uses TX_FRM for everything . 7 ,11 ,/* keep this last */ struct htt_cmd_hdr {struct htt_ver_req {sizeof (u32) - sizeof (struct htt_cmd_hdr)];/* * HTT tx MSDU descriptor * * The HTT tx MSDU descriptor is created by the host HTT SW for each * tx MSDU . The HTT tx MSDU descriptor contains the information that * the target firmware needs for the FW ' s tx processing , particularly * for creating the HW msdu descriptor . * The same HTT tx descriptor is used for HL and LL systems , though * a few fields within the tx descriptor are used only by LL or * only by HL . * The HTT tx descriptor is defined in two manners : by a struct with * bitfields , and by a series of [ dword offset , bit mask , bit shift ] * definitions . * The target should use the struct def , for simplicity and clarity , * but the host shall use the bit - mast + bit - shift defs , to be endian - * neutral . Specifically , the host shall use the get / set macros built * around the mask + shift defs . struct htt_data_tx_desc_frag {union {struct double_word_addr {struct triple_word_addr {struct htt_msdu_ext_desc {3 ];struct htt_data_tx_desc_frag frags[6 ];struct htt_msdu_ext_desc_64 {5 ];struct htt_data_tx_desc_frag frags[6 ];#define HTT_MSDU_EXT_DESC_FLAG_IPV4_CSUM_ENABLE BIT(0 )#define HTT_MSDU_EXT_DESC_FLAG_UDP_IPV4_CSUM_ENABLE BIT(1 )#define HTT_MSDU_EXT_DESC_FLAG_UDP_IPV6_CSUM_ENABLE BIT(2 )#define HTT_MSDU_EXT_DESC_FLAG_TCP_IPV4_CSUM_ENABLE BIT(3 )#define HTT_MSDU_EXT_DESC_FLAG_TCP_IPV6_CSUM_ENABLE BIT(4 )#define HTT_MSDU_CHECKSUM_ENABLE (HTT_MSDU_EXT_DESC_FLAG_IPV4_CSUM_ENABLE \#define HTT_MSDU_EXT_DESC_FLAG_IPV4_CSUM_ENABLE_64 BIT(16 )#define HTT_MSDU_EXT_DESC_FLAG_UDP_IPV4_CSUM_ENABLE_64 BIT(17 )#define HTT_MSDU_EXT_DESC_FLAG_UDP_IPV6_CSUM_ENABLE_64 BIT(18 )#define HTT_MSDU_EXT_DESC_FLAG_TCP_IPV4_CSUM_ENABLE_64 BIT(19 )#define HTT_MSDU_EXT_DESC_FLAG_TCP_IPV6_CSUM_ENABLE_64 BIT(20 )#define HTT_MSDU_EXT_DESC_FLAG_PARTIAL_CSUM_ENABLE_64 BIT(21 )#define HTT_MSDU_CHECKSUM_ENABLE_64 (HTT_MSDU_EXT_DESC_FLAG_IPV4_CSUM_ENABLE_64 \enum htt_data_tx_desc_flags0 {1 << 0 ,1 << 1 ,1 << 2 ,1 << 3 ,1 << 4 #define HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE_MASK 0 xE0#define HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE_LSB 5 enum htt_data_tx_desc_flags1 {#define HTT_DATA_TX_DESC_FLAGS1_VDEV_ID_BITS 6 #define HTT_DATA_TX_DESC_FLAGS1_VDEV_ID_MASK 0 x003F#define HTT_DATA_TX_DESC_FLAGS1_VDEV_ID_LSB 0 #define HTT_DATA_TX_DESC_FLAGS1_EXT_TID_BITS 5 #define HTT_DATA_TX_DESC_FLAGS1_EXT_TID_MASK 0 x07C0#define HTT_DATA_TX_DESC_FLAGS1_EXT_TID_LSB 6 1 << 11 ,1 << 12 ,1 << 13 ,1 << 14 ,1 << 15 #define HTT_TX_CREDIT_DELTA_ABS_M 0 xffff0000#define HTT_TX_CREDIT_DELTA_ABS_S 16 #define HTT_TX_CREDIT_DELTA_ABS_GET(word) \#define HTT_TX_CREDIT_SIGN_BIT_M 0 x00000100#define HTT_TX_CREDIT_SIGN_BIT_S 8 #define HTT_TX_CREDIT_SIGN_BIT_GET(word) \enum htt_data_tx_ext_tid {16 ,17 ,31 #define HTT_INVALID_PEERID 0 xFFFF/* * htt_data_tx_desc - used for data tx path * * Note : vdev_id irrelevant for pkt_type = = raw and no_classify = = 1 . * ext_tid : for qos - data frames ( 0 - 15 ) , see % HTT_DATA_TX_EXT_TID_ * for special kinds of tids * postponed : only for HL hosts . indicates if this is a resend * ( HL hosts manage queues on the host ) * more_in_batch : only for HL hosts . indicates if more packets are * pending . this allows target to wait and aggregate * freq : 0 means home channel of given vdev . intended for offchannel struct htt_data_tx_desc {/* %HTT_DATA_TX_DESC_FLAGS0_ */ /* %HTT_DATA_TX_DESC_FLAGS1_ */ union {struct {0 ]; /* start of frame, for FW classification engine */ struct htt_data_tx_desc_64 {/* %HTT_DATA_TX_DESC_FLAGS0_ */ /* %HTT_DATA_TX_DESC_FLAGS1_ */ union {struct {0 ]; /* start of frame, for FW classification engine */ enum htt_rx_ring_flags {1 << 0 ,1 << 1 ,1 << 2 ,1 << 3 ,1 << 4 ,1 << 5 ,1 << 6 ,1 << 7 ,1 << 8 ,1 << 9 ,1 << 10 ,1 << 11 ,1 << 12 ,1 << 13 ,1 << 14 ,1 << 15 #define HTT_RX_RING_SIZE_MIN 128 #define HTT_RX_RING_SIZE_MAX 2048 #define HTT_RX_RING_SIZE HTT_RX_RING_SIZE_MAX#define HTT_RX_RING_FILL_LEVEL (((HTT_RX_RING_SIZE) / 2 ) - 1 )#define HTT_RX_RING_FILL_LEVEL_DUAL_MAC (HTT_RX_RING_SIZE - 1 )struct htt_rx_ring_rx_desc_offsets {/* the following offsets are in 4-byte units */ struct htt_rx_ring_setup_ring32 {/* in 4-byte words */ /* rx skb size - in bytes */ /* %HTT_RX_RING_FLAGS_ */ struct htt_rx_ring_rx_desc_offsets offsets;struct htt_rx_ring_setup_ring64 {/* in 4-byte words */ /* rx skb size - in bytes */ /* %HTT_RX_RING_FLAGS_ */ struct htt_rx_ring_rx_desc_offsets offsets;struct htt_rx_ring_setup_hdr {/* supported values: 1, 2 */ struct htt_rx_ring_setup_32 {struct htt_rx_ring_setup_hdr hdr;struct htt_rx_ring_setup_ring32 rings[];struct htt_rx_ring_setup_64 {struct htt_rx_ring_setup_hdr hdr;struct htt_rx_ring_setup_ring64 rings[];/* * htt_stats_req - request target to send specified statistics * * @ msg_type : hardcoded % HTT_H2T_MSG_TYPE_STATS_REQ * @ upload_types : see % htt_dbg_stats_type . this is 24 bit field actually * so make sure its little - endian . * @ reset_types : see % htt_dbg_stats_type . this is 24 bit field actually * so make sure its little - endian . * @ cfg_val : stat_type specific configuration * @ stat_type : see % htt_dbg_stats_type * @ cookie_lsb : used for confirmation message from target - > host * @ cookie_msb : ditto as % cookie struct htt_stats_req {3 ];3 ];struct {#define HTT_STATS_REQ_CFG_STAT_TYPE_INVALID 0 xff#define HTT_STATS_BIT_MASK GENMASK(16 , 0 )/* * htt_oob_sync_req - request out - of - band sync * * The HTT SYNC tells the target to suspend processing of subsequent * HTT host - to - target messages until some other target agent locally * informs the target HTT FW that the current sync counter is equal to * or greater than ( in a modulo sense ) the sync counter specified in * the SYNC message . * * This allows other host - target components to synchronize their operation * with HTT , e . g . to ensure that tx frames don ' t get transmitted until a * security key has been downloaded to and activated by the target . * In the absence of any explicit synchronization counter value * specification , the target HTT FW will use zero as the default current * sync value . * * The HTT target FW will suspend its host - > target message processing as long * as 0 < ( in - band sync counter - out - of - band sync counter ) & 0 xff < 128 . struct htt_oob_sync_req {struct htt_aggr_conf {/* amsdu_subframes is limited by 0x1F mask */ struct htt_aggr_conf_v2 {/* amsdu_subframes is limited by 0x1F mask */ #define HTT_MGMT_FRM_HDR_DOWNLOAD_LEN 32 struct htt_mgmt_tx_desc_qca99x0 {struct htt_mgmt_tx_desc {sizeof (u32) - sizeof (struct htt_cmd_hdr)];union {struct htt_mgmt_tx_desc_qca99x0 qca99x0;enum htt_mgmt_tx_status {0 ,1 ,2 /*=== target -> host messages ===============================================*/ enum htt_main_t2h_msg_type {0 x0,0 x1,0 x2,0 x3,0 x4,0 x5,0 x6,0 x7,0 x8,0 x9,0 xa,0 xb,0 xd,0 xe,0 xf,0 x10,0 x11,/* keep this last */ enum htt_10x_t2h_msg_type {0 x0,0 x1,0 x2,0 x3,0 x4,0 x5,0 x6,0 x7,0 x8,0 x9,0 xa,0 xb,0 xc,0 xd,0 xe,0 xf,0 x11,0 x12,0 x13,/* keep this last */ enum htt_tlv_t2h_msg_type {0 x0,0 x1,0 x2,0 x3,0 x4,0 x5,0 x6,0 x7,0 x8,0 x9,0 xa,0 xb,0 xc, /* deprecated */ 0 xd,0 xe,0 xf,0 x10,0 x11,0 x12,/* 0x13 reservd */ 0 x14,0 x15,0 x16,/* keep this last */ enum htt_10_4_t2h_msg_type {0 x0,0 x1,0 x2,0 x3,0 x4,0 x5,0 x6,0 x7,0 x8,0 x9,0 xa,0 xb,0 xc,0 xd,0 xe,0 xf,0 x10,0 x11,0 x12,0 x13,0 x14,0 x15,0 x16,0 x17,0 x18,/* 0x19 to 0x2f are reserved */ 0 x30,0 x31,/* keep this last */ enum htt_t2h_msg_type {/* keep this last */ /* * htt_resp_hdr - header for target - to - host messages * * msg_type : see htt_t2h_msg_type struct htt_resp_hdr {#define HTT_RESP_HDR_MSG_TYPE_OFFSET 0 #define HTT_RESP_HDR_MSG_TYPE_MASK 0 xff#define HTT_RESP_HDR_MSG_TYPE_LSB 0 /* htt_ver_resp - response sent for htt_ver_req */ struct htt_ver_resp {#define HTT_MGMT_TX_CMPL_FLAG_ACK_RSSI BIT(0 )#define HTT_MGMT_TX_CMPL_INFO_ACK_RSSI_MASK GENMASK(7 , 0 )struct htt_mgmt_tx_completion {#define HTT_RX_INDICATION_INFO0_EXT_TID_MASK (0 x1F)#define HTT_RX_INDICATION_INFO0_EXT_TID_LSB (0 )#define HTT_RX_INDICATION_INFO0_FLUSH_VALID (1 << 5 )#define HTT_RX_INDICATION_INFO0_RELEASE_VALID (1 << 6 )#define HTT_RX_INDICATION_INFO0_PPDU_DURATION BIT(7 )#define HTT_RX_INDICATION_INFO1_FLUSH_START_SEQNO_MASK 0 x0000003F#define HTT_RX_INDICATION_INFO1_FLUSH_START_SEQNO_LSB 0 #define HTT_RX_INDICATION_INFO1_FLUSH_END_SEQNO_MASK 0 x00000FC0#define HTT_RX_INDICATION_INFO1_FLUSH_END_SEQNO_LSB 6 #define HTT_RX_INDICATION_INFO1_RELEASE_START_SEQNO_MASK 0 x0003F000#define HTT_RX_INDICATION_INFO1_RELEASE_START_SEQNO_LSB 12 #define HTT_RX_INDICATION_INFO1_RELEASE_END_SEQNO_MASK 0 x00FC0000#define HTT_RX_INDICATION_INFO1_RELEASE_END_SEQNO_LSB 18 #define HTT_RX_INDICATION_INFO1_NUM_MPDU_RANGES_MASK 0 xFF000000#define HTT_RX_INDICATION_INFO1_NUM_MPDU_RANGES_LSB 24 #define HTT_TX_CMPL_FLAG_DATA_RSSI BIT(0 )#define HTT_TX_CMPL_FLAG_PPID_PRESENT BIT(1 )#define HTT_TX_CMPL_FLAG_PA_PRESENT BIT(2 )#define HTT_TX_CMPL_FLAG_PPDU_DURATION_PRESENT BIT(3 )#define HTT_TX_DATA_RSSI_ENABLE_WCN3990 BIT(3 )#define HTT_TX_DATA_APPEND_RETRIES BIT(0 )#define HTT_TX_DATA_APPEND_TIMESTAMP BIT(1 )struct htt_rx_indication_hdr {/* %HTT_RX_INDICATION_INFO0_ */ /* %HTT_RX_INDICATION_INFO1_ */ #define HTT_RX_INDICATION_INFO0_PHY_ERR_VALID (1 << 0 )#define HTT_RX_INDICATION_INFO0_LEGACY_RATE_MASK (0 x1E)#define HTT_RX_INDICATION_INFO0_LEGACY_RATE_LSB (1 )#define HTT_RX_INDICATION_INFO0_LEGACY_RATE_CCK (1 << 5 )#define HTT_RX_INDICATION_INFO0_END_VALID (1 << 6 )#define HTT_RX_INDICATION_INFO0_START_VALID (1 << 7 )#define HTT_RX_INDICATION_INFO1_VHT_SIG_A1_MASK 0 x00FFFFFF#define HTT_RX_INDICATION_INFO1_VHT_SIG_A1_LSB 0 #define HTT_RX_INDICATION_INFO1_PREAMBLE_TYPE_MASK 0 xFF000000#define HTT_RX_INDICATION_INFO1_PREAMBLE_TYPE_LSB 24 #define HTT_RX_INDICATION_INFO2_VHT_SIG_A1_MASK 0 x00FFFFFF#define HTT_RX_INDICATION_INFO2_VHT_SIG_A1_LSB 0 #define HTT_RX_INDICATION_INFO2_SERVICE_MASK 0 xFF000000#define HTT_RX_INDICATION_INFO2_SERVICE_LSB 24 enum htt_rx_legacy_rate {0 ,1 ,/* long preamble */ 0 ,1 ,/* short preamble */ enum htt_rx_legacy_rate_type {0 ,enum htt_rx_preamble_type {0 x4,0 x8,0 x9,0 xC,0 xD,/* * Fields : phy_err_valid , phy_err_code , tsf , * usec_timestamp , sub_usec_timestamp * . . are valid only if end_valid = = 1 . * * Fields : rssi_chains , legacy_rate_type , * legacy_rate_cck , preamble_type , service , * vht_sig_ * * . . are valid only if start_valid = = 1 ; struct htt_rx_indication_ppdu {/* HTT_RX_INDICATION_INFO0_ */ struct {4 ];/* HTT_RX_INDICATION_INFO1_ */ /* HTT_RX_INDICATION_INFO2_ */ enum htt_rx_mpdu_status {0 x0,/* only accept EAPOL frames */ /* Non-data in promiscuous mode */ /* * MISC : discard for unspecified reasons . * Leave this enum value last . 0 xFFstruct htt_rx_indication_mpdu_range {/* %htt_rx_mpdu_status */ struct htt_rx_indication_prefix {struct htt_rx_indication {struct htt_rx_indication_hdr hdr;struct htt_rx_indication_ppdu ppdu;struct htt_rx_indication_prefix prefix;/* * the following fields are both dynamically sized , so * take care addressing them /* the size of this is %fw_rx_desc_bytes */ struct fw_rx_desc_base fw_desc;/* * % mpdu_ranges starts after & % prefix + roundup ( % fw_rx_desc_bytes , 4 ) * and has % num_mpdu_ranges elements . struct htt_rx_indication_mpdu_range mpdu_ranges[];/* High latency version of the RX indication */ struct htt_rx_indication_hl {struct htt_rx_indication_hdr hdr;struct htt_rx_indication_ppdu ppdu;struct htt_rx_indication_prefix prefix;struct fw_rx_desc_hl fw_desc;struct htt_rx_indication_mpdu_range mpdu_ranges[];struct htt_hl_rx_desc {union {struct {static inline struct htt_rx_indication_mpdu_range *struct htt_rx_indication *rx_ind)void *ptr = rx_ind;sizeof (rx_ind->hdr)sizeof (rx_ind->ppdu)sizeof (rx_ind->prefix)4 );return ptr;static inline struct htt_rx_indication_mpdu_range *struct htt_rx_indication_hl *rx_ind)void *ptr = rx_ind;sizeof (rx_ind->hdr)sizeof (rx_ind->ppdu)sizeof (rx_ind->prefix)sizeof (rx_ind->fw_desc);return ptr;enum htt_rx_flush_mpdu_status {0 ,1 ,/* * htt_rx_flush - discard or reorder given range of mpdus * * Note : host must check if all sequence numbers between * [ seq_num_start , seq_num_end - 1 ] are valid . struct htt_rx_flush {/* %htt_rx_flush_mpdu_status */ /* it is 6 LSBs of 802.11 seq no */ /* it is 6 LSBs of 802.11 seq no */ struct htt_rx_peer_map {6 ];struct htt_rx_peer_unmap {enum htt_txrx_sec_cast_type {0 ,enum htt_rx_pn_check_type {0 ,enum htt_rx_tkip_demic_type {0 ,enum htt_security_types {/* keep this last! */ #define ATH10K_HTT_TXRX_PEER_SECURITY_MAX 2 #define ATH10K_TXRX_NUM_EXT_TIDS 19 #define ATH10K_TXRX_NON_QOS_TID 16 enum htt_security_flags {#define HTT_SECURITY_TYPE_MASK 0 x7F#define HTT_SECURITY_TYPE_LSB 0 1 << 7 struct htt_security_indication {union {/* dont use bitfields; undefined behaviour */ /* %htt_security_flags */ struct {7 , /* %htt_security_types */ 1 ;8 ];16 ];#define HTT_RX_BA_INFO0_TID_MASK 0 x000F#define HTT_RX_BA_INFO0_TID_LSB 0 #define HTT_RX_BA_INFO0_PEER_ID_MASK 0 xFFF0#define HTT_RX_BA_INFO0_PEER_ID_LSB 4 struct htt_rx_addba {/* %HTT_RX_BA_INFO0_ */ struct htt_rx_delba {/* %HTT_RX_BA_INFO0_ */ enum htt_data_tx_status {0 ,1 ,2 ,3 /* HL only */ enum htt_data_tx_flags {#define HTT_DATA_TX_STATUS_MASK 0 x07#define HTT_DATA_TX_STATUS_LSB 0 #define HTT_DATA_TX_TID_MASK 0 x78#define HTT_DATA_TX_TID_LSB 3 1 << 7 #define HTT_TX_COMPL_INV_MSDU_ID 0 xFFFFstruct htt_append_retries {struct htt_data_tx_completion_ext {struct htt_append_retries a_retries;/* * @ brief target - > host TX completion indication message definition * * @ details * The following diagram shows the format of the TX completion indication sent * from the target to the host * * | 31 28 | 27 | 26 | 25 | 24 | 23 16 | 15 | 14 11 | 10 8 | 7 0 | * | - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - | * header : | rsvd | A2 | TP | A1 | A0 | num | t_i | tid | status | msg_type | * | - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - | * payload : | MSDU1 ID | MSDU0 ID | * | - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - | * : MSDU3 ID : MSDU2 ID : * | - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - | * | struct htt_tx_compl_ind_append_retries | * | - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - | * | struct htt_tx_compl_ind_append_tx_tstamp | * | - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - | * | MSDU1 ACK RSSI | MSDU0 ACK RSSI | * | - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - | * : MSDU3 ACK RSSI : MSDU2 ACK RSSI : * | - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - | * - msg_type * Bits 7 : 0 * Purpose : identifies this as HTT TX completion indication * - status * Bits 10 : 8 * Purpose : the TX completion status of payload fragmentations descriptors * Value : could be HTT_TX_COMPL_IND_STAT_OK or HTT_TX_COMPL_IND_STAT_DISCARD * - tid * Bits 14 : 11 * Purpose : the tid associated with those fragmentation descriptors . It is * valid or not , depending on the tid_invalid bit . * Value : 0 to 15 * - tid_invalid * Bits 15 : 15 * Purpose : this bit indicates whether the tid field is valid or not * Value : 0 indicates valid , 1 indicates invalid * - num * Bits 23 : 16 * Purpose : the number of payload in this indication * Value : 1 to 255 * - A0 = append * Bits 24 : 24 * Purpose : append the struct htt_tx_compl_ind_append_retries which contains * the number of tx retries for one MSDU at the end of this message * Value : 0 indicates no appending , 1 indicates appending * - A1 = append1 * Bits 25 : 25 * Purpose : Append the struct htt_tx_compl_ind_append_tx_tstamp which * contains the timestamp info for each TX msdu id in payload . * Value : 0 indicates no appending , 1 indicates appending * - TP = MSDU tx power presence * Bits 26 : 26 * Purpose : Indicate whether the TX_COMPL_IND includes a tx power report * for each MSDU referenced by the TX_COMPL_IND message . * The order of the per - MSDU tx power reports matches the order * of the MSDU IDs . * Value : 0 indicates not appending , 1 indicates appending * - A2 = append2 * Bits 27 : 27 * Purpose : Indicate whether data ACK RSSI is appended for each MSDU in * TX_COMP_IND message . The order of the per - MSDU ACK RSSI report * matches the order of the MSDU IDs . * The ACK RSSI values are valid when status is COMPLETE_OK ( and * this append2 bit is set ) . * Value : 0 indicates not appending , 1 indicates appending struct htt_data_tx_completion {union {struct {3 ,4 ,1 ;/* HTT_TX_CMPL_FLAG_DATA_RSSI */ /* variable length based on %num_msdus */ #define HTT_TX_PPDU_DUR_INFO0_PEER_ID_MASK GENMASK(15 , 0 )#define HTT_TX_PPDU_DUR_INFO0_TID_MASK GENMASK(20 , 16 )struct htt_data_tx_ppdu_dur {/* HTT_TX_PPDU_DUR_INFO0_ */ /* in usecs */ #define HTT_TX_COMPL_PPDU_DUR_INFO0_NUM_ENTRIES_MASK GENMASK(7 , 0 )struct htt_data_tx_compl_ppdu_dur {/* HTT_TX_COMPL_PPDU_DUR_INFO0_ */ struct htt_data_tx_ppdu_dur ppdu_dur[];struct htt_tx_compl_ind_base {1 /*or more*/]; struct htt_rc_tx_done_params {/* 1 for non-AMPDU */ /* for AMPDU */ struct htt_rc_update {6 ];struct htt_rc_tx_done_params params[]; /* variable length %num_elems */ /* see htt_rx_indication for similar fields and descriptions */ struct htt_rx_fragment_indication {union {/* %HTT_RX_FRAG_IND_INFO0_ */ struct {5 ,1 ;/* %HTT_RX_FRAG_IND_INFO1_ */ #define ATH10K_IEEE80211_EXTIV BIT(5 )#define ATH10K_IEEE80211_TKIP_MICLEN 8 /* trailing MIC */ #define HTT_RX_FRAG_IND_INFO0_HEADER_LEN 16 #define HTT_RX_FRAG_IND_INFO0_EXT_TID_MASK 0 x1F#define HTT_RX_FRAG_IND_INFO0_EXT_TID_LSB 0 #define HTT_RX_FRAG_IND_INFO0_FLUSH_VALID_MASK 0 x20#define HTT_RX_FRAG_IND_INFO0_FLUSH_VALID_LSB 5 #define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_START_MASK 0 x0000003F#define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_START_LSB 0 #define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_END_MASK 0 x00000FC0#define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_END_LSB 6 struct htt_rx_pn_ind {struct htt_rx_offload_msdu {struct htt_rx_offload_ind {struct htt_rx_in_ord_msdu_desc {struct htt_rx_in_ord_msdu_desc_ext {struct htt_rx_in_ord_ind {union {struct htt_rx_in_ord_msdu_desc,struct htt_rx_in_ord_msdu_desc_ext,#define HTT_RX_IN_ORD_IND_INFO_TID_MASK 0 x0000001f#define HTT_RX_IN_ORD_IND_INFO_TID_LSB 0 #define HTT_RX_IN_ORD_IND_INFO_OFFLOAD_MASK 0 x00000020#define HTT_RX_IN_ORD_IND_INFO_OFFLOAD_LSB 5 #define HTT_RX_IN_ORD_IND_INFO_FRAG_MASK 0 x00000040#define HTT_RX_IN_ORD_IND_INFO_FRAG_LSB 6 /* * target - > host test message definition * * The following field definitions describe the format of the test * message sent from the target to the host . * The message consists of a 4 - octet header , followed by a variable * number of 32 - bit integer values , followed by a variable number * of 8 - bit character values . * * | 31 16 | 15 8 | 7 0 | * | - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - | * | num chars | num ints | msg type | * | - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - | * | int 0 | * | - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - | * | int 1 | * | - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - | * | . . . | * | - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - | * | char 3 | char 2 | char 1 | char 0 | * | - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - | * | | | . . . | char 4 | * | - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - | * - MSG_TYPE * Bits 7 : 0 * Purpose : identifies this as a test message * Value : HTT_MSG_TYPE_TEST * - NUM_INTS * Bits 15 : 8 * Purpose : indicate how many 32 - bit integers follow the message header * - NUM_CHARS * Bits 31 : 16 * Purpose : indicate how many 8 - bit characters follow the series of integers struct htt_rx_test {/* payload consists of 2 lists: * a ) num_ints * sizeof ( _ _ le32 ) * b ) num_chars * sizeof ( u8 ) aligned to 4 bytes static inline __le32 *htt_rx_test_get_ints(struct htt_rx_test *rx_test)return (__le32 *)rx_test->payload;static inline u8 *htt_rx_test_get_chars(struct htt_rx_test *rx_test)return rx_test->payload + (rx_test->num_ints * sizeof (__le32));/* * target - > host packet log message * * The following field definitions describe the format of the packet log * message sent from the target to the host . * The message consists of a 4 - octet header , followed by a variable number * of 32 - bit character values . * * | 31 24 | 23 16 | 15 8 | 7 0 | * | - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - | * | | | | msg type | * | - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - | * | payload | * | - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - | * - MSG_TYPE * Bits 7 : 0 * Purpose : identifies this as a test message * Value : HTT_MSG_TYPE_PACKETLOG struct htt_pktlog_msg {3 ];struct htt_dbg_stats_rx_reorder_stats {/* Non QoS MPDUs received */ /* MPDUs received in-order */ /* Flush due to reorder timer expired */ /* Flush due to move out of window */ /* Flush due to DELBA */ /* MPDUs dropped due to FCS error */ /* MPDUs dropped due to monitor mode non-data packet */ /* MPDUs dropped due to invalid peer */ /* MPDUs dropped due to duplication (non aggregation) */ /* MPDUs dropped due to processed before */ /* MPDUs dropped due to duplicate in reorder queue */ /* Reorder timeout happened */ /* invalid bar ssn */ /* reorder reset due to bar ssn */ struct htt_dbg_stats_wal_tx_stats {/* Num HTT cookies queued to dispatch list */ /* Num HTT cookies dispatched */ /* Num MSDU queued to WAL */ /* Num MPDU queue to WAL */ /* Num MSDUs dropped by WMM limit */ /* Num Local frames queued */ /* Num Local frames done */ /* Num queued to HW */ /* Num PPDU reaped from HW */ /* Num underruns */ /* Num PPDUs cleaned up in TX abort */ /* Num MPDUs requeued by SW */ /* excessive retries */ /* data hw rate code */ /* Scheduler self triggers */ /* frames dropped due to excessive sw retries */ /* illegal rate phy errors */ /* wal pdev continuous xretry */ /* wal pdev continuous xretry */ /* wal pdev resets */ /* MPDU is more than txop limit */ struct htt_dbg_stats_wal_rx_stats {/* Cnts any change in ring routing mid-ppdu */ /* Total number of statuses processed */ /* Extra frags on rings 0-3 */ /* MSDUs / MPDUs delivered to HTT */ /* MSDUs / MPDUs delivered to local stack */ /* AMSDUs that have more MSDUs than the status ring size */ /* Number of PHY errors */ /* Number of PHY errors drops */ /* Number of mpdu errors - FCS, MIC, ENC etc. */ struct htt_dbg_stats_wal_peer_stats {/* REMOVE THIS ONCE REAL PEER STAT COUNTERS ARE ADDED */ struct htt_dbg_stats_wal_pdev_txrx {struct htt_dbg_stats_wal_tx_stats tx_stats;struct htt_dbg_stats_wal_rx_stats rx_stats;struct htt_dbg_stats_wal_peer_stats peer_stats;struct htt_dbg_stats_rx_rate_info {10 ];10 ];4 ];10 ];3 ];6 ];/* * htt_dbg_stats_status - * present - The requested stats have been delivered in full . * This indicates that either the stats information was contained * in its entirety within this message , or else this message * completes the delivery of the requested stats info that was * partially delivered through earlier STATS_CONF messages . * partial - The requested stats have been delivered in part . * One or more subsequent STATS_CONF messages with the same * cookie value will be sent to deliver the remainder of the * information . * error - The requested stats could not be delivered , for example due * to a shortage of memory to construct a message holding the * requested stats . * invalid - The requested stat type is either not recognized , or the * target is configured to not gather the stats type in question . * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * series_done - This special value indicates that no further stats info * elements are present within a series of stats info elems * ( within a stats upload confirmation message ) . enum htt_dbg_stats_status {0 ,1 ,2 ,3 ,7 /* * host - > target FRAG DESCRIPTOR / MSDU_EXT DESC bank * * The following field definitions describe the format of the HTT host * to target frag_desc / msdu_ext bank configuration message . * The message contains the based address and the min and max id of the * MSDU_EXT / FRAG_DESC that will be used by the HTT to map MSDU DESC and * MSDU_EXT / FRAG_DESC . * HTT will use id in HTT descriptor instead sending the frag_desc_ptr . * For QCA988X HW the firmware will use fragment_desc_ptr but in WIFI2 . 0 * the hardware does the mapping / translation . * * Total banks that can be configured is configured to 16 . * * This should be called before any TX has be initiated by the HTT * * | 31 16 | 15 8 | 7 5 | 4 0 | * | - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - | * | DESC_SIZE | NUM_BANKS | RES | SWP | pdev | msg type | * | - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - | * | BANK0_BASE_ADDRESS | * | - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - | * | . . . | * | - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - | * | BANK15_BASE_ADDRESS | * | - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - | * | BANK0_MAX_ID | BANK0_MIN_ID | * | - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - | * | . . . | * | - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - | * | BANK15_MAX_ID | BANK15_MIN_ID | * | - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - | * Header fields : * - MSG_TYPE * Bits 7 : 0 * Value : 0 x6 * - BANKx_BASE_ADDRESS * Bits 31 : 0 * Purpose : Provide a mechanism to specify the base address of the MSDU_EXT * bank physical / bus address . * - BANKx_MIN_ID * Bits 15 : 0 * Purpose : Provide a mechanism to specify the min index that needs to * mapped . * - BANKx_MAX_ID * Bits 31 : 16 * Purpose : Provide a mechanism to specify the max index that needs to * struct htt_frag_desc_bank_id {/* real is 16 but it wouldn't fit in the max htt message size * so we use a conservatively safe value for now #define HTT_FRAG_DESC_BANK_MAX 4 #define HTT_FRAG_DESC_BANK_CFG_INFO_PDEV_ID_MASK 0 x03#define HTT_FRAG_DESC_BANK_CFG_INFO_PDEV_ID_LSB 0 #define HTT_FRAG_DESC_BANK_CFG_INFO_SWAP BIT(2 )#define HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_VALID BIT(3 )#define HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_DEPTH_TYPE_MASK BIT(4 )#define HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_DEPTH_TYPE_LSB 4 enum htt_q_depth_type {0 ,1 ,#define HTT_TX_Q_STATE_NUM_PEERS (TARGET_10_4_NUM_QCACHE_PEERS_MAX + \#define HTT_TX_Q_STATE_NUM_TIDS 8 #define HTT_TX_Q_STATE_ENTRY_SIZE 1 #define HTT_TX_Q_STATE_ENTRY_MULTIPLIER 0 /** * struct htt_q_state_conf - part of htt_frag_desc_bank_cfg for host q state config * * Defines host q state format and behavior . See htt_q_state . * * @ paddr : Queue physical address * @ num_peers : Number of supported peers * @ num_tids : Number of supported TIDs * @ record_size : Defines the size of each host q entry in bytes . In practice * however firmware ( at least 10 . 4 . 3 - 00191 ) ignores this host * configuration value and uses hardcoded value of 1 . * @ record_multiplier : This is valid only when q depth type is MSDUs . It * defines the exponent for the power of 2 multiplication . * @ pad : struct padding for 32 - bit alignment struct htt_q_state_conf {2 ];struct htt_frag_desc_bank_cfg32 {/* HTT_FRAG_DESC_BANK_CFG_INFO_ */ struct htt_frag_desc_bank_id bank_id[HTT_FRAG_DESC_BANK_MAX];struct htt_q_state_conf q_state;struct htt_frag_desc_bank_cfg64 {/* HTT_FRAG_DESC_BANK_CFG_INFO_ */ struct htt_frag_desc_bank_id bank_id[HTT_FRAG_DESC_BANK_MAX];struct htt_q_state_conf q_state;#define HTT_TX_Q_STATE_ENTRY_COEFFICIENT 128 #define HTT_TX_Q_STATE_ENTRY_FACTOR_MASK 0 x3f#define HTT_TX_Q_STATE_ENTRY_FACTOR_LSB 0 #define HTT_TX_Q_STATE_ENTRY_EXP_MASK 0 xc0#define HTT_TX_Q_STATE_ENTRY_EXP_LSB 6 /** * struct htt_q_state - shared between host and firmware via DMA * * This structure is used for the host to expose it ' s software queue state to * firmware so that its rate control can schedule fetch requests for optimized * performance . This is most notably used for MU - MIMO aggregation when multiple * MU clients are connected . * * @ count : Each element defines the host queue depth . When q depth type was * configured as HTT_Q_DEPTH_TYPE_BYTES then each entry is defined as : * FACTOR * 128 * 8 ^ EXP ( see HTT_TX_Q_STATE_ENTRY_FACTOR_MASK and * HTT_TX_Q_STATE_ENTRY_EXP_MASK ) . When q depth type was configured as * HTT_Q_DEPTH_TYPE_MSDUS the number of packets is scaled by 2 * * * record_multiplier ( see htt_q_state_conf ) . * @ map : Used by firmware to quickly check which host queues are not empty . It * is a bitmap simply saying . * @ seq : Used by firmware to quickly check if the host queues were updated * since it last checked . * * FIXME : Is the q_state map [ ] size calculation really correct ? struct htt_q_state {31 ) / 32 ];#define HTT_TX_FETCH_RECORD_INFO_PEER_ID_MASK 0 x0fff#define HTT_TX_FETCH_RECORD_INFO_PEER_ID_LSB 0 #define HTT_TX_FETCH_RECORD_INFO_TID_MASK 0 xf000#define HTT_TX_FETCH_RECORD_INFO_TID_LSB 12 struct htt_tx_fetch_record {/* HTT_TX_FETCH_IND_RECORD_INFO_ */ struct htt_tx_fetch_ind {union {/* ath10k_htt_get_tx_fetch_ind_resp_ids() */ struct htt_tx_fetch_record, records);static inline void *struct htt_tx_fetch_ind *ind)return (void *)&ind->records[le16_to_cpu(ind->num_records)];struct htt_tx_fetch_resp {struct htt_tx_fetch_record records[];struct htt_tx_fetch_confirm {enum htt_tx_mode_switch_mode {0 ,1 ,#define HTT_TX_MODE_SWITCH_IND_INFO0_ENABLE BIT(0 )#define HTT_TX_MODE_SWITCH_IND_INFO0_NUM_RECORDS_MASK 0 xfffe#define HTT_TX_MODE_SWITCH_IND_INFO0_NUM_RECORDS_LSB 1 #define HTT_TX_MODE_SWITCH_IND_INFO1_MODE_MASK 0 x0003#define HTT_TX_MODE_SWITCH_IND_INFO1_MODE_LSB 0 #define HTT_TX_MODE_SWITCH_IND_INFO1_THRESHOLD_MASK 0 xfffc#define HTT_TX_MODE_SWITCH_IND_INFO1_THRESHOLD_LSB 2 #define HTT_TX_MODE_SWITCH_RECORD_INFO0_PEER_ID_MASK 0 x0fff#define HTT_TX_MODE_SWITCH_RECORD_INFO0_PEER_ID_LSB 0 #define HTT_TX_MODE_SWITCH_RECORD_INFO0_TID_MASK 0 xf000#define HTT_TX_MODE_SWITCH_RECORD_INFO0_TID_LSB 12 struct htt_tx_mode_switch_record {/* HTT_TX_MODE_SWITCH_RECORD_INFO0_ */ struct htt_tx_mode_switch_ind {/* HTT_TX_MODE_SWITCH_IND_INFO0_ */ /* HTT_TX_MODE_SWITCH_IND_INFO1_ */ 2 ];struct htt_tx_mode_switch_record records[];struct htt_channel_change {3 ];struct htt_per_peer_tx_stats_ind {struct htt_peer_tx_stats {#define ATH10K_10_2_TX_STATS_OFFSET 136 #define PEER_STATS_FOR_NO_OF_PPDUS 4 struct ath10k_10_2_peer_tx_stats {union htt_rx_pn_t {/* WEP: 24-bit PN */ /* TKIP or CCMP: 48-bit PN */ /* WAPI: 128-bit PN */ 2 ];struct htt_cmd {struct htt_cmd_hdr hdr;union {struct htt_ver_req ver_req;struct htt_mgmt_tx_desc mgmt_tx;struct htt_data_tx_desc data_tx;struct htt_rx_ring_setup_32 rx_setup_32;struct htt_rx_ring_setup_64 rx_setup_64;struct htt_stats_req stats_req;struct htt_oob_sync_req oob_sync_req;struct htt_aggr_conf aggr_conf;struct htt_aggr_conf_v2 aggr_conf_v2;struct htt_frag_desc_bank_cfg32 frag_desc_bank_cfg32;struct htt_frag_desc_bank_cfg64 frag_desc_bank_cfg64;struct htt_tx_fetch_resp tx_fetch_resp;struct htt_resp {struct htt_resp_hdr hdr;union {struct htt_ver_resp ver_resp;struct htt_mgmt_tx_completion mgmt_tx_completion;struct htt_data_tx_completion data_tx_completion;struct htt_rx_indication rx_ind;struct htt_rx_indication_hl rx_ind_hl;struct htt_rx_fragment_indication rx_frag_ind;struct htt_rx_peer_map peer_map;struct htt_rx_peer_unmap peer_unmap;struct htt_rx_flush rx_flush;struct htt_rx_addba rx_addba;struct htt_rx_delba rx_delba;struct htt_security_indication security_indication;struct htt_rc_update rc_update;struct htt_rx_test rx_test;struct htt_pktlog_msg pktlog_msg;struct htt_rx_pn_ind rx_pn_ind;struct htt_rx_offload_ind rx_offload_ind;struct htt_rx_in_ord_ind rx_in_ord_ind;struct htt_tx_fetch_ind tx_fetch_ind;struct htt_tx_fetch_confirm tx_fetch_confirm;struct htt_tx_mode_switch_ind tx_mode_switch_ind;struct htt_channel_change chan_change;struct htt_peer_tx_stats peer_tx_stats;/*** host side structures follow ***/ struct htt_tx_done {enum htt_tx_compl_state {struct htt_peer_map_event {struct htt_peer_unmap_event {struct ath10k_htt_txbuf_32 {struct htt_data_tx_desc_frag frags[2 ];struct ath10k_htc_hdr htc_hdr;struct htt_cmd_hdr cmd_hdr;struct htt_data_tx_desc cmd_tx;4 );struct ath10k_htt_txbuf_64 {struct htt_data_tx_desc_frag frags[2 ];struct ath10k_htc_hdr htc_hdr;struct htt_cmd_hdr cmd_hdr;struct htt_data_tx_desc_64 cmd_tx;4 );struct ath10k_htt {struct ath10k *ar;enum ath10k_htc_ep_id eid;struct sk_buff_head rx_indication_head;struct completion target_version_received;const enum htt_t2h_msg_type *t2h_msg_types;struct {/* * Ring of network buffer objects - This ring is * used exclusively by the host SW . This ring * mirrors the dev_addrs_ring that is shared * between the host SW and the MAC HW . The host SW * uses this netbufs ring to locate the network * buffer objects whose data buffers the HW has * filled . struct sk_buff **netbufs_ring;/* This is used only with firmware supporting IN_ORD_IND. * * With Full Rx Reorder the HTT Rx Ring is more of a temporary * buffer ring from which buffer addresses are copied by the * firmware to MAC Rx ring . Firmware then delivers IN_ORD_IND * pointing to specific ( re - ordered ) buffers . * * FIXME : With kernel generic hashing functions there ' s a lot * of hash collisions for sk_buffs . bool in_ord_rx;4 );/* * Ring of buffer addresses - * This ring holds the " physical " device address of the * rx buffers the host SW provides for the MAC HW to * fill . union {/* * Base address of ring , as a " physical " device address * rather than a CPU address . /* how many elems in the ring (power of 2) */ int size;/* size - 1 */ unsigned int size_mask;/* how many rx buffers to keep in the ring */ int fill_level;/* how many rx buffers (full+empty) are in the ring */ int fill_cnt;/* * alloc_idx - where HTT SW has deposited empty buffers * This is allocated in consistent mem , so that the FW can * read this variable , and program the HW ' s FW_IDX reg with * the value of this shadow register . struct {/* where HTT SW has processed bufs filled by rx MAC DMA */ struct {unsigned int msdu_payld;/* * refill_retry_timer - timer triggered when the ring is * not refilled to the level expected struct timer_list refill_retry_timer;/* Protects access to all rx ring buffer state variables */ unsigned int prefetch_len;/* Protects access to pending_tx, num_pending_tx */ int max_num_pending_tx;int num_pending_tx;int num_pending_mgmt_tx;struct idr pending_tx;/* FIFO for storing tx done status {ack, no-ack, discard} and msdu id */ struct htt_tx_done);/* set if host-fw communication goes haywire * used to avoid further failures bool rx_confused;/* This is used to group tx/rx completions separately and process them * in batches to reduce cache stalls struct sk_buff_head rx_msdus_q;struct sk_buff_head rx_in_ord_compl_q;struct sk_buff_head tx_fetch_ind_q;/* rx_status template */ struct ieee80211_rx_status rx_status;struct {union {struct htt_msdu_ext_desc *vaddr_desc_32;struct htt_msdu_ext_desc_64 *vaddr_desc_64;struct {union {struct ath10k_htt_txbuf_32 *vaddr_txbuff_32;struct ath10k_htt_txbuf_64 *vaddr_txbuff_64;struct {bool enabled;struct htt_q_state *vaddr;enum htt_tx_mode_switch_mode mode;enum htt_q_depth_type type;bool tx_mem_allocated;const struct ath10k_htt_tx_ops *tx_ops;const struct ath10k_htt_rx_ops *rx_ops;bool disable_tx_comp;bool bundle_tx;struct sk_buff_head tx_req_head;struct sk_buff_head tx_complete_head;struct ath10k_htt_tx_ops {int (*htt_send_rx_ring_cfg)(struct ath10k_htt *htt);int (*htt_send_frag_desc_bank_cfg)(struct ath10k_htt *htt);int (*htt_alloc_frag_desc)(struct ath10k_htt *htt);void (*htt_free_frag_desc)(struct ath10k_htt *htt);int (*htt_tx)(struct ath10k_htt *htt, enum ath10k_hw_txrx_mode txmode,struct sk_buff *msdu);int (*htt_alloc_txbuff)(struct ath10k_htt *htt);void (*htt_free_txbuff)(struct ath10k_htt *htt);int (*htt_h2t_aggr_cfg_msg)(struct ath10k_htt *htt,void (*htt_flush_tx)(struct ath10k_htt *htt);static inline int ath10k_htt_send_rx_ring_cfg(struct ath10k_htt *htt)if (!htt->tx_ops->htt_send_rx_ring_cfg)return -EOPNOTSUPP;return htt->tx_ops->htt_send_rx_ring_cfg(htt);static inline int ath10k_htt_send_frag_desc_bank_cfg(struct ath10k_htt *htt)if (!htt->tx_ops->htt_send_frag_desc_bank_cfg)return -EOPNOTSUPP;return htt->tx_ops->htt_send_frag_desc_bank_cfg(htt);static inline int ath10k_htt_alloc_frag_desc(struct ath10k_htt *htt)if (!htt->tx_ops->htt_alloc_frag_desc)return -EOPNOTSUPP;return htt->tx_ops->htt_alloc_frag_desc(htt);static inline void ath10k_htt_free_frag_desc(struct ath10k_htt *htt)if (htt->tx_ops->htt_free_frag_desc)static inline int ath10k_htt_tx(struct ath10k_htt *htt,enum ath10k_hw_txrx_mode txmode,struct sk_buff *msdu)return htt->tx_ops->htt_tx(htt, txmode, msdu);static inline void ath10k_htt_flush_tx(struct ath10k_htt *htt)if (htt->tx_ops->htt_flush_tx)static inline int ath10k_htt_alloc_txbuff(struct ath10k_htt *htt)if (!htt->tx_ops->htt_alloc_txbuff)return -EOPNOTSUPP;return htt->tx_ops->htt_alloc_txbuff(htt);static inline void ath10k_htt_free_txbuff(struct ath10k_htt *htt)if (htt->tx_ops->htt_free_txbuff)static inline int ath10k_htt_h2t_aggr_cfg_msg(struct ath10k_htt *htt,if (!htt->tx_ops->htt_h2t_aggr_cfg_msg)return -EOPNOTSUPP;return htt->tx_ops->htt_h2t_aggr_cfg_msg(htt,struct ath10k_htt_rx_ops {struct ath10k_htt *htt);void (*htt_config_paddrs_ring)(struct ath10k_htt *htt, void *vaddr);void (*htt_set_paddrs_ring)(struct ath10k_htt *htt, dma_addr_t paddr,int idx);void * (*htt_get_vaddr_ring)(struct ath10k_htt *htt);void (*htt_reset_paddrs_ring)(struct ath10k_htt *htt, int idx);bool (*htt_rx_proc_rx_frag_ind)(struct ath10k_htt *htt,struct htt_rx_fragment_indication *rx,struct sk_buff *skb);static inline size_t ath10k_htt_get_rx_ring_size(struct ath10k_htt *htt)if (!htt->rx_ops->htt_get_rx_ring_size)return 0 ;return htt->rx_ops->htt_get_rx_ring_size(htt);static inline void ath10k_htt_config_paddrs_ring(struct ath10k_htt *htt,void *vaddr)if (htt->rx_ops->htt_config_paddrs_ring)static inline void ath10k_htt_set_paddrs_ring(struct ath10k_htt *htt,int idx)if (htt->rx_ops->htt_set_paddrs_ring)static inline void *ath10k_htt_get_vaddr_ring(struct ath10k_htt *htt)if (!htt->rx_ops->htt_get_vaddr_ring)return NULL;return htt->rx_ops->htt_get_vaddr_ring(htt);static inline void ath10k_htt_reset_paddrs_ring(struct ath10k_htt *htt, int idx)if (htt->rx_ops->htt_reset_paddrs_ring)static inline bool ath10k_htt_rx_proc_rx_frag_ind(struct ath10k_htt *htt,struct htt_rx_fragment_indication *rx,struct sk_buff *skb)if (!htt->rx_ops->htt_rx_proc_rx_frag_ind)return true ;return htt->rx_ops->htt_rx_proc_rx_frag_ind(htt, rx, skb);/* the driver strongly assumes that the rx header status be 64 bytes long, * so all possible rx_desc structures must respect this assumption . #define RX_HTT_HDR_STATUS_LEN 64 /* The rx descriptor structure layout is programmed via rx ring setup * so that FW knows how to transfer the rx descriptor to the host . * Unfortunately , though , QCA6174 ' s firmware doesn ' t currently behave correctly * when modifying the structure layout of the rx descriptor beyond what it expects * ( even if it correctly programmed during the rx ring setup ) . * Therefore we must keep two different memory layouts , abstract the rx descriptor * representation and use ath10k_rx_desc_ops * for correctly accessing rx descriptor data . /* base struct used for abstracting the rx descriptor representation */ struct htt_rx_desc {union {/* This field is filled on the host using the msdu buffer * from htt_rx_indication struct fw_rx_desc_base fw_desc;/* rx descriptor for wcn3990 and possibly extensible for newer cards * Buffers like this are placed on the rx ring . struct htt_rx_desc_v2 {struct htt_rx_desc base;struct {struct rx_attention attention;struct rx_frag_info frag_info;struct rx_mpdu_start mpdu_start;struct rx_msdu_start msdu_start;struct rx_msdu_end msdu_end;struct rx_mpdu_end mpdu_end;struct rx_ppdu_start ppdu_start;struct rx_ppdu_end ppdu_end;/* QCA6174, QCA988x, QCA99x0 dedicated rx descriptor to make sure their firmware * works correctly . We keep a single rx descriptor for all these three * families of cards because from tests it seems to be the most stable solution , * e . g . having a rx descriptor only for QCA6174 seldom caused firmware crashes * during some tests . * Buffers like this are placed on the rx ring . struct htt_rx_desc_v1 {struct htt_rx_desc base;struct {struct rx_attention attention;struct rx_frag_info_v1 frag_info;struct rx_mpdu_start mpdu_start;struct rx_msdu_start_v1 msdu_start;struct rx_msdu_end_v1 msdu_end;struct rx_mpdu_end mpdu_end;struct rx_ppdu_start ppdu_start;struct rx_ppdu_end_v1 ppdu_end;/* rx_desc abstraction */ struct ath10k_htt_rx_desc_ops {/* These fields are mandatory, they must be specified in any instance */ /* sizeof() of the rx_desc structure used by this hw */ /* offset of msdu_payload inside the rx_desc structure used by this hw */ /* These fields are options. * When a field is not provided the default implementation gets used * ( see the ath10k_rx_desc_ * operations below for more info about the defaults ) bool (*rx_desc_get_msdu_limit_error)(struct htt_rx_desc *rxd);int (*rx_desc_get_l3_pad_bytes)(struct htt_rx_desc *rxd);/* Safely cast from a void* buffer containing an rx descriptor * to the proper rx_desc structure struct htt_rx_desc *(*rx_desc_from_raw_buffer)(void *buff);void (*rx_desc_get_offsets)(struct htt_rx_ring_rx_desc_offsets *offs);struct rx_attention *(*rx_desc_get_attention)(struct htt_rx_desc *rxd);struct rx_frag_info_common *(*rx_desc_get_frag_info)(struct htt_rx_desc *rxd);struct rx_mpdu_start *(*rx_desc_get_mpdu_start)(struct htt_rx_desc *rxd);struct rx_mpdu_end *(*rx_desc_get_mpdu_end)(struct htt_rx_desc *rxd);struct rx_msdu_start_common *(*rx_desc_get_msdu_start)(struct htt_rx_desc *rxd);struct rx_msdu_end_common *(*rx_desc_get_msdu_end)(struct htt_rx_desc *rxd);struct rx_ppdu_start *(*rx_desc_get_ppdu_start)(struct htt_rx_desc *rxd);struct rx_ppdu_end_common *(*rx_desc_get_ppdu_end)(struct htt_rx_desc *rxd);struct htt_rx_desc *rxd);struct htt_rx_desc *rxd);extern const struct ath10k_htt_rx_desc_ops qca988x_rx_desc_ops;extern const struct ath10k_htt_rx_desc_ops qca99x0_rx_desc_ops;extern const struct ath10k_htt_rx_desc_ops wcn3990_rx_desc_ops;static inline int struct ath10k_hw_params *hw, struct htt_rx_desc *rxd)if (hw->rx_desc_ops->rx_desc_get_l3_pad_bytes)return hw->rx_desc_ops->rx_desc_get_l3_pad_bytes(rxd);return 0 ;static inline bool struct ath10k_hw_params *hw, struct htt_rx_desc *rxd)if (hw->rx_desc_ops->rx_desc_get_msdu_limit_error)return hw->rx_desc_ops->rx_desc_get_msdu_limit_error(rxd);return false ;/* The default implementation of all these getters is using the old rx_desc, * so that it is easier to define the ath10k_htt_rx_desc_ops instances . * But probably , if new wireless cards must be supported , it would be better * to switch the default implementation to the new rx_desc , since this would * make the extension easier . static inline struct htt_rx_desc *struct ath10k_hw_params *hw, void *buff)if (hw->rx_desc_ops->rx_desc_from_raw_buffer)return hw->rx_desc_ops->rx_desc_from_raw_buffer(buff);return &((struct htt_rx_desc_v1 *)buff)->base;static inline void struct ath10k_hw_params *hw,struct htt_rx_ring_rx_desc_offsets *off)if (hw->rx_desc_ops->rx_desc_get_offsets) {else {#define desc_offset(x) (offsetof(struct htt_rx_desc_v1, x) / 4 )#undef desc_offsetstatic inline struct rx_attention *struct ath10k_hw_params *hw, struct htt_rx_desc *rxd)struct htt_rx_desc_v1 *rx_desc;if (hw->rx_desc_ops->rx_desc_get_attention)return hw->rx_desc_ops->rx_desc_get_attention(rxd);struct htt_rx_desc_v1, base);return &rx_desc->attention;static inline struct rx_frag_info_common *struct ath10k_hw_params *hw, struct htt_rx_desc *rxd)struct htt_rx_desc_v1 *rx_desc;if (hw->rx_desc_ops->rx_desc_get_frag_info)return hw->rx_desc_ops->rx_desc_get_frag_info(rxd);struct htt_rx_desc_v1, base);return &rx_desc->frag_info.common;static inline struct rx_mpdu_start *struct ath10k_hw_params *hw, struct htt_rx_desc *rxd)struct htt_rx_desc_v1 *rx_desc;if (hw->rx_desc_ops->rx_desc_get_mpdu_start)return hw->rx_desc_ops->rx_desc_get_mpdu_start(rxd);struct htt_rx_desc_v1, base);return &rx_desc->mpdu_start;static inline struct rx_mpdu_end *struct ath10k_hw_params *hw, struct htt_rx_desc *rxd)struct htt_rx_desc_v1 *rx_desc;if (hw->rx_desc_ops->rx_desc_get_mpdu_end)return hw->rx_desc_ops->rx_desc_get_mpdu_end(rxd);struct htt_rx_desc_v1, base);return &rx_desc->mpdu_end;static inline struct rx_msdu_start_common *struct ath10k_hw_params *hw, struct htt_rx_desc *rxd)struct htt_rx_desc_v1 *rx_desc;if (hw->rx_desc_ops->rx_desc_get_msdu_start)return hw->rx_desc_ops->rx_desc_get_msdu_start(rxd);struct htt_rx_desc_v1, base);return &rx_desc->msdu_start.common;static inline struct rx_msdu_end_common *struct ath10k_hw_params *hw, struct htt_rx_desc *rxd)struct htt_rx_desc_v1 *rx_desc;if (hw->rx_desc_ops->rx_desc_get_msdu_end)return hw->rx_desc_ops->rx_desc_get_msdu_end(rxd);struct htt_rx_desc_v1, base);return &rx_desc->msdu_end.common;static inline struct rx_ppdu_start *struct ath10k_hw_params *hw, struct htt_rx_desc *rxd)struct htt_rx_desc_v1 *rx_desc;if (hw->rx_desc_ops->rx_desc_get_ppdu_start)return hw->rx_desc_ops->rx_desc_get_ppdu_start(rxd);struct htt_rx_desc_v1, base);return &rx_desc->ppdu_start;static inline struct rx_ppdu_end_common *struct ath10k_hw_params *hw, struct htt_rx_desc *rxd)struct htt_rx_desc_v1 *rx_desc;if (hw->rx_desc_ops->rx_desc_get_ppdu_end)return hw->rx_desc_ops->rx_desc_get_ppdu_end(rxd);struct htt_rx_desc_v1, base);return &rx_desc->ppdu_end.common;static inline u8 *struct ath10k_hw_params *hw, struct htt_rx_desc *rxd)struct htt_rx_desc_v1 *rx_desc;if (hw->rx_desc_ops->rx_desc_get_rx_hdr_status)return hw->rx_desc_ops->rx_desc_get_rx_hdr_status(rxd);struct htt_rx_desc_v1, base);return rx_desc->rx_hdr_status;static inline u8 *struct ath10k_hw_params *hw, struct htt_rx_desc *rxd)struct htt_rx_desc_v1 *rx_desc;if (hw->rx_desc_ops->rx_desc_get_msdu_payload)return hw->rx_desc_ops->rx_desc_get_msdu_payload(rxd);struct htt_rx_desc_v1, base);return rx_desc->msdu_payload;#define HTT_RX_DESC_HL_INFO_SEQ_NUM_MASK 0 x00000fff#define HTT_RX_DESC_HL_INFO_SEQ_NUM_LSB 0 #define HTT_RX_DESC_HL_INFO_ENCRYPTED_MASK 0 x00001000#define HTT_RX_DESC_HL_INFO_ENCRYPTED_LSB 12 #define HTT_RX_DESC_HL_INFO_CHAN_INFO_PRESENT_MASK 0 x00002000#define HTT_RX_DESC_HL_INFO_CHAN_INFO_PRESENT_LSB 13 #define HTT_RX_DESC_HL_INFO_MCAST_BCAST_MASK 0 x00010000#define HTT_RX_DESC_HL_INFO_MCAST_BCAST_LSB 16 #define HTT_RX_DESC_HL_INFO_KEY_ID_OCT_MASK 0 x01fe0000#define HTT_RX_DESC_HL_INFO_KEY_ID_OCT_LSB 17 struct htt_rx_desc_base_hl {/* HTT_RX_DESC_HL_INFO_ */ struct htt_rx_chan_info {#define HTT_RX_DESC_ALIGN 8 #define HTT_MAC_ADDR_LEN 6 /* * FIX THIS * Should be : sizeof ( struct htt_host_rx_desc ) + max rx MSDU size , * rounded up to a cache line size . #define HTT_RX_BUF_SIZE 2048 /* The HTT_RX_MSDU_SIZE can't be statically computed anymore, * because it depends on the underlying device rx_desc representation static inline int ath10k_htt_rx_msdu_size(struct ath10k_hw_params *hw)return HTT_RX_BUF_SIZE - (int )hw->rx_desc_ops->rx_desc_size;/* Refill a bunch of RX buffers for each refill round so that FW/HW can handle * aggregated traffic more nicely . #define ATH10K_HTT_MAX_NUM_REFILL 100 /* * DMA_MAP expects the buffer to be an integral number of cache lines . * Rather than checking the actual cache line size , this code makes a * conservative estimate of what the cache line size could be . #define HTT_LOG2_MAX_CACHE_LINE_SIZE 7 /* 2^7 = 128 */ #define HTT_MAX_CACHE_LINE_SIZE_MASK ((1 << HTT_LOG2_MAX_CACHE_LINE_SIZE) - 1 )/* These values are default in most firmware revisions and apparently are a * sweet spot performance wise . #define ATH10K_HTT_MAX_NUM_AMSDU_DEFAULT 3 #define ATH10K_HTT_MAX_NUM_AMPDU_DEFAULT 64 int ath10k_htt_connect(struct ath10k_htt *htt);int ath10k_htt_init(struct ath10k *ar);int ath10k_htt_setup(struct ath10k_htt *htt);int ath10k_htt_tx_start(struct ath10k_htt *htt);void ath10k_htt_tx_stop(struct ath10k_htt *htt);void ath10k_htt_tx_destroy(struct ath10k_htt *htt);void ath10k_htt_tx_free(struct ath10k_htt *htt);int ath10k_htt_rx_alloc(struct ath10k_htt *htt);int ath10k_htt_rx_ring_refill(struct ath10k *ar);void ath10k_htt_rx_free(struct ath10k_htt *htt);void ath10k_htt_htc_tx_complete(struct ath10k *ar, struct sk_buff *skb);void ath10k_htt_htc_t2h_msg_handler(struct ath10k *ar, struct sk_buff *skb);bool ath10k_htt_t2h_msg_handler(struct ath10k *ar, struct sk_buff *skb);int ath10k_htt_h2t_ver_req_msg(struct ath10k_htt *htt);int ath10k_htt_h2t_stats_req(struct ath10k_htt *htt, u32 mask, u32 reset_mask,void ath10k_htt_hif_tx_complete(struct ath10k *ar, struct sk_buff *skb);int ath10k_htt_tx_fetch_resp(struct ath10k *ar,struct htt_tx_fetch_record *records,void ath10k_htt_op_ep_tx_credits(struct ath10k *ar);void ath10k_htt_tx_txq_update(struct ieee80211_hw *hw,struct ieee80211_txq *txq);void ath10k_htt_tx_txq_recalc(struct ieee80211_hw *hw,struct ieee80211_txq *txq);void ath10k_htt_tx_txq_sync(struct ath10k *ar);void ath10k_htt_tx_dec_pending(struct ath10k_htt *htt);int ath10k_htt_tx_inc_pending(struct ath10k_htt *htt);void ath10k_htt_tx_mgmt_dec_pending(struct ath10k_htt *htt);int ath10k_htt_tx_mgmt_inc_pending(struct ath10k_htt *htt, bool is_mgmt,bool is_presp);int ath10k_htt_tx_alloc_msdu_id(struct ath10k_htt *htt, struct sk_buff *skb);void ath10k_htt_tx_free_msdu_id(struct ath10k_htt *htt, u16 msdu_id);int ath10k_htt_mgmt_tx(struct ath10k_htt *htt, struct sk_buff *msdu);void ath10k_htt_rx_pktlog_completion_handler(struct ath10k *ar,struct sk_buff *skb);int ath10k_htt_txrx_compl_task(struct ath10k *ar, int budget);int ath10k_htt_rx_hl_indication(struct ath10k *ar, int budget);void ath10k_htt_set_tx_ops(struct ath10k_htt *htt);void ath10k_htt_set_rx_ops(struct ath10k_htt *htt);#endif
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¤ Dauer der Verarbeitung: 0.68 Sekunden
(vorverarbeitet am 2026-10-02)
¤ *© Formatika GbR, Deutschland
2026-10-10
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