// SPDX-License-Identifier: GPL-2.0-only
/*
* r8169_phy_config.c: RealTek 8169/8168/8101 ethernet driver.
*
* Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
* Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
* Copyright (c) a lot of people too. Please respect their work.
*
* See MAINTAINERS file for support contact information.
*/
#include <linux/delay.h>
#include <linux/phy.h>
#include "r8169.h"
typedef void (*rtl_phy_cfg_fct)(struct rtl8169_private *tp,
struct phy_device *phydev);
static void r8168d_modify_extpage(struct phy_device *phydev, int extpage,
int reg, u16 mask, u16 val)
{
int oldpage = phy_select_page(phydev, 0 x0007);
__phy_write(phydev, 0 x1e, extpage);
__phy_modify(phydev, reg, mask, val);
phy_restore_page(phydev, oldpage, 0 );
}
static void r8168d_phy_param(struct phy_device *phydev, u16 parm,
u16 mask, u16 val)
{
int oldpage = phy_select_page(phydev, 0 x0005);
__phy_write(phydev, 0 x05, parm);
__phy_modify(phydev, 0 x06, mask, val);
phy_restore_page(phydev, oldpage, 0 );
}
static void r8168g_phy_param(struct phy_device *phydev, u16 parm,
u16 mask, u16 val)
{
int oldpage = phy_select_page(phydev, 0 x0a43);
__phy_write(phydev, 0 x13, parm);
__phy_modify(phydev, 0 x14, mask, val);
phy_restore_page(phydev, oldpage, 0 );
}
static void rtl8125_phy_param(struct phy_device *phydev, u16 parm,
u16 mask, u16 val)
{
phy_lock_mdio_bus(phydev);
__phy_write_mmd(phydev, MDIO_MMD_VEND2, 0 xb87c, parm);
__phy_modify_mmd(phydev, MDIO_MMD_VEND2, 0 xb87e, mask, val);
phy_unlock_mdio_bus(phydev);
}
struct phy_reg {
u16 reg;
u16 val;
};
static void __rtl_writephy_batch(struct phy_device *phydev,
const struct phy_reg *regs, int len)
{
phy_lock_mdio_bus(phydev);
while (len-- > 0 ) {
__phy_write(phydev, regs->reg, regs->val);
regs++;
}
phy_unlock_mdio_bus(phydev);
}
#define rtl_writephy_batch(p, a) __rtl_writephy_batch(p, a, ARRAY_SIZE(a))
static void rtl8168f_config_eee_phy(struct phy_device *phydev)
{
r8168d_modify_extpage(phydev, 0 x0020, 0 x15, 0 , BIT(8 ));
r8168d_phy_param(phydev, 0 x8b85, 0 , BIT(13 ));
}
static void rtl8168g_config_eee_phy(struct phy_device *phydev)
{
phy_modify_paged(phydev, 0 x0a43, 0 x11, 0 , BIT(4 ));
}
static void rtl8168h_config_eee_phy(struct phy_device *phydev)
{
rtl8168g_config_eee_phy(phydev);
phy_modify_paged(phydev, 0 xa4a, 0 x11, 0 x0000, 0 x0200);
phy_modify_paged(phydev, 0 xa42, 0 x14, 0 x0000, 0 x0080);
}
static void rtl8125_common_config_eee_phy(struct phy_device *phydev)
{
phy_modify_paged(phydev, 0 xa6d, 0 x14, 0 x0010, 0 x0000);
phy_modify_paged(phydev, 0 xa42, 0 x14, 0 x0080, 0 x0000);
phy_modify_paged(phydev, 0 xa4a, 0 x11, 0 x0200, 0 x0000);
}
static void rtl8125_config_eee_phy(struct phy_device *phydev)
{
rtl8168g_config_eee_phy(phydev);
rtl8125_common_config_eee_phy(phydev);
}
static void rtl8169s_hw_phy_config(struct rtl8169_private *tp,
struct phy_device *phydev)
{
static const struct phy_reg phy_reg_init[] = {
{ 0 x1f, 0 x0001 },
{ 0 x06, 0 x006e },
{ 0 x08, 0 x0708 },
{ 0 x15, 0 x4000 },
{ 0 x18, 0 x65c7 },
{ 0 x1f, 0 x0001 },
{ 0 x03, 0 x00a1 },
{ 0 x02, 0 x0008 },
{ 0 x01, 0 x0120 },
{ 0 x00, 0 x1000 },
{ 0 x04, 0 x0800 },
{ 0 x04, 0 x0000 },
{ 0 x03, 0 xff41 },
{ 0 x02, 0 xdf60 },
{ 0 x01, 0 x0140 },
{ 0 x00, 0 x0077 },
{ 0 x04, 0 x7800 },
{ 0 x04, 0 x7000 },
{ 0 x03, 0 x802f },
{ 0 x02, 0 x4f02 },
{ 0 x01, 0 x0409 },
{ 0 x00, 0 xf0f9 },
{ 0 x04, 0 x9800 },
{ 0 x04, 0 x9000 },
{ 0 x03, 0 xdf01 },
{ 0 x02, 0 xdf20 },
{ 0 x01, 0 xff95 },
{ 0 x00, 0 xba00 },
{ 0 x04, 0 xa800 },
{ 0 x04, 0 xa000 },
{ 0 x03, 0 xff41 },
{ 0 x02, 0 xdf20 },
{ 0 x01, 0 x0140 },
{ 0 x00, 0 x00bb },
{ 0 x04, 0 xb800 },
{ 0 x04, 0 xb000 },
{ 0 x03, 0 xdf41 },
{ 0 x02, 0 xdc60 },
{ 0 x01, 0 x6340 },
{ 0 x00, 0 x007d },
{ 0 x04, 0 xd800 },
{ 0 x04, 0 xd000 },
{ 0 x03, 0 xdf01 },
{ 0 x02, 0 xdf20 },
{ 0 x01, 0 x100a },
{ 0 x00, 0 xa0ff },
{ 0 x04, 0 xf800 },
{ 0 x04, 0 xf000 },
{ 0 x1f, 0 x0000 },
{ 0 x0b, 0 x0000 },
{ 0 x00, 0 x9200 }
};
rtl_writephy_batch(phydev, phy_reg_init);
}
static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp,
struct phy_device *phydev)
{
phy_write_paged(phydev, 0 x0002, 0 x01, 0 x90d0);
}
static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp,
struct phy_device *phydev)
{
static const struct phy_reg phy_reg_init[] = {
{ 0 x1f, 0 x0001 },
{ 0 x04, 0 x0000 },
{ 0 x03, 0 x00a1 },
{ 0 x02, 0 x0008 },
{ 0 x01, 0 x0120 },
{ 0 x00, 0 x1000 },
{ 0 x04, 0 x0800 },
{ 0 x04, 0 x9000 },
{ 0 x03, 0 x802f },
{ 0 x02, 0 x4f02 },
{ 0 x01, 0 x0409 },
{ 0 x00, 0 xf099 },
{ 0 x04, 0 x9800 },
{ 0 x04, 0 xa000 },
{ 0 x03, 0 xdf01 },
{ 0 x02, 0 xdf20 },
{ 0 x01, 0 xff95 },
{ 0 x00, 0 xba00 },
{ 0 x04, 0 xa800 },
{ 0 x04, 0 xf000 },
{ 0 x03, 0 xdf01 },
{ 0 x02, 0 xdf20 },
{ 0 x01, 0 x101a },
{ 0 x00, 0 xa0ff },
{ 0 x04, 0 xf800 },
{ 0 x04, 0 x0000 },
{ 0 x1f, 0 x0000 },
{ 0 x1f, 0 x0001 },
{ 0 x10, 0 xf41b },
{ 0 x14, 0 xfb54 },
{ 0 x18, 0 xf5c7 },
{ 0 x1f, 0 x0000 },
{ 0 x1f, 0 x0001 },
{ 0 x17, 0 x0cc0 },
{ 0 x1f, 0 x0000 }
};
rtl_writephy_batch(phydev, phy_reg_init);
}
static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp,
struct phy_device *phydev)
{
static const struct phy_reg phy_reg_init[] = {
{ 0 x1f, 0 x0001 },
{ 0 x04, 0 x0000 },
{ 0 x03, 0 x00a1 },
{ 0 x02, 0 x0008 },
{ 0 x01, 0 x0120 },
{ 0 x00, 0 x1000 },
{ 0 x04, 0 x0800 },
{ 0 x04, 0 x9000 },
{ 0 x03, 0 x802f },
{ 0 x02, 0 x4f02 },
{ 0 x01, 0 x0409 },
{ 0 x00, 0 xf099 },
{ 0 x04, 0 x9800 },
{ 0 x04, 0 xa000 },
{ 0 x03, 0 xdf01 },
{ 0 x02, 0 xdf20 },
{ 0 x01, 0 xff95 },
{ 0 x00, 0 xba00 },
{ 0 x04, 0 xa800 },
{ 0 x04, 0 xf000 },
{ 0 x03, 0 xdf01 },
{ 0 x02, 0 xdf20 },
{ 0 x01, 0 x101a },
{ 0 x00, 0 xa0ff },
{ 0 x04, 0 xf800 },
{ 0 x04, 0 x0000 },
{ 0 x1f, 0 x0000 },
{ 0 x1f, 0 x0001 },
{ 0 x0b, 0 x8480 },
{ 0 x1f, 0 x0000 },
{ 0 x1f, 0 x0001 },
{ 0 x18, 0 x67c7 },
{ 0 x04, 0 x2000 },
{ 0 x03, 0 x002f },
{ 0 x02, 0 x4360 },
{ 0 x01, 0 x0109 },
{ 0 x00, 0 x3022 },
{ 0 x04, 0 x2800 },
{ 0 x1f, 0 x0000 },
{ 0 x1f, 0 x0001 },
{ 0 x17, 0 x0cc0 },
{ 0 x1f, 0 x0000 }
};
rtl_writephy_batch(phydev, phy_reg_init);
}
static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp,
struct phy_device *phydev)
{
phy_write_paged(phydev, 0 x0001, 0 x10, 0 xf41b);
}
static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp,
struct phy_device *phydev)
{
phy_write(phydev, 0 x1d, 0 x0f00);
phy_write_paged(phydev, 0 x0002, 0 x0c, 0 x1ec8);
}
static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp,
struct phy_device *phydev)
{
phy_set_bits(phydev, 0 x14, BIT(5 ));
phy_set_bits(phydev, 0 x0d, BIT(5 ));
phy_write_paged(phydev, 0 x0001, 0 x1d, 0 x3d98);
}
static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp,
struct phy_device *phydev)
{
static const struct phy_reg phy_reg_init[] = {
{ 0 x1f, 0 x0001 },
{ 0 x12, 0 x2300 },
{ 0 x1f, 0 x0002 },
{ 0 x00, 0 x88d4 },
{ 0 x01, 0 x82b1 },
{ 0 x03, 0 x7002 },
{ 0 x08, 0 x9e30 },
{ 0 x09, 0 x01f0 },
{ 0 x0a, 0 x5500 },
{ 0 x0c, 0 x00c8 },
{ 0 x1f, 0 x0003 },
{ 0 x12, 0 xc096 },
{ 0 x16, 0 x000a },
{ 0 x1f, 0 x0000 },
{ 0 x1f, 0 x0000 },
{ 0 x09, 0 x2000 },
{ 0 x09, 0 x0000 }
};
rtl_writephy_batch(phydev, phy_reg_init);
phy_set_bits(phydev, 0 x14, BIT(5 ));
phy_set_bits(phydev, 0 x0d, BIT(5 ));
}
static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp,
struct phy_device *phydev)
{
static const struct phy_reg phy_reg_init[] = {
{ 0 x1f, 0 x0001 },
{ 0 x12, 0 x2300 },
{ 0 x03, 0 x802f },
{ 0 x02, 0 x4f02 },
{ 0 x01, 0 x0409 },
{ 0 x00, 0 xf099 },
{ 0 x04, 0 x9800 },
{ 0 x04, 0 x9000 },
{ 0 x1d, 0 x3d98 },
{ 0 x1f, 0 x0002 },
{ 0 x0c, 0 x7eb8 },
{ 0 x06, 0 x0761 },
{ 0 x1f, 0 x0003 },
{ 0 x16, 0 x0f0a },
{ 0 x1f, 0 x0000 }
};
rtl_writephy_batch(phydev, phy_reg_init);
phy_set_bits(phydev, 0 x16, BIT(0 ));
phy_set_bits(phydev, 0 x14, BIT(5 ));
phy_set_bits(phydev, 0 x0d, BIT(5 ));
}
static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp,
struct phy_device *phydev)
{
static const struct phy_reg phy_reg_init[] = {
{ 0 x1f, 0 x0001 },
{ 0 x12, 0 x2300 },
{ 0 x1d, 0 x3d98 },
{ 0 x1f, 0 x0002 },
{ 0 x0c, 0 x7eb8 },
{ 0 x06, 0 x5461 },
{ 0 x1f, 0 x0003 },
{ 0 x16, 0 x0f0a },
{ 0 x1f, 0 x0000 }
};
rtl_writephy_batch(phydev, phy_reg_init);
phy_set_bits(phydev, 0 x16, BIT(0 ));
phy_set_bits(phydev, 0 x14, BIT(5 ));
phy_set_bits(phydev, 0 x0d, BIT(5 ));
}
static const struct phy_reg rtl8168d_1_phy_reg_init_0[] = {
/* Channel Estimation */
{ 0 x1f, 0 x0001 },
{ 0 x06, 0 x4064 },
{ 0 x07, 0 x2863 },
{ 0 x08, 0 x059c },
{ 0 x09, 0 x26b4 },
{ 0 x0a, 0 x6a19 },
{ 0 x0b, 0 xdcc8 },
{ 0 x10, 0 xf06d },
{ 0 x14, 0 x7f68 },
{ 0 x18, 0 x7fd9 },
{ 0 x1c, 0 xf0ff },
{ 0 x1d, 0 x3d9c },
{ 0 x1f, 0 x0003 },
{ 0 x12, 0 xf49f },
{ 0 x13, 0 x070b },
{ 0 x1a, 0 x05ad },
{ 0 x14, 0 x94c0 },
/*
* Tx Error Issue
* Enhance line driver power
*/
{ 0 x1f, 0 x0002 },
{ 0 x06, 0 x5561 },
{ 0 x1f, 0 x0005 },
{ 0 x05, 0 x8332 },
{ 0 x06, 0 x5561 },
/*
* Can not link to 1Gbps with bad cable
* Decrease SNR threshold form 21.07dB to 19.04dB
*/
{ 0 x1f, 0 x0001 },
{ 0 x17, 0 x0cc0 },
{ 0 x1f, 0 x0000 },
{ 0 x0d, 0 xf880 }
};
static void rtl8168d_apply_firmware_cond(struct rtl8169_private *tp,
struct phy_device *phydev,
u16 val)
{
u16 reg_val;
phy_write(phydev, 0 x1f, 0 x0005);
phy_write(phydev, 0 x05, 0 x001b);
reg_val = phy_read(phydev, 0 x06);
phy_write(phydev, 0 x1f, 0 x0000);
if (reg_val != val)
phydev_warn(phydev, "chipset not ready for firmware\n" );
else
r8169_apply_firmware(tp);
}
static void rtl8168d_1_common(struct phy_device *phydev)
{
u16 val;
phy_write_paged(phydev, 0 x0002, 0 x05, 0 x669a);
r8168d_phy_param(phydev, 0 x8330, 0 xffff, 0 x669a);
phy_write(phydev, 0 x1f, 0 x0002);
val = phy_read(phydev, 0 x0d);
if ((val & 0 x00ff) != 0 x006c) {
static const u16 set[] = {
0 x0065, 0 x0066, 0 x0067, 0 x0068,
0 x0069, 0 x006a, 0 x006b, 0 x006c
};
int i;
val &= 0 xff00;
for (i = 0 ; i < ARRAY_SIZE(set); i++)
phy_write(phydev, 0 x0d, val | set[i]);
}
}
static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp,
struct phy_device *phydev)
{
rtl_writephy_batch(phydev, rtl8168d_1_phy_reg_init_0);
/*
* Rx Error Issue
* Fine Tune Switching regulator parameter
*/
phy_write(phydev, 0 x1f, 0 x0002);
phy_modify(phydev, 0 x0b, 0 x00ef, 0 x0010);
phy_modify(phydev, 0 x0c, 0 x5d00, 0 xa200);
if (rtl8168d_efuse_read(tp, 0 x01) == 0 xb1) {
rtl8168d_1_common(phydev);
} else {
phy_write_paged(phydev, 0 x0002, 0 x05, 0 x6662);
r8168d_phy_param(phydev, 0 x8330, 0 xffff, 0 x6662);
}
/* RSET couple improve */
phy_write(phydev, 0 x1f, 0 x0002);
phy_set_bits(phydev, 0 x0d, 0 x0300);
phy_set_bits(phydev, 0 x0f, 0 x0010);
/* Fine tune PLL performance */
phy_write(phydev, 0 x1f, 0 x0002);
phy_modify(phydev, 0 x02, 0 x0600, 0 x0100);
phy_clear_bits(phydev, 0 x03, 0 xe000);
phy_write(phydev, 0 x1f, 0 x0000);
rtl8168d_apply_firmware_cond(tp, phydev, 0 xbf00);
}
static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp,
struct phy_device *phydev)
{
rtl_writephy_batch(phydev, rtl8168d_1_phy_reg_init_0);
if (rtl8168d_efuse_read(tp, 0 x01) == 0 xb1) {
rtl8168d_1_common(phydev);
} else {
phy_write_paged(phydev, 0 x0002, 0 x05, 0 x2642);
r8168d_phy_param(phydev, 0 x8330, 0 xffff, 0 x2642);
}
/* Fine tune PLL performance */
phy_write(phydev, 0 x1f, 0 x0002);
phy_modify(phydev, 0 x02, 0 x0600, 0 x0100);
phy_clear_bits(phydev, 0 x03, 0 xe000);
phy_write(phydev, 0 x1f, 0 x0000);
/* Switching regulator Slew rate */
phy_modify_paged(phydev, 0 x0002, 0 x0f, 0 x0000, 0 x0017);
rtl8168d_apply_firmware_cond(tp, phydev, 0 xb300);
}
static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp,
struct phy_device *phydev)
{
phy_write_paged(phydev, 0 x0001, 0 x17, 0 x0cc0);
r8168d_modify_extpage(phydev, 0 x002d, 0 x18, 0 xffff, 0 x0040);
phy_set_bits(phydev, 0 x0d, BIT(5 ));
}
static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp,
struct phy_device *phydev)
{
static const struct phy_reg phy_reg_init[] = {
/* Channel estimation fine tune */
{ 0 x1f, 0 x0001 },
{ 0 x0b, 0 x6c20 },
{ 0 x07, 0 x2872 },
{ 0 x1c, 0 xefff },
{ 0 x1f, 0 x0003 },
{ 0 x14, 0 x6420 },
{ 0 x1f, 0 x0000 },
};
r8169_apply_firmware(tp);
/* Enable Delay cap */
r8168d_phy_param(phydev, 0 x8b80, 0 xffff, 0 xc896);
rtl_writephy_batch(phydev, phy_reg_init);
/* Update PFM & 10M TX idle timer */
r8168d_modify_extpage(phydev, 0 x002f, 0 x15, 0 xffff, 0 x1919);
r8168d_modify_extpage(phydev, 0 x00ac, 0 x18, 0 xffff, 0 x0006);
/* DCO enable for 10M IDLE Power */
r8168d_modify_extpage(phydev, 0 x0023, 0 x17, 0 x0000, 0 x0006);
/* For impedance matching */
phy_modify_paged(phydev, 0 x0002, 0 x08, 0 x7f00, 0 x8000);
/* PHY auto speed down */
r8168d_modify_extpage(phydev, 0 x002d, 0 x18, 0 x0000, 0 x0050);
phy_set_bits(phydev, 0 x14, BIT(15 ));
r8168d_phy_param(phydev, 0 x8b86, 0 x0000, 0 x0001);
r8168d_phy_param(phydev, 0 x8b85, 0 x2000, 0 x0000);
r8168d_modify_extpage(phydev, 0 x0020, 0 x15, 0 x1100, 0 x0000);
phy_write_paged(phydev, 0 x0006, 0 x00, 0 x5a00);
phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0 x0000);
}
static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp,
struct phy_device *phydev)
{
r8169_apply_firmware(tp);
/* Enable Delay cap */
r8168d_modify_extpage(phydev, 0 x00ac, 0 x18, 0 xffff, 0 x0006);
/* Channel estimation fine tune */
phy_write_paged(phydev, 0 x0003, 0 x09, 0 xa20f);
/* Green Setting */
r8168d_phy_param(phydev, 0 x8b5b, 0 xffff, 0 x9222);
r8168d_phy_param(phydev, 0 x8b6d, 0 xffff, 0 x8000);
r8168d_phy_param(phydev, 0 x8b76, 0 xffff, 0 x8000);
/* For 4-corner performance improve */
phy_write(phydev, 0 x1f, 0 x0005);
phy_write(phydev, 0 x05, 0 x8b80);
phy_set_bits(phydev, 0 x17, 0 x0006);
phy_write(phydev, 0 x1f, 0 x0000);
/* PHY auto speed down */
r8168d_modify_extpage(phydev, 0 x002d, 0 x18, 0 x0000, 0 x0010);
phy_set_bits(phydev, 0 x14, BIT(15 ));
/* improve 10M EEE waveform */
r8168d_phy_param(phydev, 0 x8b86, 0 x0000, 0 x0001);
/* Improve 2-pair detection performance */
r8168d_phy_param(phydev, 0 x8b85, 0 x0000, 0 x4000);
rtl8168f_config_eee_phy(phydev);
/* Green feature */
phy_write(phydev, 0 x1f, 0 x0003);
phy_set_bits(phydev, 0 x19, BIT(0 ));
phy_set_bits(phydev, 0 x10, BIT(10 ));
phy_write(phydev, 0 x1f, 0 x0000);
phy_modify_paged(phydev, 0 x0005, 0 x01, 0 , BIT(8 ));
}
static void rtl8168f_hw_phy_config(struct rtl8169_private *tp,
struct phy_device *phydev)
{
/* For 4-corner performance improve */
r8168d_phy_param(phydev, 0 x8b80, 0 x0000, 0 x0006);
/* PHY auto speed down */
r8168d_modify_extpage(phydev, 0 x002d, 0 x18, 0 x0000, 0 x0010);
phy_set_bits(phydev, 0 x14, BIT(15 ));
/* Improve 10M EEE waveform */
r8168d_phy_param(phydev, 0 x8b86, 0 x0000, 0 x0001);
rtl8168f_config_eee_phy(phydev);
}
static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp,
struct phy_device *phydev)
{
r8169_apply_firmware(tp);
/* Channel estimation fine tune */
phy_write_paged(phydev, 0 x0003, 0 x09, 0 xa20f);
/* Modify green table for giga & fnet */
r8168d_phy_param(phydev, 0 x8b55, 0 xffff, 0 x0000);
r8168d_phy_param(phydev, 0 x8b5e, 0 xffff, 0 x0000);
r8168d_phy_param(phydev, 0 x8b67, 0 xffff, 0 x0000);
r8168d_phy_param(phydev, 0 x8b70, 0 xffff, 0 x0000);
r8168d_modify_extpage(phydev, 0 x0078, 0 x17, 0 xffff, 0 x0000);
r8168d_modify_extpage(phydev, 0 x0078, 0 x19, 0 xffff, 0 x00fb);
/* Modify green table for 10M */
r8168d_phy_param(phydev, 0 x8b79, 0 xffff, 0 xaa00);
/* Disable hiimpedance detection (RTCT) */
phy_write_paged(phydev, 0 x0003, 0 x01, 0 x328a);
rtl8168f_hw_phy_config(tp, phydev);
/* Improve 2-pair detection performance */
r8168d_phy_param(phydev, 0 x8b85, 0 x0000, 0 x4000);
}
static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp,
struct phy_device *phydev)
{
r8169_apply_firmware(tp);
rtl8168f_hw_phy_config(tp, phydev);
}
static void rtl8411_hw_phy_config(struct rtl8169_private *tp,
struct phy_device *phydev)
{
r8169_apply_firmware(tp);
rtl8168f_hw_phy_config(tp, phydev);
/* Improve 2-pair detection performance */
r8168d_phy_param(phydev, 0 x8b85, 0 x0000, 0 x4000);
/* Channel estimation fine tune */
phy_write_paged(phydev, 0 x0003, 0 x09, 0 xa20f);
/* Modify green table for giga & fnet */
r8168d_phy_param(phydev, 0 x8b55, 0 xffff, 0 x0000);
r8168d_phy_param(phydev, 0 x8b5e, 0 xffff, 0 x0000);
r8168d_phy_param(phydev, 0 x8b67, 0 xffff, 0 x0000);
r8168d_phy_param(phydev, 0 x8b70, 0 xffff, 0 x0000);
r8168d_modify_extpage(phydev, 0 x0078, 0 x17, 0 xffff, 0 x0000);
r8168d_modify_extpage(phydev, 0 x0078, 0 x19, 0 xffff, 0 x00aa);
/* Modify green table for 10M */
r8168d_phy_param(phydev, 0 x8b79, 0 xffff, 0 xaa00);
/* Disable hiimpedance detection (RTCT) */
phy_write_paged(phydev, 0 x0003, 0 x01, 0 x328a);
/* Modify green table for giga */
r8168d_phy_param(phydev, 0 x8b54, 0 x0800, 0 x0000);
r8168d_phy_param(phydev, 0 x8b5d, 0 x0800, 0 x0000);
r8168d_phy_param(phydev, 0 x8a7c, 0 x0100, 0 x0000);
r8168d_phy_param(phydev, 0 x8a7f, 0 x0000, 0 x0100);
r8168d_phy_param(phydev, 0 x8a82, 0 x0100, 0 x0000);
r8168d_phy_param(phydev, 0 x8a85, 0 x0100, 0 x0000);
r8168d_phy_param(phydev, 0 x8a88, 0 x0100, 0 x0000);
/* uc same-seed solution */
r8168d_phy_param(phydev, 0 x8b85, 0 x0000, 0 x8000);
/* Green feature */
phy_write(phydev, 0 x1f, 0 x0003);
phy_clear_bits(phydev, 0 x19, BIT(0 ));
phy_clear_bits(phydev, 0 x10, BIT(10 ));
phy_write(phydev, 0 x1f, 0 x0000);
}
static void rtl8168g_disable_aldps(struct phy_device *phydev)
{
phy_modify_paged(phydev, 0 x0a43, 0 x10, BIT(2 ), 0 );
}
static void rtl8168g_enable_gphy_10m(struct phy_device *phydev)
{
phy_modify_paged(phydev, 0 x0a44, 0 x11, 0 , BIT(11 ));
}
static void rtl8168g_phy_adjust_10m_aldps(struct phy_device *phydev)
{
phy_modify_paged(phydev, 0 x0bcc, 0 x14, BIT(8 ), 0 );
phy_modify_paged(phydev, 0 x0a44, 0 x11, 0 , BIT(7 ) | BIT(6 ));
r8168g_phy_param(phydev, 0 x8084, 0 x6000, 0 x0000);
phy_modify_paged(phydev, 0 x0a43, 0 x10, 0 x0000, 0 x1003);
}
static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp,
struct phy_device *phydev)
{
int ret;
r8169_apply_firmware(tp);
ret = phy_read_paged(phydev, 0 x0a46, 0 x10);
if (ret & BIT(8 ))
phy_modify_paged(phydev, 0 x0bcc, 0 x12, BIT(15 ), 0 );
else
phy_modify_paged(phydev, 0 x0bcc, 0 x12, 0 , BIT(15 ));
ret = phy_read_paged(phydev, 0 x0a46, 0 x13);
if (ret & BIT(8 ))
phy_modify_paged(phydev, 0 x0c41, 0 x15, 0 , BIT(1 ));
else
phy_modify_paged(phydev, 0 x0c41, 0 x15, BIT(1 ), 0 );
/* Enable PHY auto speed down */
phy_modify_paged(phydev, 0 x0a44, 0 x11, 0 , BIT(3 ) | BIT(2 ));
rtl8168g_phy_adjust_10m_aldps(phydev);
/* EEE auto-fallback function */
phy_modify_paged(phydev, 0 x0a4b, 0 x11, 0 , BIT(2 ));
/* Enable UC LPF tune function */
r8168g_phy_param(phydev, 0 x8012, 0 x0000, 0 x8000);
phy_modify_paged(phydev, 0 x0c42, 0 x11, BIT(13 ), BIT(14 ));
/* Improve SWR Efficiency */
phy_write(phydev, 0 x1f, 0 x0bcd);
phy_write(phydev, 0 x14, 0 x5065);
phy_write(phydev, 0 x14, 0 xd065);
phy_write(phydev, 0 x1f, 0 x0bc8);
phy_write(phydev, 0 x11, 0 x5655);
phy_write(phydev, 0 x1f, 0 x0bcd);
phy_write(phydev, 0 x14, 0 x1065);
phy_write(phydev, 0 x14, 0 x9065);
phy_write(phydev, 0 x14, 0 x1065);
phy_write(phydev, 0 x1f, 0 x0000);
rtl8168g_disable_aldps(phydev);
rtl8168g_config_eee_phy(phydev);
}
static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp,
struct phy_device *phydev)
{
r8169_apply_firmware(tp);
rtl8168g_config_eee_phy(phydev);
}
static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp,
struct phy_device *phydev)
{
u16 ioffset, rlen;
u32 data;
r8169_apply_firmware(tp);
/* CHIN EST parameter update */
r8168g_phy_param(phydev, 0 x808a, 0 x003f, 0 x000a);
/* enable R-tune & PGA-retune function */
r8168g_phy_param(phydev, 0 x0811, 0 x0000, 0 x0800);
phy_modify_paged(phydev, 0 x0a42, 0 x16, 0 x0000, 0 x0002);
rtl8168g_enable_gphy_10m(phydev);
ioffset = rtl8168h_2_get_adc_bias_ioffset(tp);
if (ioffset != 0 xffff)
phy_write_paged(phydev, 0 x0bcf, 0 x16, ioffset);
/* Modify rlen (TX LPF corner frequency) level */
data = phy_read_paged(phydev, 0 x0bcd, 0 x16);
data &= 0 x000f;
rlen = 0 ;
if (data > 3 )
rlen = data - 3 ;
data = rlen | (rlen << 4 ) | (rlen << 8 ) | (rlen << 12 );
phy_write_paged(phydev, 0 x0bcd, 0 x17, data);
/* disable phy pfm mode */
phy_modify_paged(phydev, 0 x0a44, 0 x11, BIT(7 ), 0 );
/* disable 10m pll off */
phy_modify_paged(phydev, 0 x0a43, 0 x10, BIT(0 ), 0 );
rtl8168g_disable_aldps(phydev);
rtl8168g_config_eee_phy(phydev);
}
static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp,
struct phy_device *phydev)
{
rtl8168g_phy_adjust_10m_aldps(phydev);
/* Enable UC LPF tune function */
r8168g_phy_param(phydev, 0 x8012, 0 x0000, 0 x8000);
/* Set rg_sel_sdm_rate */
phy_modify_paged(phydev, 0 x0c42, 0 x11, BIT(13 ), BIT(14 ));
/* Channel estimation parameters */
r8168g_phy_param(phydev, 0 x80f3, 0 xff00, 0 x8b00);
r8168g_phy_param(phydev, 0 x80f0, 0 xff00, 0 x3a00);
r8168g_phy_param(phydev, 0 x80ef, 0 xff00, 0 x0500);
r8168g_phy_param(phydev, 0 x80f6, 0 xff00, 0 x6e00);
r8168g_phy_param(phydev, 0 x80ec, 0 xff00, 0 x6800);
r8168g_phy_param(phydev, 0 x80ed, 0 xff00, 0 x7c00);
r8168g_phy_param(phydev, 0 x80f2, 0 xff00, 0 xf400);
r8168g_phy_param(phydev, 0 x80f4, 0 xff00, 0 x8500);
r8168g_phy_param(phydev, 0 x8110, 0 xff00, 0 xa800);
r8168g_phy_param(phydev, 0 x810f, 0 xff00, 0 x1d00);
r8168g_phy_param(phydev, 0 x8111, 0 xff00, 0 xf500);
r8168g_phy_param(phydev, 0 x8113, 0 xff00, 0 x6100);
r8168g_phy_param(phydev, 0 x8115, 0 xff00, 0 x9200);
r8168g_phy_param(phydev, 0 x810e, 0 xff00, 0 x0400);
r8168g_phy_param(phydev, 0 x810c, 0 xff00, 0 x7c00);
r8168g_phy_param(phydev, 0 x810b, 0 xff00, 0 x5a00);
r8168g_phy_param(phydev, 0 x80d1, 0 xff00, 0 xff00);
r8168g_phy_param(phydev, 0 x80cd, 0 xff00, 0 x9e00);
r8168g_phy_param(phydev, 0 x80d3, 0 xff00, 0 x0e00);
r8168g_phy_param(phydev, 0 x80d5, 0 xff00, 0 xca00);
r8168g_phy_param(phydev, 0 x80d7, 0 xff00, 0 x8400);
/* Force PWM-mode */
phy_write(phydev, 0 x1f, 0 x0bcd);
phy_write(phydev, 0 x14, 0 x5065);
phy_write(phydev, 0 x14, 0 xd065);
phy_write(phydev, 0 x1f, 0 x0bc8);
phy_write(phydev, 0 x12, 0 x00ed);
phy_write(phydev, 0 x1f, 0 x0bcd);
phy_write(phydev, 0 x14, 0 x1065);
phy_write(phydev, 0 x14, 0 x9065);
phy_write(phydev, 0 x14, 0 x1065);
phy_write(phydev, 0 x1f, 0 x0000);
rtl8168g_disable_aldps(phydev);
rtl8168g_config_eee_phy(phydev);
}
static void rtl8117_hw_phy_config(struct rtl8169_private *tp,
struct phy_device *phydev)
{
/* CHN EST parameters adjust - fnet */
r8168g_phy_param(phydev, 0 x808e, 0 xff00, 0 x4800);
r8168g_phy_param(phydev, 0 x8090, 0 xff00, 0 xcc00);
r8168g_phy_param(phydev, 0 x8092, 0 xff00, 0 xb000);
r8168g_phy_param(phydev, 0 x8088, 0 xff00, 0 x6000);
r8168g_phy_param(phydev, 0 x808b, 0 x3f00, 0 x0b00);
r8168g_phy_param(phydev, 0 x808d, 0 x1f00, 0 x0600);
r8168g_phy_param(phydev, 0 x808c, 0 xff00, 0 xb000);
r8168g_phy_param(phydev, 0 x80a0, 0 xff00, 0 x2800);
r8168g_phy_param(phydev, 0 x80a2, 0 xff00, 0 x5000);
r8168g_phy_param(phydev, 0 x809b, 0 xf800, 0 xb000);
r8168g_phy_param(phydev, 0 x809a, 0 xff00, 0 x4b00);
r8168g_phy_param(phydev, 0 x809d, 0 x3f00, 0 x0800);
r8168g_phy_param(phydev, 0 x80a1, 0 xff00, 0 x7000);
r8168g_phy_param(phydev, 0 x809f, 0 x1f00, 0 x0300);
r8168g_phy_param(phydev, 0 x809e, 0 xff00, 0 x8800);
r8168g_phy_param(phydev, 0 x80b2, 0 xff00, 0 x2200);
r8168g_phy_param(phydev, 0 x80ad, 0 xf800, 0 x9800);
r8168g_phy_param(phydev, 0 x80af, 0 x3f00, 0 x0800);
r8168g_phy_param(phydev, 0 x80b3, 0 xff00, 0 x6f00);
r8168g_phy_param(phydev, 0 x80b1, 0 x1f00, 0 x0300);
r8168g_phy_param(phydev, 0 x80b0, 0 xff00, 0 x9300);
r8168g_phy_param(phydev, 0 x8011, 0 x0000, 0 x0800);
rtl8168g_enable_gphy_10m(phydev);
r8168g_phy_param(phydev, 0 x8016, 0 x0000, 0 x0400);
rtl8168g_disable_aldps(phydev);
rtl8168h_config_eee_phy(phydev);
}
static void rtl8102e_hw_phy_config(struct rtl8169_private *tp,
struct phy_device *phydev)
{
static const struct phy_reg phy_reg_init[] = {
{ 0 x1f, 0 x0003 },
{ 0 x08, 0 x441d },
{ 0 x01, 0 x9100 },
{ 0 x1f, 0 x0000 }
};
phy_set_bits(phydev, 0 x11, BIT(12 ));
phy_set_bits(phydev, 0 x19, BIT(13 ));
phy_set_bits(phydev, 0 x10, BIT(15 ));
rtl_writephy_batch(phydev, phy_reg_init);
}
static void rtl8401_hw_phy_config(struct rtl8169_private *tp,
struct phy_device *phydev)
{
phy_set_bits(phydev, 0 x11, BIT(12 ));
phy_modify_paged(phydev, 0 x0002, 0 x0f, 0 x0000, 0 x0003);
}
static void rtl8105e_hw_phy_config(struct rtl8169_private *tp,
struct phy_device *phydev)
{
/* Disable ALDPS before ram code */
phy_write(phydev, 0 x18, 0 x0310);
msleep(100 );
r8169_apply_firmware(tp);
phy_write_paged(phydev, 0 x0005, 0 x1a, 0 x0000);
phy_write_paged(phydev, 0 x0004, 0 x1c, 0 x0000);
phy_write_paged(phydev, 0 x0001, 0 x15, 0 x7701);
}
static void rtl8402_hw_phy_config(struct rtl8169_private *tp,
struct phy_device *phydev)
{
/* Disable ALDPS before setting firmware */
phy_write(phydev, 0 x18, 0 x0310);
msleep(20 );
r8169_apply_firmware(tp);
/* EEE setting */
phy_write(phydev, 0 x1f, 0 x0004);
phy_write(phydev, 0 x10, 0 x401f);
phy_write(phydev, 0 x19, 0 x7030);
phy_write(phydev, 0 x1f, 0 x0000);
}
static void rtl8106e_hw_phy_config(struct rtl8169_private *tp,
struct phy_device *phydev)
{
static const struct phy_reg phy_reg_init[] = {
{ 0 x1f, 0 x0004 },
{ 0 x10, 0 xc07f },
{ 0 x19, 0 x7030 },
{ 0 x1f, 0 x0000 }
};
/* Disable ALDPS before ram code */
phy_write(phydev, 0 x18, 0 x0310);
msleep(100 );
r8169_apply_firmware(tp);
rtl_writephy_batch(phydev, phy_reg_init);
}
static void rtl8125_legacy_force_mode(struct phy_device *phydev)
{
phy_modify_paged(phydev, 0 xa5b, 0 x12, BIT(15 ), 0 );
}
static void rtl8125a_2_hw_phy_config(struct rtl8169_private *tp,
struct phy_device *phydev)
{
int i;
phy_modify_paged(phydev, 0 xad4, 0 x17, 0 x0000, 0 x0010);
phy_modify_paged(phydev, 0 xad1, 0 x13, 0 x03ff, 0 x03ff);
phy_modify_paged(phydev, 0 xad3, 0 x11, 0 x003f, 0 x0006);
phy_modify_paged(phydev, 0 xac0, 0 x14, 0 x1100, 0 x0000);
phy_modify_paged(phydev, 0 xacc, 0 x10, 0 x0003, 0 x0002);
phy_modify_paged(phydev, 0 xad4, 0 x10, 0 x00e7, 0 x0044);
phy_modify_paged(phydev, 0 xac1, 0 x12, 0 x0080, 0 x0000);
phy_modify_paged(phydev, 0 xac8, 0 x10, 0 x0300, 0 x0000);
phy_modify_paged(phydev, 0 xac5, 0 x17, 0 x0007, 0 x0002);
phy_write_paged(phydev, 0 xad4, 0 x16, 0 x00a8);
phy_write_paged(phydev, 0 xac5, 0 x16, 0 x01ff);
phy_modify_paged(phydev, 0 xac8, 0 x15, 0 x00f0, 0 x0030);
rtl8125_phy_param(phydev, 0 x80a2, 0 xffff, 0 x0153);
rtl8125_phy_param(phydev, 0 x809c, 0 xffff, 0 x0153);
phy_write(phydev, 0 x1f, 0 x0a43);
phy_write(phydev, 0 x13, 0 x81B3);
phy_write(phydev, 0 x14, 0 x0043);
phy_write(phydev, 0 x14, 0 x00A7);
phy_write(phydev, 0 x14, 0 x00D6);
phy_write(phydev, 0 x14, 0 x00EC);
phy_write(phydev, 0 x14, 0 x00F6);
phy_write(phydev, 0 x14, 0 x00FB);
phy_write(phydev, 0 x14, 0 x00FD);
phy_write(phydev, 0 x14, 0 x00FF);
phy_write(phydev, 0 x14, 0 x00BB);
phy_write(phydev, 0 x14, 0 x0058);
phy_write(phydev, 0 x14, 0 x0029);
phy_write(phydev, 0 x14, 0 x0013);
phy_write(phydev, 0 x14, 0 x0009);
phy_write(phydev, 0 x14, 0 x0004);
phy_write(phydev, 0 x14, 0 x0002);
for (i = 0 ; i < 25 ; i++)
phy_write(phydev, 0 x14, 0 x0000);
phy_write(phydev, 0 x1f, 0 x0000);
r8168g_phy_param(phydev, 0 x8257, 0 xffff, 0 x020F);
r8168g_phy_param(phydev, 0 x80ea, 0 xffff, 0 x7843);
r8169_apply_firmware(tp);
phy_modify_paged(phydev, 0 xd06, 0 x14, 0 x0000, 0 x2000);
r8168g_phy_param(phydev, 0 x81a2, 0 x0000, 0 x0100);
phy_modify_paged(phydev, 0 xb54, 0 x16, 0 xff00, 0 xdb00);
phy_modify_paged(phydev, 0 xa45, 0 x12, 0 x0001, 0 x0000);
phy_modify_paged(phydev, 0 xa5d, 0 x12, 0 x0000, 0 x0020);
phy_modify_paged(phydev, 0 xad4, 0 x17, 0 x0010, 0 x0000);
phy_modify_paged(phydev, 0 xa86, 0 x15, 0 x0001, 0 x0000);
rtl8168g_enable_gphy_10m(phydev);
rtl8168g_disable_aldps(phydev);
rtl8125_config_eee_phy(phydev);
}
static void rtl8125b_hw_phy_config(struct rtl8169_private *tp,
struct phy_device *phydev)
{
r8169_apply_firmware(tp);
rtl8168g_enable_gphy_10m(phydev);
phy_modify_paged(phydev, 0 xac4, 0 x13, 0 x00f0, 0 x0090);
phy_modify_paged(phydev, 0 xad3, 0 x10, 0 x0003, 0 x0001);
rtl8125_phy_param(phydev, 0 x80f5, 0 xffff, 0 x760e);
rtl8125_phy_param(phydev, 0 x8107, 0 xffff, 0 x360e);
rtl8125_phy_param(phydev, 0 x8551, 0 xff00, 0 x0800);
phy_modify_paged(phydev, 0 xbf0, 0 x10, 0 xe000, 0 xa000);
phy_modify_paged(phydev, 0 xbf4, 0 x13, 0 x0f00, 0 x0300);
r8168g_phy_param(phydev, 0 x8044, 0 xffff, 0 x2417);
r8168g_phy_param(phydev, 0 x804a, 0 xffff, 0 x2417);
r8168g_phy_param(phydev, 0 x8050, 0 xffff, 0 x2417);
r8168g_phy_param(phydev, 0 x8056, 0 xffff, 0 x2417);
r8168g_phy_param(phydev, 0 x805c, 0 xffff, 0 x2417);
r8168g_phy_param(phydev, 0 x8062, 0 xffff, 0 x2417);
r8168g_phy_param(phydev, 0 x8068, 0 xffff, 0 x2417);
r8168g_phy_param(phydev, 0 x806e, 0 xffff, 0 x2417);
r8168g_phy_param(phydev, 0 x8074, 0 xffff, 0 x2417);
r8168g_phy_param(phydev, 0 x807a, 0 xffff, 0 x2417);
phy_modify_paged(phydev, 0 xa4c, 0 x15, 0 x0000, 0 x0040);
phy_modify_paged(phydev, 0 xbf8, 0 x12, 0 xe000, 0 xa000);
rtl8125_legacy_force_mode(phydev);
rtl8168g_disable_aldps(phydev);
rtl8125_config_eee_phy(phydev);
}
static void rtl8125d_hw_phy_config(struct rtl8169_private *tp,
struct phy_device *phydev)
{
r8169_apply_firmware(tp);
rtl8168g_enable_gphy_10m(phydev);
rtl8125_legacy_force_mode(phydev);
rtl8168g_disable_aldps(phydev);
rtl8125_config_eee_phy(phydev);
}
static void rtl8125bp_hw_phy_config(struct rtl8169_private *tp,
struct phy_device *phydev)
{
r8169_apply_firmware(tp);
rtl8168g_enable_gphy_10m(phydev);
r8168g_phy_param(phydev, 0 x8010, 0 x0800, 0 x0000);
rtl8125_phy_param(phydev, 0 x8088, 0 xff00, 0 x9000);
rtl8125_phy_param(phydev, 0 x808f, 0 xff00, 0 x9000);
r8168g_phy_param(phydev, 0 x8174, 0 x2000, 0 x1800);
rtl8125_legacy_force_mode(phydev);
rtl8168g_disable_aldps(phydev);
rtl8125_config_eee_phy(phydev);
}
static void rtl8126a_hw_phy_config(struct rtl8169_private *tp,
struct phy_device *phydev)
{
r8169_apply_firmware(tp);
rtl8168g_enable_gphy_10m(phydev);
rtl8125_legacy_force_mode(phydev);
rtl8168g_disable_aldps(phydev);
rtl8125_common_config_eee_phy(phydev);
}
static void rtl8127a_1_hw_phy_config(struct rtl8169_private *tp,
struct phy_device *phydev)
{
r8169_apply_firmware(tp);
rtl8168g_enable_gphy_10m(phydev);
r8168g_phy_param(phydev, 0 x8415, 0 xff00, 0 x9300);
r8168g_phy_param(phydev, 0 x81a3, 0 xff00, 0 x0f00);
r8168g_phy_param(phydev, 0 x81ae, 0 xff00, 0 x0f00);
r8168g_phy_param(phydev, 0 x81b9, 0 xff00, 0 xb900);
rtl8125_phy_param(phydev, 0 x83b0, 0 x0e00, 0 x0000);
rtl8125_phy_param(phydev, 0 x83C5, 0 x0e00, 0 x0000);
rtl8125_phy_param(phydev, 0 x83da, 0 x0e00, 0 x0000);
rtl8125_phy_param(phydev, 0 x83ef, 0 x0e00, 0 x0000);
phy_modify_paged(phydev, 0 x0bf3, 0 x14, 0 x01f0, 0 x0160);
phy_modify_paged(phydev, 0 x0bf3, 0 x15, 0 x001f, 0 x0014);
phy_modify_paged(phydev, 0 x0bf2, 0 x14, 0 x6000, 0 x0000);
phy_modify_paged(phydev, 0 x0bf2, 0 x16, 0 xc000, 0 x0000);
phy_modify_paged(phydev, 0 x0bf2, 0 x14, 0 x1fff, 0 x0187);
phy_modify_paged(phydev, 0 x0bf2, 0 x15, 0 x003f, 0 x0003);
r8168g_phy_param(phydev, 0 x8173, 0 xffff, 0 x8620);
r8168g_phy_param(phydev, 0 x8175, 0 xffff, 0 x8671);
r8168g_phy_param(phydev, 0 x817c, 0 x0000, 0 x2000);
r8168g_phy_param(phydev, 0 x8187, 0 x0000, 0 x2000);
r8168g_phy_param(phydev, 0 x8192, 0 x0000, 0 x2000);
r8168g_phy_param(phydev, 0 x819d, 0 x0000, 0 x2000);
r8168g_phy_param(phydev, 0 x81a8, 0 x2000, 0 x0000);
r8168g_phy_param(phydev, 0 x81b3, 0 x2000, 0 x0000);
r8168g_phy_param(phydev, 0 x81be, 0 x0000, 0 x2000);
r8168g_phy_param(phydev, 0 x817d, 0 xff00, 0 xa600);
r8168g_phy_param(phydev, 0 x8188, 0 xff00, 0 xa600);
r8168g_phy_param(phydev, 0 x8193, 0 xff00, 0 xa600);
r8168g_phy_param(phydev, 0 x819e, 0 xff00, 0 xa600);
r8168g_phy_param(phydev, 0 x81a9, 0 xff00, 0 x1400);
r8168g_phy_param(phydev, 0 x81b4, 0 xff00, 0 x1400);
r8168g_phy_param(phydev, 0 x81bf, 0 xff00, 0 xa600);
phy_modify_paged(phydev, 0 x0aea, 0 x15, 0 x0028, 0 x0000);
rtl8125_phy_param(phydev, 0 x84f0, 0 xffff, 0 x201c);
rtl8125_phy_param(phydev, 0 x84f2, 0 xffff, 0 x3117);
phy_write_paged(phydev, 0 x0aec, 0 x13, 0 x0000);
phy_write_paged(phydev, 0 x0ae2, 0 x10, 0 xffff);
phy_write_paged(phydev, 0 x0aec, 0 x17, 0 xffff);
phy_write_paged(phydev, 0 x0aed, 0 x11, 0 xffff);
phy_write_paged(phydev, 0 x0aec, 0 x14, 0 x0000);
phy_modify_paged(phydev, 0 x0aed, 0 x10, 0 x0001, 0 x0000);
phy_write_paged(phydev, 0 x0adb, 0 x14, 0 x0150);
rtl8125_phy_param(phydev, 0 x8197, 0 xff00, 0 x5000);
rtl8125_phy_param(phydev, 0 x8231, 0 xff00, 0 x5000);
rtl8125_phy_param(phydev, 0 x82cb, 0 xff00, 0 x5000);
rtl8125_phy_param(phydev, 0 x82cd, 0 xff00, 0 x5700);
rtl8125_phy_param(phydev, 0 x8233, 0 xff00, 0 x5700);
rtl8125_phy_param(phydev, 0 x8199, 0 xff00, 0 x5700);
rtl8125_phy_param(phydev, 0 x815a, 0 xffff, 0 x0150);
rtl8125_phy_param(phydev, 0 x81f4, 0 xffff, 0 x0150);
rtl8125_phy_param(phydev, 0 x828e, 0 xffff, 0 x0150);
rtl8125_phy_param(phydev, 0 x81b1, 0 xffff, 0 x0000);
rtl8125_phy_param(phydev, 0 x824b, 0 xffff, 0 x0000);
rtl8125_phy_param(phydev, 0 x82e5, 0 xffff, 0 x0000);
rtl8125_phy_param(phydev, 0 x84f7, 0 xff00, 0 x2800);
phy_modify_paged(phydev, 0 x0aec, 0 x11, 0 x0000, 0 x1000);
rtl8125_phy_param(phydev, 0 x81b3, 0 xff00, 0 xad00);
rtl8125_phy_param(phydev, 0 x824d, 0 xff00, 0 xad00);
rtl8125_phy_param(phydev, 0 x82e7, 0 xff00, 0 xad00);
phy_modify_paged(phydev, 0 x0ae4, 0 x17, 0 x000f, 0 x0001);
rtl8125_phy_param(phydev, 0 x82ce, 0 xf000, 0 x4000);
rtl8125_phy_param(phydev, 0 x84ac, 0 xffff, 0 x0000);
rtl8125_phy_param(phydev, 0 x84ae, 0 xffff, 0 x0000);
rtl8125_phy_param(phydev, 0 x84b0, 0 xffff, 0 xf818);
rtl8125_phy_param(phydev, 0 x84b2, 0 xff00, 0 x6000);
rtl8125_phy_param(phydev, 0 x8ffc, 0 xffff, 0 x6008);
rtl8125_phy_param(phydev, 0 x8ffe, 0 xffff, 0 xf450);
rtl8125_phy_param(phydev, 0 x8015, 0 x0000, 0 x0200);
rtl8125_phy_param(phydev, 0 x8016, 0 x0800, 0 x0000);
rtl8125_phy_param(phydev, 0 x8fe6, 0 xff00, 0 x0800);
rtl8125_phy_param(phydev, 0 x8fe4, 0 xffff, 0 x2114);
rtl8125_phy_param(phydev, 0 x8647, 0 xffff, 0 xa7b1);
rtl8125_phy_param(phydev, 0 x8649, 0 xffff, 0 xbbca);
rtl8125_phy_param(phydev, 0 x864b, 0 xff00, 0 xdc00);
rtl8125_phy_param(phydev, 0 x8154, 0 xc000, 0 x4000);
rtl8125_phy_param(phydev, 0 x8158, 0 xc000, 0 x0000);
rtl8125_phy_param(phydev, 0 x826c, 0 xffff, 0 xffff);
rtl8125_phy_param(phydev, 0 x826e, 0 xffff, 0 xffff);
rtl8125_phy_param(phydev, 0 x8872, 0 xff00, 0 x0e00);
r8168g_phy_param(phydev, 0 x8012, 0 x0000, 0 x0800);
r8168g_phy_param(phydev, 0 x8012, 0 x0000, 0 x4000);
phy_modify_paged(phydev, 0 x0b57, 0 x13, 0 x0000, 0 x0001);
r8168g_phy_param(phydev, 0 x834a, 0 xff00, 0 x0700);
rtl8125_phy_param(phydev, 0 x8217, 0 x3f00, 0 x2a00);
r8168g_phy_param(phydev, 0 x81b1, 0 xff00, 0 x0b00);
rtl8125_phy_param(phydev, 0 x8fed, 0 xff00, 0 x4e00);
rtl8125_phy_param(phydev, 0 x88ac, 0 xff00, 0 x2300);
phy_modify_paged(phydev, 0 x0bf0, 0 x16, 0 x0000, 0 x3800);
rtl8125_phy_param(phydev, 0 x88de, 0 xff00, 0 x0000);
rtl8125_phy_param(phydev, 0 x80b4, 0 xffff, 0 x5195);
r8168g_phy_param(phydev, 0 x8370, 0 xffff, 0 x8671);
r8168g_phy_param(phydev, 0 x8372, 0 xffff, 0 x86c8);
r8168g_phy_param(phydev, 0 x8401, 0 xffff, 0 x86c8);
r8168g_phy_param(phydev, 0 x8403, 0 xffff, 0 x86da);
r8168g_phy_param(phydev, 0 x8406, 0 x1800, 0 x1000);
r8168g_phy_param(phydev, 0 x8408, 0 x1800, 0 x1000);
r8168g_phy_param(phydev, 0 x840a, 0 x1800, 0 x1000);
r8168g_phy_param(phydev, 0 x840c, 0 x1800, 0 x1000);
r8168g_phy_param(phydev, 0 x840e, 0 x1800, 0 x1000);
r8168g_phy_param(phydev, 0 x8410, 0 x1800, 0 x1000);
r8168g_phy_param(phydev, 0 x8412, 0 x1800, 0 x1000);
r8168g_phy_param(phydev, 0 x8414, 0 x1800, 0 x1000);
r8168g_phy_param(phydev, 0 x8416, 0 x1800, 0 x1000);
r8168g_phy_param(phydev, 0 x82bd, 0 xffff, 0 x1f40);
phy_modify_paged(phydev, 0 x0bfb, 0 x12, 0 x07ff, 0 x0328);
phy_write_paged(phydev, 0 x0bfb, 0 x13, 0 x3e14);
r8168g_phy_param(phydev, 0 x81c4, 0 xffff, 0 x003b);
r8168g_phy_param(phydev, 0 x81c6, 0 xffff, 0 x0086);
r8168g_phy_param(phydev, 0 x81c8, 0 xffff, 0 x00b7);
r8168g_phy_param(phydev, 0 x81ca, 0 xffff, 0 x00db);
r8168g_phy_param(phydev, 0 x81cc, 0 xffff, 0 x00fe);
r8168g_phy_param(phydev, 0 x81ce, 0 xffff, 0 x00fe);
r8168g_phy_param(phydev, 0 x81d0, 0 xffff, 0 x00fe);
r8168g_phy_param(phydev, 0 x81d2, 0 xffff, 0 x00fe);
r8168g_phy_param(phydev, 0 x81d4, 0 xffff, 0 x00c3);
r8168g_phy_param(phydev, 0 x81d6, 0 xffff, 0 x0078);
r8168g_phy_param(phydev, 0 x81d8, 0 xffff, 0 x0047);
r8168g_phy_param(phydev, 0 x81da, 0 xffff, 0 x0023);
rtl8125_phy_param(phydev, 0 x88d7, 0 xffff, 0 x01a0);
rtl8125_phy_param(phydev, 0 x88d9, 0 xffff, 0 x01a0);
rtl8125_phy_param(phydev, 0 x8ffa, 0 xffff, 0 x002a);
rtl8125_phy_param(phydev, 0 x8fee, 0 xffff, 0 xffdf);
rtl8125_phy_param(phydev, 0 x8ff0, 0 xffff, 0 xffff);
rtl8125_phy_param(phydev, 0 x8ff2, 0 xffff, 0 x0a4a);
rtl8125_phy_param(phydev, 0 x8ff4, 0 xffff, 0 xaa5a);
rtl8125_phy_param(phydev, 0 x8ff6, 0 xffff, 0 x0a4a);
rtl8125_phy_param(phydev, 0 x8ff8, 0 xffff, 0 xaa5a);
rtl8125_phy_param(phydev, 0 x88d5, 0 xff00, 0 x0200);
r8168g_phy_param(phydev, 0 x84bb, 0 xff00, 0 x0a00);
r8168g_phy_param(phydev, 0 x84c0, 0 xff00, 0 x1600);
phy_modify_paged(phydev, 0 x0a43, 0 x10, 0 x0000, 0 x0003);
rtl8125_legacy_force_mode(phydev);
rtl8168g_disable_aldps(phydev);
rtl8125_common_config_eee_phy(phydev);
}
void r8169_hw_phy_config(struct rtl8169_private *tp, struct phy_device *phydev,
enum mac_version ver)
{
static const rtl_phy_cfg_fct phy_configs[] = {
/* PCI devices. */
[RTL_GIGA_MAC_VER_02] = rtl8169s_hw_phy_config,
[RTL_GIGA_MAC_VER_03] = rtl8169s_hw_phy_config,
[RTL_GIGA_MAC_VER_04] = rtl8169sb_hw_phy_config,
[RTL_GIGA_MAC_VER_05] = rtl8169scd_hw_phy_config,
[RTL_GIGA_MAC_VER_06] = rtl8169sce_hw_phy_config,
/* PCI-E devices. */
[RTL_GIGA_MAC_VER_07] = rtl8102e_hw_phy_config,
[RTL_GIGA_MAC_VER_08] = rtl8102e_hw_phy_config,
[RTL_GIGA_MAC_VER_09] = rtl8102e_hw_phy_config,
[RTL_GIGA_MAC_VER_10] = NULL,
[RTL_GIGA_MAC_VER_14] = rtl8401_hw_phy_config,
[RTL_GIGA_MAC_VER_17] = rtl8168bef_hw_phy_config,
[RTL_GIGA_MAC_VER_18] = rtl8168cp_1_hw_phy_config,
[RTL_GIGA_MAC_VER_19] = rtl8168c_1_hw_phy_config,
[RTL_GIGA_MAC_VER_20] = rtl8168c_2_hw_phy_config,
[RTL_GIGA_MAC_VER_21] = rtl8168c_3_hw_phy_config,
[RTL_GIGA_MAC_VER_22] = rtl8168c_3_hw_phy_config,
[RTL_GIGA_MAC_VER_23] = rtl8168cp_2_hw_phy_config,
[RTL_GIGA_MAC_VER_24] = rtl8168cp_2_hw_phy_config,
[RTL_GIGA_MAC_VER_25] = rtl8168d_1_hw_phy_config,
[RTL_GIGA_MAC_VER_26] = rtl8168d_2_hw_phy_config,
[RTL_GIGA_MAC_VER_28] = rtl8168d_4_hw_phy_config,
[RTL_GIGA_MAC_VER_29] = rtl8105e_hw_phy_config,
[RTL_GIGA_MAC_VER_30] = rtl8105e_hw_phy_config,
[RTL_GIGA_MAC_VER_31] = NULL,
[RTL_GIGA_MAC_VER_32] = rtl8168e_1_hw_phy_config,
[RTL_GIGA_MAC_VER_33] = rtl8168e_1_hw_phy_config,
[RTL_GIGA_MAC_VER_34] = rtl8168e_2_hw_phy_config,
[RTL_GIGA_MAC_VER_35] = rtl8168f_1_hw_phy_config,
[RTL_GIGA_MAC_VER_36] = rtl8168f_2_hw_phy_config,
[RTL_GIGA_MAC_VER_37] = rtl8402_hw_phy_config,
[RTL_GIGA_MAC_VER_38] = rtl8411_hw_phy_config,
[RTL_GIGA_MAC_VER_39] = rtl8106e_hw_phy_config,
[RTL_GIGA_MAC_VER_40] = rtl8168g_1_hw_phy_config,
[RTL_GIGA_MAC_VER_42] = rtl8168g_2_hw_phy_config,
[RTL_GIGA_MAC_VER_43] = rtl8168g_2_hw_phy_config,
[RTL_GIGA_MAC_VER_44] = rtl8168g_2_hw_phy_config,
[RTL_GIGA_MAC_VER_46] = rtl8168h_2_hw_phy_config,
[RTL_GIGA_MAC_VER_48] = rtl8168h_2_hw_phy_config,
[RTL_GIGA_MAC_VER_51] = rtl8168ep_2_hw_phy_config,
[RTL_GIGA_MAC_VER_52] = rtl8117_hw_phy_config,
[RTL_GIGA_MAC_VER_61] = rtl8125a_2_hw_phy_config,
[RTL_GIGA_MAC_VER_63] = rtl8125b_hw_phy_config,
[RTL_GIGA_MAC_VER_64] = rtl8125d_hw_phy_config,
[RTL_GIGA_MAC_VER_66] = rtl8125bp_hw_phy_config,
[RTL_GIGA_MAC_VER_70] = rtl8126a_hw_phy_config,
[RTL_GIGA_MAC_VER_80] = rtl8127a_1_hw_phy_config,
};
if (phy_configs[ver])
phy_configs[ver](tp, phydev);
}
Messung V0.5 in Prozent C=94 H=92 G=92
¤ Diese beiden folgenden Angebotsgruppen bietet das Unternehmen0.15Angebot
(Wie Sie bei der Firma Beratungs- und Dienstleistungen beauftragen können 2026-06-07)
¤
*Eine klare Vorstellung vom Zielzustand