Quelle ionic_if.h
Sprache: C
/* SPDX-License-Identifier: (GPL-2.0 OR Linux-OpenIB) OR BSD-2-Clause */ /* Copyright (c) 2017-2020 Pensando Systems, Inc. All rights reserved. */ #ifndef _IONIC_IF_H_#define _IONIC_IF_H_#define IONIC_DEV_INFO_SIGNATURE 0 x44455649 /* 'DEVI' */ #define IONIC_DEV_INFO_VERSION 1 #define IONIC_IFNAMSIZ 16 /* * enum ionic_cmd_opcode - Device commands enum ionic_cmd_opcode {0 ,/* Device commands */ 1 ,2 ,3 ,4 ,5 ,/* Port commands */ 10 ,11 ,12 ,13 ,14 ,/* LIF commands */ 20 ,21 ,22 ,23 ,24 ,25 ,30 ,31 ,32 ,/* Queue commands */ 39 ,40 ,41 ,/* RDMA commands */ 50 ,51 ,52 ,53 ,/* SR/IOV commands */ 60 ,61 ,62 ,/* QoS commands */ 240 ,241 ,242 ,243 ,244 ,245 ,/* Firmware commands */ 252 ,253 ,254 ,255 ,/* * enum ionic_status_code - Device command return codes enum ionic_status_code {0 , /* Success */ 1 , /* Incorrect version for request */ 2 , /* Invalid cmd opcode */ 3 , /* I/O error */ 4 , /* Permission denied */ 5 , /* Bad qid */ 6 , /* Bad qtype */ 7 , /* No such element */ 8 , /* operation interrupted */ 9 , /* Try again */ 10 , /* Out of memory */ 11 , /* Bad address */ 12 , /* Device or resource busy */ 13 , /* object already exists */ 14 , /* Invalid argument */ 15 , /* No space left or alloc failure */ 16 , /* Parameter out of range */ 17 , /* Descriptor contains a bad ptr */ 18 , /* Device cmd attempted on AdminQ */ 19 , /* Operation not supported */ 29 , /* Generic error */ 30 , /* Generic RDMA error */ 31 , /* VF ID does not exist */ 32 , /* FW file is invalid or corrupted */ enum ionic_notifyq_opcode {1 ,2 ,3 ,4 ,5 ,/** * struct ionic_admin_cmd - General admin command format * @ opcode : Opcode for the command * @ rsvd : reserved byte ( s ) * @ lif_index : LIF index * @ cmd_data : Opcode - specific command bytes struct ionic_admin_cmd {60 ];/** * struct ionic_admin_comp - General admin command completion format * @ status : Status of the command ( enum ionic_status_code ) * @ rsvd : reserved byte ( s ) * @ comp_index : Index in the descriptor ring for which this is the completion * @ cmd_data : Command - specific bytes * @ color : Color bit ( Always 0 for commands issued to the * Device Cmd Registers ) struct ionic_admin_comp {11 ];#define IONIC_COMP_COLOR_MASK 0 x80static inline u8 color_match(u8 color, u8 done_color)return (!!(color & IONIC_COMP_COLOR_MASK)) == done_color;/** * struct ionic_nop_cmd - NOP command * @ opcode : opcode * @ rsvd : reserved byte ( s ) struct ionic_nop_cmd {63 ];/** * struct ionic_nop_comp - NOP command completion * @ status : Status of the command ( enum ionic_status_code ) * @ rsvd : reserved byte ( s ) struct ionic_nop_comp {15 ];/** * struct ionic_dev_init_cmd - Device init command * @ opcode : opcode * @ type : Device type * @ rsvd : reserved byte ( s ) struct ionic_dev_init_cmd {62 ];/** * struct ionic_dev_init_comp - Device init command completion * @ status : Status of the command ( enum ionic_status_code ) * @ rsvd : reserved byte ( s ) struct ionic_dev_init_comp {15 ];/** * struct ionic_dev_reset_cmd - Device reset command * @ opcode : opcode * @ rsvd : reserved byte ( s ) struct ionic_dev_reset_cmd {63 ];/** * struct ionic_dev_reset_comp - Reset command completion * @ status : Status of the command ( enum ionic_status_code ) * @ rsvd : reserved byte ( s ) struct ionic_dev_reset_comp {15 ];#define IONIC_IDENTITY_VERSION_1 1 #define IONIC_DEV_IDENTITY_VERSION_2 2 /** * struct ionic_dev_identify_cmd - Driver / device identify command * @ opcode : opcode * @ ver : Highest version of identify supported by driver * @ rsvd : reserved byte ( s ) struct ionic_dev_identify_cmd {62 ];/** * struct ionic_dev_identify_comp - Driver / device identify command completion * @ status : Status of the command ( enum ionic_status_code ) * @ ver : Version of identify returned by device * @ rsvd : reserved byte ( s ) struct ionic_dev_identify_comp {14 ];enum ionic_os_type {1 ,2 ,3 ,4 ,5 ,6 ,/** * union ionic_drv_identity - driver identity information * @ os_type : OS type ( see enum ionic_os_type ) * @ os_dist : OS distribution , numeric format * @ os_dist_str : OS distribution , string format * @ kernel_ver : Kernel version , numeric format * @ kernel_ver_str : Kernel version , string format * @ driver_ver_str : Driver version , string format * @ words : word access to struct contents union ionic_drv_identity {struct {char os_dist_str[128 ];char kernel_ver_str[32 ];char driver_ver_str[32 ];478 ];/** * enum ionic_dev_capability - Device capabilities * @ IONIC_DEV_CAP_VF_CTRL : Device supports VF ctrl operations enum ionic_dev_capability {0 ),/** * union ionic_dev_identity - device identity information * @ version : Version of device identify * @ type : Identify type ( 0 for now ) * @ rsvd : reserved byte ( s ) * @ nports : Number of ports provisioned * @ rsvd2 : reserved byte ( s ) * @ nlifs : Number of LIFs provisioned * @ nintrs : Number of interrupts provisioned * @ ndbpgs_per_lif : Number of doorbell pages per LIF * @ intr_coal_mult : Interrupt coalescing multiplication factor * Scale user - supplied interrupt coalescing * value in usecs to device units using : * device units = usecs * mult / div * @ intr_coal_div : Interrupt coalescing division factor * Scale user - supplied interrupt coalescing * value in usecs to device units using : * device units = usecs * mult / div * @ eq_count : Number of shared event queues * @ hwstamp_mask : Bitmask for subtraction of hardware tick values . * @ hwstamp_mult : Hardware tick to nanosecond multiplier . * @ hwstamp_shift : Hardware tick to nanosecond divisor ( power of two ) . * @ capabilities : Device capabilities * @ words : word access to struct contents union ionic_dev_identity {struct {2 ];3 ];478 ];enum ionic_lif_type {0 ,1 ,2 ,/** * struct ionic_lif_identify_cmd - LIF identify command * @ opcode : opcode * @ type : LIF type ( enum ionic_lif_type ) * @ ver : Version of identify returned by device * @ rsvd : reserved byte ( s ) struct ionic_lif_identify_cmd {61 ];/** * struct ionic_lif_identify_comp - LIF identify command completion * @ status : Status of the command ( enum ionic_status_code ) * @ ver : Version of identify returned by device * @ rsvd2 : reserved byte ( s ) struct ionic_lif_identify_comp {14 ];/** * enum ionic_lif_capability - LIF capabilities * @ IONIC_LIF_CAP_ETH : LIF supports Ethernet * @ IONIC_LIF_CAP_RDMA : LIF supports RDMA enum ionic_lif_capability {0 ),1 ),/** * enum ionic_logical_qtype - Logical Queue Types * @ IONIC_QTYPE_ADMINQ : Administrative Queue * @ IONIC_QTYPE_NOTIFYQ : Notify Queue * @ IONIC_QTYPE_RXQ : Receive Queue * @ IONIC_QTYPE_TXQ : Transmit Queue * @ IONIC_QTYPE_EQ : Event Queue * @ IONIC_QTYPE_MAX : Max queue type supported enum ionic_logical_qtype {0 ,1 ,2 ,3 ,4 ,16 ,/** * enum ionic_q_feature - Common Features for most queue types * * Common features use bits 0 - 15 . Per - queue - type features use higher bits . * * @ IONIC_QIDENT_F_CQ : Queue has completion ring * @ IONIC_QIDENT_F_SG : Queue has scatter / gather ring * @ IONIC_QIDENT_F_EQ : Queue can use event queue * @ IONIC_QIDENT_F_CMB : Queue is in cmb bar * @ IONIC_Q_F_2X_DESC : Double main descriptor size * @ IONIC_Q_F_2X_CQ_DESC : Double cq descriptor size * @ IONIC_Q_F_2X_SG_DESC : Double sg descriptor size * @ IONIC_Q_F_4X_DESC : Quadruple main descriptor size * @ IONIC_Q_F_4X_CQ_DESC : Quadruple cq descriptor size * @ IONIC_Q_F_4X_SG_DESC : Quadruple sg descriptor size enum ionic_q_feature {0 ),1 ),2 ),3 ),4 ),5 ),6 ),7 ),8 ),9 ),/** * enum ionic_rxq_feature - RXQ - specific Features * * Per - queue - type features use bits 16 and higher . * * @ IONIC_RXQ_F_HWSTAMP : Queue supports Hardware Timestamping enum ionic_rxq_feature {16 ),/** * enum ionic_txq_feature - TXQ - specific Features * * Per - queue - type features use bits 16 and higher . * * @ IONIC_TXQ_F_HWSTAMP : Queue supports Hardware Timestamping enum ionic_txq_feature {16 ),/** * enum ionic_hwstamp_bits - Hardware timestamp decoding bits * @ IONIC_HWSTAMP_INVALID : Invalid hardware timestamp value * @ IONIC_HWSTAMP_CQ_NEGOFFSET : Timestamp field negative offset * from the base cq descriptor . enum ionic_hwstamp_bits {0 ull,8 ,/** * struct ionic_lif_logical_qtype - Descriptor of logical to HW queue type * @ qtype : Hardware Queue Type * @ rsvd : reserved byte ( s ) * @ qid_count : Number of Queue IDs of the logical type * @ qid_base : Minimum Queue ID of the logical type struct ionic_lif_logical_qtype {3 ];/** * enum ionic_lif_state - LIF state * @ IONIC_LIF_DISABLE : LIF disabled * @ IONIC_LIF_ENABLE : LIF enabled * @ IONIC_LIF_QUIESCE : LIF Quiesced enum ionic_lif_state {0 ,1 ,2 ,/** * union ionic_lif_config - LIF configuration * @ state : LIF state ( enum ionic_lif_state ) * @ rsvd : reserved byte ( s ) * @ name : LIF name * @ mtu : MTU * @ mac : Station MAC address * @ vlan : Default Vlan ID * @ features : Features ( enum ionic_eth_hw_features ) * @ queue_count : Queue counts per queue - type * @ words : word access to struct contents union ionic_lif_config {struct {3 ];char name[IONIC_IFNAMSIZ];6 ];64 ];/** * struct ionic_lif_identity - LIF identity information ( type - specific ) * * @ capabilities : LIF capabilities * * @ eth : Ethernet identify structure * @ eth . version : Ethernet identify structure version * @ eth . rsvd : reserved byte ( s ) * @ eth . max_ucast_filters : Number of perfect unicast addresses supported * @ eth . max_mcast_filters : Number of perfect multicast addresses supported * @ eth . min_frame_size : Minimum size of frames to be sent * @ eth . max_frame_size : Maximum size of frames to be sent * @ eth . rsvd2 : reserved byte ( s ) * @ eth . hwstamp_tx_modes : Bitmask of BIT_ULL ( enum ionic_txstamp_mode ) * @ eth . hwstamp_rx_filters : Bitmask of enum ionic_pkt_class * @ eth . rsvd3 : reserved byte ( s ) * @ eth . config : LIF config struct with features , mtu , mac , q counts * * @ rdma : RDMA identify structure * @ rdma . version : RDMA version of opcodes and queue descriptors * @ rdma . qp_opcodes : Number of RDMA queue pair opcodes supported * @ rdma . admin_opcodes : Number of RDMA admin opcodes supported * @ rdma . rsvd : reserved byte ( s ) * @ rdma . npts_per_lif : Page table size per LIF * @ rdma . nmrs_per_lif : Number of memory regions per LIF * @ rdma . nahs_per_lif : Number of address handles per LIF * @ rdma . max_stride : Max work request stride * @ rdma . cl_stride : Cache line stride * @ rdma . pte_stride : Page table entry stride * @ rdma . rrq_stride : Remote RQ work request stride * @ rdma . rsq_stride : Remote SQ work request stride * @ rdma . dcqcn_profiles : Number of DCQCN profiles * @ rdma . rsvd_dimensions : reserved byte ( s ) * @ rdma . aq_qtype : RDMA Admin Qtype * @ rdma . sq_qtype : RDMA Send Qtype * @ rdma . rq_qtype : RDMA Receive Qtype * @ rdma . cq_qtype : RDMA Completion Qtype * @ rdma . eq_qtype : RDMA Event Qtype * @ words : word access to struct contents union ionic_lif_identity {struct {struct {3 ];2 ];88 ];union ionic_lif_config config;struct {10 ];struct ionic_lif_logical_qtype aq_qtype;struct ionic_lif_logical_qtype sq_qtype;struct ionic_lif_logical_qtype rq_qtype;struct ionic_lif_logical_qtype cq_qtype;struct ionic_lif_logical_qtype eq_qtype;478 ];/** * struct ionic_lif_init_cmd - LIF init command * @ opcode : Opcode * @ type : LIF type ( enum ionic_lif_type ) * @ index : LIF index * @ rsvd : reserved byte ( s ) * @ info_pa : Destination address for LIF info ( struct ionic_lif_info ) * @ rsvd2 : reserved byte ( s ) struct ionic_lif_init_cmd {48 ];/** * struct ionic_lif_init_comp - LIF init command completion * @ status : Status of the command ( enum ionic_status_code ) * @ rsvd : reserved byte ( s ) * @ hw_index : Hardware index of the initialized LIF * @ rsvd2 : reserved byte ( s ) struct ionic_lif_init_comp {12 ];/** * struct ionic_q_identify_cmd - queue identify command * @ opcode : opcode * @ rsvd : reserved byte ( s ) * @ lif_type : LIF type ( enum ionic_lif_type ) * @ type : Logical queue type ( enum ionic_logical_qtype ) * @ ver : Highest queue type version that the driver supports * @ rsvd2 : reserved byte ( s ) struct ionic_q_identify_cmd {58 ];/** * struct ionic_q_identify_comp - queue identify command completion * @ status : Status of the command ( enum ionic_status_code ) * @ rsvd : reserved byte ( s ) * @ comp_index : Index in the descriptor ring for which this is the completion * @ ver : Queue type version that can be used with FW * @ rsvd2 : reserved byte ( s ) struct ionic_q_identify_comp {11 ];/** * union ionic_q_identity - queue identity information * @ version : Queue type version that can be used with FW * @ supported : Bitfield of queue versions , first bit = ver 0 * @ rsvd : reserved byte ( s ) * @ features : Queue features ( enum ionic_q_feature , etc ) * @ desc_sz : Descriptor size * @ comp_sz : Completion descriptor size * @ sg_desc_sz : Scatter / Gather descriptor size * @ max_sg_elems : Maximum number of Scatter / Gather elements * @ sg_desc_stride : Number of Scatter / Gather elements per descriptor * @ words : word access to struct contents union ionic_q_identity {struct {6 ];478 ];/** * struct ionic_q_init_cmd - Queue init command * @ opcode : opcode * @ rsvd : reserved byte ( s ) * @ type : Logical queue type * @ ver : Queue type version * @ rsvd1 : reserved byte ( s ) * @ lif_index : LIF index * @ index : ( LIF , qtype ) relative admin queue index * @ intr_index : Interrupt control register index , or Event queue index * @ pid : Process ID * @ flags : * IRQ : Interrupt requested on completion * ENA : Enable the queue . If ENA = 0 the queue is initialized * but remains disabled , to be later enabled with the * Queue Enable command . If ENA = 1 , then queue is * initialized and then enabled . * SG : Enable Scatter - Gather on the queue . * in number of descs . The actual ring size is * ( 1 < < ring_size ) . For example , to * select a ring size of 64 descriptors write * ring_size = 6 . The minimum ring_size value is 2 * for a ring size of 4 descriptors . The maximum * ring_size value is 16 for a ring size of 64 k * descriptors . Values of ring_size < 2 and > 16 are * reserved . * EQ : Enable the Event Queue * @ cos : Class of service for this queue * @ ring_size : Queue ring size , encoded as a log2 ( size ) * @ ring_base : Queue ring base address * @ cq_ring_base : Completion queue ring base address * @ sg_ring_base : Scatter / Gather ring base address * @ rsvd2 : reserved byte ( s ) * @ features : Mask of queue features to enable , if not in the flags above . struct ionic_q_init_cmd {2 ];#define IONIC_QINIT_F_IRQ 0 x01 /* Request interrupt on completion */ #define IONIC_QINIT_F_ENA 0 x02 /* Enable the queue */ #define IONIC_QINIT_F_SG 0 x04 /* Enable scatter/gather on the queue */ #define IONIC_QINIT_F_EQ 0 x08 /* Enable event queue */ #define IONIC_QINIT_F_CMB 0 x10 /* Enable cmb-based queue */ #define IONIC_QINIT_F_DEBUG 0 x80 /* Enable queue debugging */ 12 ];/** * struct ionic_q_init_comp - Queue init command completion * @ status : Status of the command ( enum ionic_status_code ) * @ rsvd : reserved byte ( s ) * @ comp_index : Index in the descriptor ring for which this is the completion * @ hw_index : Hardware Queue ID * @ hw_type : Hardware Queue type * @ rsvd2 : reserved byte ( s ) * @ color : Color struct ionic_q_init_comp {6 ];/* the device's internal addressing uses up to 52 bits */ #define IONIC_ADDR_LEN 52 #define IONIC_ADDR_MASK (BIT_ULL(IONIC_ADDR_LEN) - 1 )enum ionic_txq_desc_opcode {0 ,1 ,2 ,3 ,/** * struct ionic_txq_desc - Ethernet Tx queue descriptor format * @ cmd : Tx operation , see IONIC_TXQ_DESC_OPCODE_ * : * * IONIC_TXQ_DESC_OPCODE_CSUM_NONE : * Non - offload send . No segmentation , * fragmentation or checksum calc / insertion is * performed by device ; packet is prepared * to send by software stack and requires * no further manipulation from device . * * IONIC_TXQ_DESC_OPCODE_CSUM_PARTIAL : * Offload 16 - bit L4 checksum * calculation / insertion . The device will * calculate the L4 checksum value and * insert the result in the packet ' s L4 * header checksum field . The L4 checksum * is calculated starting at @ csum_start bytes * into the packet to the end of the packet . * The checksum insertion position is given * in @ csum_offset , which is the offset from * @ csum_start to the checksum field in the L4 * header . This feature is only applicable to * protocols such as TCP , UDP and ICMP where a * standard ( i . e . the ' IP - style ' checksum ) * one ' s complement 16 - bit checksum is used , * using an IP pseudo - header to seed the * calculation . Software will preload the L4 * checksum field with the IP pseudo - header * checksum . * * For tunnel encapsulation , @ csum_start and * @ csum_offset refer to the inner L4 * header . Supported tunnels encapsulations * are : IPIP , GRE , and UDP . If the @ encap * is clear , no further processing by the * device is required ; software will * calculate the outer header checksums . If * the @ encap is set , the device will * offload the outer header checksums using * LCO ( local checksum offload ) ( see * Documentation / networking / checksum - offloads . rst * for more info ) . * * IONIC_TXQ_DESC_OPCODE_CSUM_HW : * Offload 16 - bit checksum computation to hardware . * If @ csum_l3 is set then the packet ' s L3 checksum is * updated . Similarly , if @ csum_l4 is set the L4 * checksum is updated . If @ encap is set then encap header * checksums are also updated . * * IONIC_TXQ_DESC_OPCODE_TSO : * Device performs TCP segmentation offload * ( TSO ) . @ hdr_len is the number of bytes * to the end of TCP header ( the offset to * the TCP payload ) . @ mss is the desired * MSS , the TCP payload length for each * segment . The device will calculate / * insert IP ( IPv4 only ) and TCP checksums * for each segment . In the first data * buffer containing the header template , * the driver will set IPv4 checksum to 0 * and preload TCP checksum with the IP * pseudo header calculated with IP length = 0 . * * Supported tunnel encapsulations are IPIP , * layer - 3 GRE , and UDP . @ hdr_len includes * both outer and inner headers . The driver * will set IPv4 checksum to zero and * preload TCP checksum with IP pseudo * header on the inner header . * * TCP ECN offload is supported . The device * will set CWR flag in the first segment if * CWR is set in the template header , and * clear CWR in remaining segments . * flags : * vlan : * Insert an L2 VLAN header using @ vlan_tci * encap : * Calculate encap header checksum * csum_l3 : * Compute L3 header checksum * csum_l4 : * Compute L4 header checksum * tso_sot : * TSO start * tso_eot : * TSO end * num_sg_elems : Number of scatter - gather elements in SG * descriptor * addr : First data buffer ' s DMA address * ( Subsequent data buffers are on txq_sg_desc ) * @ len : First data buffer ' s length , in bytes * @ vlan_tci : VLAN tag to insert in the packet ( if requested * by @ V - bit ) . Includes . 1 p and . 1 q tags * @ hword0 : half word padding * @ hdr_len : Length of packet headers , including * encapsulating outer header , if applicable * Valid for opcodes IONIC_TXQ_DESC_OPCODE_CALC_CSUM and * IONIC_TXQ_DESC_OPCODE_TSO . Should be set to zero for * all other modes . For * IONIC_TXQ_DESC_OPCODE_CALC_CSUM , @ hdr_len is length * of headers up to inner - most L4 header . For * IONIC_TXQ_DESC_OPCODE_TSO , @ hdr_len is up to * inner - most L4 payload , so inclusive of * inner - most L4 header . * @ hword1 : half word padding * @ mss : Desired MSS value for TSO ; only applicable for * IONIC_TXQ_DESC_OPCODE_TSO * @ csum_start : Offset from packet to first byte checked in L4 checksum * @ csum_offset : Offset from csum_start to L4 checksum field * @ hword2 : half word padding struct ionic_txq_desc {#define IONIC_TXQ_DESC_OPCODE_MASK 0 xf#define IONIC_TXQ_DESC_OPCODE_SHIFT 4 #define IONIC_TXQ_DESC_FLAGS_MASK 0 xf#define IONIC_TXQ_DESC_FLAGS_SHIFT 0 #define IONIC_TXQ_DESC_NSGE_MASK 0 xf#define IONIC_TXQ_DESC_NSGE_SHIFT 8 #define IONIC_TXQ_DESC_ADDR_MASK (BIT_ULL(IONIC_ADDR_LEN) - 1 )#define IONIC_TXQ_DESC_ADDR_SHIFT 12 /* common flags */ #define IONIC_TXQ_DESC_FLAG_VLAN 0 x1#define IONIC_TXQ_DESC_FLAG_ENCAP 0 x2/* flags for csum_hw opcode */ #define IONIC_TXQ_DESC_FLAG_CSUM_L3 0 x4#define IONIC_TXQ_DESC_FLAG_CSUM_L4 0 x8/* flags for tso opcode */ #define IONIC_TXQ_DESC_FLAG_TSO_SOT 0 x4#define IONIC_TXQ_DESC_FLAG_TSO_EOT 0 x8union {union {union {static inline u64 encode_txq_desc_cmd(u8 opcode, u8 flags,return cmd;static inline void decode_txq_desc_cmd(u64 cmd, u8 *opcode, u8 *flags,/** * struct ionic_txq_sg_elem - Transmit scatter - gather ( SG ) descriptor element * @ addr : DMA address of SG element data buffer * @ len : Length of SG element data buffer , in bytes * @ rsvd : reserved byte ( s ) struct ionic_txq_sg_elem {3 ];/** * struct ionic_txq_sg_desc - Transmit scatter - gather ( SG ) list * @ elems : Scatter - gather elements struct ionic_txq_sg_desc {#define IONIC_TX_MAX_SG_ELEMS 8 #define IONIC_TX_SG_DESC_STRIDE 8 struct ionic_txq_sg_elem elems[IONIC_TX_MAX_SG_ELEMS];struct ionic_txq_sg_desc_v1 {#define IONIC_TX_MAX_SG_ELEMS_V1 15 #define IONIC_TX_SG_DESC_STRIDE_V1 16 struct ionic_txq_sg_elem elems[IONIC_TX_SG_DESC_STRIDE_V1];/** * struct ionic_txq_comp - Ethernet transmit queue completion descriptor * @ status : Status of the command ( enum ionic_status_code ) * @ rsvd : reserved byte ( s ) * @ comp_index : Index in the descriptor ring for which this is the completion * @ rsvd2 : reserved byte ( s ) * @ color : Color bit struct ionic_txq_comp {11 ];enum ionic_rxq_desc_opcode {0 ,1 ,/** * struct ionic_rxq_desc - Ethernet Rx queue descriptor format * @ opcode : Rx operation , see IONIC_RXQ_DESC_OPCODE_ * : * * IONIC_RXQ_DESC_OPCODE_SIMPLE : * Receive full packet into data buffer * starting at @ addr . Results of * receive , including actual bytes received , * are recorded in Rx completion descriptor . * * @ rsvd : reserved byte ( s ) * @ len : Data buffer ' s length , in bytes * @ addr : Data buffer ' s DMA address struct ionic_rxq_desc {5 ];/** * struct ionic_rxq_sg_elem - Receive scatter - gather ( SG ) descriptor element * @ addr : DMA address of SG element data buffer * @ len : Length of SG element data buffer , in bytes * @ rsvd : reserved byte ( s ) struct ionic_rxq_sg_elem {3 ];/** * struct ionic_rxq_sg_desc - Receive scatter - gather ( SG ) list * @ elems : Scatter - gather elements struct ionic_rxq_sg_desc {#define IONIC_RX_MAX_SG_ELEMS 8 #define IONIC_RX_SG_DESC_STRIDE 8 struct ionic_rxq_sg_elem elems[IONIC_RX_SG_DESC_STRIDE];/** * struct ionic_rxq_comp - Ethernet receive queue completion descriptor * @ status : Status of the command ( enum ionic_status_code ) * @ num_sg_elems : Number of SG elements used by this descriptor * @ comp_index : Index in the descriptor ring for which this is the completion * @ rss_hash : 32 - bit RSS hash * @ csum : 16 - bit sum of the packet ' s L2 payload * If the packet ' s L2 payload is odd length , an extra * zero - value byte is included in the @ csum calculation but * not included in @ len . * @ vlan_tci : VLAN tag stripped from the packet . Valid if @ VLAN is * set . Includes . 1 p and . 1 q tags . * @ len : Received packet length , in bytes . Excludes FCS . * @ csum_calc L2 payload checksum is computed or not * @ csum_flags : See IONIC_RXQ_COMP_CSUM_F_ * : * * IONIC_RXQ_COMP_CSUM_F_TCP_OK : * The TCP checksum calculated by the device * matched the checksum in the receive packet ' s * TCP header . * * IONIC_RXQ_COMP_CSUM_F_TCP_BAD : * The TCP checksum calculated by the device did * not match the checksum in the receive packet ' s * TCP header . * * IONIC_RXQ_COMP_CSUM_F_UDP_OK : * The UDP checksum calculated by the device * matched the checksum in the receive packet ' s * UDP header * * IONIC_RXQ_COMP_CSUM_F_UDP_BAD : * The UDP checksum calculated by the device did * not match the checksum in the receive packet ' s * UDP header . * * IONIC_RXQ_COMP_CSUM_F_IP_OK : * The IPv4 checksum calculated by the device * matched the checksum in the receive packet ' s * first IPv4 header . If the receive packet * contains both a tunnel IPv4 header and a * transport IPv4 header , the device validates the * checksum for both IPv4 headers . * * IONIC_RXQ_COMP_CSUM_F_IP_BAD : * The IPv4 checksum calculated by the device did * not match the checksum in the receive packet ' s * first IPv4 header . If the receive packet * contains both a tunnel IPv4 header and a * transport IPv4 header , the device validates the * checksum for both IP headers . * * IONIC_RXQ_COMP_CSUM_F_VLAN : * The VLAN header was stripped and placed in @ vlan_tci . * * IONIC_RXQ_COMP_CSUM_F_CALC : * The checksum was calculated by the device . * * @ pkt_type_color : Packet type and color bit ; see IONIC_RXQ_COMP_PKT_TYPE_MASK struct ionic_rxq_comp {#define IONIC_RXQ_COMP_CSUM_F_TCP_OK 0 x01#define IONIC_RXQ_COMP_CSUM_F_TCP_BAD 0 x02#define IONIC_RXQ_COMP_CSUM_F_UDP_OK 0 x04#define IONIC_RXQ_COMP_CSUM_F_UDP_BAD 0 x08#define IONIC_RXQ_COMP_CSUM_F_IP_OK 0 x10#define IONIC_RXQ_COMP_CSUM_F_IP_BAD 0 x20#define IONIC_RXQ_COMP_CSUM_F_VLAN 0 x40#define IONIC_RXQ_COMP_CSUM_F_CALC 0 x80#define IONIC_RXQ_COMP_PKT_TYPE_MASK 0 x7fenum ionic_pkt_type {0 x00,0 x01,0 x03,0 x05,0 x08,0 x18,0 x28,/* below types are only used if encap offloads are enabled on lif */ 0 x40,0 x41,0 x43,0 x45,0 x48,0 x58,0 x68,enum ionic_eth_hw_features {0 ),1 ),2 ),3 ),4 ),5 ),6 ),7 ),8 ),9 ),10 ),11 ),12 ),13 ),14 ),15 ),16 ),17 ),18 ),19 ),20 ),/** * enum ionic_pkt_class - Packet classification mask . * * Used with rx steering filter , packets indicated by the mask can be steered * toward a specific receive queue . * * @ IONIC_PKT_CLS_NTP_ALL : All NTP packets . * @ IONIC_PKT_CLS_PTP1_SYNC : PTPv1 sync * @ IONIC_PKT_CLS_PTP1_DREQ : PTPv1 delay - request * @ IONIC_PKT_CLS_PTP1_ALL : PTPv1 all packets * @ IONIC_PKT_CLS_PTP2_L4_SYNC : PTPv2 - UDP sync * @ IONIC_PKT_CLS_PTP2_L4_DREQ : PTPv2 - UDP delay - request * @ IONIC_PKT_CLS_PTP2_L4_ALL : PTPv2 - UDP all packets * @ IONIC_PKT_CLS_PTP2_L2_SYNC : PTPv2 - ETH sync * @ IONIC_PKT_CLS_PTP2_L2_DREQ : PTPv2 - ETH delay - request * @ IONIC_PKT_CLS_PTP2_L2_ALL : PTPv2 - ETH all packets * @ IONIC_PKT_CLS_PTP2_SYNC : PTPv2 sync * @ IONIC_PKT_CLS_PTP2_DREQ : PTPv2 delay - request * @ IONIC_PKT_CLS_PTP2_ALL : PTPv2 all packets * @ IONIC_PKT_CLS_PTP_SYNC : PTP sync * @ IONIC_PKT_CLS_PTP_DREQ : PTP delay - request * @ IONIC_PKT_CLS_PTP_ALL : PTP all packets enum ionic_pkt_class {0 ),1 ),2 ),3 ) |4 ),5 ),6 ) |7 ),8 ),9 ) |/** * struct ionic_q_control_cmd - Queue control command * @ opcode : opcode * @ type : Queue type * @ lif_index : LIF index * @ index : Queue index * @ oper : Operation ( enum ionic_q_control_oper ) * @ rsvd : reserved byte ( s ) struct ionic_q_control_cmd {55 ];typedef struct ionic_admin_comp ionic_q_control_comp;enum ionic_q_control_oper {0 ,1 ,2 ,/** * enum ionic_phy_type - Physical connection type * @ IONIC_PHY_TYPE_NONE : No PHY installed * @ IONIC_PHY_TYPE_COPPER : Copper PHY * @ IONIC_PHY_TYPE_FIBER : Fiber PHY enum ionic_phy_type {0 ,1 ,2 ,/** * enum ionic_xcvr_state - Transceiver status * @ IONIC_XCVR_STATE_REMOVED : Transceiver removed * @ IONIC_XCVR_STATE_INSERTED : Transceiver inserted * @ IONIC_XCVR_STATE_PENDING : Transceiver pending * @ IONIC_XCVR_STATE_SPROM_READ : Transceiver data read * @ IONIC_XCVR_STATE_SPROM_READ_ERR : Transceiver data read error enum ionic_xcvr_state {0 ,1 ,2 ,3 ,4 ,/* * enum ionic_xcvr_pid - Supported link modes enum ionic_xcvr_pid {0 ,/* CU */ 1 ,2 ,3 ,4 ,5 ,6 ,7 ,8 ,9 ,/* Fiber */ 50 ,51 ,52 ,53 ,54 ,55 ,56 ,57 ,58 ,59 ,60 ,61 ,62 ,63 ,64 ,65 ,66 ,67 ,68 ,69 ,70 ,71 ,72 ,73 ,74 ,75 ,76 ,77 ,78 ,79 ,80 ,81 ,82 ,/** * enum ionic_port_type - Port types * @ IONIC_PORT_TYPE_NONE : Port type not configured * @ IONIC_PORT_TYPE_ETH : Port carries ethernet traffic ( inband ) * @ IONIC_PORT_TYPE_MGMT : Port carries mgmt traffic ( out - of - band ) enum ionic_port_type {0 ,1 ,2 ,/** * enum ionic_port_admin_state - Port config state * @ IONIC_PORT_ADMIN_STATE_NONE : Port admin state not configured * @ IONIC_PORT_ADMIN_STATE_DOWN : Port admin disabled * @ IONIC_PORT_ADMIN_STATE_UP : Port admin enabled enum ionic_port_admin_state {0 ,1 ,2 ,/** * enum ionic_port_oper_status - Port operational status * @ IONIC_PORT_OPER_STATUS_NONE : Port disabled * @ IONIC_PORT_OPER_STATUS_UP : Port link status up * @ IONIC_PORT_OPER_STATUS_DOWN : Port link status down enum ionic_port_oper_status {0 ,1 ,2 ,/** * enum ionic_port_fec_type - Ethernet Forward error correction ( FEC ) modes * @ IONIC_PORT_FEC_TYPE_NONE : FEC Disabled * @ IONIC_PORT_FEC_TYPE_FC : FireCode FEC * @ IONIC_PORT_FEC_TYPE_RS : ReedSolomon FEC enum ionic_port_fec_type {0 ,1 ,2 ,/** * enum ionic_port_pause_type - Ethernet pause ( flow control ) modes * @ IONIC_PORT_PAUSE_TYPE_NONE : Disable Pause * @ IONIC_PORT_PAUSE_TYPE_LINK : Link level pause * @ IONIC_PORT_PAUSE_TYPE_PFC : Priority - Flow Control enum ionic_port_pause_type {0 ,1 ,2 ,/** * enum ionic_port_loopback_mode - Loopback modes * @ IONIC_PORT_LOOPBACK_MODE_NONE : Disable loopback * @ IONIC_PORT_LOOPBACK_MODE_MAC : MAC loopback * @ IONIC_PORT_LOOPBACK_MODE_PHY : PHY / SerDes loopback enum ionic_port_loopback_mode {0 ,1 ,2 ,/** * struct ionic_xcvr_status - Transceiver Status information * @ state : Transceiver status ( enum ionic_xcvr_state ) * @ phy : Physical connection type ( enum ionic_phy_type ) * @ pid : Transceiver link mode ( enum ionic_xcvr_pid ) * @ sprom : Transceiver sprom contents struct ionic_xcvr_status {256 ];/** * union ionic_port_config - Port configuration * @ speed : port speed ( in Mbps ) * @ mtu : mtu * @ state : port admin state ( enum ionic_port_admin_state ) * @ an_enable : autoneg enable * @ fec_type : fec type ( enum ionic_port_fec_type ) * @ pause_type : pause type ( enum ionic_port_pause_type ) * @ loopback_mode : loopback mode ( enum ionic_port_loopback_mode ) * @ words : word access to struct contents union ionic_port_config {struct {#define IONIC_SPEED_400G 400000 /* 400G in Mbps */ #define IONIC_SPEED_200G 200000 /* 200G in Mbps */ #define IONIC_SPEED_100G 100000 /* 100G in Mbps */ #define IONIC_SPEED_50G 50000 /* 50G in Mbps */ #define IONIC_SPEED_40G 40000 /* 40G in Mbps */ #define IONIC_SPEED_25G 25000 /* 25G in Mbps */ #define IONIC_SPEED_10G 10000 /* 10G in Mbps */ #define IONIC_SPEED_1G 1000 /* 1G in Mbps */ #define IONIC_PAUSE_TYPE_MASK 0 x0f#define IONIC_PAUSE_FLAGS_MASK 0 xf0#define IONIC_PAUSE_F_TX 0 x10#define IONIC_PAUSE_F_RX 0 x2064 ];/** * struct ionic_port_status - Port Status information * @ status : link status ( enum ionic_port_oper_status ) * @ id : port id * @ speed : link speed ( in Mbps ) * @ link_down_count : number of times link went from up to down * @ fec_type : fec type ( enum ionic_port_fec_type ) * @ rsvd : reserved byte ( s ) * @ xcvr : transceiver status struct ionic_port_status {48 ];struct ionic_xcvr_status xcvr;/** * struct ionic_port_identify_cmd - Port identify command * @ opcode : opcode * @ index : port index * @ ver : Highest version of identify supported by driver * @ rsvd : reserved byte ( s ) struct ionic_port_identify_cmd {61 ];/** * struct ionic_port_identify_comp - Port identify command completion * @ status : Status of the command ( enum ionic_status_code ) * @ ver : Version of identify returned by device * @ rsvd : reserved byte ( s ) struct ionic_port_identify_comp {14 ];/** * struct ionic_port_init_cmd - Port initialization command * @ opcode : opcode * @ index : port index * @ rsvd : reserved byte ( s ) * @ info_pa : destination address for port info ( struct ionic_port_info ) * @ rsvd2 : reserved byte ( s ) struct ionic_port_init_cmd {6 ];48 ];/** * struct ionic_port_init_comp - Port initialization command completion * @ status : Status of the command ( enum ionic_status_code ) * @ rsvd : reserved byte ( s ) struct ionic_port_init_comp {15 ];/** * struct ionic_port_reset_cmd - Port reset command * @ opcode : opcode * @ index : port index * @ rsvd : reserved byte ( s ) struct ionic_port_reset_cmd {62 ];/** * struct ionic_port_reset_comp - Port reset command completion * @ status : Status of the command ( enum ionic_status_code ) * @ rsvd : reserved byte ( s ) struct ionic_port_reset_comp {15 ];/** * enum ionic_stats_ctl_cmd - List of commands for stats control * @ IONIC_STATS_CTL_RESET : Reset statistics enum ionic_stats_ctl_cmd {0 ,/** * enum ionic_txstamp_mode - List of TX Timestamping Modes * @ IONIC_TXSTAMP_OFF : Disable TX hardware timetamping . * @ IONIC_TXSTAMP_ON : Enable local TX hardware timetamping . * @ IONIC_TXSTAMP_ONESTEP_SYNC : Modify TX PTP Sync packets . * @ IONIC_TXSTAMP_ONESTEP_P2P : Modify TX PTP Sync and PDelayResp . enum ionic_txstamp_mode {0 ,1 ,2 ,3 ,/** * enum ionic_port_attr - List of device attributes * @ IONIC_PORT_ATTR_STATE : Port state attribute * @ IONIC_PORT_ATTR_SPEED : Port speed attribute * @ IONIC_PORT_ATTR_MTU : Port MTU attribute * @ IONIC_PORT_ATTR_AUTONEG : Port autonegotiation attribute * @ IONIC_PORT_ATTR_FEC : Port FEC attribute * @ IONIC_PORT_ATTR_PAUSE : Port pause attribute * @ IONIC_PORT_ATTR_LOOPBACK : Port loopback attribute * @ IONIC_PORT_ATTR_STATS_CTRL : Port statistics control attribute enum ionic_port_attr {0 ,1 ,2 ,3 ,4 ,5 ,6 ,7 ,/** * struct ionic_port_setattr_cmd - Set port attributes on the NIC * @ opcode : Opcode * @ index : Port index * @ attr : Attribute type ( enum ionic_port_attr ) * @ rsvd : reserved byte ( s ) * @ state : Port state * @ speed : Port speed * @ mtu : Port MTU * @ an_enable : Port autonegotiation setting * @ fec_type : Port FEC type setting * @ pause_type : Port pause type setting * @ loopback_mode : Port loopback mode * @ stats_ctl : Port stats setting * @ rsvd2 : reserved byte ( s ) struct ionic_port_setattr_cmd {union {60 ];/** * struct ionic_port_setattr_comp - Port set attr command completion * @ status : Status of the command ( enum ionic_status_code ) * @ rsvd : reserved byte ( s ) * @ color : Color bit struct ionic_port_setattr_comp {14 ];/** * struct ionic_port_getattr_cmd - Get port attributes from the NIC * @ opcode : Opcode * @ index : port index * @ attr : Attribute type ( enum ionic_port_attr ) * @ rsvd : reserved byte ( s ) struct ionic_port_getattr_cmd {61 ];/** * struct ionic_port_getattr_comp - Port get attr command completion * @ status : Status of the command ( enum ionic_status_code ) * @ rsvd : reserved byte ( s ) * @ state : Port state * @ speed : Port speed * @ mtu : Port MTU * @ an_enable : Port autonegotiation setting * @ fec_type : Port FEC type setting * @ pause_type : Port pause type setting * @ loopback_mode : Port loopback mode * @ rsvd2 : reserved byte ( s ) * @ color : Color bit struct ionic_port_getattr_comp {3 ];union {11 ];/** * struct ionic_lif_status - LIF status register * @ eid : most recent NotifyQ event id * @ port_num : port the LIF is connected to * @ rsvd : reserved byte ( s ) * @ link_status : port status ( enum ionic_port_oper_status ) * @ link_speed : speed of link in Mbps * @ link_down_count : number of times link went from up to down * @ rsvd2 : reserved byte ( s ) struct ionic_lif_status {/* units of 1Mbps: eg 10000 = 10Gbps */ 46 ];/** * struct ionic_lif_reset_cmd - LIF reset command * @ opcode : opcode * @ rsvd : reserved byte ( s ) * @ index : LIF index * @ rsvd2 : reserved byte ( s ) struct ionic_lif_reset_cmd {15 ];typedef struct ionic_admin_comp ionic_lif_reset_comp;enum ionic_dev_state {0 ,1 ,2 ,/** * enum ionic_dev_attr - List of device attributes * @ IONIC_DEV_ATTR_STATE : Device state attribute * @ IONIC_DEV_ATTR_NAME : Device name attribute * @ IONIC_DEV_ATTR_FEATURES : Device feature attributes enum ionic_dev_attr {0 ,1 ,2 ,/** * struct ionic_dev_setattr_cmd - Set Device attributes on the NIC * @ opcode : Opcode * @ attr : Attribute type ( enum ionic_dev_attr ) * @ rsvd : reserved byte ( s ) * @ state : Device state ( enum ionic_dev_state ) * @ name : The bus info , e . g . PCI slot - device - function , 0 terminated * @ features : Device features * @ rsvd2 : reserved byte ( s ) struct ionic_dev_setattr_cmd {union {char name[IONIC_IFNAMSIZ];60 ];/** * struct ionic_dev_setattr_comp - Device set attr command completion * @ status : Status of the command ( enum ionic_status_code ) * @ rsvd : reserved byte ( s ) * @ features : Device features * @ rsvd2 : reserved byte ( s ) * @ color : Color bit struct ionic_dev_setattr_comp {3 ];union {11 ];/** * struct ionic_dev_getattr_cmd - Get Device attributes from the NIC * @ opcode : opcode * @ attr : Attribute type ( enum ionic_dev_attr ) * @ rsvd : reserved byte ( s ) struct ionic_dev_getattr_cmd {62 ];/** * struct ionic_dev_getattr_comp - Device set attr command completion * @ status : Status of the command ( enum ionic_status_code ) * @ rsvd : reserved byte ( s ) * @ features : Device features * @ rsvd2 : reserved byte ( s ) * @ color : Color bit struct ionic_dev_getattr_comp {3 ];union {11 ];/* * RSS parameters #define IONIC_RSS_HASH_KEY_SIZE 40 enum ionic_rss_hash_types {0 ),1 ),2 ),3 ),4 ),5 ),/** * enum ionic_lif_attr - List of LIF attributes * @ IONIC_LIF_ATTR_STATE : LIF state attribute * @ IONIC_LIF_ATTR_NAME : LIF name attribute * @ IONIC_LIF_ATTR_MTU : LIF MTU attribute * @ IONIC_LIF_ATTR_MAC : LIF MAC attribute * @ IONIC_LIF_ATTR_FEATURES : LIF features attribute * @ IONIC_LIF_ATTR_RSS : LIF RSS attribute * @ IONIC_LIF_ATTR_STATS_CTRL : LIF statistics control attribute * @ IONIC_LIF_ATTR_TXSTAMP : LIF TX timestamping mode * @ IONIC_LIF_ATTR_MAX : maximum attribute value enum ionic_lif_attr {0 ,1 ,2 ,3 ,4 ,5 ,6 ,7 ,255 ,/** * struct ionic_lif_setattr_cmd - Set LIF attributes on the NIC * @ opcode : Opcode * @ attr : Attribute type ( enum ionic_lif_attr ) * @ index : LIF index * @ state : LIF state ( enum ionic_lif_state ) * @ name : The netdev name string , 0 terminated * @ mtu : Mtu * @ mac : Station mac * @ features : Features ( enum ionic_eth_hw_features ) * @ rss : RSS properties * @ rss . types : The hash types to enable ( see rss_hash_types ) * @ rss . key : The hash secret key * @ rss . rsvd : reserved byte ( s ) * @ rss . addr : Address for the indirection table shared memory * @ stats_ctl : stats control commands ( enum ionic_stats_ctl_cmd ) * @ txstamp_mode : TX Timestamping Mode ( enum ionic_txstamp_mode ) * @ rsvd : reserved byte ( s ) struct ionic_lif_setattr_cmd {union {char name[IONIC_IFNAMSIZ];6 ];struct {6 ];60 ];/** * struct ionic_lif_setattr_comp - LIF set attr command completion * @ status : Status of the command ( enum ionic_status_code ) * @ rsvd : reserved byte ( s ) * @ comp_index : Index in the descriptor ring for which this is the completion * @ features : features ( enum ionic_eth_hw_features ) * @ rsvd2 : reserved byte ( s ) * @ color : Color bit struct ionic_lif_setattr_comp {union {11 ];/** * struct ionic_lif_getattr_cmd - Get LIF attributes from the NIC * @ opcode : Opcode * @ attr : Attribute type ( enum ionic_lif_attr ) * @ index : LIF index * @ rsvd : reserved byte ( s ) struct ionic_lif_getattr_cmd {60 ];/** * struct ionic_lif_getattr_comp - LIF get attr command completion * @ status : Status of the command ( enum ionic_status_code ) * @ rsvd : reserved byte ( s ) * @ comp_index : Index in the descriptor ring for which this is the completion * @ state : LIF state ( enum ionic_lif_state ) * @ mtu : Mtu * @ mac : Station mac * @ features : Features ( enum ionic_eth_hw_features ) * @ txstamp_mode : TX Timestamping Mode ( enum ionic_txstamp_mode ) * @ rsvd2 : reserved byte ( s ) * @ color : Color bit struct ionic_lif_getattr_comp {union {6 ];11 ];/** * struct ionic_lif_setphc_cmd - Set LIF PTP Hardware Clock * @ opcode : Opcode * @ rsvd1 : reserved byte ( s ) * @ lif_index : LIF index * @ rsvd2 : reserved byte ( s ) * @ tick : Hardware stamp tick of an instant in time . * @ nsec : Nanosecond stamp of the same instant . * @ frac : Fractional nanoseconds at the same instant . * @ mult : Cycle to nanosecond multiplier . * @ shift : Cycle to nanosecond divisor ( power of two ) . * @ rsvd3 : reserved byte ( s ) struct ionic_lif_setphc_cmd {4 ];24 ];enum ionic_rx_mode {0 ),1 ),2 ),3 ),4 ),5 ),/** * struct ionic_rx_mode_set_cmd - Set LIF ' s Rx mode command * @ opcode : opcode * @ rsvd : reserved byte ( s ) * @ lif_index : LIF index * @ rx_mode : Rx mode flags : * IONIC_RX_MODE_F_UNICAST : Accept known unicast packets * IONIC_RX_MODE_F_MULTICAST : Accept known multicast packets * IONIC_RX_MODE_F_BROADCAST : Accept broadcast packets * IONIC_RX_MODE_F_PROMISC : Accept any packets * IONIC_RX_MODE_F_ALLMULTI : Accept any multicast packets * IONIC_RX_MODE_F_RDMA_SNIFFER : Sniff RDMA packets * @ rsvd2 : reserved byte ( s ) struct ionic_rx_mode_set_cmd {29 ];typedef struct ionic_admin_comp ionic_rx_mode_set_comp;enum ionic_rx_filter_match_type {0 x0,0 x1,0 x2,0 x10,/** * struct ionic_rx_filter_add_cmd - Add LIF Rx filter command * @ opcode : opcode * @ qtype : Queue type * @ lif_index : LIF index * @ qid : Queue ID * @ match : Rx filter match type ( see IONIC_RX_FILTER_MATCH_xxx ) * @ vlan : VLAN filter * @ vlan . vlan : VLAN ID * @ mac : MAC filter * @ mac . addr : MAC address ( network - byte order ) * @ mac_vlan : MACVLAN filter * @ mac_vlan . vlan : VLAN ID * @ mac_vlan . addr : MAC address ( network - byte order ) * @ pkt_class : Packet classification filter * @ rsvd : reserved byte ( s ) struct ionic_rx_filter_add_cmd {union {struct {struct {6 ];struct {6 ];54 ];/** * struct ionic_rx_filter_add_comp - Add LIF Rx filter command completion * @ status : Status of the command ( enum ionic_status_code ) * @ rsvd : reserved byte ( s ) * @ comp_index : Index in the descriptor ring for which this is the completion * @ filter_id : Filter ID * @ rsvd2 : reserved byte ( s ) * @ color : Color bit struct ionic_rx_filter_add_comp {7 ];/** * struct ionic_rx_filter_del_cmd - Delete LIF Rx filter command * @ opcode : opcode * @ rsvd : reserved byte ( s ) * @ lif_index : LIF index * @ filter_id : Filter ID * @ rsvd2 : reserved byte ( s ) struct ionic_rx_filter_del_cmd {56 ];typedef struct ionic_admin_comp ionic_rx_filter_del_comp;enum ionic_vf_attr {1 ,2 ,3 ,4 ,5 ,6 ,7 ,/** * enum ionic_vf_link_status - Virtual Function link status * @ IONIC_VF_LINK_STATUS_AUTO : Use link state of the uplink * @ IONIC_VF_LINK_STATUS_UP : Link always up * @ IONIC_VF_LINK_STATUS_DOWN : Link always down enum ionic_vf_link_status {0 ,1 ,2 ,/** * struct ionic_vf_setattr_cmd - Set VF attributes on the NIC * @ opcode : Opcode * @ attr : Attribute type ( enum ionic_vf_attr ) * @ vf_index : VF index * @ macaddr : mac address * @ vlanid : vlan ID * @ maxrate : max Tx rate in Mbps * @ spoofchk : enable address spoof checking * @ trust : enable VF trust * @ linkstate : set link up or down * @ stats_pa : set DMA address for VF stats * @ pad : reserved byte ( s ) struct ionic_vf_setattr_cmd {union {6 ];60 ];struct ionic_vf_setattr_comp {9 ];/** * struct ionic_vf_getattr_cmd - Get VF attributes from the NIC * @ opcode : Opcode * @ attr : Attribute type ( enum ionic_vf_attr ) * @ vf_index : VF index * @ rsvd : reserved byte ( s ) struct ionic_vf_getattr_cmd {60 ];struct ionic_vf_getattr_comp {union {6 ];11 ];enum ionic_vf_ctrl_opcode {0 ,1 ,/** * struct ionic_vf_ctrl_cmd - VF control command * @ opcode : Opcode for the command * @ ctrl_opcode : VF control operation type * @ vf_index : VF Index . It is unused if op START_ALL is used . struct ionic_vf_ctrl_cmd {/* private: */ 60 ];/** * struct ionic_vf_ctrl_comp - VF_CTRL command completion . * @ status : Status of the command ( enum ionic_status_code ) struct ionic_vf_ctrl_comp {/* private: */ 15 ];/** * struct ionic_qos_identify_cmd - QoS identify command * @ opcode : opcode * @ ver : Highest version of identify supported by driver * @ rsvd : reserved byte ( s ) struct ionic_qos_identify_cmd {62 ];/** * struct ionic_qos_identify_comp - QoS identify command completion * @ status : Status of the command ( enum ionic_status_code ) * @ ver : Version of identify returned by device * @ rsvd : reserved byte ( s ) struct ionic_qos_identify_comp {14 ];#define IONIC_QOS_TC_MAX 8 #define IONIC_QOS_ALL_TC 0 xFF/* Capri max supported, should be renamed. */ #define IONIC_QOS_CLASS_MAX 7 #define IONIC_QOS_PCP_MAX 8 #define IONIC_QOS_CLASS_NAME_SZ 32 #define IONIC_QOS_DSCP_MAX 64 #define IONIC_QOS_ALL_PCP 0 xFF#define IONIC_DSCP_BLOCK_SIZE 8 /* * enum ionic_qos_class enum ionic_qos_class {0 ,1 ,2 ,3 ,4 ,5 ,6 ,/** * enum ionic_qos_class_type - Traffic classification criteria * @ IONIC_QOS_CLASS_TYPE_NONE : No QoS * @ IONIC_QOS_CLASS_TYPE_PCP : Dot1Q PCP * @ IONIC_QOS_CLASS_TYPE_DSCP : IP DSCP enum ionic_qos_class_type {0 ,1 ,2 ,/** * enum ionic_qos_sched_type - QoS class scheduling type * @ IONIC_QOS_SCHED_TYPE_STRICT : Strict priority * @ IONIC_QOS_SCHED_TYPE_DWRR : Deficit weighted round - robin enum ionic_qos_sched_type {0 ,1 ,/** * union ionic_qos_config - QoS configuration structure * @ flags : Configuration flags * IONIC_QOS_CONFIG_F_ENABLE enable * IONIC_QOS_CONFIG_F_NO_DROP drop / nodrop * IONIC_QOS_CONFIG_F_RW_DOT1Q_PCP enable dot1q pcp rewrite * IONIC_QOS_CONFIG_F_RW_IP_DSCP enable ip dscp rewrite * IONIC_QOS_CONFIG_F_NON_DISRUPTIVE Non - disruptive TC update * @ sched_type : QoS class scheduling type ( enum ionic_qos_sched_type ) * @ class_type : QoS class type ( enum ionic_qos_class_type ) * @ pause_type : QoS pause type ( enum ionic_qos_pause_type ) * @ name : QoS class name * @ mtu : MTU of the class * @ pfc_cos : Priority - Flow Control class of service * @ dwrr_weight : QoS class scheduling weight * @ strict_rlmt : Rate limit for strict priority scheduling * @ rw_dot1q_pcp : Rewrite dot1q pcp to value ( valid iff F_RW_DOT1Q_PCP ) * @ rw_ip_dscp : Rewrite ip dscp to value ( valid iff F_RW_IP_DSCP ) * @ dot1q_pcp : Dot1q pcp value * @ ndscp : Number of valid dscp values in the ip_dscp field * @ ip_dscp : IP dscp values * @ words : word access to struct contents union ionic_qos_config {struct {#define IONIC_QOS_CONFIG_F_ENABLE BIT(0 )#define IONIC_QOS_CONFIG_F_NO_DROP BIT(1 )/* Used to rewrite PCP or DSCP value. */ #define IONIC_QOS_CONFIG_F_RW_DOT1Q_PCP BIT(2 )#define IONIC_QOS_CONFIG_F_RW_IP_DSCP BIT(3 )/* Non-disruptive TC update */ #define IONIC_QOS_CONFIG_F_NON_DISRUPTIVE BIT(4 )char name[IONIC_QOS_CLASS_NAME_SZ];/* flow control */ /* scheduler */ union {/* marking */ /* Used to rewrite PCP or DSCP value. */ union {/* classification */ union {struct {64 ];/** * union ionic_qos_identity - QoS identity structure * @ version : Version of the identify structure * @ type : QoS system type * @ rsvd : reserved byte ( s ) * @ config : Current configuration of classes * @ words : word access to struct contents union ionic_qos_identity {struct {62 ];union ionic_qos_config config[IONIC_QOS_CLASS_MAX];478 ];/** * struct ionic_qos_init_cmd - QoS config init command * @ opcode : Opcode * @ group : QoS class id * @ rsvd : reserved byte ( s ) * @ info_pa : destination address for qos info * @ rsvd1 : reserved byte ( s ) struct ionic_qos_init_cmd {6 ];48 ];typedef struct ionic_admin_comp ionic_qos_init_comp;/** * struct ionic_qos_reset_cmd - QoS config reset command * @ opcode : Opcode * @ group : QoS class id * @ rsvd : reserved byte ( s ) struct ionic_qos_reset_cmd {62 ];/** * struct ionic_qos_clear_stats_cmd - Qos config reset command * @ opcode : Opcode * @ group_bitmap : bitmap of groups to be cleared * @ rsvd : reserved byte ( s ) struct ionic_qos_clear_stats_cmd {62 ];typedef struct ionic_admin_comp ionic_qos_reset_comp;/** * struct ionic_fw_download_cmd - Firmware download command * @ opcode : opcode * @ rsvd : reserved byte ( s ) * @ addr : dma address of the firmware buffer * @ offset : offset of the firmware buffer within the full image * @ length : number of valid bytes in the firmware buffer struct ionic_fw_download_cmd {3 ];typedef struct ionic_admin_comp ionic_fw_download_comp;/** * enum ionic_fw_control_oper - FW control operations * @ IONIC_FW_RESET : Reset firmware * @ IONIC_FW_INSTALL : Install firmware * @ IONIC_FW_ACTIVATE : Activate firmware * @ IONIC_FW_INSTALL_ASYNC : Install firmware asynchronously * @ IONIC_FW_INSTALL_STATUS : Firmware installation status * @ IONIC_FW_ACTIVATE_ASYNC : Activate firmware asynchronously * @ IONIC_FW_ACTIVATE_STATUS : Firmware activate status * @ IONIC_FW_UPDATE_CLEANUP : Clean up after an interrupted fw update enum ionic_fw_control_oper {0 ,1 ,2 ,3 ,4 ,5 ,6 ,7 ,/** * struct ionic_fw_control_cmd - Firmware control command * @ opcode : opcode * @ rsvd : reserved byte ( s ) * @ oper : firmware control operation ( enum ionic_fw_control_oper ) * @ slot : slot to activate * @ rsvd1 : reserved byte ( s ) struct ionic_fw_control_cmd {3 ];58 ];/** * struct ionic_fw_control_comp - Firmware control copletion * @ status : Status of the command ( enum ionic_status_code ) * @ rsvd : reserved byte ( s ) * @ comp_index : Index in the descriptor ring for which this is the completion * @ slot : Slot where the firmware was installed * @ rsvd1 : reserved byte ( s ) * @ color : Color bit struct ionic_fw_control_comp {10 ];/****************************************************************** * * * * * * * * * * * * * * * * * * * RDMA Commands * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * /** * struct ionic_rdma_reset_cmd - Reset RDMA LIF cmd * @ opcode : opcode * @ rsvd : reserved byte ( s ) * @ lif_index : LIF index * @ rsvd2 : reserved byte ( s ) * * There is no RDMA specific dev command completion struct . Completion uses * the common struct ionic_admin_comp . Only the status is indicated . * Nonzero status means the LIF does not support RDMA . struct ionic_rdma_reset_cmd {60 ];/** * struct ionic_rdma_queue_cmd - Create RDMA Queue command * @ opcode : opcode , 52 , 53 * @ rsvd : reserved byte ( s ) * @ lif_index : LIF index * @ qid_ver : ( qid | ( RDMA version < < 24 ) ) * @ cid : intr , eq_id , or cq_id * @ dbid : doorbell page id * @ depth_log2 : log base two of queue depth * @ stride_log2 : log base two of queue stride * @ dma_addr : address of the queue memory * @ rsvd2 : reserved byte ( s ) * * The same command struct is used to create an RDMA event queue , completion * queue , or RDMA admin queue . The cid is an interrupt number for an event * queue , an event queue id for a completion queue , or a completion queue id * for an RDMA admin queue . * * The queue created via a dev command must be contiguous in dma space . * * The dev commands are intended only to be used during driver initialization , * to create queues supporting the RDMA admin queue . Other queues , and other * types of RDMA resources like memory regions , will be created and registered * via the RDMA admin queue , and will support a more complete interface * providing scatter gather lists for larger , scattered queue buffers and * memory registration . * * There is no RDMA specific dev command completion struct . Completion uses * the common struct ionic_admin_comp . Only the status is indicated . struct ionic_rdma_queue_cmd {40 ];/****************************************************************** * * * * * * * * * * * * * * * * * * * Notify Events * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * /** * struct ionic_notifyq_event - Generic event reporting structure * @ eid : event number * @ ecode : event code * @ data : unspecified data about the event * * This is the generic event report struct from which the other * actual events will be formed . struct ionic_notifyq_event {54 ];/** * struct ionic_link_change_event - Link change event notification * @ eid : event number * @ ecode : event code = IONIC_EVENT_LINK_CHANGE * @ link_status : link up / down , with error bits ( enum ionic_port_status ) * @ link_speed : speed of the network link * @ rsvd : reserved byte ( s ) * * Sent when the network link state changes between UP and DOWN struct ionic_link_change_event {/* units of 1Mbps: e.g. 10000 = 10Gbps */ 48 ];/** * struct ionic_reset_event - Reset event notification * @ eid : event number * @ ecode : event code = IONIC_EVENT_RESET * @ reset_code : reset type * @ state : 0 = pending , 1 = complete , 2 = error * @ rsvd : reserved byte ( s ) * * Sent when the NIC or some subsystem is going to be or * has been reset . struct ionic_reset_event {52 ];/** * struct ionic_heartbeat_event - Sent periodically by NIC to indicate health * @ eid : event number * @ ecode : event code = IONIC_EVENT_HEARTBEAT * @ rsvd : reserved byte ( s ) struct ionic_heartbeat_event {54 ];/** * struct ionic_log_event - Sent to notify the driver of an internal error * @ eid : event number * @ ecode : event code = IONIC_EVENT_LOG * @ data : log data struct ionic_log_event {54 ];/** * struct ionic_xcvr_event - Transceiver change event * @ eid : event number * @ ecode : event code = IONIC_EVENT_XCVR * @ rsvd : reserved byte ( s ) struct ionic_xcvr_event {54 ];/* * struct ionic_port_stats - Port statistics structure struct ionic_port_stats {struct ionic_mgmt_port_stats {enum ionic_pb_buffer_drop_stats {0 ,enum ionic_oflow_drop_stats {/* struct ionic_port_pb_stats - packet buffers system stats * uses ionic_pb_buffer_drop_stats for drop_counts [ ] struct ionic_port_pb_stats {/** * struct ionic_port_identity - port identity structure * @ version : identity structure version * @ type : type of port ( enum ionic_port_type ) * @ num_lanes : number of lanes for the port * @ autoneg : autoneg supported * @ min_frame_size : minimum frame size supported * @ max_frame_size : maximum frame size supported * @ fec_type : supported fec types * @ pause_type : supported pause types * @ loopback_mode : supported loopback mode * @ speeds : supported speeds * @ rsvd2 : reserved byte ( s ) * @ config : current port configuration * @ words : word access to struct contents union ionic_port_identity {struct {4 ];2 ];2 ];16 ];44 ];union ionic_port_config config;478 ];/** * struct ionic_port_info - port info structure * @ config : Port configuration data * @ status : Port status data * @ stats : Port statistics data * @ mgmt_stats : Port management statistics data * @ sprom_epage : Extended Transceiver sprom * @ sprom_page1 : Extended Transceiver sprom , page 1 * @ sprom_page2 : Extended Transceiver sprom , page 2 * @ sprom_page17 : Extended Transceiver sprom , page 17 * @ rsvd : reserved byte ( s ) * @ pb_stats : uplink pb drop stats struct ionic_port_info {union ionic_port_config config;struct ionic_port_status status;union {struct ionic_port_stats stats;struct ionic_mgmt_port_stats mgmt_stats;union {384 ];struct {128 ];128 ];128 ];376 ];/* pb_stats must start at 2k offset */ struct ionic_port_pb_stats pb_stats;/* * struct ionic_lif_stats - LIF statistics structure struct ionic_lif_stats {/* RX */ /* RX drops */ /* TX */ /* TX drops */ /* Rx Queue/Ring drops */ /* Tx Queue/Ring drops */ /* RDMA/ROCE TX */ /* RDMA/ROCE RX */ /* RDMA/ROCE REQ Error/Debugs (768 - 895) */ /* RDMA/ROCE RESP Error/Debugs (896 - 1023) */ /** * struct ionic_lif_info - LIF info structure * @ config : LIF configuration structure * @ status : LIF status structure * @ stats : LIF statistics structure struct ionic_lif_info {union ionic_lif_config config;struct ionic_lif_status status;struct ionic_lif_stats stats;union ionic_dev_cmd {16 ];struct ionic_admin_cmd cmd;struct ionic_nop_cmd nop;struct ionic_dev_identify_cmd identify;struct ionic_dev_init_cmd init;struct ionic_dev_reset_cmd reset;struct ionic_dev_getattr_cmd getattr;struct ionic_dev_setattr_cmd setattr;struct ionic_port_identify_cmd port_identify;struct ionic_port_init_cmd port_init;struct ionic_port_reset_cmd port_reset;struct ionic_port_getattr_cmd port_getattr;struct ionic_port_setattr_cmd port_setattr;struct ionic_vf_setattr_cmd vf_setattr;struct ionic_vf_getattr_cmd vf_getattr;struct ionic_vf_ctrl_cmd vf_ctrl;struct ionic_lif_identify_cmd lif_identify;struct ionic_lif_init_cmd lif_init;struct ionic_lif_reset_cmd lif_reset;struct ionic_qos_identify_cmd qos_identify;struct ionic_qos_init_cmd qos_init;struct ionic_qos_reset_cmd qos_reset;struct ionic_qos_clear_stats_cmd qos_clear_stats;struct ionic_q_identify_cmd q_identify;struct ionic_q_init_cmd q_init;struct ionic_q_control_cmd q_control;struct ionic_fw_download_cmd fw_download;struct ionic_fw_control_cmd fw_control;union ionic_dev_cmd_comp {4 ];struct ionic_admin_comp comp;struct ionic_nop_comp nop;struct ionic_dev_identify_comp identify;struct ionic_dev_init_comp init;struct ionic_dev_reset_comp reset;struct ionic_dev_getattr_comp getattr;struct ionic_dev_setattr_comp setattr;struct ionic_port_identify_comp port_identify;struct ionic_port_init_comp port_init;struct ionic_port_reset_comp port_reset;struct ionic_port_getattr_comp port_getattr;struct ionic_port_setattr_comp port_setattr;struct ionic_vf_setattr_comp vf_setattr;struct ionic_vf_getattr_comp vf_getattr;struct ionic_vf_ctrl_comp vf_ctrl;struct ionic_lif_identify_comp lif_identify;struct ionic_lif_init_comp lif_init;struct ionic_qos_identify_comp qos_identify;struct ionic_q_identify_comp q_identify;struct ionic_q_init_comp q_init;struct ionic_fw_control_comp fw_control;/** * struct ionic_hwstamp_regs - Hardware current timestamp registers * @ tick_low : Low 32 bits of hardware timestamp * @ tick_high : High 32 bits of hardware timestamp struct ionic_hwstamp_regs {/** * union ionic_dev_info_regs - Device info register format ( read - only ) * @ signature : Signature value of 0 x44455649 ( ' DEVI ' ) * @ version : Current version of info * @ asic_type : Asic type * @ asic_rev : Asic revision * @ fw_status : Firmware status * bit 0 - 1 = fw running * bit 4 - 7 - 4 bit generation number , changes on fw restart * @ fw_heartbeat : Firmware heartbeat counter * @ serial_num : Serial number * @ rsvd_pad1024 : reserved byte ( s ) * @ fw_version : Firmware version * @ hwstamp : Hardware current timestamp registers * @ words : word access to struct contents union ionic_dev_info_regs {#define IONIC_DEVINFO_FWVERS_BUFLEN 32 #define IONIC_DEVINFO_SERIAL_BUFLEN 32 struct {#define IONIC_FW_STS_F_RUNNING 0 x01#define IONIC_FW_STS_F_GENERATION 0 xF0char fw_version[IONIC_DEVINFO_FWVERS_BUFLEN];char serial_num[IONIC_DEVINFO_SERIAL_BUFLEN];948 ];struct ionic_hwstamp_regs hwstamp;512 ];/** * union ionic_dev_cmd_regs - Device command register format ( read - write ) * @ doorbell : Device Cmd Doorbell , write - only * Write a 1 to signal device to process cmd , * poll done for completion . * @ done : Done indicator , bit 0 = = 1 when command is complete * @ cmd : Opcode - specific command bytes * @ comp : Opcode - specific response bytes * @ rsvd : reserved byte ( s ) * @ data : Opcode - specific side - data * @ words : word access to struct contents union ionic_dev_cmd_regs {struct {union ionic_dev_cmd cmd;union ionic_dev_cmd_comp comp;48 ];478 ];512 ];/** * union ionic_dev_regs - Device register format for bar 0 page 0 * @ info : Device info registers * @ devcmd : Device command registers * @ words : word access to struct contents union ionic_dev_regs {struct {union ionic_dev_info_regs info;union ionic_dev_cmd_regs devcmd;1024 ];union ionic_adminq_cmd {struct ionic_admin_cmd cmd;struct ionic_nop_cmd nop;struct ionic_q_identify_cmd q_identify;struct ionic_q_init_cmd q_init;struct ionic_q_control_cmd q_control;struct ionic_lif_setattr_cmd lif_setattr;struct ionic_lif_getattr_cmd lif_getattr;struct ionic_lif_setphc_cmd lif_setphc;struct ionic_rx_mode_set_cmd rx_mode_set;struct ionic_rx_filter_add_cmd rx_filter_add;struct ionic_rx_filter_del_cmd rx_filter_del;struct ionic_rdma_reset_cmd rdma_reset;struct ionic_rdma_queue_cmd rdma_queue;struct ionic_fw_download_cmd fw_download;struct ionic_fw_control_cmd fw_control;union ionic_adminq_comp {struct ionic_admin_comp comp;struct ionic_nop_comp nop;struct ionic_q_identify_comp q_identify;struct ionic_q_init_comp q_init;struct ionic_lif_setattr_comp lif_setattr;struct ionic_lif_getattr_comp lif_getattr;struct ionic_admin_comp lif_setphc;struct ionic_rx_filter_add_comp rx_filter_add;struct ionic_fw_control_comp fw_control;#define IONIC_BARS_MAX 6 #define IONIC_PCI_BAR_DBELL 1 #define IONIC_PCI_BAR_CMB 2 #define IONIC_BAR0_SIZE 0 x8000#define IONIC_BAR2_SIZE 0 x800000#define IONIC_BAR0_DEV_INFO_REGS_OFFSET 0 x0000#define IONIC_BAR0_DEV_CMD_REGS_OFFSET 0 x0800#define IONIC_BAR0_DEV_CMD_DATA_REGS_OFFSET 0 x0c00#define IONIC_BAR0_INTR_STATUS_OFFSET 0 x1000#define IONIC_BAR0_INTR_CTRL_OFFSET 0 x2000#define IONIC_DEV_CMD_DONE 0 x00000001#define IONIC_ASIC_TYPE_NONE 0 #define IONIC_ASIC_TYPE_CAPRI 1 #define IONIC_ASIC_TYPE_ELBA 2 #define IONIC_ASIC_TYPE_GIGLIO 3 #define IONIC_ASIC_TYPE_SALINA 4 /** * struct ionic_doorbell - Doorbell register layout * @ p_index : Producer index * @ ring : Selects the specific ring of the queue to update * Type - specific meaning : * ring = 0 : Default producer / consumer queue * ring = 1 : ( CQ , EQ ) Re - Arm queue . RDMA CQs * send events to EQs when armed . EQs send * interrupts when armed . * @ qid_lo : Queue destination for the producer index and flags ( low bits ) * @ qid_hi : Queue destination for the producer index and flags ( high bits ) * @ rsvd2 : reserved byte ( s ) struct ionic_doorbell {struct ionic_intr_status {2 ];struct ionic_notifyq_cmd {/* Not used but needed for qcq structure */ union ionic_notifyq_comp {struct ionic_notifyq_event event;struct ionic_link_change_event link_change;struct ionic_reset_event reset;struct ionic_heartbeat_event heartbeat;struct ionic_log_event log;/* Deprecate */ struct ionic_identity {union ionic_drv_identity drv;union ionic_dev_identity dev;union ionic_lif_identity lif;union ionic_port_identity port;union ionic_qos_identity qos;union ionic_q_identity txq;#endif /* _IONIC_IF_H_ */
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