/* SPDX-License-Identifier: GPL-2.0 */ /* Marvell RVU Admin Function driver * * Copyright (C) 2024 Marvell. * #ifndef RVU_MBOX_REG_H#define RVU_MBOX_REG_H#include "../rvu.h" #include "../rvu_reg.h" /* RVUM block registers */ #define RVU_PF_DISC (0 x0)#define RVU_PRIV_PFX_DISC(a) (0 x8000208 | (a) << 16 )#define RVU_PRIV_HWVFX_DISC(a) (0 xD000000 | (a) << 12 )/* Mbox Registers */ /* RVU AF BAR0 Mbox registers for AF => PFx */ #define RVU_MBOX_AF_PFX_ADDR(a) (0 x5000 | (a) << 4 )#define RVU_MBOX_AF_PFX_CFG(a) (0 x6000 | (a) << 4 )#define RVU_MBOX_AF_AFPFX_TRIGX(a) (0 x9000 | (a) << 3 )#define RVU_MBOX_AF_PFAF_INT(a) (0 x2980 | (a) << 6 )#define RVU_MBOX_AF_PFAF_INT_W1S(a) (0 x2988 | (a) << 6 )#define RVU_MBOX_AF_PFAF_INT_ENA_W1S(a) (0 x2990 | (a) << 6 )#define RVU_MBOX_AF_PFAF_INT_ENA_W1C(a) (0 x2998 | (a) << 6 )#define RVU_MBOX_AF_PFAF1_INT(a) (0 x29A0 | (a) << 6 )#define RVU_MBOX_AF_PFAF1_INT_W1S(a) (0 x29A8 | (a) << 6 )#define RVU_MBOX_AF_PFAF1_INT_ENA_W1S(a) (0 x29B0 | (a) << 6 )#define RVU_MBOX_AF_PFAF1_INT_ENA_W1C(a) (0 x29B8 | (a) << 6 )/* RVU PF => AF mbox registers */ #define RVU_MBOX_PF_PFAF_TRIGX(a) (0 xC00 | (a) << 3 )#define RVU_MBOX_PF_INT (0 xC20)#define RVU_MBOX_PF_INT_W1S (0 xC28)#define RVU_MBOX_PF_INT_ENA_W1S (0 xC30)#define RVU_MBOX_PF_INT_ENA_W1C (0 xC38)#define RVU_AF_BAR2_SEL (0 x9000000)#define RVU_AF_BAR2_PFID (0 x16400)#define NIX_CINTX_INT_W1S(a) (0 xd30 | (a) << 12 )#define NIX_QINTX_CNT(a) (0 xc00 | (a) << 12 )#define RVU_MBOX_AF_VFAF_INT(a) (0 x3000 | (a) << 6 )#define RVU_MBOX_AF_VFAF_INT_W1S(a) (0 x3008 | (a) << 6 )#define RVU_MBOX_AF_VFAF_INT_ENA_W1S(a) (0 x3010 | (a) << 6 )#define RVU_MBOX_AF_VFAF_INT_ENA_W1C(a) (0 x3018 | (a) << 6 )#define RVU_MBOX_AF_VFAF_INT_ENA_W1C(a) (0 x3018 | (a) << 6 )#define RVU_MBOX_AF_VFAF1_INT(a) (0 x3020 | (a) << 6 )#define RVU_MBOX_AF_VFAF1_INT_W1S(a) (0 x3028 | (a) << 6 )#define RVU_MBOX_AF_VFAF1_IN_ENA_W1S(a) (0 x3030 | (a) << 6 )#define RVU_MBOX_AF_VFAF1_IN_ENA_W1C(a) (0 x3038 | (a) << 6 )#define RVU_MBOX_AF_AFVFX_TRIG(a, b) (0 x10000 | (a) << 4 | (b) << 3 )#define RVU_MBOX_AF_VFX_ADDR(a) (0 x20000 | (a) << 4 )#define RVU_MBOX_AF_VFX_CFG(a) (0 x28000 | (a) << 4 )#define RVU_MBOX_PF_VFX_PFVF_TRIGX(a) (0 x2000 | (a) << 3 )#define RVU_MBOX_PF_VFPF_INTX(a) (0 x1000 | (a) << 3 )#define RVU_MBOX_PF_VFPF_INT_W1SX(a) (0 x1020 | (a) << 3 )#define RVU_MBOX_PF_VFPF_INT_ENA_W1SX(a) (0 x1040 | (a) << 3 )#define RVU_MBOX_PF_VFPF_INT_ENA_W1CX(a) (0 x1060 | (a) << 3 )#define RVU_MBOX_PF_VFPF1_INTX(a) (0 x1080 | (a) << 3 )#define RVU_MBOX_PF_VFPF1_INT_W1SX(a) (0 x10a0 | (a) << 3 )#define RVU_MBOX_PF_VFPF1_INT_ENA_W1SX(a) (0 x10c0 | (a) << 3 )#define RVU_MBOX_PF_VFPF1_INT_ENA_W1CX(a) (0 x10e0 | (a) << 3 )#define RVU_MBOX_PF_VF_ADDR (0 xC40)#define RVU_MBOX_PF_LMTLINE_ADDR (0 xC48)#define RVU_MBOX_PF_VF_CFG (0 xC60)#define RVU_MBOX_VF_VFPF_TRIGX(a) (0 x3000 | (a) << 3 )#define RVU_MBOX_VF_INT (0 x20)#define RVU_MBOX_VF_INT_W1S (0 x28)#define RVU_MBOX_VF_INT_ENA_W1S (0 x30)#define RVU_MBOX_VF_INT_ENA_W1C (0 x38)#define RVU_MBOX_VF_VFAF_TRIGX(a) (0 x2000 | (a) << 3 )#endif /* RVU_MBOX_REG_H */
Messung V0.5 in Prozent C=95 H=91 G=92
¤ Dauer der Verarbeitung: 0.12 Sekunden
(vorverarbeitet am 2026-06-07)
¤ *© Formatika GbR, Deutschland
