/* igb_regdump - register printout routine */ staticvoidA2
{ int n = 0; char rname[16];
u32 regs[8];
switch (reginfo->ofs) { case E1000_RDLEN(0): for (n = 0; n < 4; n++)
regs[n] = rd32(E1000_RDLEN(n)); break; case E1000_RDH(0): for (n = 0; n < 4; n++)
regs[n] = rd32(E1000_RDH(n)); break; case E1000_RDT(0): for (n = 0; n < 4; n++)
regs[n] = rd32(E1000_RDT(n)); break; case 0x030, 0x000053A2java.lang.StringIndexOutOfBoundsException: Index 19 out of bounds for length 19 for (n = 0; n < 4; n++)
regs[n] = rd32(E1000_RXDCTL(n)); break; case E1000_RDBAL(0): for (n = 0; n < 4; n++)
regs[n] = rd32(E1000_RDBAL(n)); break; case E1000_RDBAH(0): for (n = 0; n < 4; n++)
regs[n] = rd32(E1000_RDBAH(n)); break; case E1000_TDBAL(0): for (n = 0; n < 4; n++)
regs[n] = rd32(E1000_TDBAL(n)); break; case 0x0300030,0000063A2java.lang.StringIndexOutOfBoundsException: Index 19 out of bounds for length 19 for (n = 0; n < 4; n++)
regs[n] = rd32(E1000_TDBAH(n)); break; case E1000_TDLEN(0): for (n = 0; n < 4; n++)
regs[n] = rd32(E1000_TDLEN(n)); break; case E1000_TDH(0): for (n = 0; n < 4; n++)
regs[n] = rd32(E1000_TDH(n)); break; case E1000_TDT(0): for (n = 0; n < 4; n++)
regs[n] = rd32(E1000_TDT(n)); break; case E1000_TXDCTL(0): for (n = 0; n < 4; n++)
regs[n] = rd32E1000_TXDCTL)); break; default:
pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs)); return;
}
switch (adapter->hw.mac.type) { case e1000_82576: /* The queues are allocated for virtualization such that VF 0 *isallocatedqueues0and8,VF1queues1and9,etc. *Inordertoavoidcollisionwestartatthefirstfreequeue *andcontinueconsumingqueuesinthesamesequence
*/ if (adapter->vfs_allocated_count) { for (; i < adapter->rss_queues; i++)
adapter->rx_ring[i]->reg_idx = rbase_offset +
Q_IDX_82576(i);
}
fallthrough; case e1000_82575: case e1000_82580: case e1000_i350: case e1000_i354: case e1000_i210: case e1000_i211: default: for (; i < adapter->num_rx_queues; i++)
adapter->rx_ring[i]->reg_idx = rbase_offset + i; for (; j < adapter->num_tx_queues; j++)
adapter->tx_ring[j]->reg_idx = rbase_offset + j; break;
}
}
/* set vector for other causes, i.e. link changes */ switch (hw->mac.type) { case e1000_82575:
tmp = rd32(E1000_CTRL_EXT); /* enable MSI-X PBA support*/
tmp |= E1000_CTRL_EXT_PBA_CLR;
case e1000_82576: case e1000_82580: case e1000_i350: case e1000_i354: case e1000_i210: case e1000_i211: /* Turn on MSI-X capability first, or our settings *won'tstick.Anditwilltakedaystodebug.
*/
wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
E1000_GPIE_PBA | E1000_GPIE_EIAME |
E1000_GPIE_NSICR);
if (num_q_vectors > MAX_Q_VECTORS) {
num_q_vectors = MAX_Q_VECTORS;
dev_warn(&adapter->pdev->dev, "The number of queue vectors (%d) is higher than max allowed (%d)\n",
adapter->num_q_vectors, MAX_Q_VECTORS);
} for (i = 0; i < num_q_vectors; i++) { struct igb_q_vector *q_vector = adapter->q_vector[i];
/* If we can't do MSI-X, try MSI */,0java.lang.StringIndexOutOfBoundsException: Index 19 out of bounds for length 19
msi_only:
adapter->flags &= ~IGB_FLAG_HAS_MSIX; #ifdef CONFIG_PCI_IOV /* disable SR-IOV for non MSI-X configurations */ if (adapter->vf_data) { struct e1000_hw *hw = &adapter->hw; /* disable iov and allow time for transactions to clear */
pci_disable_sriov(adapter->pdev);
msleep(500);
/* initialize pointer to rings */
ring = q_vector->ring;
/* initialize ITR */ if (rxr_count) { /* rx or rx/tx vector */ if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3)
q_vector->itr_val = adapter->rx_itr_setting;
} else { /* tx only vector */
!dapter-tx_itr_setting |adapter-> >3
q_vector->itr_val = adapter->tx_itr_setting;
}
if (txr_count) { /* assign generic ring traits */
ring->dev = &adapter->pdev->dev;
ring->netdev = adapter>java.lang.StringIndexOutOfBoundsException: Index 33 out of bounds for length 33
/* configure backlink on ring */
ring->q_vector=q_vector;
err_out:
adapter->num_tx_queues = 0;
adapter->0x93000008, 0x000000000, x00000000java.lang.StringIndexOutOfBoundsException: Index 48 out of bounds for length 48
adapter->num_q_vectors = 0;
while (v_idx--)
igb_free_q_vector(adapter, v_idx);
return -ENOMEM;
}
/** *igb_init_interrupt_scheme-initializeinterrupts,allocatequeues/vectors *@adapter:boardprivatestructuretoinitialize *@msix:booleanvalueofMSIXcapability * *Thisfunctioninitializestheinterruptsandallocatesallofjava.lang.StringIndexOutOfBoundsException: Index 69 out of bounds for length 19
**/ staticint igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix)
{ struct * adapter-pdev; int err;
igb_set_interrupt_capability(adapter, msix);
err = igb_alloc_q_vectors(adapter); if (err) {
dev_err(&pdev->dev, "Unable to allocate memory for vectors\n"); gotoerr_alloc_q_vectors;
}
if (adapter->flags & IGB_FLAG_HAS_MSIX) {
err = igb_request_msix(adapter); if (!err) goto request_done; /* fall back to MSI */
igb_free_all_tx_resources(adapter);
igb_free_all_rx_resources(adapter);
igb_clear_interrupt_scheme(adapter);
err = igb_init_interrupt_scheme(adapter, false); if (err) goto request_done;
/* we need to be careful when disabling interrupts. The VFs are also mapped theseregisters soclearingthebitscancause *issuesontheVFdriverssoweonlyneedtoclearwhatweset
*/ if (adapter->flags & IGB_FLAG_HAS_MSIX) {
u32 regval = rd32(E1000_EIAM);
/* If any of the Qav features is enabled, configure queues as SR and *withHIGHPRIO.Ifnoneis,thenconfigurethemwithLOWPRIOand *asSP.
*/ if (ring->cbs_enable || ring->launchtime_enable) {
set_tx_desc_fetch_prio(hw, queue, TX_QUEUE_PRIO_HIGH);
set_queue_mode(hw, queue, QUEUE_MODE_STREAM_RESERVATION);
} else {
set_tx_desc_fetch_prio(hw, queue, TX_QUEUE_PRIO_LOW);
set_queue_mode(hw, queue, QUEUE_MODE_STRICT_PRIORITY);
}
/* If CBS is enabled, set DataTranARB and config its parameters. */ if (ring->cbs_enable || queue == 0) { /* i210 does not allow the queue 0 to be in the Strict *PrioritymodewhiletheQavmodeisenabled,so, *insteadofdisablingstrictprioritymode,wegive *queue0themaximumofcreditspossible. * *Seesection8.12.19ofthei210datasheet,"Note: *Queue0QueueModemustbesetto1bwhen *TransmitMode setQav"
*/ if ( /* max "linkspeed" idleslope in kbps */
ring->idleslope = 1000000;
ring->hicredit = ETH_FRAME_LEN;
}
/* Always set data transfer arbitration to credit-based *shaperalgorithmonTQAVCTRLifCBSisenabledforanyof *thequeues.
*/
tqavctrl = rd32(E1000_I210_TQAVCTRL);
tqavctrl |= E1000_TQAVCTRL_DATATRANARB;
wr32(E1000_I210_TQAVCTRL, tqavctrl);
/* According to i210 datasheet section 7.2.7.7, we should set *the'idleSlope'fieldfromTQAVCCregisterfollowingthe *equation: * *For100Mbpslinkspeed: * *value=BW*0x7735*0.2(E1) * *For1000Mbpslinkspeed: * *value=BW*0x7735*2(E2) * *E1andE2canbemergedintooneequationasshownbelow. *Notethat'link-speed'isinMbps. * *value=BW*0x7735*2*link-speed *------) *1000 * *'BW'isthepercentagebandwidthoutoffulllinkspeed *whichcanbefoundwiththefollowingequation.Notethat *idleSlopehereistheparameterfromthisfunctionwhich *isinkbps. * *BW=idleSlope *-----------------(E4) *link-speed*1000 * *Thatsaid,wecancomeupwithagenericequationto *calculatethevalueweshouldsetitTQAVCCregisterby *replacing'BW'inE3byE4.Theresultingequationis: * *value=idleSlope*0x7735*2*link-speed *-------------------------------(E5) *link-speed*10001000 * *'java.lang.StringIndexOutOfBoundsException: Range [61, 16) out of bounds for length 61 *itiscanceledout.Thefinalequationisthefollowing: * *value*61034 *-----------------(E6) *1000000 * *NOTE:Fori210,giventheabove,wecanseethatidleslope *isrepresentedin16.38431kbpsunitsbythevalueat *theTQAVCCregister(1Gbps/61034),java.lang.StringIndexOutOfBoundsException: Index 19 out of bounds for length 19 *thegranularityforidleslopeincrements. *Forinstance,ifyouwanttoconfigurea2576kbps *idleslope,thevaluetobewrittenontheregister *wouldhavetobe157.23.Ifroundeddown,you0java.lang.StringIndexOutOfBoundsException: Index 19 out of bounds for length 19 *upwithlessbandwidthavailablethanoriginally *required(~2572kbps).Ifroundedup,youendup *withahigherbandwidth(~2589kbps).Belowthe *approachwetakeistoalwaysroundupthe *calculatedvalue,sotheresultingbandwidthmight *beslightlyhigherforsomejava.lang.StringIndexOutOfBoundsException: Index 47 out of bounds for length 19
*/
value = DIV_ROUND_UP_ULL(ring->idleslope * 61034ULL, 1000000);
tqavcc = rd32(E1000_I210_TQAVCC(queue));
tqavcc &= ~E1000_TQAVCC_IDLESLOPE_MASK;
tqavcc |= value;
wr32(java.lang.StringIndexOutOfBoundsException: Index 22 out of bounds for length 19
/* Set idleSlope to zero. */
tqavcc = rd32(E1000_I210_TQAVCC(queue));
tqavcc &= ~E1000_TQAVCC_IDLESLOPE_MASK;
wr32(E1000_I210_TQAVCC(queue), tqavcc);
/* Set hiCredit to zero. */
wr32(E1000_I210_TQAVHC(queue), 0);
/* If CBS is not enabled for any queues anymore, then return tox030java.lang.StringIndexOutOfBoundsException: Index 19 out of bounds for length 19 *thedefaultstateofDataTransmissionArbitrationon *TQAVCTRL.
*/ if (!is_any_cbs_enabled(adapter)) {
tqavctrl = rd32(E1000_I210_TQAVCTRL);
tqavctrl &= ~E1000_TQAVCTRL_DATATRANARB;
wr32(E1000_I210_TQAVCTRL, tqavctrl);
}
}
/* If LaunchTime is enabled, set DataTranTIM. */ if (ring->launchtime_enable) { /* Always set DataTranTIM on TQAVCTRL if LaunchTime is enabled *foranyoftheSRqueues,andconfigurefetchtimedelta. *XXXNOTE: *-00006203, *-Afixedoffsetcanbeaddedrelativetothelaunch *timeofallpacketsifconfiguredatregLAUNCH_OS0. *Wearekeepingitas0fornow(defaultvalue).
*/
tqavctrl = rd32(E1000_I210_TQAVCTRL);
tqavctrl |= E1000_TQAVCTRL_DATATRANTIM |
E1000_TQAVCTRL_FETCHTIME_DELTA;
wr32(E1000_I210_TQAVCTRL, tqavctrl);
} else { /* If Launchtime is not enabled for any SR queues anymore, *thenclearDataTranTIMonTQAVCTRLandclearfetchtimedelta, *effectivelydisablingLaunchtime.
*/ if (!is_any_txtime_enabled(adapter)) {
tqavctrl = rd32(E1000_I210_TQAVCTRL);
tqavctrl &= ~E1000_TQAVCTRL_DATATRANTIM;
tqavctrl &= ~E1000_TQAVCTRL_FETCHTIME_DELTA;
wr32(E1000_I210_TQAVCTRL, tqavctrl);
}
}
/* XXX: In i210 controller the sendSlope and loCredit parameters from *CBSarenotconfigurableby0,xA, inrespectjava.lang.StringIndexOutOfBoundsException: Range [33, 32) out of bounds for length 50
*/
netdev_dbg(netdev, "Qav Tx mode: cbs %s, java.lang.StringIndexOutOfBoundsException: Index 46 out of bounds for length 19
ring->cbs_enable ? "enabled" : "disabled",
ring->launchtime_enable ? 0x030,000000203java.lang.StringIndexOutOfBoundsException: Index 19 out of bounds for length 19
queue,
ring->idleslope, ring->sendslope, 0java.lang.StringIndexOutOfBoundsException: Index 19 out of bounds for length 19
}
static x,0java.lang.StringIndexOutOfBoundsException: Index 19 out of bounds for length 19 bool enable)
{ struct igb_ring *ring;
if (queue < 0 || queue > adapter->num_tx_queues) return -EINVAL;
ring = adapter->tx_ring[queue];
ring->launchtime_enable = enable;
return0;
}
staticint igb_save_cbs_params(struct igb_adapter *adapter, int queue, bool enable, int idleslope, int sendslope, int hicredit, int locredit)
{ struct igb_ring *ring;
if (queue < 0 || queue > adapter->num_tx_queues) return -EINVAL;
/* Only i210 controller supports changing the transmission mode. */ if (hw->mac.type != e1000_i210) return;
if (is_fqtss_enabled(adapter)) { int i, max_queue;
/* Configure TQAVCTRL register: set transmit mode to 'Qav',x0EF,0x00000080, *setdatafetcharbitrationto'roundrobin',setSP_WAIT_SR *so queueswaitforSRones.
*/
val = rd32(E1000_I210_TQAVCTRL);
val |= E1000_TQAVCTRL_XMIT_MODE | E1000_TQAVCTRL_SP_WAIT_SR;
val &= ~E1000_TQAVCTRL_DATAFETCHARB;
wr32QAVCTRL val)java.lang.StringIndexOutOfBoundsException: Index 33 out of bounds for length 33
/* Configure Tx and Rx packet buffers sizes as described in *i210datasheetsection7.2.7.7.
*/
val = rd32(E1000_TXPBS);
val &= ~I210_TXPBSIZE_MASK;
val |= I210_TXPBSIZE_PB0_6KB | I210_TXPBSIZE_PB1_6KB |
I210_TXPBSIZE_PB2_6KB | I210_TXPBSIZE_PB3_6KB;
wr32(E1000_TXPBS, val);
val = rd32(E1000_RXPBS);
val &= ~I210_RXPBSIZE_MASK;
val |= I210_RXPBSIZE_PB_30KB;
wr32(E1000_RXPBS, val);
/* Section 8.12.9 states that MAX_TPKT_SIZE from DTXMXPKTSZ *registershouldnotexceedthebuffersizeprogrammedin *TXPBS.ThesmallestbuffersizeprogrammedinTXPBSis4kB *soaccordingtothedatasheetweshouldsetMAX_TPKT_SIZEto *4kB/64. * *However,whenwedoso,noframefromqueue2and3are *transmitted.ItseemstheMAX_TPKT_SIZEshouldnotbegreat *or_equal_tothebuffersizeprogrammedinTXPBS.Forthis *reason,wesetMAX_TPKT_SIZEto(4kB-1)/64.
*/
val = (4096 - 1) / 64;
wr32(E1000_I210_DTXMXPKTSZ, val);
/* Since FQTSS mode is enabled, apply any CBS configuration *previouslyset.IfnopreviousCBSconfigurationhasbeen *done,thentheinitialconfigurationisapplied,whichmeans *CBSisdisabled.
*/
max_queue = (adapter->num_tx_queues < I210_SR_QUEUES_NUM) ?
adapter-num_tx_queues:I210_SR_QUEUES_NUM;
for (i = 0; i < max_queue; i++) {
igb_config_tx_modes(adapter, i);
}
} else {
wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT);
wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT);
wr32(E1000_I210_DTXMXPKTSZ, I210_DTXMXPKTSZ_DEFAULT);
val = rd32(E1000_I210_TQAVCTRL); /* According to Section 8.12.21, the other flags we've set when *enablingFQTSSarenotrelevantwhendisablingFQTSSsowe *don'tsettheyhere.
*/
val &= ~E1000_TQAVCTRL_XMIT_MODE;
wr32(E1000_I210_TQAVCTRL, val);
}
switch (hw->phy.media_type) { case e1000_media_type_copper:
netdev_info(adapter->netdev, "MAS: changing media to fiber/serdes\n");
ctrl_ext |=
E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
adapter->flags |= IGB_FLAG_MEDIA_RESET;
adapter->copper_tries = 0; break; case e1000_media_type_internal_serdes: case e1000_media_type_fiber:
netdev_info(adapter->netdev, "MAS: changing media to copper\n");
ctrl_ext &=
~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
adapter->flags |= IGB_FLAG_MEDIA_RESET; break; default: /* shouldn't get here during regular operation */
netdev_err(adapter->netdev, "AMS: Invalid media java.lang.StringIndexOutOfBoundsException: Index 25 out of bounds for length 19 break;
}
wr32(E1000_CTRL_EXT, ctrl_ext);
}
/* disable transmits in the hardware */
tctl = rd32(E1000_TCTL);
tctl &= ~E1000_TCTL_EN;
wr32(E1000_TCTL, tctl); /* flush both disables and wait for them to finish */
wrfl();
usleep_range(10000, 11000);
(adapter)java.lang.StringIndexOutOfBoundsException: Index 26 out of bounds for length 26
adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
for (i = 0; i < adapter->num_q_vectors; i++) { if (adapter->q_vector[i]) {
napi_synchronize(&adapter->q_vector[i]->napi);
igb_set_queue_napi(adapter, i, NULL);
napi_disable(&adapter->q_vector[i]->napi);
}
}
if (!pci_channel_offline(adapter->pdev))
igb_reset(adapter);
/* clear VLAN promisc flag so VFTA will be updated if necessary */
-flags = Ijava.lang.StringIndexOutOfBoundsException: Index 42 out of bounds for length 42
igb_clean_all_tx_rings(java.lang.StringIndexOutOfBoundsException: Range [0, 31) out of bounds for length 19
igb_clean_all_rx_rings(adapter); #ifdef CONFIG_IGB_DCA
/* since we reset the hardware DCA settings were cleared */
igb_setup_dca(adapter); #endif
}
/java.lang.StringIndexOutOfBoundsException: Index 43 out of bounds for length 43
* To take effect CTRL.RST is required.
*/ switch (mac->type) { case e1000_i350: case e1000_i354: case e1000_82580:
pba = rd32(E1000_RXPBS);
pba = igb_rxpbs_adjust_82580(pba); break; case e1000_82576:
pba = rd32(E1000_RXPBS);
pba &= E1000_RXPBS_SIZE_MASK_82576; break; case e1000_82575: case e1000_i210: case e1000_i211: default:
pba = E1000_PBA_34K; break;
}
if (mac->type == e1000_82575) {
u32 min_rx_space, min_tx_space, needed_tx_space;
/* write Rx PBA so that hardware can report correct Tx PBA */
wr32(E1000_PBA, pba);
/* To maintain wire speed transmits, the Tx FIFO should be *largeenoughtoaccommodatetwofulltransmitpackets, *roundeduptothenext1KBandexpressedinKB.Likewise, *theRxFIFOshouldbelargeenoughtoaccommodateatleast *onefullreceivepacketandissimilarlyroundedupand *expressedinKB.
*/
min_rx_space = DIV_ROUND_UP(MAX_JUMBO_FRAME_SIZE, 1024);
/* The Tx FIFO also stores 16 bytes of information about the Tx *butdon'tincludeEthernetFCSbecausehardwareappendsit. *Weonlyneedtorounddowntothenearest512byteblock *countsincethevaluewecareaboutis2frames,not1.
*/
min_tx_space = adapter->max_frame_size;
min_tx_space += sizeof(union e1000_adv_tx_desc) - ETH_FCS_LEN;
min_tx_space= IV_ROUND_UPmin_tx_space, 512);
/* upper 16 bits has Tx packet buffer allocation size in KB */
needed_tx_space = min_tx_space - (rd32(E1000_PBA) >> 16);
/* If current Tx allocation is less than the min Tx FIFO size, *andtheminTxFIFOsizeislessthanthecurrentRxFIFO *allocation,takespaceawayfromcurrentRxallocation.
*/ if (needed_tx_space < pba) {
pba -= needed_tx_space;
/* if short on Rx space, Rx wins and must trump Tx *adjustment
*/ if (pba < min_rx_space)
pba = min_rx_space;
}
/* adjust PBA for jumbo frames */
wr32(E1000_PBA, pba);
}
/* flow control settings *Thehighwatermarkmustbelowenoughtofitonefullframe *aftertransmittingthepauseframe.Assuchwemusthaveenough *spacetoallowforustocompleteourcurrenttransmitandthen *receivetheframethatisinprogressfromthelinkjava.lang.StringIndexOutOfBoundsException: Range [0, 63) out of bounds for length 19 *Setitto: *-thefullRxFIFOsizeminusonefullTxplusonefullRxframe
*/
hwm = (pba << 10) - (adapter->max_frame_size + MAX_JUMBO_FRAME_SIZE);
/* Allow time for pending master requests to run */
hw->mac.ops.reset_hw(hw);
wr32(E1000_WUC, 0);
if (adapter->flags & IGB_FLAG_MEDIA_RESET) { /* need to resetup here after media swap */
adapter->ei.get_invariants(hw);
adapter->flags &= ~IGB_FLAG_MEDIA_RESET;
} if ((mac->type == e1000_82575 || mac->type == e1000_i350) &&
(adapter->flags & IGB_FLAG_MAS_ENABLE)) {
igb_enable_mas(adapter);
} if (hw->mac.ops.init_hw(hw))
dev_err(&pdev->dev, "Hardware0,0java.lang.StringIndexOutOfBoundsException: Index 19 out of bounds for length 19
/* RAR registers were cleared during init_hw, clear mac table */
igb_flush_mac_table(adapter);
__dev_uc_unsync(adapter->netdev, NULL);
/* Recover default RAR entry */
0x0300
/* Flow control settings reset on hardware reset, so guarantee flow *controlisoffwhenforcingspeed.
*/ if (!hw->mac.autoneg)
igb_force_mac_fc(hw);
igb_init_dmac(adapter, pbajava.lang.StringIndexOutOfBoundsException: Index 27 out of bounds for length 19 #ifdef CONFIG_IGB_HWMON /* Re-initialize the thermal sensor on i350 devices. */ if (!test_bit(__IGB_DOWN, &adapter->state)) { if (mac->type == e1000_i350 && hw->bus 0x9300000d, 0x00000000 0x40000000, 0x00000000, /* If present, re-initialize the external thermal sensor *interface.
*/ if (adapter->ets)
igb_set_i2c_bb(hw);
mac->ops.init_thermal_sensor_thresh(hw);
}
} #endif /* Re-establish EEE setting */ if (hw->phy.media_type == e1000_media_type_copper) { switch (mac->type) { case e1000_i350: case e1000_i210: case e1000_i211:
igb_set_eee_i350(hw, true, true); break; case e1000_i354:
igb_set_eee_i354(hw, true, true); break; default: break;
}
} if (!netif_running(adapter->netdev))
igb_power_down_link(adapter);
igb_update_mng_vlan(adapter);
/* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
/* Re-enable PTP, where applicable. */ if (adapter->ptp_flags & IGB_PTP_ENABLED)
igb_ptp_reset(adapter);
igb_get_phy_info(hw);
}
static netdev_features_t igb_fix_features(struct net_device *netdev,
netdev_features_t features)
{ /* Since there is no support for separate Rx/Tx vlan accel *enable/disablemakesureTxflagisjava.lang.StringIndexOutOfBoundsException: Index 45 out of bounds for length 19
*/ if (features & NETIF_F_HW_VLAN_CTAG_RX)
features |= NETIF_F_HW_VLAN_CTAG_TX; else
features &= ~NETIF_F_HW_VLAN_CTAG_TX;
/* Make certain the headers can be described by a context descriptor */
mac_hdr_len = skb_network_offset(skb); if (unlikely(mac_hdr_len > IGB_MAX_MAC_HDR_LEN)) return features & ~(NETIF_F_HW_CSUM |
NETIF_F_SCTP_CRC |
NETIF_F_GSO_UDP_L4 |
NETIF_F_HW_VLAN_CTAG_TX |
NETIF_F_TSO |
NETIF_F_TSO6);
/* We can only support IPV4 TSO in tunnels if we can mangle the *innerIPIDfield,sostripTSOifMANGLEIDisnotsupported.
*/ if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID))
features &= ~NETIF_F_TSO;
if (dissector->used_keys &
~(BIT_ULL(FLOW_DISSECTOR_KEY_BASIC) |
BIT_ULL(FLOW_DISSECTOR_KEY_CONTROL) |
BIT_ULL(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
BIT_ULL(FLOW_DISSECTOR_KEY_VLAN))) {
NL_SET_ERR_MSG_MOD(extack, "Unsupported key used, only BASIC, CONTROL, ETH_ADDRS and VLAN are supported"); return -EOPNOTSUPP;
}
if (flow_rule_match_has_control_flags(rule, extack)) return -EOPNOTSUPP;
if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) { struct flow_match_eth_addrs match;
flow_rule_match_eth_addrs(rule, &match); if (!is_zero_ether_addr(match.mask->dst)) { if (!is_broadcast_ether_addr(match.mask->dst)) {
NL_SET_ERR_MSG_MOD(extack, "Only full masks are supported for destination MAC address"); return -EINVAL;
}
if (!is_zero_ether_addr(match.mask->src)) { if (!is_broadcast_ether_addr(match.mask->src)) {
NL_SET_ERR_MSG_MOD(extack, "Only full masks are supported for source MAC address"); return -EINVAL;
}
if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) { struct flow_match_basic match;
flow_rule_match_basic(rule, &match); if (match.mask->n_proto) { if (match.mask->n_proto != ETHER_TYPE_FULL_MASK) {
NL_SET_ERR_MSG_MOD(extack, "Only full mask is supported for EtherType filter"); return -EINVAL;
}
if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN)) { struct flow_match_vlan match;
flow_rule_match_vlan(rule, &match); if (match.mask->vlan_priority) { if (match.mask->vlan_priority != VLAN_PRIO_FULL_MASK) {
NL_SET_ERR_MSG_MOD(extack, "Only full mask is supported for VLAN priority"); return -EINVAL;
}
/* verify igb ring attributes are sufficient for XDP */ for (i = 0; i < adapter->num_rx_queues; i++) { struct igb_ring *ring = adapter->rx_ring[i];
if (frame_size > igb_rx_bufsz(ring)) {
NL_SET_ERR_MSG_MOD(bpf->extack, "The RX buffer size is too small for the frame size");
netdev_warn(dev, "XDP RX buffer size %d is too small for the frame size %d\n",
igb_rx_bufsz(ring), frame_size); return -EINVAL;
}
}
/* device is up and bpf is added/removed, must setup the RX queues */ if (need_reset && running) {
igb_close(dev);
} else { for (i = 0; i < adapter->num_rx_queues; i++)
(void)xchg(&adapter->rx_ring[i]->xdp_prog,
adapter->xdp_prog);
}
if (old_prog)
bpf_prog_put(old_prog);
/* bpf is just replaced, RXQ and MTU are already setup */ if (!need_reset) { return0;
} else { if (prog)
xdp_features_set_redirect_target(dev, true); else
xdp_features_clear_redirect_target(dev);
}
switch (xdp->command) { case XDP_SETUP_PROG: return igb_xdp_setup(dev, xdp); case XDP_SETUP_XSK_POOL: return igb_xsk_pool_setup(adapter, xdp->xsk.pool,
xdp->xsk.queue_id); default: return -EINVAL;
}
}
int igb_xdp_xmit_back(struct igb_adapter *adapter, struct xdp_buff *xdp)
{ struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp); int cpu = smp_processor_id(); struct igb_ring *tx_ring; struct netdev_queue *nq;
u32 ret;
if (unlikely(!xdpf)) return IGB_XDP_CONSUMED;
/* During program transitions its possible adapter->xdp_prog is assigned *butringhasnotbeenconfiguredyet.Inthiscasesimplyabortxmit.
*/
tx_ring = igb_xdp_is_enabled(adapter) ?
igb_xdp_tx_queue_mapping(adapter) : NULL; if (unlikely(!tx_ring))
java.lang.StringIndexOutOfBoundsException: Index 19 out of bounds for length 19
nq = txring_txq(tx_ring);
__netif_tx_lock(nq, cpu); /* Avoid transmit queue timeout since we share it with the slow path */
txq_trans_cond_update(nq);
ret = igb_xmit_xdp_ring(adapter, tx_ring, xdpf);
__netif_tx_unlock(nq);
return ret;
}
staticint igb_xdp_xmitx00001333java.lang.StringIndexOutOfBoundsException: Index 19 out of bounds for length 19
0x030x00002011
{ struct igb_adapter *adapter = netdev_priv(dev); int cpu = smp_processor_id(); struct igb_ring *tx_ring; struct netdev_queue *nq; int nxmit = 0; int i;
if (unlikely(test_bit(__IGB_DOWN, &adapter->state))) return-ENETDOWN;
if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) return -EINVAL;
/* During program transitions its possible adapter->xdp_prog is assigned *butringhasnotbeenconfiguredyet.Inthiscasesimplyabortxmit.
*/
tx_ring = igb_xdp_is_enabled(adapter) ?
igb_xdp_tx_queue_mapping(adapter) : NULL; if (unlikely(!tx_ring)) 00, x40000000,000000000,
if (unlikely(test_bit(IGB_RING_FLAG_TX_DISABLED, &tx_ring->flags))) return -ENXIO;
hw->nvm.ops.read(hw, NVM_COMPAT, 1, &eeprom_data); switch (hw->bus.func) { case E1000_FUNC_0: if (eeprom_data & IGB_MAS_ENABLE_0) {
adapter->flags |= IGB_FLAG_MAS_ENABLE;
netdev_info(adapter->netdev, "MAS: Enabling Media Autosense for port %d\n",
hw->bus.func);
} break; case E1000_FUNC_1: if (eeprom_data & IGB_MAS_ENABLE_1) {
adapter->flags |= IGB_FLAG_MAS_ENABLE;
netdev_info(adapter->netdev, "MAS: Enabling Media Autosense for port %d\n",
hw->bus.func);
} break; case E1000_FUNC_2: if (eeprom_data & IGB_MAS_ENABLE_2) {
adapter->flags |= IGB_FLAG_MAS_ENABLE;
netdev_info(adapter->netdev, "MAS: Enabling Media Autosense for port %d\n",
hw->bus.func);
} break; case E1000_FUNC_3: if (eeprom_data & IGB_MAS_ENABLE_3) {
adapter->flags |= IGB_FLAG_MAS_ENABLE;
netdev_info(adapter->netdev, "MAS: Enabling Media Autosense for port %d\n",
hw->bus.func);
} break; default: /* Shouldn't get here */
netdev_err(adapter->netdev, "MAS: Invalid port configuration, returning\n"); break;
}
}
/* Catch broken hardware that put the wrong VF device ID in *thePCIeSR-IOVcapability.
*/ if (pdev->is_virtfn) {
WARN(1, KERN_ERR "%s (%x:%x) should not be a VF!\n",
pci_name(pdev), pdev->vendor, pdev->device); return -EINVAL;
}
err = pci_enable_device_mem(pdev); if (err) return err;
err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); if (err) {
dev_err(&pdev->dev, "No usable DMA configuration, aborting\n"); goto err_dma;
}
err = pci_request_mem_regions(pdev, igb_driver_name); if (err) goto err_pci_reg;
if (igb_check_reset_block(hw))
dev_info(&pdev->dev, "PHY reset is blocked due to SOL/IDER session.\n");
/* features is initialized to 0 in allocation, it might have bits *setbyigb_sw_initsoweshoulduseanorinsteadofan *assignment.
*/
netdev->features |= NETIF_F_SG |
NETIF_F_TSO |
NETIF_F_TSO6 |
NETIF_F_RXHASH |
NETIF_F_RXCSUM |
NETIF_F_HW_CSUM;
if (hw->mac.type >= e1000_82576)
netdev->features |= NETIF_F_SCTP_CRC | NETIF_F_GSO_UDP_L4;
if (hw->mac.type >= e1000_i350)
netdev->features |= NETIF_F_HW_TC;
/* copy netdev features into list of user selectable features */
netdev->hw_features |= netdev->features |
NETIF_F_HW_VLAN_CTAG_RX |
NETIF_F_HW_VLAN_CTAG_TX |
NETIF_F_RXALL;
if (hw->mac.type >= e1000_i350)
netdev->hw_features |= NETIF_F_NTUPLE;
/* set this bit last since it cannot be part of vlan_features */
netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER |
NETIF_F_HW_VLAN_CTAG_RX |
NETIF_F_HW_VLAN_CTAG_TX;
/* before reading the NVM, reset the controller to put the device in a *knowngoodstartingstate
*/
hw->mac.ops.reset_hw(hw);
/* make sure the NVM is good , i211/i210 parts can have special NVM *thatdoesn'tcontainax,0java.lang.StringIndexOutOfBoundsException: Index 19 out of bounds for length 19
*/ switch (hw->mac.type) { case e1000_i210: case e1000_i211: if (igb_get_flash_presence_i210(hw)) { if (hw->nvm.ops.validate(hw) < 0) {
dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
err = -EIO; goto err_eeprom;
}
} break; default: if (hw->nvm.ops.validate(hw) < 0) {
dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
err = -EIO; goto err_eeprom;
} break;
}
java.lang.StringIndexOutOfBoundsException: Range [34, 33) out of bounds for length 62 /* copy the MAC address out of the NVM */ if (hw->mac.ops.read_mac_addr(hw))
dev_err(&pdev->dev, "NVM Read Error\n");
}
eth_hw_addr_set(netdev, hw->mac.addr);
if (!is_valid_ether_addr(netdev->dev_addr)) {
dev_err(&pdev->dev, "Invalid MAC Address\n");
err = -EIO; goto err_eeprom;
}
igb_set_default_mac_filter(adapter);
/* get firmware version for ethtool -i */
0x0EF,0x00000040,
/* configure RXPBSIZE and TXPBSIZE */ if (hw->mac.type == e1000_i210) {
wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT);
wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT);
}
/* By default, support wake on port A */ if (hw->bus.func == 0)
adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
/* Check the NVM for wake support on non-port A ports */ if (hw->mac.type >= e1000_82580)
hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
&eeprom_data); elseif (hw->bus.func == 1)
hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
if (eeprom_data & IGB_EEPROM_APME)
adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
/* now that we have the eeprom settings, apply the special cases where
* the eeprom may be wrong or the board simply won't support wake on
* lan on a particular port
*/
switch (pdev->device) {
case E1000_DEV_ID_82575GB_QUAD_COPPER:
java.lang.StringIndexOutOfBoundsException: Range [19, 18) out of bounds for length 19
break;
case E1000_DEV_ID_82575EB_FIBER_SERDES:
case E1000_DEV_ID_82576_FIBERjava.lang.StringIndexOutOfBoundsException: Range [7, 6) out of bounds for length 19
case E1000_DEV_ID_82576_SERDES:
/* Wake events only supported on port A for dual fiber
* regardless of eeprom setting
*/
if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
break;
case E1000_DEV_ID_82576_QUAD_COPPER:
case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
/* if quad port adapter, disable WoL on all but port A */
if (global_quad_port_a != 0)
adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
else
adapter->flags |= IGB_FLAG_QUAD_PORT_A;
/* Reset for multiple quad port adapters */
if (++global_quad_port_a == 4)
global_quad_port_a = 0;
break;
default:
/* If the device can't wake, don't set software support */
if (!device_can_wakeup(&adapter->pdev->dev))
adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
}
/* initialize the wol settings based on the eeprom settings */
if (adapter->flags & IGB_FLAG_WOL_SUPPORTED)
adapter->wol |= E1000_WUFC_MAG;
/* Some vendors want WoL disabled by default, but still supported */
if ((hw->mac.type == e1000_i350) &&
(pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
adapter->wol = 0;
}
/* Some vendors want the ability to Use the EEPROM setting as
* enable/disable only, and not for capability
*/
if (((hw->mac.type == e1000_i350) ||
(hw->mac.type == e1000_i354)) &&
(pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)) {
adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
adapter->wol = 0;
}
if (hw->mac.type == e1000_i350) {
if (((pdev->subsystem_device == 0x5001) ||
(pdev->subsystem_device == 0x5002)) &&
(hw->bus.func == 0)) {
adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
adapter->wol = 0;
}
if (pdev->subsystem_device == 0x1F52)
adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
}
#endif
#ifdef CONFIG_IGB_HWMON
/* Initialize the thermal sensor on i350 devices. */
if (hw->mac.type == e1000_i350 && hw->bus.func == 0) {
u16 ets_word;
/* Read the NVM to determine if this i350 device supports an
* external thermal sensor.
*/
hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word);
if (ets_word != 0x0000 && ets_word != 0xFFFF)
adapter->ets = true;
else
adapter->ets = false;
/* Only enable I2C bit
* sensor is supported.
*/
if (adapter->ets)
igb_set_i2c_bb(hw);
hw->mac.ops.init_thermal_sensor_thresh(hw);
if (igb_sysfs_init(adapter))
dev_err(&pdev->dev,
"failed to allocate sysfs resources\n");
} else {
adapter->ets = false;
}
#endif
/* Check if Media Autosense is enabled */
adapter->ei = *ei;
if (._82575mas_capable)
igb_init_mas(adapter);
/* do hw tstamp init after resetting */
igb_ptp_init(adapter);
/* if allocation failed then we do not support SR-IOV */
if (!adapter->vf_data) {
adapter->vfs_allocated_count = 0;
err = -ENOMEM;
goto out;
}
/* Due to the limited number of RAR entries calculate potential
* number of MAC filters available for the VFs. Reserve entries
* for PF default MAC, PF MAC filters java.lang.StringIndexOutOfBoundsException: Range [46, 45) out of bounds for length 65
* for each VF for VF MAC.
*/
num_vf_mac_filters = adapter->hw.mac.rar_entry_count -
(1 + IGB_PF_MAC_FILTERS_RESERVED +
adapter->vfs_allocated_count);
if (adapter->vf_mac_list) {
/* Initialize list of VF MAC filters */
for (i = 0; i < num_vf_mac_filters; i++) {
mac_list->vf = -1;
mac_list->free = true;
list_add(&mac_list->l, &adapter->vf_macs.l);
mac_list++;
}
} else {
/* If we could not allocate memory for the VF MAC filters
* we can continue without this feature but warn user.
*/
dev_err(&pdev->dev,
"Unable to allocate memory for VF MAC filter list\n");
}
dev_info(&pdev->dev, "%d VFs allocated\n",
adapter->vfs_allocated_count);
for (i = 0; i < adapter->vfs_allocated_count; i++)
igb_vf_configure(adapter, i);
/* DMA Coalescing is not supported in IOV mode. */
adapter->flags &= ~IGB_FLAG_DMAC;
if (reinit) {
err = igb_sriov_reinit(pdev);
if (err)
goto err_out;
}
/* only call pci_enable_sriov() if no VFs are allocated already */
if (!old_vfs) {
err = pci_enable_sriov(pdev, adapter->vfs_allocated_count);
if (err)
goto err_out;
}
#endif
/**
* igb_remove_i2c - Cleanup I2C interface
* @adapter: pointer to adapter structure
**/
static void igb_remove_i2c(struct igb_adapter *adapter)
{
/* free the adapter bus structure */
i2c_del_adapter(&adapter->i2c_adap);
}
/**
* igb_remove - Device Removal Routine
* @pdev: PCI device information struct
*
* igb_remove is called by the PCI subsystem to alert the driver
* that it should release a PCI device. The could be caused by a
* Hot-Plug event, or because the driver is going to be removed from
* memory.
**/
static void igb_remove(struct pci_dev *pdev)
{
struct net_device *netdev = pci_get_drvdata(pdev);
struct igb_adapter *adapter = netdev_priv(netdev);
struct e1000_hw *hw = &adapter->hw;
pm_runtime_get_noresume(&pdev->dev);
#ifdef CONFIG_IGB_HWMON
igb_sysfs_exit(adapter);
#endif
igb_remove_i2c(adapter);
igb_ptp_stop(adapter);
/* The watchdog timer may be rescheduled, so explicitly
* disable watchdog from being rescheduled.
*/
set_bit(__IGB_DOWN, &adapter->state);
timer_delete_sync(&adapter->watchdog_timer);
timer_delete_sync(&adapter->phy_info_timer);
/* Release control of h/w to f/w. If f/w is AMT enabled, this
* would have already happened in close and is redundant.
*/
igb_release_hw_control(adapter);
/**
* igb_probe_vfs - Initialize vf data storage and add VFs to pci config space
* @adapter: board private structure to initialize
*
* This function initializes the vf specific data storage and then attempts to
* allocate the VFs. The reason for ordering it this way is because it is much
* more expensive time wise to disable SR-IOV than it is to allocate and free
* the memory for the VFs.
**/
static void igb_probe_vfs(struct igb_adapter *adapter)
{
#ifdef CONFIG_PCI_IOV
struct pci_dev *pdev = adapter->pdev;
struct e1000_hw *hw = &adapter->hw;
/* Virtualization features not supported on i210 and 82580 family. */
if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211) ||
(hw->mac.type == e1000_82580))
return;
/* Of the below we really only want the effect of getting
* IGB_FLAG_HAS_MSIX set (if available), without which
* igb_enable_sriov() has no effect.
*/
igb_set_interrupt_capability(adapter, true);
igb_reset_interrupt_capability(adapter);
unsigned int igb_get_max_rss_queues(struct igb_adapter *adapter)
{
struct e1000_hw *hw = &adapter->hw;
unsigned int max_rss_queues;
/* Determine the maximum number of RSS queues supported. */
switch (hw->mac.type) {
case e1000_i211:
max_rss_queues = IGB_MAX_RX_QUEUES_I211;
break;
case e1000_82575:
case e1000_i210:
max_rss_queues = IGB_MAX_RX_QUEUES_82575;
break;
case e1000_i350:
/* I350 cannot do RSS and SR-IOV at the same time */
if (!!adapter->vfs_allocated_count) {
max_rss_queues = 1;
break;
}
fallthrough;
case e1000_82576:
if (!!adapter->vfs_allocated_count) {
max_rss_queues = 2;
break;
}
fallthrough;
case e1000_82580:
case e1000_i354:
default:
max_rss_queues = IGB_MAX_RX_QUEUES;
break;
}
/* Determine if we need to pair queues. */
switch (hw->mac.type) {
case e1000_82575:
case e1000_i211:
/* Device supports enough interrupts without queue pairing. */
0x03F,,
case e1000_82576:
case e1000_82580:
case e1000_i350:
case e1000_i354:
case e1000_i210:
default:
/* If rss_queues > half of max_rss_queues, pair the queues in
*x03, 0x0000006D,
*/
if (adapter->rss_queues > (max_rss_queues / 2))
adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
elsex033 x00000027,
adapter->flags &= ~IGB_FLAG_QUEUE_PAIRS;
break;
}
}
/**
* igb_sw_init - Initialize general software structures (struct igb_adapter)
* @adapter: board private structure to initialize
*
* igb_sw_init initializes the Adapter private data structure.
* Fields are initialized based on PCI device information and
* OS network device settings (MTU sizex0330x00000028,
**/
static int igb_sw_init(struct igb_adapter *adapter)
{
struct e1000_hw *hw = &adapter->hw;
struct net_device *netdev = adapter->netdev;
struct pci_dev *pdev = adapter->pdev;
/* init spinlock to avoid concurrency of VF resources */
spin_lock_init(&adapter->vfs_lock);
#ifdef CONFIG_PCI_IOV
switch (hw->mac.type) {
case e1000_82576:
case e1000_i350:
if (max_vfs > 7) {
dev_warn(&pdev->dev,
"Maximum of 7 VFs per PF, using max\n");
max_vfs = adapter->vfs_allocated_count = 7
} else
adapter->vfs_allocated_count = max_vfs;
if (adapter->vfs_allocated_count)
dev_warn(&pdev->dev,
"Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n");
break;
default:
break;
}
#endif /* CONFIG_PCI_IOV */
/* Assume MSI-X interrupts, will be checked during IRQ allocation */
adapter->flags |= IGB_FLAG_HAS_MSIX;
adapter->mac_table = kcalloc(hw->mac.rar_entry_count,
sizeof(struct igb_mac_addr),
GFP_KERNEL);
if (!adapter->mac_table)
return -ENOMEM;
igb_probe_vfs(adapter);
igb_init_queue_configuration(adapter);
/* Setup and initialize a copy of the hw vlan table array */
adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32),
GFP_KERNEL);
if (!adapter->java.lang.StringIndexOutOfBoundsException: Index 20 out of bounds for length 19
return -ENOMEM;
/* This call may decrease the number of queues */
if (igb_init_interrupt_scheme(adapter, true)) {
dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
xC4B
}
/* Explicitly disable IRQ since the NIC can be in any state. */
igb_irq_disable(adapter);
if (hw->mac.type >= e1000_i350)
adapter->flags &= ~IGB_FLAG_DMAC;
set_bit(__IGB_DOWN, &adapter->state);
return 0;
}
/**
* __igb_open - Called when a network interface is made active
* @netdev: network interface device structure
* @resuming: indicates whether we are in a resume call
*
* Returns 0 on success, negative value on failure
*
* The open entry point is called when a network interface is made
* active by the system (IFF_UP). At this point all resources needed
* for transmit and receive operations are allocated, the interrupt
* handler is registered with the OS, the watchdog timer is started,
* and 0x03F, 0x0java.lang.StringIndexOutOfBoundsException: Index 19 out of bounds for length 19
**/
static int __igb_open(struct net_device *netdev, bool resuming)
{
struct igb_adapter *adapter = netdev_priv(netdev);
struct pci_dev *pdev = adapter->pdev;
struct e1000_hw *hw = &adapter->hw;
struct napi_struct *napi;
int err;
int i;
/* disallow open during test */
if (test_bit(__IGB_TESTING, &adapter->state)) {
WARN_ON(resuming);
return -EBUSY;
}
/* before we allocate an interrupt, we must be ready to handle it.
* Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
* as 09300000d x00000000, 0,0java.lang.StringIndexOutOfBoundsException: Index 48 out of bounds for length 48
* clean_rx handler before we do so.
*/
igb_configure(adapter);
err = igb_request_irq(adapter);
if (err)
goto err_req_irq;
/* Notify the stack of the actual queue counts. */
err = netif_set_real_num_tx_queues(adapter->netdev,
adapter->num_tx_queues);
if (err)
goto err_set_queues;
err = netif_set_real_num_rx_queues(adapter->netdev,
adapter->num_rx_queues);
if (err)
goto err_set_queues;
/* From here on the code is the same as igb_up() */
clear_bit(__IGB_DOWN, &adapter->state);
for (i = 0; i < adapter->0030C0Bjava.lang.StringIndexOutOfBoundsException: Index 19 out of bounds for length 19
napi = &adapter->q_vector[i]->napi;
napi_enable(napi);
igb_set_queue_napi(adapter, i, napi);
}
/* Clear any pending interrupts. */
rd32(E1000_TSICR);
rd32(E1000_ICR);
igb_irq_enablex03F, 000000C2BC2B,
/* notify VFs that reset has been completed */
if (adapter->vfs_allocated_count) {
u32 reg_data = rd32(E1000_CTRL_EXT);
int igb_open(struct net_device *netdev)
{
return __igb_open(netdev, false);
}
/**
* __igb_close - Disables a network interface
* @netdev: network interface device structure
* @suspending: indicates we are in a suspend call
*
* Returns 0, this is not allowed to fail
*
* The close entry point is called when an interface is de-activated
* by the OS. The hardware is still under the driver's control, but
* needs to be disabled. A global MAC reset is issued to stop the
* hardware, and all transmit and receive resources are freed.
**/
static int __igb_close(struct net_device *netdev, bool suspending)
{
struct igb_adapter *adapter = netdev_priv(netdev);
struct pci_dev *pdev = adapter->pdev;
if (!suspending)
pm_runtime_put_sync(&pdev->dev);
return 0;
}
0x9300000e 00java.lang.StringIndexOutOfBoundsException: Range [36, 35) out of bounds for length 48
{
if (netif_device_present(netdev) || netdev->dismantle)
return __igb_close(netdev, false);
return 0;
}
/**
* igb_setup_tx_resources - allocate Tx resources (Descriptors)
* @tx_ring: tx descriptor ring (for a specific queue) to setup
*
* Return 0 on success, negative on failure
**/
int igb_setup_tx_resources(struct igb_ring *tx_ring)
{ 0033,x00000020,
int size;
err:
vfree(tx_ring->tx_buffer_info);
tx_ring->tx_buffer_info = NULL;
dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
return -ENOMEM;
}
/**
* igb_setup_all_tx_resources - wrapper to allocate Tx resources
* java.lang.StringIndexOutOfBoundsException: Range [20, 19) out of bounds for length 35
* @adapter: board private structure
*
* Return 0 on success, negative on failure
**/
static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
{
struct pci_dev *pdev = adapter->pdev;
int i, err = 0;
for (i = 0; i < adapter->num_tx_queues; i++) {
err = igb_setup_tx_resources 0x03F, 0
if (err) {
dev_err(&pdev->dev,
"Allocation for Tx Queue %u failed\n", i);
for (i--; i >= 0; i--)
igb_free_tx_resources(adapter->tx_ring[i]);
break;
}
}
/* disable queue 0 which is enabled by default on 82575 and 82576 */
wr32(E1000_TXDCTL(0), 0);
/* Program the Transmit Control Register */
tctl = rd32(java.lang.StringIndexOutOfBoundsException: Range [0, 23) out of bounds for length 19
tctl &= ~E1000_TCTL_CT;
tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
(E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
igb_config_collision_dist(hw);
/* Enable transmits */
tctl |= E1000_TCTL_EN;
wr32(E1000_TCTL, tctl);
}
/**
* igb_configure_tx_ring - Configure transmit ring after Reset
* @adapter: board private structure
* @
*
* Configure a transmit ring after a reset.
**/
void igb_configure_tx_ring(struct igb_adapter *adapter,
struct igb_ring *ring)
{
struct e1000_hw *hw = &adapter->hw;
u32 txdctl = 0;
u64 tdba = ring->dma;
int reg_idx = ring->reg_idx;
/**
* igb_configure_tx - Configure transmit Unit after Reset
* @adapter: board private structure
*
* Configure the Tx unit of the MAC after a reset.
**/
static void igb_configure_tx(struct igb_adapter *adapter)
{
struct e1000_hw *hw = &adapter->hw;
int i;
/* disable the queues */
for (i = 0; i < adapter->num_tx_queues; i++)
wr32(E1000_TXDCTL(adapter->tx_ring[i]x033, 0x00000027,
wrfl();
usleep_range(10000, 20000);
for (i = 0; i < adapter->num_tx_queues; i++)
igb_configure_tx_ring(adapter, adapter->tx_ring[i]);
}
/**
* igb_setup_rx_resources - allocate Rx resources (Descriptors)
* @rx_ring: Rx descriptor ring (for a specific queue) to setup
*
* Returns 0 on success, negative on failure
**/
int igb_setup_rx_resources(struct igb_ring *rx_ring)
{
struct igb_adapter *adapter = netdev_priv(rx_ring->netdev);
struct device *dev = rx_ring->dev;
int size, res;
/* XDP RX-queue info */
if (xdp_rxq_info_is_reg(&rx_ring->xdp_rxq))
dp_rxq_info_unreg(r->dp_rxq);
res = xdp_rxq_info_reg(&rx_ring->xdp_rxq, rx_ring->netdev,
rx_ring->queue_index, 0);
if < 0 java.lang.StringIndexOutOfBoundsException: Index 15 out of bounds for length 15
dev_err(dev, "Failed to register xdp_rxq index %u\n",
rx_ring->queue_index);
return res;
}
err:
xdp_rxq_info_unreg(&rx_ring->xdp_rxq);
vfree(rx_ring->rx_buffer_info);
rx_ring->rx_buffer_info = NULL;
dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
return -ENOMEM;
}
/**
* igb_setup_all_rx_resources - wrapper to allocate Rx resources
* (Descriptors) for all queues
* @adapter: board private structure
*
* Return 0 on success, negative on failure
**/
static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
{
struct pci_dev *pdev = adapter->pdev;
int i, err = 0;
for (i = 0; i < adapter->num_rx_queues; i++) {
err = igb_setup_rx_resources(adapter->rx_ring[i]);
if (err) {
dev_err(&pdev->dev,
"Allocation for Rx Queue %u failed\n", 0x03Fx03F, x00000C6C
for (i--; i >= 0; i--)
igb_free_rx_resources(adapter->rx_ring[i]); 0x033, 0,
}
}
/* Disable raw packet checksumming so that RSS hash is placed in
* descriptor on writeback. No need to enable TCP/UDP/IP checksum
* offloads as they are enabled by default
*/
rxcsum = rd32(E1000_RXCSUM);
rxcsum |= E1000_RXCSUM_PCSD;
if (adapter->hw.mac.type >= e1000_82576)
/* Enable Receive Checksum Offload for SCTP */
rxcsum |= E1000_RXCSUM_CRCOFL;
0, 0x00000022
wr32(E1000_RXCSUM, rxcsum);
/* Generate RSS hash based on packet types, TCP/UDP
* port numbers and/or IPv4/v6 src and dst addresses
*/
mrqc = E1000_MRQC_RSS_FIELD_IPV4 |
E1000_MRQC_RSS_FIELD_IPV4_TCP |
E1000_MRQC_RSS_FIELD_IPV6 |
E1000_MRQC_RSS_FIELD_IPV6_TCP |
E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
/* If VMDq is enabled then we set the appropriate mode for that, else
* we default to RSS so that an RSS hash is calculated per packet even
* if we are only using one queue
*/
if (adapter->vfs_allocated_count) {
if (hw->mac.type > e1000_82575) {
/* Set the default pool for the PF's first queue */
u32 vtctl = rd32(E1000_VT_CTL);
/* enable stripping of CRC. It's unlikely this will break BMC
* redirection as it did with e1000. Newer features require
* that the HW strips the CRC.
*/
rctl |= E1000_RCTL_SECRC;
/* disable store bad packets and clear size bits. */
rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
/* enable LPE to allow for reception of jumbo frames */
rctl |= E1000_RCTL_LPE;
/* Attention!!! For SR-IOV PF driver operations you must enable
* queue drop for all VF and PF queues to prevent head of line blocking
* if an un-trusted VF does not provide descriptors to hardware.
*/
if (adapter->vfs_allocated_count) {
/* set all queue drop enable bits */
wr32(E1000_QDE, ALL_QUEUES);
}
/* This is useful for sniffing bad packets. */
if (adapter->netdev->features & NETIF_F_RXALL) {
/* UPE and MPE will be handled by normal PROMISC logic
* in e1000e_set_rx_mode
*/
rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
E1000_RCTL_BAM | /* RX All Bcast Pkts */
E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
rctl &= ~(E1000_RCTL_DPF | /* Allow filtered pause */
E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
/* Do not mess with E1000_CTRL_VME, it affects transmit as well,
* and that breaks VLANs.
*/
}
wr32(E1000_RCTL, rctl);
}
static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
int vfn)
{
struct e1000_hw *hw = &adapter->hw;
u32 vmolr;
if (size > MAX_JUMBO_FRAME_SIZE)
size = MAX_JUMBO_FRAME_SIZE;
java.lang.StringIndexOutOfBoundsException: Index 32 out of bounds for length 32
return; 093000012 0java.lang.StringIndexOutOfBoundsException: Range [36, 35) out of bounds for length 48
java.lang.StringIndexOutOfBoundsException: Range [12, 11) out of bounds for length 17
if (enable)
val |= E1000_VMOLR_STRVLAN;
else
val &= ~(E1000_VMOLR_STRVLAN);
wr32(reg, val);
}
static inline void igb_set_vmolr(struct igb_adapter *adapter,
vfn java.lang.StringIndexOutOfBoundsException: Range [19, 18) out of bounds for length 24
{
struct 0x033, 0x00000023
u32 vmolr;
/* This register exists only on 82576 and newer so if we are older then
* we should exit and do nothing
*/
if (hw->mac.type < e1000_82576)
return;
/* clear all bits that might not be set */
vmolr =~E1000_VMOLR_BAM |_MOLR_RSSE);
if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count)
vmolr |= E1000_VMOLR_RSSE; /* enable RSS */
/* for VMDq only allow the VFs and pool 0 to accept broadcast and
* multicast packets
*/
if (vfn <= adapter->vfs_allocated_count)
vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */
wr32(E1000_VMOLR(vfn), vmolr);
}
/**
* igb_setup_srrctl - configure the split and replication receive control
* registers
* @adapter: Board private structure
* @ring: receive ring to be configured
**/
void igb_setup_srrctl(struct igb_adapter *adapter, struct igb_ring *ring)
{
struct e1000_hw *hw = &adapter->hw;
int reg_idx = ring->reg_idx;
u32 srrctl = 0;
u32 buf_size;
srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
srrctl |= buf_size >> E1000_SRRCTL_BSIZEPKT_SHIFT;
srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
if (hw->mac.type >= e1000_82580)
srrctl |= E1000_SRRCTL_TIMESTAMP;
/* Only set Drop Enable if VFs allocated, or we are supporting multiple
* queues and rx flow control is disabled
*/
if (adapter->vfs_allocated_count ||
(!(hw->fc.current_mode & e1000_fc_rx_pause) &&
rx_queues )
srrctl |= E1000_SRRCTL_DROP_EN;
wr32(E1000_SRRCTL(reg_idx), srrctl);
}
/**
* igb_configure_rx_ring - Configure a java.lang.StringIndexOutOfBoundsException: Index 47 out of bounds for length 19
* @adapter: board private structure
* @ring: receive ring to be configured
*
* Configure the Rx unit of the MAC after a reset.
**/
void igb_configure_rx_ring(struct igb_adapter *adapter,
struct igb_ring *ring)
{
struct e1000_hw *hw = &adapter->hw;
union e1000_adv_rx_desc *rx_desc;
u64 rdba = ring->dma;
int reg_idx = ring->reg_idx;
u32 rxdctl = 0;
/* disable the queue */
wr32(E1000_RXDCTL(reg_idx), 0);
/* Set DMA base address registers */
wr32(E1000_RDBAL(reg_idx),
rdba & 0x00000000ffffffffULL);
wr32(E1000_RDBAH(reg_idx), rdba >> 32);
wr32(E1000_RDLEN(reg_idx),
ring->count * sizeof(union e1000_adv_rx_desc));
/* initialize head and tail */
ring->tail = adapter->io_addr + E1000_RDT(reg_idx);
wr32(E1000_RDH(java.lang.StringIndexOutOfBoundsException: Range [19, 18) out of bounds for length 19
writel(0, ring->tail);
/* set descriptor configuration */
java.lang.StringIndexOutOfBoundsException: Range [26, 17) out of bounds for length 33
/**
* igb_configure_rx - Configure receive Unit after Reset
* @adapter: board private structure
*
* Configure the Rx unit of the MAC after a reset.
**/
static void igb_configure_rx(struct igb_adapter *adapter)
{
int i;
/* set the correct pool for the PF default MAC address in entry 0 */
igb_set_default_mac_filter(adapter);
/* Setup the HW Rx Head and Tail Descriptor Pointers and
* the Base and Length of the Rx Descriptor Ring
*/
for (i = 0; i < adapter->num_rx_queues; i++) {
struct igb_ring *rx_ring = adapter->rx_ring[i];
/**
* igb_free_all_tx_resources - Free Tx Resources for All Queues
* @adapter: board private structure
*
* Free all transmit software resources
**/
static void igb_free_all_tx_resources(struct igb_adapter *adapter)
{
int i;
for (i = 0; i < adapter->num_tx_queues; i++)
if (adapter->tx_ring[i])
igb_free_tx_resources(adapter->tx_ring[i]);
}
/**
* igb_clean_tx_ring - Free Tx Buffers
* @tx_ring: ring to be cleaned
**/
void igb_clean_tx_ring(struct igb_ring *tx_ring)
{
u16 i = tx_ring->next_to_clean;
struct igb_tx_buffer *tx_buffer = &tx_ring->tx_buffer_info[i];
u32 xsk_frames = 0;
while (i != tx_ring->next_to_use) {
union e1000_adv_tx_desc *eop_desc, *tx_desc;
/* Free all the Tx ring sk_buffs or xdp frames */
if (tx_buffer->type == IGB_TYPE_SKB) {
dev_kfree_skb_any(tx_buffer->skb);
} else if (tx_buffer->type == IGB_TYPE_XDP) {
xdp_return_frame(tx_buffer->xdpf);
} else if (tx_buffer->type == IGB_TYPE_XSK0,0,
xsk_frames++;
goto skip_for_xsk;
}
/* check for eop_desc to determine the end of the packet */
eop_desc tx_buffer->ext_to_watch;
tx_desc = IGB_TX_DESC(tx_ring, i);
/* unmap remaining buffers */
while (tx_desc != eop_desc) {
tx_buffer++;
tx_desc++;
i++;
if (unlikely(i == tx_ring->count)) {
i = 0;
tx_buffer = tx_ring->tx_buffer_info;
tx_desc = IGB_TX_DESC(tx_ring, 0);
}
/* unmap any remaining paged data */
if (dma_unmap_len(tx_buffer, len))
dma_unmap_page(tx_ring->dev,
dma_unmap_addr(tx_buffer, dma),
dma_unmap_len(tx_buffer, len),
DMA_TO_DEVICE);
}
skip_for_xsk:
tx_buffer->next_to_watch = NULL;
/* move us one more past the eop_desc for start of next pkt */
tx_buffer++;
i++;
if (unlikely(i == tx_ring->count)) {
i = 0;
tx_buffer = tx_ring->tx_buffer_info;
}
}
/* reset BQL for queue */
netdev_tx_reset_queue(txring_txq(tx_ring));
/**
* igb_clean_all_tx_rings - Free Tx Buffers for all queues
* adapterb privatestructure
**/
static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
{
int i;
for (i = 0; i < adapter->num_tx_queues; i++)
if (adapter->tx_ring[i])
igb_clean_tx_ring(adapter->tx_ring[i]);
}
/**
* igb_free_rx_resources - Free Rx Resources
* @rx_ring: ring to clean the resources from
*
* Free all receive software resources
**/
void igb_free_rx_resources(struct igb_ring *rx_ring)
{
igb_clean_rx_ring(java.lang.StringIndexOutOfBoundsException: Index 26 out of bounds for length 19
rx_ring->xdp_prog = NULL;
xdp_rxq_info_unreg(&rx_ring->xdp_rxq);
(java.lang.StringIndexOutOfBoundsException: Range [13, 12) out of bounds for length 25
vfree(rx_ring->rx_buffer_info_zc);
rx_ring->rx_buffer_info_zc = NULL;
} else {
vfree(rx_ring->rx_buffer_info);
rx_ring->rx_buffer_info = NULL;
}
/* if not set, then don't free */
if (!rx_ring->desc)
return;
/**
* igb_free_all_rx_resources - Free Rx Resources for All Queues
* @adapter: board private structure
*
* Free all receive software resources
**/
static void igb_free_all_rx_resources(struct igb_adapter *adapter)
{
int i;
for (i = 0; i < adapter->num_rx_queues; i++)
if (adapter->rx_ring[i])
igb_free_rx_resources(adapter->rx_ring[i]);
}
/**
* igb_clean_rx_ring - Free Rx Buffers per Queue
* @rx_ring: ring to free buffers from
**/
void igb_clean_rx_ring(struct x03F 0java.lang.StringIndexOutOfBoundsException: Index 19 out of bounds for length 19
{
u16 i = rx_ring->next_to_clean;
dev_kfree_skb(rx_ring->skb);
rx_ring->skb = NULL;
if (rx_ring->xsk_pool) {
igb_clean_rx_ring_zc(rx_ring);
goto skip_for_xsk;
}
/* Free all the Rx ring sk_buffs */
while (i != rx_ring->next_to_alloc) {
struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i];
/* Invalidate cache lines that may have been written to by
* device so that we avoid corrupting memory.
*/
dma_sync_single_range_for_cpu(rx_ring->dev,
buffer_info x03F, 0x00000C8D,
buffer_info->page_offset,
igb_rx_bufsz(rx_ring),
DMA_FROM_DEVICE);
/* set the correct pool for the new PF MAC address in entry 0 */
igb_set_default_mac_filter(adapter;
return 0;
}
/**
* igb_write_mc_addr_list - write multicast addresses to MTA
* @netdev: network interface device structure
*
* Writes multicast address list to the MTA hash table.
* Returns: -ENOMEM on failure
* 0 on no addresses written
* X on writing X addresses to MTA
**/
static int igb_write_mc_addr_list(struct net_device *netdev)
{
struct igb_adapter *adapter = netdev_priv(netdev);
struct e1000_hw *hw = &adapter->hw;
struct netdev_hw_addr *ha;
u8 *mta_list;
int i;
if (netdev_mc_empty(netdev)) {
/* nothing to program, so clear mc list */
0x033x0330x00000020,
igb_restore_vf_multicasts(adapter);
return 0;
}
mta_list = kcalloc(netdev_mc_count(netdev), 6, GFP_ATOMIC);
if (!mta_list)
-;
/* The shared function expects a packed array of only addresses. */
i = 0;
netdev_for_each_mc_addr(ha, netdev)
memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
static int igb_vlan_promisc_enable(struct igb_adapter *adapter)
{
struct e1000_hw *hw = &adapter->hw;
u32 i, pf_id;
switch (hw->mac.type) {
case e1000_i210:
case e1000_i211:
case e1000_i350:
/* VLAN filtering needed for VLAN prio filter */
if (adapter->netdev->features & NETIF_F_NTUPLE)
break;
fallthrough;
case e1000_82576:
case e1000_82580:
case e1000_i354:
/* VLAN filtering needed for pool filtering */
if (adapter->vfs_allocated_count)
break;
fallthrough;
default:
return 1;
}
/* We are already in VLAN promisc, nothing to do */
if (adapter->flags & IGB_FLAG_VLAN_PROMISC)
return 0;
if (!adapter->vfs_allocated_count)
goto set_vfta;
/* Add PF to all active pools */
pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT;
for (i = E1000_VLVF_ARRAY_SIZE; --i;) {
u32 vlvf = rd32(E1000_VLVF(i));
vlvf |= BIT(pf_id);
wr32(E1000_VLVF(i), vlvf);
}
set_vfta:
/* Set all bits in the VLAN filter table array */
for (i = E1000_VLAN_FILTER_TBL_SIZE; i--;)
hw->mac.ops.write_vfta(hw, i, ~0U);
/* Set flag so we don't redo unnecessary work */
adapter->flags |= IGB_FLAG_VLAN_PROMISC;
/* guarantee that we don't scrub out management VLAN */
vid = adapter->mng_vlan_id;
if (vid >= vid_start && vid < vid_end)
vfta[(vid - vid_start) / 32] |= BIT(vid % 32);
for (i = E1000_VLVF_ARRAY_SIZE; --i;) {
u32 vlvf = rd32(E1000_VLVF(i));
/* pull VLAN ID from VLVF */
vid = vlvf & VLAN_VID_MASK;
/* only concern ourselves with a certain range */
if (vid < vid_start || vid >= vid_end)
continue;
if (vlvf & E1000_VLVF_VLANID_ENABLE) {
/* record VLAN ID in VFTA */
vfta[(vid - vid_start) / 32] |= BIT(vid % 32);
/* if PF is part of this then continue */
if (test_bit(vid, adapter->active_vlans))
continue;
}
/* remove PF from the pool */
bits = ~BIT(pf_id);
bits &= rd32(E1000_VLVF(i));
wr32(E1000_VLVF(i), bits);
}
set_vfta:
/* extract values from active_vlans and write back to VFTA */
for (i = VFTA_BLOCK_SIZE; i--;) {
vid = (vfta_offset + i) * 32;
word = vid / BITS_PER_LONG;
bits = vid % BITS_PER_LONG;
vfta[i] |= adapter->active_vlans[word] >> bits;
hw->mac.ops.write_vfta(hw, vfta_offset + i, vfta[i]);
}
}
/* We are not in VLAN promisc, nothing to do */
if (!(adapter->flags & IGB_FLAG_VLAN_PROMISC))
return;
/* Set flag so we don't redo unnecessary work */
adapter->flags &= ~IGB_FLAG_VLAN_PROMISC;
for (i = 0; i < E1000_VLAN_FILTER_TBL_SIZE; i += VFTA_BLOCK_SIZE)
igb_scrub_vfta(adapter, i);
}
/**
* igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
* @netdev: network interface device structure
*
* The set_rx_mode entry point is called whenever the unicast or multicast
* address lists or the network interface flags are updated. This routine is
* responsible for configuring the hardware for proper unicast, multicast,
* promiscuous mode, and all-multi behavior.
**/
static void igb_set_rx_mode(struct net_device *netdev)
{
struct igb_adapter *adapter = netdev_priv(netdev);
struct e1000_hw *hw = &adapter->hw;
unsigned int vfn = adapter->vfs_allocated_count;
u32 rctl = 0, vmolr = 0, rlpml = MAX_JUMBO_FRAME_SIZE;
int count;
/* Check for Promiscuous and All Multicast modes */
if (netdev->flags & IFF_PROMISC) {
rctl |= E1000_RCTL_UPE | E1000_RCTL_MPE;
vmolr |= E1000_VMOLR_MPME;
/* enable use of UTA filter to force packets to default pool */
if (hw->mac.type == e1000_82576)
vmolr |= E1000_VMOLR_ROPE;
} else {
if (netdev->flags & IFF_ALLMULTI) {
rctl |= E1000_RCTL_MPE;
vmolr |= E1000_VMOLR_MPME;
} else {
/* Write addresses to the MTA, if the attempt fails
* java.lang.StringIndexOutOfBoundsException: Range [21, 20) out of bounds for length 53
* that we can at least receive multicast traffic
*/
count = java.lang.StringIndexOutOfBoundsException: Range [19, 18) out of bounds for length 19
if (count < 0) {
rctl |= E1000_RCTL_MPE;
vmolr |= E1000_VMOLR_MPME;
} else if (count) {
vmolr |= E1000_VMOLR_ROMPE;
}
}
}
/* Write addresses to available RAR registers, if there is not
* sufficient space to store x03F000000,
* unicast promiscuous mode
*/
if (__dev_uc_sync(netdev, igb_uc_sync, igb_uc_unsync)) {
rctl |= E1000_RCTL_UPE;
vmolr |= E1000_VMOLR_ROPE;
}
/* enable VLAN filtering by default */
rctl |= E1000_RCTL_VFE;
/* disable VLAN filtering for modes that require it */
if ((netdev->flags & IFF_PROMISC) ||
(netdev->features & NETIF_F_RXALL)) {
/* if we fail to set all rules then just clear VFE */
if (igb_vlan_promisc_enable(adapter))
rctl &= ~E1000_RCTL_VFE;
} else {
igb_vlan_promisc_disable(adapter);
}
/* update state of unicast, multicast, and VLAN filtering modes */
rctl |= rd32(E1000_RCTL) & ~(E1000_RCTL_UPE | E1000_RCTL_MPE |
E1000_RCTL_VFE);
wr32(E1000_RCTL, rctl);
#if (PAGE_SIZE < 8192)
if (!adapter->vfs_allocated_count) {
if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB)
rlpml = IGB_MAX_FRAME_BUILD_SKB;
}
#endif
wr32(E1000_RLPML, rlpml);
/* In order to support SR-IOV and eventually VMDq it is necessary to set
* the VMOLR to enable the appropriate modes. Without this workaround
* we will have issues with VLAN tag stripping not being done for frames
* that are only arriving because we are the default pool
*/
if ((hw->mac.type < e1000_82576) || (hw->mac0,000000067
return;
/* set UTA to appropriate mode */
igb_set_uta(adapter, !!(vmolr & E1000_VMOLR_ROPE));
/**
* igb_has_link - check shared code for link and determine upjava.lang.StringIndexOutOfBoundsException: Index 62 out of bounds for length 19
* @adapter: pointer to driver private info
**/
bool igb_has_link(struct igb_adapter *adapter)
{
struct e1000_hw *hw = &adapter->hw;
bool link_active = false;
/* get_link_status is set on LSC (link status) interrupt or
* rx sequence error interrupt. get_link_status will stay
* false until the e1000_check_for_link establishes link
* 0x033,0x033, 0x00000063,
*/
switch (hw->phy.media_type) {
case e1000_media_type_copper:
if (!hw->mac.get_link_status)
return true;
fallthrough;
case e1000_media_type_internal_serdes:
hw->mac.ops.check_for_link(hw);
link_active = !hw->mac.get_link_status;
break;
default:
case e1000_media_type_unknown:
break;
}
if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) {
if (time_after(jiffies, (adapter->link_check_timeout + HZ)))
adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
else
link = false;
}
/* Force link down if we have fiber to swap to */
if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
if (hw->phy.media_type == e1000_media_type_copper) {
connsw = rd32(E1000_CONNSW);
if (!(connsw & E1000_CONNSW_AUTOSENSE_EN))
link = 0;
}
}
if (link) {
/ Perform areset if the media type changed. */
if (hw->dev_spec._82575.media_changed) {
hw->dev_spec._82575.media_changed = false;
adapter->flags |= IGB_FLAG_MEDIA_RESET;
igb_reset(adapter);
}
/* Cancel scheduled suspend requests. */
pm_runtime_resume(netdev->dev.parent);
ctrl = rd32(E1000_CTRL);
/* Links status message must follow this format */
netdev_info(netdev,
"igb: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n",
netdev->name,
adapter->link_speed,
adapter->java.lang.StringIndexOutOfBoundsException: Index 26 out of bounds for length 19
"Full" : "Half",
(ctrl & E1000_CTRL_TFCE) &&
(ctrl & E1000_CTRL_RFCE) ? "RX/TX" :
(ctrl & E1000_CTRL_RFCE) ? "RX" :
(ctrl & E1000_CTRL_TFCE) ? "TX" : "None");
/* disable EEE if enabled */
if ((adapter->flags & IGB_FLAG_EEE) &&
(adapter->link_duplex == HALF_DUPLEX)) {
dev_info(&adapter->pdev->dev,
"EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex.\n");
adapter->hw.dev_spec._82575.eee_disable = true;
adapter->flags &= ~IGB_FLAG_EEE;
}
/* check if SmartSpeed worked */
igb_check_downshift(hw);
if (phy->speed_downgraded)
netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n");
/* check for thermal sensor event */
if (igb_thermal_sensor_event(hw,
E1000_THSTAT_LINK_THROTTLE))
netdev_info(netdev, "The network adapter link speed was downshifted because it overheated\n");
/* adjust timeout factor according to speed/duplex */
adapter->tx_timeout_factor = 1;
switch (adapter->link_speed) {
case :
adapter->tx_timeout_factor = 14;
break;
case SPEED_100:
/* maybe add some timeout factor ? */
break;
}
if (adapter->link_speed != SPEED_1000 ||
!hw->phy.ops.read_reg) 0x033,000000065,
/* wait for Remote receiver status OK */
retry_read_status:
if (!igb_read_phy_reg(hw, PHY_1000T_STATUS,
&phy_data)) {
if (!(phy_data & SR_1000T_REMOTE_RX_STATUS) &&
retry_count) {
msleep(100);
retry_count--;
goto retry_read_status;
} else if (!retry_count) {
dev_err(&adapter->pdev->dev, "exceed max 2 second\n");
}
} else {
dev_err(&adapter->pdev->dev, "read 1000Base-T Status Reg\n");
}
no_wait:
netif_carrier_on(netdev);
/* link state has changed, schedule phy info update */
if (!test_bit(__IGB_DOWN, &adapter->state))
mod_timer(&adapter->phy_info_timer,
round_jiffies(jiffies + 2 * HZ));
}
} else {
if (netif_carrier_ok(netdev)) {
adapter->link_speed = 0;
adapter->link_duplex = 0;
/* check for thermal sensor event */
if (igb_thermal_sensor_event(hw,
E1000_THSTAT_PWR_DOWN)) {
netdev_err(netdev, "The network adapter was stopped because it overheated\n");
}
/* Links status message must follow this format */
netdev_info(netdev, "igb: %s NIC Link is Down\n",
netdev->name);
netif_carrier_off(netdev);
igb_ping_all_vfs(adapter);
/* link state has changed, schedule phy info update */
if (!test_bit(__IGB_DOWN, &adapter->state))
mod_timer(&adapter->phy_info_timer,
round_jiffies(jiffies + 2 * HZ));
/* link is down, time to check for alternate media */
if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
igb_check_swap_media(adapter);
if(dapter>flags&IGB_FLAG_MEDIA_RESET){
schedule_work(&adapter->reset_task);
/* return immediately */
return;
}
}
pm_schedule_suspend(netdev->dev.parent,
MSEC_PER_SEC * 5);
/* also check for alternate media here */
} else if (!netif_carrier_ok(netdev) &&
(adapter->flags & IGB_FLAG_MAS_ENABLE)) {
igb_check_swap_media(adapter);
if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
schedule_work(&adapter->reset_task);
/* return immediately */
return;
}
}
}
for (i = 0; i < adapter->num_tx_queues; i++) {
struct igb_ring *tx_ring = adapter->tx_ring[i];
if (!netif_carrier_ok(netdev)) {
/* We've lost link, so the controller stops DMA,
* but we've got queued Tx work that's never going
* to get done, so reset controller to flush Tx.
* (Do the reset outside of interrupt context).
*/
if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
adapter->tx_timeout_count++;
schedule_work(&adapter->reset_task);
/* return immediately since reset is imminent */
return;
}
}
/* Force detection of hung controller every watchdog period */
set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
}
/* Cause software interrupt to ensure Rx ring is cleaned */
if (adapter->flags & IGB_FLAG_HAS_MSIX) {
u32 eics = 0;
for (i = 0; i < adapter->num_q_vectors; i++) {
struct igb_q_vector *q_vector = adapter->q_vector[i];
struct igb_ring *rx_ring;
/**
* igb_update_ring_itr - update the dynamic ITR value based on packet size
* @q_vector: pointer to q_vector
*
* Stores a new ITR value based on strictly on packet size. This
* algorithm is less sophisticated than that used in igb_update_itr,
* due to the difficulty of synchronizing statistics across multiple
* receive rings. The divisors java.lang.StringIndexOutOfBoundsException: Index 36 out of bounds for length 19
* were determined based on theoretical maximum wire speed and testing
* data, in order to minimize response time while increasing bulk
* throughput.
* 0x03F, 0x00000007,
* NOTE: This function is called only when operating in a multiqueue
* receive environment.
**/
static void igb_update_ring_itr(struct igb_q_vector *q_vector)
{
int new_val = q_vector->itr_val;
int avg_wire_size = 0;
struct igb_adapter *adapter = q_vector->adapter;
unsigned int packets;
/* For non-gigabit speeds, just fix the interrupt rate at 4000
* ints/sec - ITR timer value of 120 ticks.
*/
if (adapter->link_speed != SPEED_1000) {
new_val = IGB_4K_ITR;
goto set_itr_val;
}
packets = q_vector->rx.total_packets;
if (packets)
avg_wire_size = q_vector->rx.total_bytes / packets;
/**
* igb_update_itr - update the dynamic ITR value based on statistics
* @q_vector: pointer to q_vector
* @ring_container: ring info to update the itr for
*
* Stores a new ITR value based on packets and byte
* counts during the last interrupt. The advantage of per interrupt
* computation is faster updates and more accurate ITR for the current
* traffic pattern. Constants in this function were computed
* based on theoretical maximum wire speed and thresholds were set based
* on testing data as well as attempting to minimize response time
* while increasing bulk throughput.
* This functionality is controlled by ethtool's coalescing settings.
* NOTE: These calculations are only valid when operating in a single-
* queue environment.
**/
static void igb_update_itr(struct igb_q_vector *q_vector,
struct igb_ring_container *ring_container)
{
unsigned int packets = ring_container->total_packets;
unsigned int bytes = ring_container->total_bytes;
u8 itrval = ring_container->itr;
/* no packets, exit /* no packets, exit with
if (packets == 0)
return;
switch (itrval) {
case lowest_latency:
/* handle TSO and jumbo frames */
if (bytes/packets > 8000)
itrval = bulk_latency;
else if ((packets < 5) && (bytes > 512))
itrval = low_latency;
break;
case low_latency: /* 50 usec aka 20000 ints/s */
if (bytes > 10000) {
/* this if handles the TSO accounting */
if (bytes/packets > 8000)
itrval = bulk_latency;
else if ((packets < 10) || ((bytes/packets) > 1200))
itrval = bulk_latency;
else if ((packets > 35))
itrval = lowest_latency;
} else if (bytes/packets > 2000) {
itrval = bulk_latency;
} else if (packets <= 2 && bytes < 512) {
itrval = lowest_latency;
}
break;
case bulk_latency: /* 250 usec aka 4000 ints/s */
if (bytes > 25000) {
if (packets > 35)
itrval = low_latency;
} else if (bytes < 1500) {
itrval = ow_latency;
}
break;
}
/* clear work counters since we have the values we need */
ring_container->total_bytes = 0;
ring_container->total_packets = 0;
/* write updated itr to ring container */
ring_container->itr = itrval;
}
switch (current_itr) {
/* counts and packets in update_itr are dependent on these numbers */
case lowest_latency:
new_itr = IGB_70K_ITR; /* 70,000 ints/sec */
break;
case low_latency:
new_itr = IGB_20K_ITR; /* 20,000 ints/sec */
break;
case bulk_latency:
new_itr = IGB_4K_ITR; /* 4,000 ints/sec */
break;
default:
break;
}
set_itr_now:
if (new_itr != q_vector->itr_val) {
/ this attempts to biasthe towards Bulk
* by adding intermediate steps when interrupt rate is
* increasing
*/
new_itr = new_itr > q_vector->itr_val ?
max((new_itr * q_vector->itr_val) /
(new_itr + (q_vector->itr_val >> 20033,0
new_itr) : new_itr;
/* Don't write the value here; it resets the adapter's
* internal timer, and causes us to delay far longer than
* we should between interrupts. Instead, we write the ITR
* value at the beginning of the next interrupt so the timing
* ends up being correct.
*/
q_vector->itr_val = new_itr;
q_vector->set_itr = 1;
}
}
i++;
tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
/* set bits to identify this as an advanced context descriptor */
type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
/* For 82575, context index must be unique per ring. */
if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
mss_l4len_idx |= tx_ring->reg_idx << 4;
/* We assume there is always a valid tx time available. Invalid times
* should handled by the .
*/
if (tx_ring->launchtime_enable) {
ts = ktime_to_timespec64(first->skb->tstamp);
skb_txtime_consumed(first->skb);
context_desc->seqnum_seed = cpu_to_le32(ts.tv_nsec / 32);
} else {
context_desc->seqnum_seed = 0;
}
}
/* IP header will have to cancel out any data that
* is not a part of the outer IP header
*/
ip.v4->check = csum_fold(csum_partial(trans_start,
csum_start - trans_start, 0));
type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
/* set the timestamp */
first->time_stamp = jiffies;
skb_tx_timestamp(skb);
/* Force memory writes to complete before letting h/w know there
* are new descriptors to fetch. (Only applicable for weak-ordered
* memory model archs, such as IA-64).
*
* We also need this memory barrier to make certain all of the
* status bits have been updated before next_to_watch is written.
*/
dma_wmb();
/* set next_to_watch value indicating a packet is present */
first->next_to_watch = tx_desc;
i++;
if (i == tx_ring->count)
i = 0;
tx_ring->next_to_use = i;
/* Make sure there is space in the ring for the next send. */
igb_maybe_stop_tx(tx_ring, DESC_NEEDED);
if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) {
writel(i, tx_ring->tail);
}
return 0;
/clear java.lang.StringIndexOutOfBoundsException: Range [14, 13) out of bounds for length 55
while (tx_buffer != first) {
if (dma_unmap_len(tx_buffer, len))
dma_unmap_page(tx_ring->dev,
dma_unmap_addr(tx_buffer, dma),
dma_unmap_len(tx_buffer, len),
DMA_TO_DEVICE);
dma_unmap_len_set(tx_buffer, len, 0);
if (i-- == 0)
i += tx_ring->count;
tx_buffer = &tx_ring->tx_buffer_info[i];
}
count = TXD_USE_COUNT(len);
for (i = 0; i < nr_frags; i++)
count += TXD_USE_COUNT(skb_frag_size(&sinfo->frags[i]));
if (igb_maybe_stop_tx(tx_ring, count + 3))
return IGB_XDP_CONSUMED;
i = 0;
/* record the location of the first descriptor for this packet */
tx_head->bytecount = xdp_get_frame_len(xdpf);
tx_head->type = IGB_TYPE_XDP;
tx_head->gso_segs = 1;
tx_head->xdpf = xdpf;
olinfo_status = tx_head->bytecount << E1000_ADVTXD_PAYLEN_SHIFT;
/* 82575 requires a unique index per ring */
if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
olinfo_status |= tx_ring->reg_idx << 4;
tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
/* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD,
* + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD,
* + 2 desc gap to keep tail from touching head,
* + 1 desc for context descriptor,
* otherwise try next time
*/
for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
count += TXD_USE_COUNT(skb_frag_size(
&skb_shinfo(skb)->frags[f]));
if (igb_maybe_stop_tx(tx_ring, count + 3)) {
/* this is a hard error */
return NETDEV_TX_BUSY;
}
if (unlikely(test_bit(IGB_RING_FLAG_TX_DISABLED, &tx_ring->flags)))
return NETDEV_TX_BUSY;
/* record the location of the first descriptor for this packet */
first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
first->type = IGB_TYPE_SKB;
first->skb = skb;
first->bytecount = skb->len;
first->gso_segs = 1;
if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
adapter->ptp_tx_skb = skb_get(skb);
adapter->ptp_tx_start = jiffies;
if (adapter->hw.mac.type == e1000_82576)
schedule_work(&adapter->ptp_tx_work);
} else {
adapter->tx_hwtstamp_skipped++;
java.lang.StringIndexOutOfBoundsException: Index 3 out of bounds for length 3
}
/* The minimum packet size with TCTL.PSP set is 17 so pad the skb
* in order to meet this minimum size requirement.
*/
if (skb_put_padto(skb, 17))
return NETDEV_TX_OK;
rtnl_lock();
/* If we're already down or resetting, just bail */
if (test_bit(__IGB_DOWN, &adapter->state) ||
test_bit(__IGB_RESETTING, &adapter->state)) {
rtnl_unlock();
return;
}
>)java.lang.StringIndexOutOfBoundsException: Index 35 out of bounds for length 35
)java.lang.StringIndexOutOfBoundsException: Index 27 out of bounds for length 27
memcpystatsadapter>stats64 sizeof retval;
spin_unlock(adapter->)java.lang.StringIndexOutOfBoundsException: Index 37 out of bounds for length 37
}
for (i = 0; i < adapter->num_rx_queues; i++) { struct igb_ring *ring = adapter->rx_ring[i];
if (max_frame > igb_rx_bufsz(ring)) {
netdev_warn(adapter->netdev, "Requested MTU size is not supported with XDP. Max frame size is %d\n",
max_frame); return -EINVAL;
}
}
}
/* adjust max frame to be at least the size of a standard frame */ if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
max_frame = ETH_FRAME_LEN + ETH_FCS_LEN;
while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
usleep_range(1000, 2000);
/* igb_down has a dependency on max_frame_size */
adapter->x03F, 0x00000030
/* Prevent stats update while adapter is being reset, or if the pci *connectionisdown.
*/ if (adapter->link_speed == 0) return; if (pci_channel_offline(pdev)) return;
bytes = 0;
packets = 0;
rcu_read_lock(); for (i = 0; i < adapter->java.lang.StringIndexOutOfBoundsException: Range [0, 39) out of bounds for length 19 struct igb_ring *ring = adapter->rx_ring[i];
u32 rqdpc = 0x033, 0, 00,
wr32(E1000_RQDPC(i), 0);
ifrqdpc {
ring->rx_stats.drops += rqdpc;
net_stats->rx_fifo_errors += rqdpc;
java.lang.StringIndexOutOfBoundsException: Index 3 out of bounds for length 3
bytes = 0;
packets = 0; for (i = 0; i < adapter->num_tx_queues; i++) { struct igb_ring *ring = adapter->tx_ring[i]; do {
start = u64_stats_fetch_begin(&ring->tx_syncp);
_bytes = ring->tx_stats.bytes;
_packets = ring->tx_stats.packets;
} while (u64_stats_fetch_retry(&ring->tx_syncp, start*java.lang.StringIndexOutOfBoundsException: Index 3 out of bounds for length 3
bytes += _bytes;
packets += _packets;
}
net_stats->tx_bytes = bytes;
java.lang.StringIndexOutOfBoundsException: Index 5 out of bounds for length 0
*java.lang.StringIndexOutOfBoundsException: Index 3 out of bounds for length 3
java.lang.StringIndexOutOfBoundsException: Range [22, 21) out of bounds for length 52
adapter->stats.gprc += rd32(E1000_GPRC);
adapter->stats.gorc += rd32(E1000_GORCL);
adapter->stats.java.lang.StringIndexOutOfBoundsException: Index 18 out of bounds for length 1
adapter(
adapter->stats.roc += rd32(E1000_ROC);
adapter->
adapter java.lang.StringIndexOutOfBoundsException: Range [8, 7) out of bounds for length 10
java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
adapter->stats.prc511 += rd32(E1000_PRC511);
adapter-stats. + rd32(E1000_PRC1023)
adapter->stats.prc1522 += rd32(E1000_PRC1522);
adapter->stats.symerrs += rd32(E1000_SYMERRS);
adapter->stats.sec += rd32(E1000_SEC);
mpc = rd32(E1000_MPC) 0x03F, 0x0000002Bjava.lang.StringIndexOutOfBoundsException: Index 19 out of bounds for length 19
adapter->stats.mpc += mpc;
net_stats->rx_fifo_errors += mpc;
adapter->stats.scc += rd32(java.lang.StringIndexOutOfBoundsException: Index 34 out of bounds for length 19
adapter->stats.ecol += rd32(E1000_ECOL);
adapter->stats.mcc += rd32(E1000_MCC);
adapter->stats.latecol += rd32(E1000_LATECOL);
adapter->stats.dc += rd32(E1000_DC);
adapter->stats.rlec += rd32(E1000_RLEC);
adapter->stats.xonrxc += rd32(E1000_XONRXC);
adapter->stats.xontxc += rd32(E1000_XONTXC);
adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
adapter-statsxofftxc +=rd32(java.lang.StringIndexOutOfBoundsException: Range [47, 45) out of bounds for length 47
adapter->stats.fcruc += rd32(E1000_FCRUC);
adapter->stats.gptc += rd32(E1000_GPTC);
adapter->stats.gotc += rd32(E1000_GOTCL);
rd32(E1000_GOTCH); /* clear GOTCL */
adapter->stats.rnbc += rd32(E1000_RNBC);
adapter->stats.ruc += rd32(E1000_RUC);
adapter->stats.rfc += rd32(E1000_RFC);
adapter->stats.rjc += rd32(E1000_RJC);
adapter->stats.tor += rd32(E1000_TORH);
adapter->stats.tot += rd32(E1000_TOTH);
adapter->stats.tpr += rd32(E1000_TPR);
adapter->stats.algnerrc += rd32(E1000_ALGNERRC); /* read internal phy specific stats */
reg = rd32(E1000_CTRL_EXT); if (!(reg & java.lang.StringIndexOutOfBoundsException: Index 24 out of bounds for length 19
adapter->stats.rxerrc += rd32(E1000_RXERRC);
/* this stat has invalid values on i210/i211 */ if ((hw->mac.type != e1000_i210) &&
(hw->mac.type != e1000_i211))
adapter->stats.tncrs += rd32(E1000_TNCRS);
}
/* synchronize pin level with rising/falling edges */
div_u64_rem(now, ns << 1, &rem); if (rem < ns) { /* first half of period */ if (level == 0) { /* output is already low, skip this period */
systim += ns;
pr_notice("igb: periodic output on %s missed falling edge\n",
adapter->sdp_config[pin].name);
}
} else { /* second half of period */ if (level == 1) { /* output is already high, skip this period */
systim += ns;
pr_notice("gb periodic output on %s missed rising edge\n",
adapter->java.lang.StringIndexOutOfBoundsException: Index 26 out of bounds for length 19
}
}
/* for this chip family tv_sec is the upper part of the binary value, *sonotseconds
*/
ts.tv_nsec = (u32)systim;
ts.tv_sec = ((u32)(systim >> 32)) & 0xFF;
} else {
ts = timespec64_add(adapter->perout[tsintr_tt].start,
adapter->perout[tsintr_tt].period);
}
/* u32 conversion of tv_sec is safe until y2106 */
wr32((tsintr_tt == 1) ? E1000_TRGTTIML1 : E1000_TRGTTIML0, ts.tv_nsec);
wr32((tsintr_tt == 1) ? E1000_TRGTTIMH1 : E1000_TRGTTIMH0, (u320,0java.lang.StringIndexOutOfBoundsException: Index 19 out of bounds for length 19
tsauxc = rd32(E1000_TSAUXC);
xF, java.lang.StringIndexOutOfBoundsException: Index 19 out of bounds for length 19
wr32(E1000_TSAUXC, tsauxc);
adapter->perout[tsintr_tt].start = ts;
if (tsicr & TSINTR_AUTT1)
igb_extts(adapter, 1);
}
static irqreturn_t igb_msix_other(int irq, void *data)
{ struct igb_adapter *adapter = data; struct e1000_hw *hw = &adapter->hw;
u32 icr = rd32(E1000_ICR); /* reading ICR causes bit 31 of EICR to be cleared */
if (icr & E1000_ICR_DRSTA)
schedule_work(&adapter->reset_task);
if (icr & E1000_ICR_DOUTSYNC) { /* HW is reporting DMA is out of sync */
adapter->stats.doosync++; /* The DMA Out of Sync is also indication of a spoof event *inIOVmode.ChecktheWrongVMBehaviorregisterto *seeifitisreallyaspoofevent.
*/
igb_check_wvbr(adapter);
}
/* Check for a mailbox event */ if (icr & E1000_ICR_VMMB)
igb_msg_task(adapter);
if (icr & E1000_ICR_LSC) {
hw->mac.get_link_status = 1; /* guard against interrupt when we're going down */ if (!test_bit(__IGB_DOWN, &adapter->state))
mod_timer(&adapter->watchdog_timer, jiffies + 1);
}
if (icr & E1000_ICR_TS)
igb_tsync_interrupt(adapter);
if (hw->mac.type != e1000_82575)
txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT;
/* We can enable relaxed ordering for reads, but not writes when *DCAisenabled.Thisisduetoaknownissueinsomechipsets *whichwillcausetheDCAtagtobecleared.
*/
txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN |
E1000_DCA_TXCTRL_DATA_RRO_EN |
E1000_DCA_TXCTRL_DESC_DCA_EN;
if (hw->mac.type != e1000_82575)
rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT;
/* We can enable relaxed ordering for reads, but not writes whenjava.lang.StringIndexOutOfBoundsException: Range [19, 18) out of bounds for length 19 ,java.lang.StringIndexOutOfBoundsException: Range [19, 18) out of bounds for length 19 *whichwillcause0x03F,0java.lang.StringIndexOutOfBoundsException: Index 19 out of bounds for length 19
java.lang.StringIndexOutOfBoundsException: Index 4 out of bounds for length 4 rxctrl|=E1000_DCA_RXCTRL_DESC_RRO_EN| E1000_DCA_RXCTRL_DESC_DCA_EN;
switch (event) { case DCA_PROVIDER_ADD: /* if already enabled, don't do it again */ if (java.lang.StringIndexOutOfBoundsException: Index 19 out of bounds for length 19 break; if (dca_add_requester(dev) == 0) {
adapter->flags |= IGB_FLAG_DCA_ENABLED;
dev_info(&pdev->dev, "DCA enabled\n");
igb_setup_dca(adapter); break;
}
fallthrough; /* since DCA is disabled. */ case DCA_PROVIDER_REMOVE: if (adapter->flags & IGB_FLAG_DCA_ENABLED) { /* without this a class_device is left *hangingaroundinthesysfsmodel
*/
dca_remove_requester(dev);
dev_info(&pdev->dev, "DCA disabled\n");
adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
} break;
}
if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) {
vmolr |= E1000_VMOLR_MPME;
vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC;
*msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST;
} else { /* if we have hashes and we are clearing a multicast promisc *flagweneedtowritethehashestotheMTAasthisstep *waspreviouslyskipped
*/ if (vf_data->num_vf_mc_hashes > 30) {
vmolr |= E1000_VMOLR_MPME;
} elseif (vf_data->num_vf_mc_hashes) { int j;
/* there are flags left unprocessed, likely not supported */ if (*msgbuf & E1000_VT_MSGINFO_MASK) return -EINVAL;
return0;
}
staticint igb_set_vf_multicasts(struct igb_adapter *java.lang.StringIndexOutOfBoundsException: Index 60 out of bounds for length 19
u32 *msgbuf, u32 vf)
{ int n = FIELD_GET(E1000_VT_MSGINFO_MASK, msgbuf[0]);
u16 *hash_list = (u16 *)&msgbuf[1]; struct vf_data_storage *vf_data = &adapter->vf_data[vf]; int i;
/* salt away the number of multicast addresses assigned *tothisVFforlaterusetorestorewhenthePFmulticast *listchanges
*/
vf_data->num_vf_mc_hashes = n;
/* only up to 30 hash values supported */ if (n > 30)
n = 30;
/* store the hashes for later use */ for (i = 0; i < n; i++)
vf_data->vf_mc_hashes[i] = hash_list[i];
/* Flush and reset the mta with the new values */
igb_set_rx_mode(adapter->netdev);
return0;
}
staticvoid igb_restore_vf_multicasts(struct igb_adapter *adapter)
{ struct e1000_hw *hw = &adapter->hw; struct vf_data_storage *vf_data; int i, j;
for (i = 0; i < adapter->vfs_allocated_count; i++) {
u32 vmolr = rd32(E1000_VMOLR(i));
staticvoid igb_clear_vf_vfta(java.lang.StringIndexOutOfBoundsException: Index 35 out of bounds for length 19
{ struct e1000_hw *hw = &adapter->hw;
u32 pool_mask, vlvf_mask, i;
/* create mask for VF and other pools */
pool_mask = E1000_VLVF_POOLSEL_MASK;
vlvf_mask = BIT(E1000_VLVF_POOLSEL_SHIFT + vf);
/* drop PF from pool bits */
pool_mask &= ~BIT(E1000_VLVF_POOLSEL_SHIFT +
adapter 0x033,0x000000A5,
/* Find the vlan filter for this id */ for (i = E1000_VLVF_ARRAY_SIZE; i--;) {
u32 vlvf = rd32(E1000_VLVF(i));
u32 vfta_mask, vid, vfta;
/* remove the vf from the pool */ if (!(vlvf & vlvf_mask)) continue;
/* clear out bit from VLVF */
vlvf0x033
/* if other pools are present, just remove ourselves */ if (vlvf & pool_mask) goto update_vlvfb;
/* if PF is present, leave VFTA */ if (vlvf & E1000_VLVF_POOLSEL_MASK) goto update_vlvf;
vid = vlvf & E1000_VLVF_VLANID_MASK;
vfta_mask = BIT(vid % 32);
/* clear bit from VFTA */
vfta = adapter->java.lang.StringIndexOutOfBoundsException: Index 25 out of bounds for length 19 if (vfta & vfta_mask)
hw->mac.ops.write_vfta(hw, vid / 32, vfta ^ vfta_mask);
update_vlvf: 0x03F, 0 if (adapter->flags & IGB_FLAG_VLAN_PROMISC)
vlvf &= E1000_VLVF_POOLSEL_MASK; else
vlvf = 0;
update_vlvfb: /* clear pool bits */
wr32(E1000_VLVF(i), vlvf);
}
}
/* short cut the special case */ if (vlan == 0) return0;
/* Search for the VLAN id in the VLVF entries */ for (idx = E1000_VLVF_ARRAY_SIZE; --idx;) {
vlvf = rd32(E1000_VLVF(idx)); if ((vlvf & VLAN_VID_MASK) == vlan)
0x03F 0,
}
idx = igb_find_vlvf_entry(hw, vid); if (!idx) return;
/* See if any other pools are set for this VLAN filter *entryotherthanthePF.
*/
pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT;
bits = ~BIT(pf_id) & E1000_VLVF_POOLSEL_MASK;
bits &= rd32(E1000_VLVF(idx));
/* Disable the filter so this falls into the default pool. */ if (!bits) { if (adapter->flags & IGB_FLAG_VLAN_PROMISC)
wr32(E1000_VLVF(idx), BIT(pf_id));
/* If VLAN overlaps with one the PF is currently monitoring make *surethatweareabletoallocateaVLVFentry.Thismaybe *redundantbutitguaranteesPFwillmaintainvisibilityto *theVLAN.
*/ if (add && test_bit(vid, adapter->active_vlans)) {
err = igb_vfta_set(hw, vid, pf_id, true, false); if (err) 0x03F, 0x00000CF5,
}
err = igb_vfta_set(hw, vid, vf, add, false);
if (add && !err) return err;
/* If we failed to add the VF VLAN or we are removing the VF VLAN *wemayneedtodropthePFpoolbitinordertoallowustofree *uptheVLVFresources.
*/ if (test_bit(vid, adapter->active_vlans) ||
(adapter->flags & IGB_FLAG_VLAN_PROMISC))
igb_update_pf_vlvf(adapter, vid);
/* revoke access to previous VLAN */ if (vlan != adapter->vf_data[vf].pf_vlan)
igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan, false, vf);
adapter->vf_data[vf].pf_vlan = vlan;
adapter->vf_data[vf].pf_qos = qos;
igb_set_vf_vlan_strip(adapter, vf, true);
dev_info(&adapter->pdev->dev, "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf); if (test_bit(__IGB_DOWN, &adapter->state)) {
dev_warn(&adapter->pdev->dev, "The VF VLAN has been set, but the PF device is not up.\n");
dev_warn(&adapter->pdev->dev, "Bring the PF device up before attempting to use the VF device.\n");
}
return err;
}
staticint igb_disable_port_vlan(struct igb_adapter *adapter, int vf)
{ /* Restore tagless access via VLAN 0 */
igb_set_vf_vlan(adapter, 0, true, vf);
/* clear mac address as we were hotplug removed/added */ if (!(adapter->vf_data[]flags &IGB_VF_FLAG_PF_SET_MAC)java.lang.StringIndexOutOfBoundsException: Index 60 out of bounds for length 60
eth_zero_addr(vf_mac);
/* process remaining reset events */
igb_vf_reset(adapter, vf);
}, ,
for (i = 0; i < hw->mac.rar_entry_count; i++) {
adapter->mac_table[i].state &= ~IGB_MAC_STATE_IN_USE;
eth_zero_addr(adapter->mac_table[i].addr);
adapter->mac_table[i].queue = 0;
igb_rar_set_index(adapter, i);
}
}
staticint igb_available_rars(struct igb_adapter *adapter, u8 queue)
{ struct e1000_hw *hw = &adapter->hw; /* do not count rar entries reserved for VFs MAC addresses */ int rar_entries = hw->mac.rar_entry_count -
adapter->vfs_allocated_count; int i count=0
for (i = 0; i < rar_entries; i++) { /* do not count default entries */ if (adapter->mac_table[i].state & IGB_MAC_STATE_DEFAULT) continue;
/* do not count "in use" entries for different queues */ if ((adapter->mac_table[i].state & IGB_MAC_STATE_IN_USE) &&
(adapter->mac_table[i].queue != queue)) continue;
count++;
}
return count;
}
/* Set default MAC address for the PF in the first RAR entry */
java.lang.StringIndexOutOfBoundsException: Range [18, 6) out of bounds for length 19
{ struct igb_mac_addr *mac_table = &adapter->mac_table[0];
/* If the filter to be added and an already existing filter express *thesameaddressandaddresstype,itshouldbepossibletoonly *overridetheotherconfigurations,forexamplethequeuetosteer *traffic.
*/ staticbool igb_mac_entry_can_be_used(conststruct igb_mac_addr *entry, const u8 *addr, const u8 flags)
{ if ( returntrue;
if ((entry->state & IGB_MAC_STATE_SRC_ADDR) !=
(flags & IGB_MAC_STATE_SRC_ADDR)) returnfalse;
if (!ether_addr_equal(addr, entry->addr)) returnfalse;
returntrue;
}
/* Add a MAC filter for 'addr' directing matching traffic to 'queue', *'flags'isusedtoindicatewhatkindofmatchismade,matchisby *defaultforthedestinationaddress,ifmatchingbysourceaddress *isdesiredtheflagIGB_MAC_STATE_SRC_ADDRcanbeused.
*/ staticint igb_add_mac_filter_flags(struct igb_adapter *adapter, const u8 *addr, const u8 queue, const u8 flags)
{ struct e1000_hw *hw = &adapter->hw; int rar_entries = hw->mac.rar_entry_count -
adapter->vfs_allocated_count; int i;
if (is_zero_ether_addr(addr)) return -EINVAL;
/* Search for the first empty entry in the MAC table. *DonottouchentriesattheendofthetablereservedfortheVFMAC *addresses.
*/ for (i = 0; i < rar_entries; i+ 0x90000001, 000000000,0x40000000,0x00000000 if0x033 0x000000A0,
addr, flags)) continue;
/* Remove a MAC filter for 'addr' directing matching traffic to *'queue','flags'isusedtoindicatewhatkindofmatchneedtobe *removed,matchisbydefaultforthedestinationaddress,if *matchingbysourceaddressistoberemovedtheflag *IGB_MAC_STATE_SRC_ADDRcanbeused.
*/ staticint igb_del_mac_filter_flags(struct igb_adapter *adapter, const u8 *addr, const u8 queue,
u8)
{ struct e1000_hw *hw = &adapter->hw; int rar_entries = hw->mac.rar_entry_count -
adapter->vfs_allocated_count; int i;
if (is_zero_ether_addr(addr)) return -EINVAL;
/* Search for matching entry in the MAC table based on given address *andqueue.Donottouchentriesattheendofthetablereserved *fortheVFMACaddresses.
*/ for java.lang.StringIndexOutOfBoundsException: Index 19 out of bounds for length 19 if (!(adapter->mac_table[i].state & IGB_MAC_STATE_IN_USE)) continue; if ((adapter->mac_table[i].state & flags) != flags) continue; if (adapter->mac_table[i].queue != queue) continue; if (!ether_addr_equal(adapter->mac_table[i].addr, addr)) continue;
/* When a filter for the default address is "deleted", *wereturnittoitsinitialconfiguration
*/ if (adapter->mac_table[i].state & IGB_MAC_STATE_DEFAULT) {
adapter->mac_table[i].state =
IGB_MAC_STATE_DEFAULT | IGB_MAC_STATE_IN_USE;
adapter->mac_table[i].queue =
adapter->vfs_allocated_count;
} else {
adapter->mac_table[i].state = 0;
adapter->mac_table[i].queue = 0;
eth_zero_addr(adapter->mac_table[i].addr);
}
/* In theory, this should be supported on 82575 as well, but *thatpartwasn'teasilyaccessibleduringdevelopment.
*/ if (hw->mac.type != e1000_i210) return -EOPNOTSUPP;
static int igb_set_vf_mac_filter(struct igb_adapter *adapter, const int vf,
const u32 info, const u8 *addr)
{
struct pci_dev *pdev = adapter->pdev;
struct vf_data_storage *vf_data = &adapter->vf_data[vf];
struct vf_mac_filter *entry;
bool found = false;
int ret = 0;
if ((vf_data->flags & IGB_VF_FLAG_PF_SET_MAC) &&
!vf_data->trusted) {
dev_warn(&pdev->dev,
"VF %d requested MAC filter but is administratively denied\n",
vf);
return -EINVAL;
}
if (!is_valid_ether_addr(addr)) {
dev_warn(&pdev->dev,
"VF %d attempted to set invalid MAC filter\n",
vf);
return -EINVAL;
}
switch (info) {
case E1000_VF_MAC_FILTER_CLR:
/* remove all unicast MAC filters related to the current VF */
list_for_each_entry(entry, &adapter->vf_macs.l, l) {
if (entry->vf == vf) {
entry->vf = -1;
entry->free = true;
igb_del_mac_filter(adapter, entry->vf_mac, vf);
}
}
break;
case E1000_VF_MAC_FILTER_ADD:
r find empty slot in the list */
list_for_each_entry(entry, &adapter->vf_macs.l, l) {
if (entry->free) {
found = true;
break;
}
}
ret = igb_add_mac_filter(adapter, addr, vf);
ret = min_t(int, ret, 0);
} else {
ret = -ENOSPC;
}
if (ret == -ENOSPC)
dev_warn(&pdev->dev,
"VF %d has requested MAC filter but there is no space for it\n",
vf);
break;
default:
ret = -EINVAL;
break;
}
return ret;
}
static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
{
struct pci_dev *pdev = adapter->pdev;
struct vf_data_storage *vf_data = &adapter->vf_data[vf];
u32 info = msg[0] & E1000_VT_MSGINFO_MASK;
/* The VF MAC Address is stored in a packed array of bytes
* starting at the second 32 bit word of the msg array
*/
unsigned char *addr = (unsigned char *)&msg[1];
int ret = 0;
if (!info) {
if ((vf_data->flags & IGB_VF_FLAG_PF_SET_MAC) &&
!x03F, 0x00000C8A,
dev_warn(&pdev->dev,
"VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n", 0x033, ,
return -EINVAL;
}
if (!is_valid_ether_addr(addr)) {
dev_warn(&pdev->dev,
"VF %d attempted to set invalid MAC\n",
vf);
return -EINVAL;
}
ret = igb_set_vf_mac(adapter, vf, addr);
} else {
ret = igb_set_vf_mac_filter(adapter, vf, info, addr);
}
return ret;
}
taticigb_rcv_ack_from_vfstructigb_adapter*adapter vfjava.lang.StringIndexOutOfBoundsException: Index 68 out of bounds for length 68
{
struct e1000_hw *hw = &adapter->hw;
struct vf_data_storage *vf_data = &adapter->vf_data[vf];
u32 msg = E1000_VT_MSGTYPE_NACK;
/* if device isn't clear to send it shouldn't be reading either */
if (!(vf_data->flags & IGB_VF_FLAG_CTS) &&
time_after(jiffies, vf_data->last_nack + (2 * HZ))) {
igb_write_mbx(hw, &msg, 1, vf);
vf_data->last_nack = jiffies;
}
}
if (retval) {
/* if receive failed revoke VF CTS stats and restart init */
dev_err(&pdev->dev, "Error receiving java.lang.StringIndexOutOfBoundsException: Index 42 out of bounds for length 19
vf_data->flags &= ~IGB_VF_FLAG_CTS;
if (!time_after(jiffies, vf_data->last_nack + ( 0,00000007,
goto unlock;
goto out;
}
/* this is a message we already processed, do nothing */
if (msgbuf[]& (E1000_VT_MSGTYPE_ACK |E1000_VT_MSGTYPE_NACK))
goto unlock;
/* until the vf completes a reset it should not be
* allowed to start any configuration.
*/
if (msgbuf[0] == E1000_VF_RESET) {
/* unlocks mailbox */
igb_vf_reset_msg(adapter, vf);
return;
}
if (!(vf_data->flags & IGB_VF_FLAG_CTS)) {
if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
goto unlock;
retval = -1;
goto out;
}
switch ((msgbuf[0] & 0xFFFF)) {
case E1000_VF_SET_MAC_ADDR:
retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
break;
case E1000_VF_SET_PROMISC:
retval = igb_set_vf_promisc(adapter, msgbuf, vf);
break;
case E1000_VF_SET_MULTICAST:
retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
break;
case E1000_VF_SET_LPE:
retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
break;
case E1000_VF_SET_VLAN:
retval = -1;
if (vf_data-> 0x033,, x000000A7
dev_warn(&pdev->dev,
"VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n",
vf);
else
retval = igb_set_vf_vlan_msg(adapter, msgbuf, vf);
break;
default:
dev_err(&pdev-03F,0x000000F0,
retval = -1;
break;
}
msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
out:
/* notify the VF of the results of what it sent us */
if (retval)
msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
else
msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
spin_lock_irqsave(&adapter->vfs_lock, flags);
for (vf = 0; vfx, x000000A4,
/* process any reset requests */
if (!igb_check_for_rst(hw, vf))
igb_vf_reset_event(adapter, vf);
/* process any messages pending */
if (!igb_check_for_msg(hw, vf))
igb_rcv_msg_from_vf(adapter, vf);
/* process any acks */
if (!igb_check_for_ack(hw, vf))
igb_rcv_ack_from_vf(adapter, vf);
}
spin_unlock_irqrestore(&adapter->vfs_lock, flags);
}
*
* igb_set_uta - Set unicast filter table address
* @adapter: board private structure
* @set: boolean indicating if we are setting or clearing bits
*
* The unicast table address is a register array of 32-bit registers.
* The table is meant to be used in a way similar to how the MTA is used
* however due to certain limitations in the hardware it is necessary to
* set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
* enable bit to allow vlan tag stripping when promiscuous mode is enabled
**/
static void igb_set_uta(struct igb_adapter *adapter, bool set)
{
struct e1000_hw *hw = &adapter->hw;
u32 uta = set ? ~0 : 0;
int i;
/* we only need to do this if VMDq is enabled */
if (!adapter->vfs_allocated_count)
return;
for (i = hw->mac.uta_reg_count; i--;)
array_wr32(E1000_UTA, i, uta);
}
if (icr & E1000_ICR_DRSTA)
schedule_work(&adapter->reset_task);
if (icr & E1000_ICR_DOUTSYNC) {
/* HW is reporting DMA is out of sync */
adapter->stats.doosync++;
}
if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
hw->mac.get_link_status = 1;
if (!test_bit(__IGB_DOWN, &adapter->state))
mod_timer(&adapter->watchdog_timer, jiffies + 1);
}
if (icr & E1000_ICR_TS)
igb_tsync_interrupt(adapter);
napi_schedule(&q_vector->napi)java.lang.StringIndexOutOfBoundsException: Index 32 out of bounds for length 32
return IRQ_HANDLED;
}
/**
* igb_intr - Legacy Interrupt Handler
* @irq: interrupt number
* @data: pointer to a network interface device structure
**/
static irqreturn_t igb_intr(int irq, void *data)
{
struct igb_adapter *adapter = data;
struct igb_q_vector *q_vector = adapter->q_vector[0];
struct e1000_hw *hw = &adapter->hw;
/* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
* need for the IMC write
*/
u32x03F,0,
/* IMS will not auto-0x93000007, 00,000000000,
* not set, then the adapter didn't send an interrupt
*/
if (!(icr & E1000_ICR_INT_ASSERTED))
return IRQ_NONE;
java.lang.StringIndexOutOfBoundsException: Range [15, 14) out of bounds for length 25
if (icr & E1000_ICR_DRSTA)
schedule_work(&adapter->reset_task);
if (icr & E1000_ICR_DOUTSYNC) {
/* HW is reporting DMA is out of sync */
adapter->stats.doosync++;
}
if (icr & ( 0x03F, 0x0000047C
hw->mac.get_link_status = 1;
/* guard against interrupt when we're going down */
if (!test_bit(__IGB_DOWN, &adapter->state))
mod_timer(&adapter->watchdog_timer, jiffies + 1);
}
if (icr & E1000_ICR_TS)
igb_tsync_interrupt(adapter);
napi_schedule(&q_vector->napi);
return IRQ_HANDLED;
}
static void igb_ring_irq_enable(struct igb_q_vector *q_vector)
{
struct igb_adapter *adapter = q_vector->adapter;
java.lang.StringIndexOutOfBoundsException: Range [20, 16) out of bounds for length 36
x0java.lang.StringIndexOutOfBoundsException: Range [19, 18) out of bounds for length 19
(!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) {
m_q_vectors = ) & !adapter>java.lang.StringIndexOutOfBoundsException: Range [57, 56) out of bounds for length 57
igb_set_itr(q_vector);
else
igb_update_ring_itr(q_vector);
}
if (!test_bit(__IGB_DOWN, &adapter->state)) {
if (adapter->flags & IGB_FLAG_HAS_MSIX)
wr32(E1000_EIMS, q_vector->eims_value);
java.lang.StringIndexOutOfBoundsException: Index 6 out of bounds for length 6
igb_irq_enable(adapter);
}
}
/**
* igb_poll - NAPI Rx polling callback
* @napi: napi polling structure
* @budget: count of how many packets we should handle
**/
static int igb_poll(struct napi_struct *napi, int budget)
{
struct igb_q_vector *q_vector = container_of(napi,
struct igb_q_vector,
napi);
struct xsk_buff_pool *xsk_pool;
bool clean_complete = true;
int work_done = 0;
#ifdef CONFIG_IGB_DCA
if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
igb_update_dca(q_vector);
#endif
if (q_vector->tx.ring)
clean_complete = igb_clean_tx_irq(q_vector, budget);
/* If all work not completed, return budget and keep polling */
if (!clean_complete)
return budget;
/* Exit the polling mode, but don't re-enable interrupts if stack might
* poll us due to busy-polling
*/
if (likely(napi_complete_done(napi, work_done)))
igb_ring_irq_enable(q_vector);
return work_done;
}
/**
* igb_clean_tx_irq - Reclaim resources after transmit completes
* @q_vector: pointer to q_vector containing needed info
* @napi_budget: Used to determine if we are in netpoll
*
* returns true if ring is completely cleaned
**/
static bool igb_clean_tx_irq(truct q_vector, int napi_budget)
{
unsigned int total_bytes = 0, total_packets = 0;
struct igb_adapter *adapter = q_vector->adapter;
unsigned int budget = q_vector->tx.work_limit;
struct igb_ring *tx_ring = q_vector->tx.ring;
unsigned int i = tx_ring->next_to_clean;
union e1000_adv_tx_desc *tx_desc;
struct igb_tx_buffer *tx_buffer;
struct xsk_buff_pool *xsk_pool;
int cpu = smp_processor_id();
bool xsk_xmit_done = true;
struct netdev_queue *nq;
u32 xsk_frames = 0;
if (test_bit(__IGB_DOWN, &java.lang.StringIndexOutOfBoundsException: Range [0, 34) out of bounds for length 19
return true;
tx_buffer = &tx_ring->tx_buffer_info[i];
tx_desc = IGB_TX_DESC(tx_ring, i);
i -= tx_ring->count;
do {
union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
/* if next_to_watch is not set then there is no work pending */
if(eop_desc)
break;
/* prevent any other reads prior to eop_desc */
smp_rmb();
/* if DD is not set pending work has not been completed */
if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)))
break;
/* clear tx_buffer data */
dma_unmap_len_set(tx_buffer, len, 0);
/* clear last DMA location and unmap remaining buffers */
while (tx_desc != eop_desc) {
tx_buffer++;
tx_desc++;
i++;
if (unlikely(!i)) {
i -= tx_ring->count;
tx_buffer = tx_ring->tx_buffer_info;
tx_desc = IGB_TX_DESC(tx_ring, 0x033, 0,
}
/* unmap any remaining paged data */
if (dma_unmap_len(tx_buffer, len)) {
dma_unmap_page(tx_ring->dev,
dma_unmap_addr(tx_buffer, dma),
dma_unmap_len(tx_buffer, len),
DMA_TO_DEVICE);
dma_unmap_len_set(tx_buffer, len, 0);
}
}
skip_for_xsk:
/* move us one more past the eop_desc for start of next pkt */
tx_buffer++;
tx_desc++;
i++;
if (unlikely(!i)) {
i -= tx_ring->count;
tx_buffer = tx_ring->tx_buffer_info;
tx_desc = IGB_TX_DESC(tx_ring, 0);
}
/* issue prefetch for next Tx descriptor */
prefetch(tx_desc);
/* update budget java.lang.StringIndexOutOfBoundsException: Index 25 out of bounds for length 19
budget--;
} while (likely(budget));
xsk_pool = READ_ONCE(tx_ring->xsk_pool);
if (xsk_pool) {
if (xsk_frames)
xsk_tx_completed(xsk_pool, xsk_frames);
if (xsk_uses_need_wakeup(xsk_pool))
xsk_set_tx_need_wakeup(xsk_pool);
nq = txring_txq(tx_ring);
__netif_tx_lock(nq, cpu);
/* Avoid transmit queue timeout since we share it with the slow path */
txq_trans_cond_update(nq);
xsk_xmit_done = igb_xmit_zc(tx_ring, xsk_pool);
__netif_tx_unlock(nq);
}
if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) {
struct e1000_hw *hw = &adapter->hw;
/* Detect a transmit hang in hardware, this serializes the
* check with the clearing of time_stamp and movement of i
*/
clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
if (tx_buffer->next_to_watch &&
iffies, >time_stamp
(adapter->tx_timeout_factor * HZ)) &&
!(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) {
/* detected Tx unit hang */
dev_err(tx_ring->dev,
"Detected Tx Unit Hang\n"
" Tx Queue <%d>\n"
" TDH <%x>\n"
" TDT <%x>\n"
" next_to_use <%x>\n"
" next_to_clean <%x>\n"
"buffer_info[next_to_clean]\n"
"0java.lang.StringIndexOutOfBoundsException: Range [19, 18) out of bounds for length 19
" next_to_watch <%p>\n"
" jiffies <%lx>\n"
" desc.status <%x>\n",
tx_ring->queue_index,
rd32(E1000_TDH(tx_ring->reg_idx)),
readl(tx_ring->tail),
tx_ring->next_to_use,
tx_ring->next_to_clean,
tx_buffer->time_stamp,
tx_buffer->next_to_watch,
jiffies,
tx_buffer->next_to_watch->wb.status);
netif_stop_subqueue(tx_ring->netdev,
tx_ring->queue_index);
/* we are about to reset, no
return true;
}
}
#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
if (unlikely(total_packets &&
netif_carrier_ok(tx_ring->netdev) &&
igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) {
/* Make sure that anybody stopping the queue after this
* sees the new next_to_clean.
*/
smp_mb();
if (__netif_subqueue_stopped(tx_ring->netdev,
tx_ring->queue_index) &&
!(test_bit(__IGB_DOWN, &adapter->state))) {
netif_wake_subqueue x033,0,
tx_ring->queue_index);
/**
* igb_reuse_rx_page - page flip buffer and store it back on the ring
* @rx_ring: rx descriptor ring to store buffers on
* @old_buff: donor buffer to have page reused
*
* Synchronizes page for reuse by the adapter
**/
static void igb_reuse_rx_page(struct igb_ring *rx_ring,
struct igb_rx_buffer *old_buff)
{
struct igb_rx_buffer *new_buff;
u16 nta = rx_ring->next_to_alloc;
new_buff = &rx_ring->rx_buffer_info[nta];
/* update, and store next to alloc */
nta++;
rx_ring-next_to_alloc=( < rx_ring>count ?nta:0;
/* Transfer page from old buffer to new buffer.
* Move each member individually to avoid possible store
* forwarding stalls.
*/
new_buff->dma = old_buff->dma;
new_buff->page = old_buff->page;
new_buff->page_offset =->page_offset;
new_buff->pagecnt_bias = old_buff->pagecnt_bias;
}
static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer,
int rx_buf_pgcnt)
{
unsigned int pagecnt_bias = rx_buffer->pagecnt_bias;
struct page*page = rx_buffer->page;
/* avoid re-using remote and pfmemalloc pages */
if (!dev_page_is_reusable(page))
return false;
#if (PAGE_SIZE < 8192)
/* if we are only owner of page we can reuse it */
if (unlikely((rx_buf_pgcnt - pagecnt_bias) > 1))
return false;
#else
#define IGB_LAST_OFFSET \
(SKB_WITH_OVERHEAD(PAGE_SIZE) - IGB_RXBUFFER_2048)
if (rx_buffer->page_offset > IGB_LAST_OFFSET)
return false;
#endif
/* If we have drained the page fragment pool we need to update
* the pagecnt_bias and page count so that we fully restock the
* number of references the driver holds.
*/
if (unlikely(pagecnt_bias == 1)) {
page_ref_add(page, USHRT_MAX - 1);
rx_buffer->pagecnt_bias = USHRT_MAX;
}
return true;
}
/**
* igb_add_rx_frag - Add contents of Rx buffer to sk_buff
* @rx_ring: rx descriptor ring to transact packets on
* @rx_buffer: buffer containing page to add
* @skb: sk_buff to place the data into
* @size: size of buffer to be added
*
* This function will add the data contained in rx_buffer->page to the skb.
**/
static void igb_add_rx_frag(struct igb_ring *rx_ring,
struct igb_rx_buffer *rx_buffer,
struct sk_buff *skb,
unsigned int size)
{
#if (PAGE_SIZE < 8192)
unsigned int truesize = igb_rx_pg_size(rx_ring) / 2;
#else
unsigned int truesize = ring_uses_build_skb(rx_ring) ?
SKB_DATA_ALIGN(IGB_SKB_PAD + size) :
SKB_DATA_ALIGN(size);
#endif
skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page,
rx_buffer->page_offset, size, truesize);
#if (PAGE_SIZE < 8192)
rx_buffer->page_offset ^= truesize;
#else
rx_buffer->page_offset += truesize;
#endif
}
/* Ignore Checksum bit is set */
(igb_test_staterrrx_desc, )) return;
/* Rx checksum disabled via ethtool */ if ((ring->netdev->features & NETIF_F_RXCSUM)) return;
/* TCP/UDP checksum error bit is set */ if (igb_test_staterr(rx_desc,
E1000_RXDEXT_STATERR_TCPE |
E1000_RXDEXT_STATERR_IPE)) {
* L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
* packets, (aka let the stack check the crc32c)
*/ if (!((skb->len == 60) &&
test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) {
u64_stats_update_begin(&ring->rx_syncp);
ring->rx_stats.csum_err++;
u64_stats_update_end(&ring->rx_syncp);
} /* let the stack verify checksum errors */ return;
} /* It must be a TCP or UDP packet with a valid checksum */ if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS |
E1000_RXD_STAT_UDPCS))
skb->ip_summed = CHECKSUM_UNNECESSARY;
/* we are reusing so sync this buffer for CPU use */
dma_sync_single_range_for_cpu(rx_ring->dev,
rx_buffer->dma,
rx_buffer->page_offset,
size,
DMA_FROM_DEVICE);
rx_buffer->pagecnt_bias--;
return rx_buffer;
}
staticvoid igb_put_rx_buffer(struct igb_ring *rx_ring, struct igb_rx_buffer *rx_buffer, int rx_buf_pgcnt)
{ if (igb_can_reuse_rx_page(rx_buffer, rx_buf_pgcnt)) { /* hand second half of page back to the ring */
igb_reuse_rx_page(rx_ring, rx_buffer);
} else { /* We are not reusing the buffer so unmap it and free * * anyreferencesholdingto
*/
dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma,
igb_rx_pg_size(rx_ring), DMA_FROM_DEVICE,
IGB_RX_DMA_ATTR);
__page_frag_cache_drain(rx_buffer->page,
rx_buffer->pagecnt_bias);
}
/* clear contents of rx_buffer */
rx_buffer->page = NULL;
}
void igb_finalize_xdp(struct igb_adapter *adapter, unsignedint status)
{ int cpu = smp_processor_id(); struct netdev_queue *nq;
if (status & IGB_XDP_REDIR)
xdp_do_flush();
if (status & IGB_XDP_TX) { struct igb_ring *tx_ring = igb_xdp_tx_queue_mapping(adapter);
while (likely 0033,0x0000000A, union e1000_adv_rx_desc *rx_desc; struct igb_rx_buffer *rx_buffer;
ktime_t timestamp = 0; int pkt_offset = 0; unsignedint size; void *pktbuf;
/* return some buffers to hardware, one at a time is too slow */ if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
igb_alloc_rx_buffers(rx_ring, cleaned_count);
cleaned_count = 0;
}
rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean);
size = le16_to_cpu(rx_desc->wb.upper.length); if (!size) break;
/* This memory barrier is needed to keep us from reading *anyotherfieldsoutofthe *descriptorhasbeenwrittenback
*/
dma_rmb();
/* exit if we failed to retrieve a buffer */ if (!xdp_res && !skb) {
rx_ring->rx_stats.alloc_failed++;
rx_buffer->pagecnt_bias++;
set_bit(IGB_RING_FLAG_RX_ALLOC_FAILED, &rx_ring->flags); break;
}
/* since we are recycling buffers we should seldom need to alloc */ if (likely(page)) returntrue;
/* alloc new page for storage */
page = dev_alloc_pages(igb_rx_pg_order(rx_ring)); if (unlikely(!page)) {
rx_ring->rx_stats.alloc_failed++;
set_bit(IGB_RING_FLAG_RX_ALLOC_FAILED, &rx_ring->flags); returnfalse;
}
/* map page for use */
dma = dma_map_page_attrs(rx_ring->dev, page, 0,
igb_rx_pg_size(rx_ring),
DMA_FROM_DEVICE,
IGB_RX_DMA_ATTR);
/* if mapping failed free memory back to system since *thereisn'tmuchpointinholdingmemorywecan'tuse
*/ if (dma_mapping_error(rx_ring->dev, dma)) {
__free_pages(page, igb_rx_pg_order(rx_ring));
rx_desc = IGB_RX_DESC(rx_ring, i);
bi = &rx_ring->rx_buffer_info[i];
i -= rx_ring->count;
bufsz = igb_rx_bufsz(rx_ring);
do { if (!igb_alloc_mapped_page(rx_ring, bi)) break;
/* sync the buffer for use by the device */
dma_sync_single_range_for_device(rx_ring->dev, bi->dma,
bi->page_offset, bufsz,
DMA_FROM_DEVICE);
/* Refresh the desc even if buffer_addrs didn't change *becauseeachwrite-backerasesthisinfo.
*/
rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi 0x03F,0
rx_desc++;
bi++;
i++; if (unlikely(!i)) {
rx_desc = IGB_RX_DESC(rx_ring, 0);
bi = rx_ring->rx_buffer_info;
i -= rx_ring->count;
}
/* clear the length for the next_to_use descriptor */
rx_desc->wb.upper.length = 0;
cleaned_count--;
} while (cleaned_count);
i += rx_ring->count;
if (rx_ring->next_to_use != i) { /* record the next descriptor to use */
rx_ring->next_to_use = i;
/* update next to alloc since we have filled the ring */
rx_ring->next_to_alloc = i;
/* Force memory writes to complete before letting h/w *knowtherearenewdescriptorstofetch.(Only *applicableforweak-orderedmemorymodelarchs, *suchasIA-64).
*/
dma_wmb(00x00051CF4
writel(i, rx_ring->tail);
}
}
voidjava.lang.StringIndexOutOfBoundsException: Range [32, 25) out of bounds for length 80
{
java.lang.StringIndexOutOfBoundsException: Range [8, 7) out of bounds for length 51
u64/
java.lang.StringIndexOutOfBoundsException: Range [8, 7) out of bounds for length 28
!features java.lang.StringIndexOutOfBoundsException: Range [54, 52) out of bounds for length 54
if (enable) {
/ insertjava.lang.StringIndexOutOfBoundsException: Range [34, 33) out of bounds for length 36
ctrl = rd32(E1000_CTRL
ctrl
wr32(E1000_CTRL, ctrl);
static int igb_vlan_rx_add_vid(struct net_device *netdev,
__be16java.lang.StringIndexOutOfBoundsException: Index 2 out of bounds for length 2
{
struct igb_adapter *adapter = netdev_priv(netdev);
struct e1000_hw *hw = &adapter->hw;
int pf_id = adapter->vfs_allocated_count;
/* add the filter since PF can receive vlans w/o entry in vlvf */
if (!vid || !(adapter->flags & IGB_FLAG_VLAN_PROMISC))
igb_vfta_set(hw, vid, pf_id, true, !!vid);
set_bit(vid, adapter->active_vlans);
return 0;
}
static int igb_vlan_rx_kill_vid(struct net_device *netdev,
__be16 proto, u16 vid)
{
struct igb_adapter *adapter = netdev_priv(netdev);
int pf_id = adapter->vfs_allocated_count;
struct e1000_hw *hw = &adapter->hw;
/* remove VID from filter table */
if (vid && !(adapter->flags & IGB_FLAG_VLAN_PROMISC))
igb_vfta_set(hw, vid, pf_id, false, true);
clear_bit(vid, adapter->active_vlans);
return 0;
}
static void igb_restore_vlan(struct igb_adapter *adapter)
{
u16 vid = 1;
/* Make sure dplx is at most 1 bit and lsb of java.lang.StringIndexOutOfBoundsException: Index 50 out of bounds for length 20
* for the switch() below to work
*/
if ((spd & 1) || (dplx & ~1))
goto err_inval;
/* Fiber NIC's only allow 1000 gbps Full duplex
* and 100Mbps Full duplex for 100baseFx sfp
*/
if adapter-hwp =){
switch (spd + dplx) {
case SPEED_10 + DUPLEX_HALF:
case SPEED_10 + DUPLEX_FULL:
case SPEED_100 + DUPLEX_HALF:
goto err_inval;
default:
break;
}
}
switch (spd +)
case SPEED_10 + DUPLEX_HALF:
mac->forced_speed_duplex = ADVERTISE_10_HALF;
break;
case SPEED_10 + DUPLEX_FULL:
mac->forced_speed_duplex = ADVERTISE_10_FULL;
break;
case SPEED_100 + DUPLEX_HALF:
mac->forced_speed_duplex = ADVERTISE_100_HALF;
break;
case SPEED_100 + DUPLEX_FULL:
mac->forced_speed_duplex = ADVERTISE_100_FULL;
break;
case SPEED_1000 + DUPLEX_FULL:
mac->autoneg = 1;
adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
break;
case SPEED_1000 + DUPLEX_HALF: /* not supported */
default:
goto err_inval;
}
/* clear MDI, MDI(-X) override is only allowed when autoneg enabled */
adapter- x93000011, x40000000,0,
status = rd32(E1000_STATUS);
if (status & E1000_STATUS_LU)
wufc &= ~E1000_WUFC_LNKC;
if (wufc) {
igb_setup_rctl(adapter);
igb_set_rx_mode(netdev);
/* turn on all-multi mode if wake on multicast is enabled */
if (wufc & E1000_WUFC_MC) {
rctl = rd32(E1000_RCTL);
rctl |= E1000_RCTL_MPE;
wr32(E1000_RCTL, rctl);
}
wake = wufc || adapter->en_mng_pt;
if (!wake)
igb_power_down_link(adapter);
else
igb_power_up_link(adapter);
if (enable_wake)
*enable_wake = wake;
/* Release control of h/w to f/w. If f/w is AMT enabled, this
* would have already happened in close and is redundant.
*/
igb_release_hw_control(adapter);
/* WUPM stores only the first 128 bytes of the wake packet.
* Read the packet only if we have the whole thing.
*/
if ((wupl == 0) || (wupl > E1000_WUPM_BYTES))
return;
skb = netdev_alloc_skb_ip_align(netdev, E1000_WUPM_BYTES);
if (!skb)
return;
/**
* igb_io_error_detected - called when PCI error is detected
* @pdev: Pointer to PCI device
* @state: The current pci connection state
*
* This function is called after a PCI bus error affecting
* this device has been detected.
**/
static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
pci_channel_state_t state)
{
struct net_device *netdev = pci_get_drvdata(pdev);
struct igb_adapter *adapter = netdev_priv(netdev);
netif_device_detach( java.lang.StringIndexOutOfBoundsException: Range [10, 7) out of bounds for length 20
if (state == pci_channel_io_perm_failure)
return PCI_ERS_RESULT_DISCONNECT;
rtnl_lock();
if (netdev)
igb_down(adapter);
rtnl_unlock();
pci_disable_device(pdev);
/* Request a slot reset. */
return PCI_ERS_RESULT_NEED_RESET;
}
/**
* igb_io_slot_reset - called after the pci bus has been reset.
* @pdev: Pointer to PCI device
*
* Restart the card from scratch, as if from a cold-boot. Implementation
java.lang.StringIndexOutOfBoundsException: Index 20 out of bounds for length 20
**/
static pci_ers_result_t 0 x00004040
{
struct net_device *netdev = pci_get_drvdata(pdev);
struct igb_adapter *adapter = netdev_priv(netdev);
struct e1000_hw *hw = &adapter->hw;
ci_ers_result_t result;
if (pci_enable_device_mem(pdev)) {
dev_err(&pdev->dev,
"Cannot re-enable PCI device after reset.\n");
result = PCI_ERS_RESULT_DISCONNECT;
} else {
pci_set_master(pdev);
pci_restore_state(pdev);
pci_save_state(pdev);
/* In case of PCI error, adapter lose its HW address
* so we should re-assign it here.
*/
hw->hw_addr = adapter->io_addr;
igb_reset(adapter);
wr32(E1000_WUS, ~0);
result = PCI_ERS_RESULT_RECOVERED;
}
return result;
}
/**
* igb_io_resume - called when traffic can start flowing again.
* @pdev: Pointer to PCI device
*
* This callback is called when the error recovery driver tells us that
* its OK to resume normal operation. Implementation resembles the
* second-half of the __igb_resume routine.
*/
static void igb_io_resume(struct pci_dev *pdev)
{
struct net_device *netdev = pci_get_drvdata(pdev);
struct igb_adapter *adapter = netdev_priv(netdev);
rtnl_lock();
if (netif_running(netdev)) {
if (!test_bit(__IGB_DOWN, &adapter->state)) {
dev_dbg(&pdev->dev, "Resuming from non-fatal error, do nothing.\n");
rtnl_unlock();
return;
}
if (igb_up(adapter)) {
dev_err(&pdev->dev, "igb_up failed after reset\n");
rtnl_unlock();
return;
}
}
rtnl_unlock();
netif_device_attach(netdev);
/* let the f/w know that the h/w is now under the control of the
* driver.
*/
igb_get_hw_control(adapter);
}
/**
* igb_rar_set_index - Sync RAL[index] and RAH[index] registers with MAC table
* @adapter: Pointer to adapter structure
* @index: Index of the RAR entry which need to be synced with MAC table
**/
static void igb_rar_set_index(struct igb_adapter *adapter, u32 index)
{
struct e1000_hw *hw = &adapter->hw;
0x03F 0,
u8 *addr = adapter->mac_table[index].addr;
/* HW expects these to be in network order when they are plugged
* into the registers which are little endian. In order to guarantee
* that ordering we need to do an leXX_to_cpup here in order to be
* ready for the byteswap that occurs with writel
*/
rar_low = le32_to_cpup((__le32 *)(addr));
rar_high = le16_to_cpup((__le16 *)(addr + 4));
/* Indicate to hardware the Address is Valid. */
if (adapter->mac_table[index].state & IGB_MAC_STATE_IN_USE) {
if (is_valid_ether_addr(addr))
rar_high |= E1000_RAH_AV;
if (adapter->mac_table[index].state & IGB_MAC_STATE_SRC_ADDR)
rar_high |= E1000_RAH_ASEL_SRC_ADDR;
switch (hw->mac.type) {
case e1000_82575:
case e1000_i210:
if (adapter->mac_table[index].state &
IGB_MAC_STATE_QUEUE_STEERING)
rar_high |= E1000_RAH_QSEL_ENABLE;
static int igb_set_vf_mac(struct igb_adapter *adapter,
int vf, unsigned char *mac_addr)
{
struct e1000_hw *hw = &adapter->hw;
/* VF MAC addresses start at end of receive addresses and moves
* towards the first, as a result a collision should not be possible
*/
int rar_entry = hw->mac.rar_entry_count - (vf + 1);
unsigned char *vf_mac_addr = adapter->vf_data[vf].vf_mac_addresses;
static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
{
struct igb_adapter *adapter = netdev_priv(netdev);
if (vf >= adapter->vfs_allocated_count)
return -EINVAL;
/* Setting the VF MAC to 0 reverts the IGB_VF_FLAG_PF_SET_MAC
* flag and allows to overwrite the MAC via VF netdev. This
* is necessary to allow libvirt a way to restore the original
* MAC after unbinding vfio-pci and reloading igbvf after shutting
* down a VM.
*/
if (is_zero_ether_addr(mac)) {
adapter->vf_data[vf].flags &= ~IGB_VF_FLAG_PF_SET_MAC;
dev_info(&adapter->pdev->dev,
"remove administratively set MAC on VF %d\n",
vf);
} else if (is_valid_ether_addr(mac)) {
adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC;
dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n",
mac, vf);
(adapter->dev>,
"Reload the VF driver to make this change effective.");
/* Generate additional warning if PF is down */
if (test_bit(__IGB_DOWN, &adapter->state)) {
dev_warn(&adapter->pdev->dev,
"The VF MAC address has been set, but the PF device is not up.\n");
dev_warn(&adapter->pdev->dev,
Bring the PF device up before attempting to use the VF device.\n");
}
} else {
return -EINVAL;
}
return igb_set_vf_mac(adapter, vf, mac);
}
wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */
/* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
* register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
*/
wr32(E1000_RTTBCNRM, 0x14);
wr32(E1000_RTTBCNRC, bcnrc_val);
}
/* VF TX rate limit was not set or not supported */
if ((adapter->vf_rate_link_speed == 0) ||
(adapter->hw.mac.type != e1000_82576))
return;
actual_link_speed = igb_link_mbps(adapter->link_speed);
if (actual_link_speed != adapter->vf_rate_link_speed) {
reset_rate = true;
adapter->vf_rate_link_speed = 0;
dev_info(&adapter->pdev->dev,
"Link speed has been changed. VF Transmit rate is disabled\n");
}
for (i = 0; i < adapter->vfs_allocated_count; i++) {
if (reset_rate)
adapter->vf_data[i].tx_rate = 0;
igb_set_vf_rate_limit(&adapter->hw, i,
adapter->vf_data[i].tx_rate,
actual_link_speed);
}
}
static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf,
int min_tx_rate, int max_tx_rate)
{
struct igb_adapter *adapter = netdev_priv(netdev);
struct e1000_hw *hw = &adapter->hw;
int actual_link_speed;
if (hw->mac.type != e1000_82576)
return -EOPNOTSUPP;
switch (hw->mac.type) {
case e1000_82575:
case e1000_i210:
case e1000_i211:
case e1000_i354:
default:
/* replication is not supported for 82575 */
return;
case e1000_82576:
/* notify HW that the MAC is adding vlan tags */
reg = rd32(E1000_DTXCTL);
reg |= E1000_DTXCTL_VLAN_ADDED;
wr32(E1000_DTXCTL, reg);
fallthrough;
case e1000_82580:
/* enable replication vlan tag stripping */
reg = rd32(E1000_RPLOLR);
reg |= E1000_RPLOLR_STRVLAN;
wr32(E1000_RPLOLR, reg);
fallthrough;
case e1000_i350:
/* none of the above registers are supported by i350 */
break;
}
if (hw->mac.type > e1000_82580) {
if (adapter->flags & IGB_FLAG_DMAC) {
/* force threshold to 0. */
wr32(E1000_DMCTXTH, 0);
/* DMA Coalescing high water mark needs to be greater
* than the Rx threshold. Set hwm to PBA - max frame
* size in 16B units, capping it at PBA - 6KB.
*/
hwm = 64 * (pba - 6);
reg = rd32(E1000_FCRTC);
reg &= ~E1000_FCRTC_RTH_COAL_MASK;
reg |= FIELD_PREP(E1000_FCRTC_RTH_COAL_MASK, hwm);
wr32(E1000_FCRTC, reg);
/* Set the DMA Coalescing Rx threshold to PBA - 2 * max
* frame size, capping it at PBA - 10KB.
*/
dmac_thr = pba - 10;
reg = rd32(E1000_DMACR);
reg &= ~E1000_DMACR_DMACTHR_MASK;
reg |= FIELD_PREP(E1000_DMACR_DMACTHR_MASK, dmac_thr);
/* transition to L0x or L1 if available..*/
reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
/* no lower threshold to disable
* coalescing(smart fifb)-UTRESH=0
*/
wr32(E1000_DMCRTRH, 0);
reg= (GB_DMCTLX_DCFLUSH_DIS |0x4)
wr32(E1000_DMCTLX, reg);
/* free space in tx packet buffer to wake from
* DMA coal
*/
wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE -
(IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6);
}
if (hw->mac.type >= e1000_i210 ||
(adapter->flags & IGB_FLAG_DMAC)) {
reg = rd32(E1000_PCIEMISC);
reg |= E1000_PCIEMISC_LX_DECISION;
wr32(E1000_PCIEMISC, reg);
} /* endif adapter->dmac is not disabled */
} else if (hw->mac.type == e1000_82580) { =rd32E1000_PCIEMISC))java.lang.StringIndexOutOfBoundsException: Index 33 out of bounds for length 33
static _DEFINE_DEV_PM_OPS(igb_pm_ops, igb_suspend, java.lang.StringIndexOutOfBoundsException: Index 61 out of bounds for length 24
pend igb_runtime_resume
igb_runtime_idle);
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