/** * __ew32_prepare - prepare to write to MAC CSR register on certain parts * @hw: pointer to the HW structure * * When updating the MAC CSR registers, the Manageability Engine (ME) could * be accessing the registers at the same time. Normally, this is handled in * h/w by an arbiter but on some parts there is a bug that acknowledges Host * accesses later than it should which could result in the register to have * an incorrect value. Workaround this by checking the FWSM register which * has bit 24 set while ME is accessing MAC CSR registers, wait if it is set * and try again a number of times.
**/ staticvoid __ew32_prepare(struct e1000_hw *hw)
{
s32 i = E1000_ICH_FWSM_PCIM2PCI_COUNT;
while ((er32(FWSM) & E1000_ICH_FWSM_PCIM2PCI) && --i)
udelay(50);
}
/** * e1000_desc_unused - calculate if we have unused descriptors * @ring: pointer to ring struct to perform calculation on
**/ staticint e1000_desc_unused(struct e1000_ring *ring)
{ if (ring->next_to_clean > ring->next_to_use) return ring->next_to_clean - ring->next_to_use - 1;
/** * e1000e_systim_to_hwtstamp - convert system time value to hw time stamp * @adapter: board private structure * @hwtstamps: time stamp structure to update * @systim: unsigned 64bit system time value. * * Convert the system time value stored in the RX/TXSTMP registers into a * hwtstamp which can be used by the upper level time stamping functions. * * The 'systim_lock' spinlock is used to protect the consistency of the * system time value. This is needed because reading the 64 bit time * value involves reading two 32 bit registers. The first read latches the * value.
**/ staticvoid e1000e_systim_to_hwtstamp(struct e1000_adapter *adapter, struct skb_shared_hwtstamps *hwtstamps,
u64 systim)
{
u64 ns; unsignedlong flags;
/** * e1000e_rx_hwtstamp - utility function which checks for Rx time stamp * @adapter: board private structure * @status: descriptor extended error and status field * @skb: particular skb to include time stamp * * If the time stamp is valid, convert it into the timecounter ns value * and store that result into the shhwtstamps structure which is passed * up the network stack.
**/ staticvoid e1000e_rx_hwtstamp(struct e1000_adapter *adapter, u32 status, struct sk_buff *skb)
{ struct e1000_hw *hw = &adapter->hw;
u64 rxstmp;
/* The Rx time stamp registers contain the time stamp. No other * received packet will be time stamped until the Rx time stamp * registers are read. Because only one packet can be time stamped * at a time, the register values must belong to this packet and * therefore none of the other additional attributes need to be * compared.
*/
rxstmp = (u64)er32(RXSTMPL);
rxstmp |= (u64)er32(RXSTMPH) << 32;
e1000e_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), rxstmp);
adapter->flags2 &= ~FLAG2_CHECK_RX_HWTSTAMP;
}
/** * e1000_receive_skb - helper function to handle Rx indications * @adapter: board private structure * @netdev: pointer to netdev struct * @staterr: descriptor extended error and status field as written by hardware * @vlan: descriptor vlan field as written by hardware (no le/be conversion) * @skb: pointer to sk_buff to be indicated to stack
**/ staticvoid e1000_receive_skb(struct e1000_adapter *adapter, struct net_device *netdev, struct sk_buff *skb,
u32 staterr, __le16 vlan)
{
u16 tag = le16_to_cpu(vlan);
e1000e_rx_hwtstamp(adapter, staterr, skb);
skb->protocol = eth_type_trans(skb, netdev);
if (staterr & E1000_RXD_STAT_VP)
__vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), tag);
napi_gro_receive(&adapter->napi, skb);
}
/** * e1000_rx_checksum - Receive Checksum Offload * @adapter: board private structure * @status_err: receive descriptor status and error fields * @skb: socket buffer with received data
**/ staticvoid e1000_rx_checksum(struct e1000_adapter *adapter, u32 status_err, struct sk_buff *skb)
{
u16 status = (u16)status_err;
u8 errors = (u8)(status_err >> 24);
skb_checksum_none_assert(skb);
/* Rx checksum disabled */ if (!(adapter->netdev->features & NETIF_F_RXCSUM)) return;
/* Ignore Checksum bit is set */ if (status & E1000_RXD_STAT_IXSM) return;
/* TCP/UDP checksum error bit or IP checksum error bit is set */ if (errors & (E1000_RXD_ERR_TCPE | E1000_RXD_ERR_IPE)) { /* let the stack verify checksum errors */
adapter->hw_csum_err++; return;
}
/* TCP/UDP Checksum has not been calculated */ if (!(status & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))) return;
/* It must be a TCP or UDP packet with a valid checksum */
skb->ip_summed = CHECKSUM_UNNECESSARY;
adapter->hw_csum_good++;
}
if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) { /* Force memory writes to complete before letting h/w * know there are new descriptors to fetch. (Only * applicable for weak-ordered memory model archs, * such as IA-64).
*/
wmb(); if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
e1000e_update_rdt_wa(rx_ring, i); else
writel(i, rx_ring->tail);
}
i++; if (i == rx_ring->count)
i = 0;
buffer_info = &rx_ring->buffer_info[i];
}
rx_ring->next_to_use = i;
}
/** * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split * @rx_ring: Rx descriptor ring * @cleaned_count: number to reallocate * @gfp: flags for allocation
**/ staticvoid e1000_alloc_rx_buffers_ps(struct e1000_ring *rx_ring, int cleaned_count, gfp_t gfp)
{ struct e1000_adapter *adapter = rx_ring->adapter; struct net_device *netdev = adapter->netdev; struct pci_dev *pdev = adapter->pdev; union e1000_rx_desc_packet_split *rx_desc; struct e1000_buffer *buffer_info; struct e1000_ps_page *ps_page; struct sk_buff *skb; unsignedint i, j;
i = rx_ring->next_to_use;
buffer_info = &rx_ring->buffer_info[i];
while (cleaned_count--) {
rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
for (j = 0; j < PS_PAGE_BUFFERS; j++) {
ps_page = &buffer_info->ps_pages[j]; if (j >= adapter->rx_ps_pages) { /* all unused desc entries get hw null ptr */
rx_desc->read.buffer_addr[j + 1] =
~cpu_to_le64(0); continue;
} if (!ps_page->page) {
ps_page->page = alloc_page(gfp); if (!ps_page->page) {
adapter->alloc_rx_buff_failed++; goto no_buffers;
}
ps_page->dma = dma_map_page(&pdev->dev,
ps_page->page,
0, PAGE_SIZE,
DMA_FROM_DEVICE); if (dma_mapping_error(&pdev->dev,
ps_page->dma)) {
dev_err(&adapter->pdev->dev, "Rx DMA page map failed\n");
adapter->rx_dma_failed++; goto no_buffers;
}
} /* Refresh the desc even if buffer_addrs * didn't change because each write-back * erases this info.
*/
rx_desc->read.buffer_addr[j + 1] =
cpu_to_le64(ps_page->dma);
}
if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) { /* Force memory writes to complete before letting h/w * know there are new descriptors to fetch. (Only * applicable for weak-ordered memory model archs, * such as IA-64).
*/
wmb(); if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
e1000e_update_rdt_wa(rx_ring, i << 1); else
writel(i << 1, rx_ring->tail);
}
i++; if (i == rx_ring->count)
i = 0;
buffer_info = &rx_ring->buffer_info[i];
}
no_buffers:
rx_ring->next_to_use = i;
}
/** * e1000_alloc_jumbo_rx_buffers - Replace used jumbo receive buffers * @rx_ring: Rx descriptor ring * @cleaned_count: number of buffers to allocate this pass * @gfp: flags for allocation
**/
i = rx_ring->next_to_use;
buffer_info = &rx_ring->buffer_info[i];
while (cleaned_count--) {
skb = buffer_info->skb; if (skb) {
skb_trim(skb, 0); goto check_page;
}
skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp); if (unlikely(!skb)) { /* Better luck next round */
adapter->alloc_rx_buff_failed++; break;
}
buffer_info->skb = skb;
check_page: /* allocate a new page if necessary */ if (!buffer_info->page) {
buffer_info->page = alloc_page(gfp); if (unlikely(!buffer_info->page)) {
adapter->alloc_rx_buff_failed++; break;
}
}
if (!buffer_info->dma) {
buffer_info->dma = dma_map_page(&pdev->dev,
buffer_info->page, 0,
PAGE_SIZE,
DMA_FROM_DEVICE); if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
adapter->alloc_rx_buff_failed++; break;
}
}
if (unlikely(++i == rx_ring->count))
i = 0;
buffer_info = &rx_ring->buffer_info[i];
}
if (likely(rx_ring->next_to_use != i)) {
rx_ring->next_to_use = i; if (unlikely(i-- == 0))
i = (rx_ring->count - 1);
/* Force memory writes to complete before letting h/w * know there are new descriptors to fetch. (Only * applicable for weak-ordered memory model archs, * such as IA-64).
*/
wmb(); if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
e1000e_update_rdt_wa(rx_ring, i); else
writel(i, rx_ring->tail);
}
}
/** * e1000_clean_rx_irq - Send received data up the network stack * @rx_ring: Rx descriptor ring * @work_done: output parameter for indicating completed work * @work_to_do: how many packets we can clean * * the return value indicates whether actual cleaning was done, there * is no guarantee that everything was cleaned
**/ staticbool e1000_clean_rx_irq(struct e1000_ring *rx_ring, int *work_done, int work_to_do)
{ struct e1000_adapter *adapter = rx_ring->adapter; struct net_device *netdev = adapter->netdev; struct pci_dev *pdev = adapter->pdev; struct e1000_hw *hw = &adapter->hw; union e1000_rx_desc_extended *rx_desc, *next_rxd; struct e1000_buffer *buffer_info, *next_buffer;
u32 length, staterr; unsignedint i; int cleaned_count = 0; bool cleaned = false; unsignedint total_rx_bytes = 0, total_rx_packets = 0;
/* !EOP means multiple descriptors were used to store a single * packet, if that's the case we need to toss it. In fact, we * need to toss every packet with the EOP bit clear and the * next frame that _does_ have the EOP bit set, as it is by * definition only a frame fragment
*/ if (unlikely(!(staterr & E1000_RXD_STAT_EOP)))
adapter->flags2 |= FLAG2_IS_DISCARDING;
if (adapter->flags2 & FLAG2_IS_DISCARDING) { /* All receives must fit into a single buffer */
e_dbg("Receive packet consumed multiple buffers\n"); /* recycle */
buffer_info->skb = skb; if (staterr & E1000_RXD_STAT_EOP)
adapter->flags2 &= ~FLAG2_IS_DISCARDING; goto next_desc;
}
/* adjust length to remove Ethernet CRC */ if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) { /* If configured to store CRC, don't subtract FCS, * but keep the FCS bytes out of the total_rx_bytes * counter
*/ if (netdev->features & NETIF_F_RXFCS)
total_rx_bytes -= 4; else
length -= 4;
}
total_rx_bytes += length;
total_rx_packets++;
/* code added for copybreak, this should improve * performance for small packets with large amounts * of reassembly being done in the stack
*/ if (length < copybreak) { struct sk_buff *new_skb =
napi_alloc_skb(&adapter->napi, length); if (new_skb) {
skb_copy_to_linear_data_offset(new_skb,
-NET_IP_ALIGN,
(skb->data -
NET_IP_ALIGN),
(length +
NET_IP_ALIGN)); /* save the skb in buffer_info as good */
buffer_info->skb = skb;
skb = new_skb;
} /* else just continue with the old one */
} /* end copybreak code */
skb_put(skb, length);
/* return some buffers to hardware, one at a time is too slow */ if (cleaned_count >= E1000_RX_BUFFER_WRITE) {
adapter->alloc_rx_buf(rx_ring, cleaned_count,
GFP_ATOMIC);
cleaned_count = 0;
}
if (test_bit(__E1000_DOWN, &adapter->state)) return;
if (!adapter->tx_hang_recheck && (adapter->flags2 & FLAG2_DMA_BURST)) { /* May be block on write-back, flush and detect again * flush pending descriptor writebacks to memory
*/
ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD); /* execute the writes immediately */
e1e_flush(); /* Due to rare timing issues, write to TIDV again to ensure * the write is successful
*/
ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD); /* execute the writes immediately */
e1e_flush();
adapter->tx_hang_recheck = true; return;
}
adapter->tx_hang_recheck = false;
if (er32(TDH(0)) == er32(TDT(0))) {
e_dbg("false hang detected, ignoring\n"); return;
}
/* Real hang detected */
netif_stop_queue(netdev);
/* detected Hardware unit hang */
e_err("Detected Hardware Unit Hang:\n" " TDH <%x>\n" " TDT <%x>\n" " next_to_use <%x>\n" " next_to_clean <%x>\n" "buffer_info[next_to_clean]:\n" " time_stamp <%lx>\n" " next_to_watch <%x>\n" " jiffies <%lx>\n" " next_to_watch.status <%x>\n" "MAC Status <%x>\n" "PHY Status <%x>\n" "PHY 1000BASE-T Status <%x>\n" "PHY Extended Status <%x>\n" "PCI Status <%x>\n",
readl(tx_ring->head), readl(tx_ring->tail), tx_ring->next_to_use,
tx_ring->next_to_clean, tx_ring->buffer_info[eop].time_stamp,
eop, jiffies, eop_desc->upper.fields.status, er32(STATUS),
phy_status, phy_1000t_status, phy_ext_status, pci_status);
e1000e_dump(adapter);
/* Suggest workaround for known h/w issue */ if ((hw->mac.type == e1000_pchlan) && (er32(CTRL) & E1000_CTRL_TFCE))
e_err("Try turning off Tx pause (flow control) via ethtool\n");
}
/** * e1000e_tx_hwtstamp_work - check for Tx time stamp * @work: pointer to work struct * * This work function polls the TSYNCTXCTL valid bit to determine when a * timestamp has been taken for the current stored skb. The timestamp must * be for this skb because only one such packet is allowed in the queue.
*/ staticvoid e1000e_tx_hwtstamp_work(struct work_struct *work)
{ struct e1000_adapter *adapter = container_of(work, struct e1000_adapter,
tx_hwtstamp_work); struct e1000_hw *hw = &adapter->hw;
/* Clear the global tx_hwtstamp_skb pointer and force writes * prior to notifying the stack of a Tx timestamp.
*/
adapter->tx_hwtstamp_skb = NULL;
wmb(); /* force write prior to skb_tstamp_tx */
#define TX_WAKE_THRESHOLD 32 if (count && netif_carrier_ok(netdev) &&
e1000_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD) { /* Make sure that anybody stopping the queue after this * sees the new next_to_clean.
*/
smp_mb();
if (netif_queue_stopped(netdev) &&
!(test_bit(__E1000_DOWN, &adapter->state))) {
netif_wake_queue(netdev);
++adapter->restart_queue;
}
}
if (adapter->detect_tx_hung) { /* Detect a transmit hang in hardware, this serializes the * check with the clearing of time_stamp and movement of i
*/
adapter->detect_tx_hung = false; if (tx_ring->buffer_info[i].time_stamp &&
time_after(jiffies, tx_ring->buffer_info[i].time_stamp
+ (adapter->tx_timeout_factor * HZ)) &&
!(er32(STATUS) & E1000_STATUS_TXOFF))
schedule_work(&adapter->print_hang_task); else
adapter->tx_hang_recheck = false;
}
adapter->total_tx_bytes += total_tx_bytes;
adapter->total_tx_packets += total_tx_packets; return count < tx_ring->count;
}
/** * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split * @rx_ring: Rx descriptor ring * @work_done: output parameter for indicating completed work * @work_to_do: how many packets we can clean * * the return value indicates whether actual cleaning was done, there * is no guarantee that everything was cleaned
**/ staticbool e1000_clean_rx_irq_ps(struct e1000_ring *rx_ring, int *work_done, int work_to_do)
{ struct e1000_adapter *adapter = rx_ring->adapter; struct e1000_hw *hw = &adapter->hw; union e1000_rx_desc_packet_split *rx_desc, *next_rxd; struct net_device *netdev = adapter->netdev; struct pci_dev *pdev = adapter->pdev; struct e1000_buffer *buffer_info, *next_buffer; struct e1000_ps_page *ps_page; struct sk_buff *skb; unsignedint i, j;
u32 length, staterr; int cleaned_count = 0; bool cleaned = false; unsignedint total_rx_bytes = 0, total_rx_packets = 0;
while (staterr & E1000_RXD_STAT_DD) { if (*work_done >= work_to_do) break;
(*work_done)++;
skb = buffer_info->skb;
dma_rmb(); /* read descriptor and rx_buffer_info after status DD */
/* in the packet split case this is header only */
prefetch(skb->data - NET_IP_ALIGN);
i++; if (i == rx_ring->count)
i = 0;
next_rxd = E1000_RX_DESC_PS(*rx_ring, i);
prefetch(next_rxd);
/* see !EOP comment in other Rx routine */ if (!(staterr & E1000_RXD_STAT_EOP))
adapter->flags2 |= FLAG2_IS_DISCARDING;
if (adapter->flags2 & FLAG2_IS_DISCARDING) {
e_dbg("Packet Split buffers didn't pick up the full packet\n");
dev_kfree_skb_irq(skb); if (staterr & E1000_RXD_STAT_EOP)
adapter->flags2 &= ~FLAG2_IS_DISCARDING; goto next_desc;
}
if (!length) {
e_dbg("Last part of the packet spanning multiple descriptors\n");
dev_kfree_skb_irq(skb); goto next_desc;
}
/* Good Receive */
skb_put(skb, length);
{ /* this looks ugly, but it seems compiler issues make * it more efficient than reusing j
*/ int l1 = le16_to_cpu(rx_desc->wb.upper.length[0]);
/* page alloc/put takes too long and effects small * packet throughput, so unsplit small packets and * save the alloc/put
*/ if (l1 && (l1 <= copybreak) &&
((length + l1) <= adapter->rx_ps_bsize0)) {
ps_page = &buffer_info->ps_pages[0];
/* strip the ethernet crc, problem is we're using pages now so * this whole operation can get a little cpu intensive
*/ if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) { if (!(netdev->features & NETIF_F_RXFCS))
pskb_trim(skb, skb->len - 4);
}
/* return some buffers to hardware, one at a time is too slow */ if (cleaned_count >= E1000_RX_BUFFER_WRITE) {
adapter->alloc_rx_buf(rx_ring, cleaned_count,
GFP_ATOMIC);
cleaned_count = 0;
}
/** * e1000_clean_jumbo_rx_irq - Send received data up the network stack; legacy * @rx_ring: Rx descriptor ring * @work_done: output parameter for indicating completed work * @work_to_do: how many packets we can clean * * the return value indicates whether actual cleaning was done, there * is no guarantee that everything was cleaned
**/ staticbool e1000_clean_jumbo_rx_irq(struct e1000_ring *rx_ring, int *work_done, int work_to_do)
{ struct e1000_adapter *adapter = rx_ring->adapter; struct net_device *netdev = adapter->netdev; struct pci_dev *pdev = adapter->pdev; union e1000_rx_desc_extended *rx_desc, *next_rxd; struct e1000_buffer *buffer_info, *next_buffer;
u32 length, staterr; unsignedint i; int cleaned_count = 0; bool cleaned = false; unsignedint total_rx_bytes = 0, total_rx_packets = 0; struct skb_shared_info *shinfo;
/* errors is only valid for DD + EOP descriptors */ if (unlikely((staterr & E1000_RXD_STAT_EOP) &&
((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
!(netdev->features & NETIF_F_RXALL)))) { /* recycle both page and skb */
buffer_info->skb = skb; /* an error means any chain goes out the window too */ if (rx_ring->rx_skb_top)
dev_kfree_skb_irq(rx_ring->rx_skb_top);
rx_ring->rx_skb_top = NULL; goto next_desc;
} #define rxtop (rx_ring->rx_skb_top) if (!(staterr & E1000_RXD_STAT_EOP)) { /* this descriptor is only the beginning (or middle) */ if (!rxtop) { /* this is the beginning of a chain */
rxtop = skb;
skb_fill_page_desc(rxtop, 0, buffer_info->page,
0, length);
} else { /* this is the middle of a chain */
shinfo = skb_shinfo(rxtop);
skb_fill_page_desc(rxtop, shinfo->nr_frags,
buffer_info->page, 0,
length); /* re-use the skb, only consumed the page */
buffer_info->skb = skb;
}
e1000_consume_page(buffer_info, rxtop, length); goto next_desc;
} else { if (rxtop) { /* end of the chain */
shinfo = skb_shinfo(rxtop);
skb_fill_page_desc(rxtop, shinfo->nr_frags,
buffer_info->page, 0,
length); /* re-use the current skb, we only consumed the * page
*/
buffer_info->skb = skb;
skb = rxtop;
rxtop = NULL;
e1000_consume_page(buffer_info, skb, length);
} else { /* no chain, got EOP, this buf is the packet * copybreak to save the put_page/alloc_page
*/ if (length <= copybreak &&
skb_tailroom(skb) >= length) {
memcpy(skb_tail_pointer(skb),
page_address(buffer_info->page),
length); /* re-use the page, so don't erase * buffer_info->page
*/
skb_put(skb, length);
} else {
skb_fill_page_desc(skb, 0,
buffer_info->page, 0,
length);
e1000_consume_page(buffer_info, skb,
length);
}
}
}
/* probably a little skewed due to removing CRC */
total_rx_bytes += skb->len;
total_rx_packets++;
/* eth type trans needs skb->data to point to something */ if (!pskb_may_pull(skb, ETH_HLEN)) {
e_err("pskb_may_pull failed.\n");
dev_kfree_skb_irq(skb); goto next_desc;
}
/* return some buffers to hardware, one at a time is too slow */ if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) {
adapter->alloc_rx_buf(rx_ring, cleaned_count,
GFP_ATOMIC);
cleaned_count = 0;
}
/* there also may be some cached data from a chained receive */ if (rx_ring->rx_skb_top) {
dev_kfree_skb(rx_ring->rx_skb_top);
rx_ring->rx_skb_top = NULL;
}
/* Zero out the descriptor ring */
memset(rx_ring->desc, 0, rx_ring->size);
/* read ICR disables interrupts using IAM */ if (icr & E1000_ICR_LSC) {
hw->mac.get_link_status = true; /* ICH8 workaround-- Call gig speed drop workaround on cable * disconnect (LSC) before accessing any PHY registers
*/ if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
(!(er32(STATUS) & E1000_STATUS_LU)))
schedule_work(&adapter->downshift_task);
/* 80003ES2LAN workaround-- For packet buffer work-around on * link down event; disable receives here in the ISR and reset * adapter in watchdog
*/ if (netif_carrier_ok(netdev) &&
adapter->flags & FLAG_RX_NEEDS_RESTART) { /* disable receives */
u32 rctl = er32(RCTL);
ew32(RCTL, rctl & ~E1000_RCTL_EN);
adapter->flags |= FLAG_RESTART_NOW;
} /* guard against interrupt when we're going down */ if (!test_bit(__E1000_DOWN, &adapter->state))
mod_timer(&adapter->watchdog_timer, jiffies + 1);
}
/* Reset on uncorrectable ECC error */ if ((icr & E1000_ICR_ECCER) && (hw->mac.type >= e1000_pch_lpt)) {
u32 pbeccsts = er32(PBECCSTS);
if (!icr || test_bit(__E1000_DOWN, &adapter->state)) return IRQ_NONE; /* Not our interrupt */
/* IMS will not auto-mask if INT_ASSERTED is not set, and if it is * not set, then the adapter didn't send an interrupt
*/ if (!(icr & E1000_ICR_INT_ASSERTED)) return IRQ_NONE;
/* Interrupt Auto-Mask...upon reading ICR, * interrupts are masked. No need for the * IMC write
*/
if (icr & E1000_ICR_LSC) {
hw->mac.get_link_status = true; /* ICH8 workaround-- Call gig speed drop workaround on cable * disconnect (LSC) before accessing any PHY registers
*/ if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
(!(er32(STATUS) & E1000_STATUS_LU)))
schedule_work(&adapter->downshift_task);
/* 80003ES2LAN workaround-- * For packet buffer work-around on link down event; * disable receives here in the ISR and * reset adapter in watchdog
*/ if (netif_carrier_ok(netdev) &&
(adapter->flags & FLAG_RX_NEEDS_RESTART)) { /* disable receives */
rctl = er32(RCTL);
ew32(RCTL, rctl & ~E1000_RCTL_EN);
adapter->flags |= FLAG_RESTART_NOW;
} /* guard against interrupt when we're going down */ if (!test_bit(__E1000_DOWN, &adapter->state))
mod_timer(&adapter->watchdog_timer, jiffies + 1);
}
/* Reset on uncorrectable ECC error */ if ((icr & E1000_ICR_ECCER) && (hw->mac.type >= e1000_pch_lpt)) {
u32 pbeccsts = er32(PBECCSTS);
if (icr & adapter->eiac_mask)
ew32(ICS, (icr & adapter->eiac_mask));
if (icr & E1000_ICR_LSC) {
hw->mac.get_link_status = true; /* guard against interrupt when we're going down */ if (!test_bit(__E1000_DOWN, &adapter->state))
mod_timer(&adapter->watchdog_timer, jiffies + 1);
}
if (!test_bit(__E1000_DOWN, &adapter->state))
ew32(IMS, E1000_IMS_OTHER | IMS_OTHER_MASK);
/* Write the ITR value calculated at the end of the * previous interrupt.
*/ if (rx_ring->set_itr) {
u32 itr = rx_ring->itr_val ?
1000000000 / (rx_ring->itr_val * 256) : 0;
/* set vector for Other Causes, e.g. link changes */
vector++;
ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 16); if (rx_ring->itr_val)
writel(1000000000 / (rx_ring->itr_val * 256),
hw->hw_addr + E1000_EITR_82574(vector)); else
writel(1, hw->hw_addr + E1000_EITR_82574(vector));
/* Cause Tx interrupts on every write back */
ivar |= BIT(31);
/** * e1000e_set_interrupt_capability - set MSI or MSI-X if supported * @adapter: board private structure * * Attempt to configure interrupts using the best available * capabilities of the hardware and kernel.
**/ void e1000e_set_interrupt_capability(struct e1000_adapter *adapter)
{ int err; int i;
switch (adapter->int_mode) { case E1000E_INT_MODE_MSIX: if (adapter->flags & FLAG_HAS_MSIX) {
adapter->num_vectors = 3; /* RxQ0, TxQ0 and other */
adapter->msix_entries = kcalloc(adapter->num_vectors, sizeof(struct
msix_entry),
GFP_KERNEL); if (adapter->msix_entries) { struct e1000_adapter *a = adapter;
for (i = 0; i < adapter->num_vectors; i++)
adapter->msix_entries[i].entry = i;
err = pci_enable_msix_range(a->pdev,
a->msix_entries,
a->num_vectors,
a->num_vectors); if (err > 0) return;
} /* MSI-X failed, so fall through and try MSI */
e_err("Failed to initialize MSI-X interrupts. Falling back to MSI interrupts.\n");
e1000e_reset_interrupt_capability(adapter);
}
adapter->int_mode = E1000E_INT_MODE_MSI;
fallthrough; case E1000E_INT_MODE_MSI: if (!pci_enable_msi(adapter->pdev)) {
adapter->flags |= FLAG_MSI_ENABLED;
} else {
adapter->int_mode = E1000E_INT_MODE_LEGACY;
e_err("Failed to initialize MSI interrupts. Falling back to legacy interrupts.\n");
}
fallthrough; case E1000E_INT_MODE_LEGACY: /* Don't do anything; this is the system default */ break;
}
/* store the number of vectors being used */
adapter->num_vectors = 1;
}
/** * e1000_request_irq - initialize interrupts * @adapter: board private structure * * Attempts to configure interrupts using the best available * capabilities of the hardware and kernel.
**/ staticint e1000_request_irq(struct e1000_adapter *adapter)
{ struct net_device *netdev = adapter->netdev; int err;
if (adapter->msix_entries) {
err = e1000_request_msix(adapter); if (!err) return err; /* fall back to MSI */
e1000e_reset_interrupt_capability(adapter);
adapter->int_mode = E1000E_INT_MODE_MSI;
e1000e_set_interrupt_capability(adapter);
} if (adapter->flags & FLAG_MSI_ENABLED) {
err = request_irq(adapter->pdev->irq, e1000_intr_msi, 0,
netdev->name, netdev); if (!err) return err;
/* fall back to legacy interrupt */
e1000e_reset_interrupt_capability(adapter);
adapter->int_mode = E1000E_INT_MODE_LEGACY;
}
err = request_irq(adapter->pdev->irq, e1000_intr, IRQF_SHARED,
netdev->name, netdev); if (err)
e_err("Unable to allocate interrupt, Error: %d\n", err);
/** * e1000e_get_hw_control - get control of the h/w from f/w * @adapter: address of board private structure * * e1000e_get_hw_control sets {CTRL_EXT|SWSM}:DRV_LOAD bit. * For ASF and Pass Through versions of f/w this means that * the driver is loaded. For AMT version (only with 82573) * of the f/w this means that the network i/f is open.
**/ void e1000e_get_hw_control(struct e1000_adapter *adapter)
{ struct e1000_hw *hw = &adapter->hw;
u32 ctrl_ext;
u32 swsm;
/* Let firmware know the driver has taken over */ if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) {
swsm = er32(SWSM);
ew32(SWSM, swsm | E1000_SWSM_DRV_LOAD);
} elseif (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) {
ctrl_ext = er32(CTRL_EXT);
ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
}
}
/** * e1000e_release_hw_control - release control of the h/w to f/w * @adapter: address of board private structure * * e1000e_release_hw_control resets {CTRL_EXT|SWSM}:DRV_LOAD bit. * For ASF and Pass Through versions of f/w this means that the * driver is no longer loaded. For AMT version (only with 82573) i * of the f/w this means that the network i/f is closed. *
**/ void e1000e_release_hw_control(struct e1000_adapter *adapter)
{ struct e1000_hw *hw = &adapter->hw;
u32 ctrl_ext;
u32 swsm;
/* Let firmware taken over control of h/w */ if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) {
swsm = er32(SWSM);
ew32(SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
} elseif (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) {
ctrl_ext = er32(CTRL_EXT);
ew32(CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
}
}
/** * e1000_alloc_ring_dma - allocate memory for a ring structure * @adapter: board private structure * @ring: ring struct for which to allocate dma
**/ staticint e1000_alloc_ring_dma(struct e1000_adapter *adapter, struct e1000_ring *ring)
{ struct pci_dev *pdev = adapter->pdev;
ring->desc = dma_alloc_coherent(&pdev->dev, ring->size, &ring->dma,
GFP_KERNEL); if (!ring->desc) return -ENOMEM;
return 0;
}
/** * e1000e_setup_tx_resources - allocate Tx resources (Descriptors) * @tx_ring: Tx descriptor ring * * Return 0 on success, negative on failure
**/ int e1000e_setup_tx_resources(struct e1000_ring *tx_ring)
{ struct e1000_adapter *adapter = tx_ring->adapter; int err = -ENOMEM, size;
err_pages: for (i = 0; i < rx_ring->count; i++) {
buffer_info = &rx_ring->buffer_info[i];
kfree(buffer_info->ps_pages);
}
err:
vfree(rx_ring->buffer_info);
e_err("Unable to allocate memory for the receive descriptor ring\n"); return err;
}
/** * e1000_update_itr - update the dynamic ITR value based on statistics * @itr_setting: current adapter->itr * @packets: the number of packets during this measurement interval * @bytes: the number of bytes during this measurement interval * * Stores a new ITR value based on packets and byte * counts during the last interrupt. The advantage of per interrupt * computation is faster updates and more accurate ITR for the current * traffic pattern. Constants in this function were computed * based on theoretical maximum wire speed and thresholds were set based * on testing data as well as attempting to minimize response time * while increasing bulk throughput. This functionality is controlled * by the InterruptThrottleRate module parameter.
**/ staticunsignedint e1000_update_itr(u16 itr_setting, int packets, int bytes)
{ unsignedint retval = itr_setting;
/* counts and packets in update_itr are dependent on these numbers */ switch (current_itr) { case lowest_latency:
new_itr = 70000; break; case low_latency:
new_itr = 20000; /* aka hwitr = ~200 */ break; case bulk_latency:
new_itr = 4000; break; default: break;
}
set_itr_now: if (new_itr != adapter->itr) { /* this attempts to bias the interrupt rate towards Bulk * by adding intermediate steps when interrupt rate is * increasing
*/
new_itr = new_itr > adapter->itr ?
min(adapter->itr + (new_itr >> 2), new_itr) : new_itr;
adapter->itr = new_itr;
adapter->rx_ring->itr_val = new_itr; if (adapter->msix_entries)
adapter->rx_ring->set_itr = 1; else
e1000e_write_itr(adapter, new_itr);
}
}
/** * e1000e_write_itr - write the ITR value to the appropriate registers * @adapter: address of board private structure * @itr: new ITR value to program * * e1000e_write_itr determines if the adapter is in MSI-X mode * and, if so, writes the EITR registers with the ITR value. * Otherwise, it writes the ITR value into the ITR register.
**/ void e1000e_write_itr(struct e1000_adapter *adapter, u32 itr)
{ struct e1000_hw *hw = &adapter->hw;
u32 new_itr = itr ? 1000000000 / (itr * 256) : 0;
if (!tx_cleaned || work_done == budget) return budget;
/* Exit the polling mode, but don't re-enable interrupts if stack might * poll us due to busy-polling
*/ if (likely(napi_complete_done(napi, work_done))) { if (adapter->itr_setting & 3)
e1000_set_itr(adapter); if (!test_bit(__E1000_DOWN, &adapter->state)) { if (adapter->msix_entries)
ew32(IMS, adapter->rx_ring->ims_val); else
e1000_irq_enable(adapter);
}
}
if (!(adapter->flags & FLAG_MNG_PT_ENABLED)) return;
manc = er32(MANC);
/* enable receiving management packets to the host. this will probably * generate destination unreachable messages from the host OS, but * the packets will be handled on SMBUS
*/
manc |= E1000_MANC_EN_MNG2HOST;
manc2h = er32(MANC2H);
switch (hw->mac.type) { default:
manc2h |= (E1000_MANC2H_PORT_623 | E1000_MANC2H_PORT_664); break; case e1000_82574: case e1000_82583: /* Check if IPMI pass-through decision filter already exists; * if so, enable it.
*/ for (i = 0, j = 0; i < 8; i++) {
mdef = er32(MDEF(i));
/* Ignore filters with anything other than IPMI ports */ if (mdef & ~(E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664)) continue;
/* Enable this decision filter in MANC2H */ if (mdef)
manc2h |= BIT(i);
j |= mdef;
}
if (j == (E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664)) break;
/* Create new decision filter in an empty filter */ for (i = 0, j = 0; i < 8; i++) if (er32(MDEF(i)) == 0) {
ew32(MDEF(i), (E1000_MDEF_PORT_623 |
E1000_MDEF_PORT_664));
manc2h |= BIT(1);
j++; break;
}
if (!j)
e_warn("Unable to create IPMI pass-through filter\n"); break;
}
ew32(MANC2H, manc2h);
ew32(MANC, manc);
}
/** * e1000_configure_tx - Configure Transmit Unit after Reset * @adapter: board private structure * * Configure the Tx unit of the MAC after a reset.
**/ staticvoid e1000_configure_tx(struct e1000_adapter *adapter)
{ struct e1000_hw *hw = &adapter->hw; struct e1000_ring *tx_ring = adapter->tx_ring;
u64 tdba;
u32 tdlen, tctl, tarc;
if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
e1000e_update_tdt_wa(tx_ring, 0);
/* Set the Tx Interrupt Delay register */
ew32(TIDV, adapter->tx_int_delay); /* Tx irq moderation */
ew32(TADV, adapter->tx_abs_int_delay);
if (adapter->flags2 & FLAG2_DMA_BURST) {
u32 txdctl = er32(TXDCTL(0));
txdctl &= ~(E1000_TXDCTL_PTHRESH | E1000_TXDCTL_HTHRESH |
E1000_TXDCTL_WTHRESH); /* set up some performance related parameters to encourage the * hardware to use the bus more efficiently in bursts, depends * on the tx_int_delay to be enabled, * wthresh = 1 ==> burst write is disabled to avoid Tx stalls * hthresh = 1 ==> prefetch when one or more available * pthresh = 0x1f ==> prefetch if internal cache 31 or less * BEWARE: this seems to work but should be considered first if * there are Tx hangs or other Tx related bugs
*/
txdctl |= E1000_TXDCTL_DMA_BURST_ENABLE;
ew32(TXDCTL(0), txdctl);
} /* erratum work around: set txdctl the same for both queues */
ew32(TXDCTL(1), er32(TXDCTL(0)));
/* Program the Transmit Control Register */
tctl = er32(TCTL);
tctl &= ~E1000_TCTL_CT;
tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
(E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
if (adapter->flags & FLAG_TARC_SPEED_MODE_BIT) {
tarc = er32(TARC(0)); /* set the speed mode bit, we'll clear it if we're not at * gigabit link later
*/ #define SPEED_MODE_BIT BIT(21)
tarc |= SPEED_MODE_BIT;
ew32(TARC(0), tarc);
}
/* errata: program both queues to unweighted RR */ if (adapter->flags & FLAG_TARC_SET_BIT_ZERO) {
tarc = er32(TARC(0));
tarc |= 1;
ew32(TARC(0), tarc);
tarc = er32(TARC(1));
tarc |= 1;
ew32(TARC(1), tarc);
}
reg_val = er32(TARC(0)); /* SPT and KBL Si errata workaround to avoid Tx hang. * Dropping the number of outstanding requests from * 3 to 2 in order to avoid a buffer overrun.
*/
reg_val &= ~E1000_TARC0_CB_MULTIQ_3_REQ;
reg_val |= E1000_TARC0_CB_MULTIQ_2_REQ;
ew32(TARC(0), reg_val);
}
}
/* Workaround Si errata on PCHx - configure jumbo frame flow. * If jumbo frames not set, program related MAC/PHY registers * to h/w defaults
*/ if (hw->mac.type >= e1000_pch2lan) {
s32 ret_val;
if (ret_val)
e_dbg("failed to enable|disable jumbo frame workaround mode\n");
}
/* Program MC offset vector base */
rctl = er32(RCTL);
rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
(adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
/* Do not Store bad packets */
rctl &= ~E1000_RCTL_SBP;
/* Enable Long Packet receive */ if (adapter->netdev->mtu <= ETH_DATA_LEN)
rctl &= ~E1000_RCTL_LPE; else
rctl |= E1000_RCTL_LPE;
/* Some systems expect that the CRC is included in SMBUS traffic. The * hardware strips the CRC before sending to both SMBUS (BMC) and to * host memory when this is enabled
*/ if (adapter->flags2 & FLAG2_CRC_STRIPPING)
rctl |= E1000_RCTL_SECRC;
/* Workaround Si errata on 82577 PHY - configure IPG for jumbos */ if ((hw->phy.type == e1000_phy_82577) && (rctl & E1000_RCTL_LPE)) {
u16 phy_data;
/* Enable Extended Status in all Receive Descriptors */
rfctl = er32(RFCTL);
rfctl |= E1000_RFCTL_EXTEN;
ew32(RFCTL, rfctl);
/* 82571 and greater support packet-split where the protocol * header is placed in skb->data and the packet data is * placed in pages hanging off of skb_shinfo(skb)->nr_frags. * In the case of a non-split, skb->data is linearly filled, * followed by the page buffers. Therefore, skb->data is * sized to hold the largest protocol header. * * allocations using alloc_page take too long for regular MTU * so only enable packet split for jumbo frames * * Using pages when the page size is greater than 16k wastes * a lot of memory, since we allocate 3 pages at all times * per packet.
*/
pages = PAGE_USE_COUNT(adapter->netdev->mtu); if ((pages <= 3) && (PAGE_SIZE <= 16384) && (rctl & E1000_RCTL_LPE))
adapter->rx_ps_pages = pages; else
adapter->rx_ps_pages = 0;
switch (adapter->rx_ps_pages) { case 3:
psrctl |= PAGE_SIZE << E1000_PSRCTL_BSIZE3_SHIFT;
fallthrough; case 2:
psrctl |= PAGE_SIZE << E1000_PSRCTL_BSIZE2_SHIFT;
fallthrough; case 1:
psrctl |= PAGE_SIZE >> E1000_PSRCTL_BSIZE1_SHIFT; break;
}
ew32(PSRCTL, psrctl);
}
/* This is useful for sniffing bad packets. */ if (adapter->netdev->features & NETIF_F_RXALL) { /* UPE and MPE will be handled by normal PROMISC logic * in e1000e_set_rx_mode
*/
rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
E1000_RCTL_BAM | /* RX All Bcast Pkts */
E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */
E1000_RCTL_DPF | /* Allow filtered pause */
E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */ /* Do not mess with E1000_CTRL_VME, it affects transmit as well, * and that breaks VLANs.
*/
}
ew32(RCTL, rctl); /* just started the receive unit, no need to restart */
adapter->flags &= ~FLAG_RESTART_NOW;
}
/** * e1000_configure_rx - Configure Receive Unit after Reset * @adapter: board private structure * * Configure the Rx unit of the MAC after a reset.
**/ staticvoid e1000_configure_rx(struct e1000_adapter *adapter)
{ struct e1000_hw *hw = &adapter->hw; struct e1000_ring *rx_ring = adapter->rx_ring;
u64 rdba;
u32 rdlen, rctl, rxcsum, ctrl_ext;
/* disable receives while setting up the descriptors */
rctl = er32(RCTL); if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX))
ew32(RCTL, rctl & ~E1000_RCTL_EN);
e1e_flush();
usleep_range(10000, 11000);
if (adapter->flags2 & FLAG2_DMA_BURST) { /* set the writeback threshold (only takes effect if the RDTR * is set). set GRAN=1 and write back up to 0x4 worth, and * enable prefetching of 0x20 Rx descriptors * granularity = 01 * wthresh = 04, * hthresh = 04, * pthresh = 0x20
*/
ew32(RXDCTL(0), E1000_RXDCTL_DMA_BURST_ENABLE);
ew32(RXDCTL(1), E1000_RXDCTL_DMA_BURST_ENABLE);
}
/* set the Receive Delay Timer Register */
ew32(RDTR, adapter->rx_int_delay);
/* Setup the HW Rx Head and Tail Descriptor Pointers and * the Base and Length of the Rx Descriptor Ring
*/
rdba = rx_ring->dma;
ew32(RDBAL(0), (rdba & DMA_BIT_MASK(32)));
ew32(RDBAH(0), (rdba >> 32));
ew32(RDLEN(0), rdlen);
ew32(RDH(0), 0);
ew32(RDT(0), 0);
rx_ring->head = adapter->hw.hw_addr + E1000_RDH(0);
rx_ring->tail = adapter->hw.hw_addr + E1000_RDT(0);
if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
e1000e_update_rdt_wa(rx_ring, 0);
/* Enable Receive Checksum Offload for TCP and UDP */
rxcsum = er32(RXCSUM); if (adapter->netdev->features & NETIF_F_RXCSUM)
rxcsum |= E1000_RXCSUM_TUOFL; else
rxcsum &= ~E1000_RXCSUM_TUOFL;
ew32(RXCSUM, rxcsum);
/* With jumbo frames, excessive C-state transition latencies result * in dropped transactions.
*/ if (adapter->netdev->mtu > ETH_DATA_LEN) {
u32 lat =
((er32(PBA) & E1000_PBA_RXA_MASK) * 1024 -
adapter->max_frame_size) * 8 / 1000;
if (adapter->flags & FLAG_IS_ICH) {
u32 rxdctl = er32(RXDCTL(0));
ew32(RXDCTL(0), rxdctl | 0x3 | BIT(8));
}
dev_info(&adapter->pdev->dev, "Some CPU C-states have been disabled in order to enable jumbo frames\n");
cpu_latency_qos_update_request(&adapter->pm_qos_req, lat);
} else {
cpu_latency_qos_update_request(&adapter->pm_qos_req,
PM_QOS_DEFAULT_VALUE);
}
/* Enable Receives */
ew32(RCTL, rctl);
}
/** * e1000e_write_mc_addr_list - write multicast addresses to MTA * @netdev: network interface device structure * * Writes multicast address list to the MTA hash table. * Returns: -ENOMEM on failure * 0 on no addresses written * X on writing X addresses to MTA
*/ staticint e1000e_write_mc_addr_list(struct net_device *netdev)
{ struct e1000_adapter *adapter = netdev_priv(netdev); struct e1000_hw *hw = &adapter->hw; struct netdev_hw_addr *ha;
u8 *mta_list; int i;
if (netdev_mc_empty(netdev)) { /* nothing to program, so clear mc list */
hw->mac.ops.update_mc_addr_list(hw, NULL, 0); return 0;
}
mta_list = kcalloc(netdev_mc_count(netdev), ETH_ALEN, GFP_ATOMIC); if (!mta_list) return -ENOMEM;
/* update_mc_addr_list expects a packed array of only addresses. */
i = 0;
netdev_for_each_mc_addr(ha, netdev)
memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
/** * e1000e_write_uc_addr_list - write unicast addresses to RAR table * @netdev: network interface device structure * * Writes unicast address list to the RAR table. * Returns: -ENOMEM on failure/insufficient address space * 0 on no addresses written * X on writing X addresses to the RAR table
**/ staticint e1000e_write_uc_addr_list(struct net_device *netdev)
{ struct e1000_adapter *adapter = netdev_priv(netdev); struct e1000_hw *hw = &adapter->hw; unsignedint rar_entries; int count = 0;
rar_entries = hw->mac.ops.rar_get_count(hw);
/* save a rar entry for our hardware address */
rar_entries--;
/* save a rar entry for the LAA workaround */ if (adapter->flags & FLAG_RESET_OVERWRITES_LAA)
rar_entries--;
/* return ENOMEM indicating insufficient memory for addresses */ if (netdev_uc_count(netdev) > rar_entries) return -ENOMEM;
if (!netdev_uc_empty(netdev) && rar_entries) { struct netdev_hw_addr *ha;
/* write the addresses in reverse order to avoid write * combining
*/
netdev_for_each_uc_addr(ha, netdev) { int ret_val;
if (!rar_entries) break;
ret_val = hw->mac.ops.rar_set(hw, ha->addr, rar_entries--); if (ret_val < 0) return -ENOMEM;
count++;
}
}
/* zero out the remaining RAR entries not used above */ for (; rar_entries > 0; rar_entries--) {
ew32(RAH(rar_entries), 0);
ew32(RAL(rar_entries), 0);
}
e1e_flush();
return count;
}
/** * e1000e_set_rx_mode - secondary unicast, Multicast and Promiscuous mode set * @netdev: network interface device structure * * The ndo_set_rx_mode entry point is called whenever the unicast or multicast * address list or the network interface flags are updated. This routine is * responsible for configuring the hardware for proper unicast, multicast, * promiscuous mode, and all-multi behavior.
**/ staticvoid e1000e_set_rx_mode(struct net_device *netdev)
{ struct e1000_adapter *adapter = netdev_priv(netdev); struct e1000_hw *hw = &adapter->hw;
u32 rctl;
if (pm_runtime_suspended(netdev->dev.parent)) return;
/* Check for Promiscuous and All Multicast modes */
rctl = er32(RCTL);
if (netdev->flags & IFF_PROMISC) {
rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); /* Do not hardware filter VLANs in promisc mode */
e1000e_vlan_filter_disable(adapter);
} else { int count;
if (netdev->flags & IFF_ALLMULTI) {
rctl |= E1000_RCTL_MPE;
} else { /* Write addresses to the MTA, if the attempt fails * then we should just turn on promiscuous mode so * that we can at least receive multicast traffic
*/
count = e1000e_write_mc_addr_list(netdev); if (count < 0)
rctl |= E1000_RCTL_MPE;
}
e1000e_vlan_filter_enable(adapter); /* Write addresses to available RAR registers, if there is not * sufficient space to store all the addresses then enable * unicast promiscuous mode
*/
count = e1000e_write_uc_addr_list(netdev); if (count < 0)
rctl |= E1000_RCTL_UPE;
}
ew32(RCTL, rctl);
if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
e1000e_vlan_strip_enable(adapter); else
e1000e_vlan_strip_disable(adapter);
}
/** * e1000e_get_base_timinca - get default SYSTIM time increment attributes * @adapter: board private structure * @timinca: pointer to returned time increment attributes * * Get attributes for incrementing the System Time Register SYSTIML/H at * the default base frequency, and set the cyclecounter shift value.
**/
s32 e1000e_get_base_timinca(struct e1000_adapter *adapter, u32 *timinca)
{ struct e1000_hw *hw = &adapter->hw;
u32 incvalue, incperiod, shift;
/* Make sure clock is enabled on I217/I218/I219 before checking * the frequency
*/ if ((hw->mac.type >= e1000_pch_lpt) &&
!(er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) &&
!(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_ENABLED)) {
u32 fextnvm7 = er32(FEXTNVM7);
/** * e1000e_config_hwtstamp - configure the hwtstamp registers and enable/disable * @adapter: board private structure * @config: timestamp configuration * @extack: netlink extended ACK for error report * * Outgoing time stamping can be enabled and disabled. Play nice and * disable it when requested, although it shouldn't cause any overhead * when no packet needs it. At most one packet in the queue may be * marked for time stamping, otherwise it would be impossible to tell * for sure to which packet the hardware time stamp belongs. * * Incoming time stamping has to be configured via the hardware filters. * Not all combinations are supported, in particular event type has to be * specified. Matching the kind of event packet is not supported, with the * exception of "all V2 events regardless of level 2 or 4".
**/ staticint e1000e_config_hwtstamp(struct e1000_adapter *adapter, struct kernel_hwtstamp_config *config, struct netlink_ext_ack *extack)
{ struct e1000_hw *hw = &adapter->hw;
u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED;
u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
u32 rxmtrl = 0;
u16 rxudp = 0; bool is_l4 = false; bool is_l2 = false;
u32 regval;
if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP)) {
NL_SET_ERR_MSG(extack, "No HW timestamp support"); return -EINVAL;
}
/** * e1000e_power_up_phy - restore link in case the phy was powered down * @adapter: address of board private structure * * The phy may be powered down to save power and turn off link when the * driver is unloaded and wake on lan is not enabled (among others) * *** this routine MUST be followed by a call to e1000e_reset ***
**/ void e1000e_power_up_phy(struct e1000_adapter *adapter)
{ if (adapter->hw.phy.ops.power_up)
adapter->hw.phy.ops.power_up(&adapter->hw);
adapter->hw.mac.ops.setup_link(&adapter->hw);
}
/** * e1000_power_down_phy - Power down the PHY * @adapter: board private structure * * Power down the PHY so no link is implied when interface is down. * The PHY cannot be powered down if management or WoL is active.
*/ staticvoid e1000_power_down_phy(struct e1000_adapter *adapter)
{ if (adapter->hw.phy.ops.power_down)
adapter->hw.phy.ops.power_down(&adapter->hw);
}
/** * e1000_flush_tx_ring - remove all descriptors from the tx_ring * @adapter: board private structure * * We want to clear all pending descriptors from the TX ring. * zeroing happens when the HW reads the regs. We assign the ring itself as * the data of the next descriptor. We don't care about the data we are about * to reset the HW.
*/ staticvoid e1000_flush_tx_ring(struct e1000_adapter *adapter)
{ struct e1000_hw *hw = &adapter->hw; struct e1000_ring *tx_ring = adapter->tx_ring; struct e1000_tx_desc *tx_desc = NULL;
u32 tdt, tctl, txd_lower = E1000_TXD_CMD_IFCS;
u16 size = 512;
tx_desc->lower.data = cpu_to_le32(txd_lower | size);
tx_desc->upper.data = 0; /* flush descriptors to memory before notifying the HW */
wmb();
tx_ring->next_to_use++; if (tx_ring->next_to_use == tx_ring->count)
tx_ring->next_to_use = 0;
ew32(TDT(0), tx_ring->next_to_use);
usleep_range(200, 250);
}
/** * e1000_flush_rx_ring - remove all descriptors from the rx_ring * @adapter: board private structure * * Mark all descriptors in the RX ring as consumed and disable the rx ring
*/ staticvoid e1000_flush_rx_ring(struct e1000_adapter *adapter)
{
u32 rctl, rxdctl; struct e1000_hw *hw = &adapter->hw;
rxdctl = er32(RXDCTL(0)); /* zero the lower 14 bits (prefetch and host thresholds) */
rxdctl &= 0xffffc000;
/* update thresholds: prefetch threshold to 31, host threshold to 1 * and make sure the granularity is "descriptors" and not "cache lines"
*/
rxdctl |= (0x1F | BIT(8) | E1000_RXDCTL_THRESH_UNIT_DESC);
ew32(RXDCTL(0), rxdctl); /* momentarily enable the RX ring for the changes to take effect */
ew32(RCTL, rctl | E1000_RCTL_EN);
e1e_flush();
usleep_range(100, 150);
ew32(RCTL, rctl & ~E1000_RCTL_EN);
}
/** * e1000_flush_desc_rings - remove all descriptors from the descriptor rings * @adapter: board private structure * * In i219, the descriptor rings must be emptied before resetting the HW * or before changing the device state to D3 during runtime (runtime PM). * * Failure to do this will cause the HW to enter a unit hang state which can * only be released by PCI reset on the device *
*/
/* First, disable MULR fix in FEXTNVM11 */
fext_nvm11 = er32(FEXTNVM11);
fext_nvm11 |= E1000_FEXTNVM11_DISABLE_MULR_FIX;
ew32(FEXTNVM11, fext_nvm11); /* do nothing if we're not in faulty state, or if the queue is empty */
tdlen = er32(TDLEN(0));
pci_read_config_word(adapter->pdev, PCICFG_DESC_RING_STATUS,
&hang_state); if (!(hang_state & FLUSH_DESC_REQUIRED) || !tdlen) return;
e1000_flush_tx_ring(adapter); /* recheck, maybe the fault is caused by the rx ring */
pci_read_config_word(adapter->pdev, PCICFG_DESC_RING_STATUS,
&hang_state); if (hang_state & FLUSH_DESC_REQUIRED)
e1000_flush_rx_ring(adapter);
}
/** * e1000e_systim_reset - reset the timesync registers after a hardware reset * @adapter: board private structure * * When the MAC is reset, all hardware bits for timesync will be reset to the * default values. This function will restore the settings last in place. * Since the clock SYSTIME registers are reset, we will simply restore the * cyclecounter to the kernel real clock time.
**/ staticvoid e1000e_systim_reset(struct e1000_adapter *adapter)
{ struct ptp_clock_info *info = &adapter->ptp_clock_info; struct e1000_hw *hw = &adapter->hw; struct netlink_ext_ack extack = {}; unsignedlong flags;
u32 timinca;
s32 ret_val;
if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP)) return;
if (info->adjfine) { /* restore the previous ptp frequency delta */
ret_val = info->adjfine(info, adapter->ptp_delta);
} else { /* set the default base frequency if no adjustment possible */
ret_val = e1000e_get_base_timinca(adapter, &timinca); if (!ret_val)
ew32(TIMINCA, timinca);
}
if (ret_val) {
dev_warn(&adapter->pdev->dev, "Failed to restore TIMINCA clock rate delta: %d\n",
ret_val); return;
}
/* reset the systim ns time counter */
spin_lock_irqsave(&adapter->systim_lock, flags);
timecounter_init(&adapter->tc, &adapter->cc,
ktime_to_ns(ktime_get_real()));
spin_unlock_irqrestore(&adapter->systim_lock, flags);
/* restore the previous hwtstamp configuration settings */
ret_val = e1000e_config_hwtstamp(adapter, &adapter->hwtstamp_config,
&extack); if (ret_val) { if (extack._msg)
e_err("%s\n", extack._msg);
}
}
/** * e1000e_reset - bring the hardware into a known good state * @adapter: board private structure * * This function boots the hardware and enables some settings that * require a configuration cycle of the hardware - those cannot be * set/changed during runtime. After reset the device needs to be * properly configured for Rx, Tx etc.
*/ void e1000e_reset(struct e1000_adapter *adapter)
{ struct e1000_mac_info *mac = &adapter->hw.mac; struct e1000_fc_info *fc = &adapter->hw.fc; struct e1000_hw *hw = &adapter->hw;
u32 tx_space, min_tx_space, min_rx_space;
u32 pba = adapter->pba;
u16 hwm;
/* reset Packet Buffer Allocation to default */
ew32(PBA, pba);
if (adapter->max_frame_size > (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)) { /* To maintain wire speed transmits, the Tx FIFO should be * large enough to accommodate two full transmit packets, * rounded up to the next 1KB and expressed in KB. Likewise, * the Rx FIFO should be large enough to accommodate at least * one full receive packet and is similarly rounded up and * expressed in KB.
*/
pba = er32(PBA); /* upper 16 bits has Tx packet buffer allocation size in KB */
tx_space = pba >> 16; /* lower 16 bits has Rx packet buffer allocation size in KB */
pba &= 0xffff; /* the Tx fifo also stores 16 bytes of information about the Tx * but don't include ethernet FCS because hardware appends it
*/
min_tx_space = (adapter->max_frame_size + sizeof(struct e1000_tx_desc) - ETH_FCS_LEN) * 2;
min_tx_space = ALIGN(min_tx_space, 1024);
min_tx_space >>= 10; /* software strips receive CRC, so leave room for it */
min_rx_space = adapter->max_frame_size;
min_rx_space = ALIGN(min_rx_space, 1024);
min_rx_space >>= 10;
/* If current Tx allocation is less than the min Tx FIFO size, * and the min Tx FIFO size is less than the current Rx FIFO * allocation, take space away from current Rx allocation
*/ if ((tx_space < min_tx_space) &&
((min_tx_space - tx_space) < pba)) {
pba -= min_tx_space - tx_space;
/* if short on Rx space, Rx wins and must trump Tx * adjustment
*/ if (pba < min_rx_space)
pba = min_rx_space;
}
ew32(PBA, pba);
}
/* flow control settings * * The high water mark must be low enough to fit one full frame * (or the size used for early receive) above it in the Rx FIFO. * Set it to the lower of: * - 90% of the Rx FIFO size, and * - the full Rx FIFO size minus one full frame
*/ if (adapter->flags & FLAG_DISABLE_FC_PAUSE_TIME)
fc->pause_time = 0xFFFF; else
fc->pause_time = E1000_FC_PAUSE_TIME;
fc->send_xon = true;
fc->current_mode = fc->requested_mode;
/* Alignment of Tx data is on an arbitrary byte boundary with the * maximum size per Tx descriptor limited only to the transmit * allocation of the packet buffer minus 96 bytes with an upper * limit of 24KB due to receive synchronization limitations.
*/
adapter->tx_fifo_limit = min_t(u32, ((er32(PBA) >> 16) << 10) - 96,
24 << 10);
/* Disable Adaptive Interrupt Moderation if 2 full packets cannot * fit in receive buffer.
*/ if (adapter->itr_setting & 0x3) { if ((adapter->max_frame_size * 2) > (pba << 10)) { if (!(adapter->flags2 & FLAG2_DISABLE_AIM)) {
dev_info(&adapter->pdev->dev, "Interrupt Throttle Rate off\n");
adapter->flags2 |= FLAG2_DISABLE_AIM;
e1000e_write_itr(adapter, 0);
}
} elseif (adapter->flags2 & FLAG2_DISABLE_AIM) {
dev_info(&adapter->pdev->dev, "Interrupt Throttle Rate on\n");
adapter->flags2 &= ~FLAG2_DISABLE_AIM;
adapter->itr = 20000;
e1000e_write_itr(adapter, adapter->itr);
}
}
if (hw->mac.type >= e1000_pch_spt)
e1000_flush_desc_rings(adapter); /* Allow time for pending master requests to run */
mac->ops.reset_hw(hw);
/* For parts with AMT enabled, let the firmware know * that the network interface is in control
*/ if (adapter->flags & FLAG_HAS_AMT)
e1000e_get_hw_control(adapter);
ew32(WUC, 0);
if (mac->ops.init_hw(hw))
e_err("Hardware Error\n");
e1000_update_mng_vlan(adapter);
/* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
ew32(VET, ETH_P_8021Q);
e1000e_reset_adaptive(hw);
/* restore systim and hwtstamp settings */
e1000e_systim_reset(adapter);
/* Set EEE advertisement as appropriate */ if (adapter->flags2 & FLAG2_HAS_EEE) {
s32 ret_val;
u16 adv_addr;
switch (hw->phy.type) { case e1000_phy_82579:
adv_addr = I82579_EEE_ADVERTISEMENT; break; case e1000_phy_i217:
adv_addr = I217_EEE_ADVERTISEMENT; break; default:
dev_err(&adapter->pdev->dev, "Invalid PHY type setting EEE advertisement\n"); return;
}
ret_val = hw->phy.ops.acquire(hw); if (ret_val) {
dev_err(&adapter->pdev->dev, "EEE advertisement - unable to acquire PHY\n"); return;
}
if (!netif_running(adapter->netdev) &&
!test_bit(__E1000_TESTING, &adapter->state))
e1000_power_down_phy(adapter);
e1000_get_phy_info(hw);
if ((adapter->flags & FLAG_HAS_SMART_POWER_DOWN) &&
!(adapter->flags & FLAG_SMART_POWER_DOWN)) {
u16 phy_data = 0; /* speed up time to link by disabling smart power down, ignore * the return value of this function because there is nothing * different we would do if it failed
*/
e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
phy_data &= ~IGP02E1000_PM_SPD;
e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
} if (hw->mac.type >= e1000_pch_spt && adapter->int_mode == 0) {
u32 reg;
/* due to rare timing issues, write to TIDV/RDTR again to ensure the * write is successful
*/
ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD);
/* execute the writes immediately */
e1e_flush();
}
/** * e1000e_sanitize_systim - sanitize raw cycle counter reads * @hw: pointer to the HW structure * @systim: PHC time value read, sanitized and returned * @sts: structure to hold system time before and after reading SYSTIML, * may be NULL * * Errata for 82574/82583 possible bad bits read from SYSTIMH/L: * check to see that the time is incrementing at a reasonable * rate and is a multiple of incvalue.
**/ static u64 e1000e_sanitize_systim(struct e1000_hw *hw, u64 systim, struct ptp_system_timestamp *sts)
{
u64 time_delta, rem, temp;
u64 systim_next;
u32 incvalue; int i;
incvalue = er32(TIMINCA) & E1000_TIMINCA_INCVALUE_MASK; for (i = 0; i < E1000_MAX_82574_SYSTIM_REREADS; i++) { /* latch SYSTIMH on read of SYSTIML */
ptp_read_system_prets(sts);
systim_next = (u64)er32(SYSTIML);
ptp_read_system_postts(sts);
systim_next |= (u64)er32(SYSTIMH) << 32;
time_delta = systim_next - systim;
temp = time_delta; /* VMWare users have seen incvalue of zero, don't div / 0 */
rem = incvalue ? do_div(temp, incvalue) : (time_delta != 0);
systim = systim_next;
if ((time_delta < E1000_82574_SYSTIM_EPSILON) && (rem == 0)) break;
}
return systim;
}
/** * e1000e_read_systim - read SYSTIM register * @adapter: board private structure * @sts: structure which will contain system time before and after reading * SYSTIML, may be NULL
**/
u64 e1000e_read_systim(struct e1000_adapter *adapter, struct ptp_system_timestamp *sts)
{ struct e1000_hw *hw = &adapter->hw;
u32 systimel, systimel_2, systimeh;
u64 systim; /* SYSTIMH latching upon SYSTIML read does not work well. * This means that if SYSTIML overflows after we read it but before * we read SYSTIMH, the value of SYSTIMH has been incremented and we * will experience a huge non linear increment in the systime value * to fix that we test for overflow and if true, we re-read systime.
*/
ptp_read_system_prets(sts);
systimel = er32(SYSTIML);
ptp_read_system_postts(sts);
systimeh = er32(SYSTIMH); /* Is systimel is so large that overflow is possible? */ if (systimel >= (u32)0xffffffff - E1000_TIMINCA_INCVALUE_MASK) {
ptp_read_system_prets(sts);
systimel_2 = er32(SYSTIML);
ptp_read_system_postts(sts); if (systimel > systimel_2) { /* There was an overflow, read again SYSTIMH, and use * systimel_2
*/
systimeh = er32(SYSTIMH);
systimel = systimel_2;
}
}
systim = (u64)systimel;
systim |= (u64)systimeh << 32;
if (adapter->flags2 & FLAG2_CHECK_SYSTIM_OVERFLOW)
systim = e1000e_sanitize_systim(hw, systim, sts);
e_dbg("icr is %08X\n", icr); if (icr & E1000_ICR_RXSEQ) {
adapter->flags &= ~FLAG_MSI_TEST_FAILED; /* Force memory writes to complete before acknowledging the * interrupt is handled.
*/
wmb();
}
return IRQ_HANDLED;
}
/** * e1000_test_msi_interrupt - Returns 0 for successful test * @adapter: board private struct * * code flow taken from tg3.c
**/ staticint e1000_test_msi_interrupt(struct e1000_adapter *adapter)
{ struct net_device *netdev = adapter->netdev; struct e1000_hw *hw = &adapter->hw; int err;
/* poll_enable hasn't been called yet, so don't need disable */ /* clear any pending events */
er32(ICR);
/* free the real vector and request a test handler */
e1000_free_irq(adapter);
e1000e_reset_interrupt_capability(adapter);
/* Assume that the test fails, if it succeeds then the test * MSI irq handler will unset this flag
*/
adapter->flags |= FLAG_MSI_TEST_FAILED;
err = pci_enable_msi(adapter->pdev); if (err) goto msi_test_failed;
/** * e1000_test_msi - Returns 0 if MSI test succeeds or INTx mode is restored * @adapter: board private struct * * code flow taken from tg3.c, called with e1000 interrupts disabled.
**/ staticint e1000_test_msi(struct e1000_adapter *adapter)
{ int err;
u16 pci_cmd;
if (!(adapter->flags & FLAG_MSI_ENABLED)) return 0;
/* disable SERR in case the MSI write causes a master abort */
pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd); if (pci_cmd & PCI_COMMAND_SERR)
pci_write_config_word(adapter->pdev, PCI_COMMAND,
pci_cmd & ~PCI_COMMAND_SERR);
/** * e1000e_open - Called when a network interface is made active * @netdev: network interface device structure * * Returns 0 on success, negative value on failure * * The open entry point is called when a network interface is made * active by the system (IFF_UP). At this point all resources needed * for transmit and receive operations are allocated, the interrupt * handler is registered with the OS, the watchdog timer is started, * and the stack is notified that the interface is ready.
**/ int e1000e_open(struct net_device *netdev)
{ struct e1000_adapter *adapter = netdev_priv(netdev); struct e1000_hw *hw = &adapter->hw; struct pci_dev *pdev = adapter->pdev; int err; int irq;
/* disallow open during test */ if (test_bit(__E1000_TESTING, &adapter->state)) return -EBUSY;
/* If AMT is enabled, let the firmware know that the network * interface is now open and reset the part to a known state.
*/ if (adapter->flags & FLAG_HAS_AMT) {
e1000e_get_hw_control(adapter);
e1000e_reset(adapter);
}
e1000e_power_up_phy(adapter);
adapter->mng_vlan_id = E1000_MNG_VLAN_NONE; if ((adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
e1000_update_mng_vlan(adapter);
/* before we allocate an interrupt, we must be ready to handle it. * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt * as soon as we call pci_request_irq, so we have to setup our * clean_rx handler before we do so.
*/
e1000_configure(adapter);
err = e1000_request_irq(adapter); if (err) goto err_req_irq;
/* Work around PCIe errata with MSI interrupts causing some chipsets to * ignore e1000e MSI messages, which means we need to test our MSI * interrupt now
*/ if (adapter->int_mode != E1000E_INT_MODE_LEGACY) {
err = e1000_test_msi(adapter); if (err) {
e_err("Interrupt allocation failed\n"); goto err_req_irq;
}
}
/* From here on the code is the same as e1000e_up() */
clear_bit(__E1000_DOWN, &adapter->state);
/** * e1000e_close - Disables a network interface * @netdev: network interface device structure * * Returns 0, this is not allowed to fail * * The close entry point is called when an interface is de-activated * by the OS. The hardware is still under the drivers control, but * needs to be disabled. A global MAC reset is issued to stop the * hardware, and all transmit and receive resources are freed.
**/ int e1000e_close(struct net_device *netdev)
{ struct e1000_adapter *adapter = netdev_priv(netdev); struct pci_dev *pdev = adapter->pdev; int count = E1000_CHECK_RESET_COUNT;
while (test_bit(__E1000_RESETTING, &adapter->state) && count--)
usleep_range(10000, 11000);
/* kill manageability vlan ID if supported, but not if a vlan with * the same ID is registered on the host OS (let 8021q kill it)
*/ if (adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN)
e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q),
adapter->mng_vlan_id);
/* If AMT is enabled, let the firmware know that the network * interface is now closed
*/ if ((adapter->flags & FLAG_HAS_AMT) &&
!test_bit(__E1000_TESTING, &adapter->state))
e1000e_release_hw_control(adapter);
if (adapter->flags & FLAG_RESET_OVERWRITES_LAA) { /* activate the work around */
e1000e_set_laa_state_82571(&adapter->hw, 1);
/* Hold a copy of the LAA in RAR[14] This is done so that * between the time RAR[0] gets clobbered and the time it * gets fixed (in e1000_watchdog), the actual LAA is in one * of the RARs and no incoming packets directed to this port * are dropped. Eventually the LAA will be in RAR[0] and * RAR[14]
*/
hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr,
adapter->hw.mac.rar_entry_count - 1);
}
return 0;
}
/** * e1000e_update_phy_task - work thread to update phy * @work: pointer to our work struct * * this worker thread exists because we must acquire a * semaphore to read the phy, which we could msleep while * waiting for it, and we can't msleep in a timer.
**/ staticvoid e1000e_update_phy_task(struct work_struct *work)
{ struct e1000_adapter *adapter = container_of(work, struct e1000_adapter,
update_phy_task); struct e1000_hw *hw = &adapter->hw;
if (test_bit(__E1000_DOWN, &adapter->state)) return;
e1000_get_phy_info(hw);
/* Enable EEE on 82579 after link up */ if (hw->phy.type >= e1000_phy_82579)
e1000_set_eee_pchlan(hw);
}
/** * e1000_update_phy_info - timre call-back to update PHY info * @t: pointer to timer_list containing private info adapter * * Need to wait a few seconds after link up to get diagnostic information from * the phy
**/ staticvoid e1000_update_phy_info(struct timer_list *t)
{ struct e1000_adapter *adapter = timer_container_of(adapter, t,
phy_info_timer);
if (test_bit(__E1000_DOWN, &adapter->state)) return;
ret_val = hw->phy.ops.acquire(hw); if (ret_val) return;
/* A page set is expensive so check if already on desired page. * If not, set to the page with the PHY status registers.
*/
hw->phy.addr = 1;
ret_val = e1000e_read_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
&phy_data); if (ret_val) goto release; if (phy_data != (HV_STATS_PAGE << IGP_PAGE_SHIFT)) {
ret_val = hw->phy.ops.set_page(hw,
HV_STATS_PAGE << IGP_PAGE_SHIFT); if (ret_val) goto release;
}
/* Single Collision Count */
hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
ret_val = hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data); if (!ret_val)
adapter->stats.scc += phy_data;
/* Prevent stats update while adapter is being reset, or if the pci * connection is down.
*/ if (adapter->link_speed == 0) return; if (pci_channel_offline(pdev)) return;
/* Fill out the OS statistics structure */
netdev->stats.multicast = adapter->stats.mprc;
netdev->stats.collisions = adapter->stats.colc;
/* Rx Errors */
/* RLEC on some newer hardware can be incorrect so build * our own version based on RUC and ROC
*/
netdev->stats.rx_errors = adapter->stats.rxerrc +
adapter->stats.crcerrs + adapter->stats.algnerrc +
adapter->stats.ruc + adapter->stats.roc + adapter->stats.cexterr;
netdev->stats.rx_length_errors = adapter->stats.ruc +
adapter->stats.roc;
netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
netdev->stats.rx_frame_errors = adapter->stats.algnerrc;
netdev->stats.rx_missed_errors = adapter->stats.mpc;
/* With 82574 controllers, PHY needs to be checked periodically * for hung state and reset, if two calls return true
*/ if (e1000_check_phy_82574(hw))
adapter->phy_hang_count++; else
adapter->phy_hang_count = 0;
/* Checking if MAC is in DMoff state*/ if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) {
pcim_state = er32(STATUS); while (pcim_state & E1000_STATUS_PCIM_STATE) { if (tries++ == dmoff_exit_timeout) {
e_dbg("Error in exiting dmoff\n"); break;
}
usleep_range(10000, 20000);
pcim_state = er32(STATUS);
/* Checking if MAC exited DMoff state */ if (!(pcim_state & E1000_STATUS_PCIM_STATE))
e1000_phy_hw_reset(&adapter->hw);
}
}
/* update snapshot of PHY registers on LSC */
e1000_phy_read_status(adapter);
mac->ops.get_link_up_info(&adapter->hw,
&adapter->link_speed,
&adapter->link_duplex);
e1000_print_link_info(adapter);
/* check if SmartSpeed worked */
e1000e_check_downshift(hw); if (phy->speed_downgraded)
netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n");
/* On supported PHYs, check for duplex mismatch only * if link has autonegotiated at 10/100 half
*/ if ((hw->phy.type == e1000_phy_igp_3 ||
hw->phy.type == e1000_phy_bm) &&
hw->mac.autoneg &&
(adapter->link_speed == SPEED_10 ||
adapter->link_speed == SPEED_100) &&
(adapter->link_duplex == HALF_DUPLEX)) {
u16 autoneg_exp;
e1e_rphy(hw, MII_EXPANSION, &autoneg_exp);
if (!(autoneg_exp & EXPANSION_NWAY))
e_info("Autonegotiated half duplex but link partner cannot autoneg. Try forcing full duplex if link gets many collisions.\n");
}
/* adjust timeout factor according to speed/duplex */
adapter->tx_timeout_factor = 1; switch (adapter->link_speed) { case SPEED_10:
txb2b = false;
adapter->tx_timeout_factor = 16; break; case SPEED_100:
txb2b = false;
adapter->tx_timeout_factor = 10; break;
}
/* workaround: re-program speed mode bit after * link-up event
*/ if ((adapter->flags & FLAG_TARC_SPEED_MODE_BIT) &&
!txb2b) {
u32 tarc0;
if (!test_bit(__E1000_DOWN, &adapter->state))
mod_timer(&adapter->phy_info_timer,
round_jiffies(jiffies + 2 * HZ));
}
} else { if (netif_carrier_ok(netdev)) {
adapter->link_speed = 0;
adapter->link_duplex = 0; /* Link status message must follow this format */
netdev_info(netdev, "NIC Link is Down\n");
netif_carrier_off(netdev);
netif_stop_queue(netdev); if (!test_bit(__E1000_DOWN, &adapter->state))
mod_timer(&adapter->phy_info_timer,
round_jiffies(jiffies + 2 * HZ));
/* 8000ES2LAN requires a Rx packet buffer work-around * on link down event; reset the controller to flush * the Rx packet buffer.
*/ if (adapter->flags & FLAG_RX_NEEDS_RESTART)
adapter->flags |= FLAG_RESTART_NOW; else
pm_schedule_suspend(netdev->dev.parent,
LINK_TIMEOUT);
}
}
/* If the link is lost the controller stops DMA, but * if there is queued Tx work it cannot be done. So * reset the controller to flush the Tx packet buffers.
*/ if (!netif_carrier_ok(netdev) &&
(e1000_desc_unused(tx_ring) + 1 < tx_ring->count))
adapter->flags |= FLAG_RESTART_NOW;
/* If reset is necessary, do it outside of interrupt context. */ if (adapter->flags & FLAG_RESTART_NOW) {
schedule_work(&adapter->reset_task); /* return immediately since reset is imminent */ return;
}
/* Cause software interrupt to ensure Rx ring is cleaned */ if (adapter->msix_entries)
ew32(ICS, adapter->rx_ring->ims_val); else
ew32(ICS, E1000_ICS_RXDMT0);
/* flush pending descriptors to memory before detecting Tx hang */
e1000e_flush_descriptors(adapter);
/* Force detection of hung controller every watchdog period */
adapter->detect_tx_hung = true;
/* With 82571 controllers, LAA may be overwritten due to controller * reset from the other port. Set the appropriate LAA in RAR[0]
*/ if (e1000e_get_laa_state_82571(hw))
hw->mac.ops.rar_set(hw, adapter->hw.mac.addr, 0);
if (adapter->flags2 & FLAG2_CHECK_PHY_HANG)
e1000e_check_82574_phy_workaround(adapter);
/* Clear valid timestamp stuck in RXSTMPL/H due to a Rx error */ if (adapter->hwtstamp_config.rx_filter != HWTSTAMP_FILTER_NONE) { if ((adapter->flags2 & FLAG2_CHECK_RX_HWTSTAMP) &&
(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID)) {
er32(RXSTMPH);
adapter->rx_hwtstamp_cleared++;
} else {
adapter->flags2 |= FLAG2_CHECK_RX_HWTSTAMP;
}
}
/* Reset the timer */ if (!test_bit(__E1000_DOWN, &adapter->state))
mod_timer(&adapter->watchdog_timer,
round_jiffies(jiffies + 2 * HZ));
}
/* txd_cmd re-enables FCS, so we'll re-disable it here as desired. */ if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS))
tx_desc->lower.data &= ~(cpu_to_le32(E1000_TXD_CMD_IFCS));
/* Force memory writes to complete before letting h/w * know there are new descriptors to fetch. (Only * applicable for weak-ordered memory model archs, * such as IA-64).
*/
wmb();
netif_stop_queue(adapter->netdev); /* Herbert's original patch had: * smp_mb__after_netif_stop_queue(); * but since that doesn't exist yet, just open code it.
*/
smp_mb();
/* We need to check again in a case another CPU has just * made room available.
*/ if (e1000_desc_unused(tx_ring) < size) return -EBUSY;
/* A reprieve! */
netif_start_queue(adapter->netdev);
++adapter->restart_queue; return 0;
}
staticint e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size)
{
BUG_ON(size > tx_ring->count);
if (e1000_desc_unused(tx_ring) >= size) return 0; return __e1000_maybe_stop_tx(tx_ring, size);
}
if (test_bit(__E1000_DOWN, &adapter->state)) {
dev_kfree_skb_any(skb); return NETDEV_TX_OK;
}
if (skb->len <= 0) {
dev_kfree_skb_any(skb); return NETDEV_TX_OK;
}
/* The minimum packet size with TCTL.PSP set is 17 bytes so * pad skb in order to meet this minimum size requirement
*/ if (skb_put_padto(skb, 17)) return NETDEV_TX_OK;
mss = skb_shinfo(skb)->gso_size; if (mss) {
u8 hdr_len;
/* TSO Workaround for 82571/2/3 Controllers -- if skb->data * points to just header, pull a few bytes of payload from * frags into skb->data
*/
hdr_len = skb_tcp_all_headers(skb); /* we do this workaround for ES2LAN, but it is un-necessary, * avoiding it could save a lot of cycles
*/ if (skb->data_len && (hdr_len == len)) { unsignedint pull_size;
pull_size = min_t(unsignedint, 4, skb->data_len); if (!__pskb_pull_tail(skb, pull_size)) {
e_err("__pskb_pull_tail failed.\n");
dev_kfree_skb_any(skb); return NETDEV_TX_OK;
}
len = skb_headlen(skb);
}
}
/* reserve a descriptor for the offload context */ if ((mss) || (skb->ip_summed == CHECKSUM_PARTIAL))
count++;
count++;
nr_frags = skb_shinfo(skb)->nr_frags; for (f = 0; f < nr_frags; f++)
count += DIV_ROUND_UP(skb_frag_size(&skb_shinfo(skb)->frags[f]),
adapter->tx_fifo_limit);
if (adapter->hw.mac.tx_pkt_filtering)
e1000_transfer_dhcp_info(adapter, skb);
/* need: count + 2 desc gap to keep tail from touching * head, otherwise try next time
*/ if (e1000_maybe_stop_tx(tx_ring, count + 2)) return NETDEV_TX_BUSY;
/* Old method was to assume IPv4 packet by default if TSO was enabled. * 82571 hardware supports TSO capabilities for IPv6 as well... * no longer assume, we must.
*/ if (protocol == htons(ETH_P_IP))
tx_flags |= E1000_TX_FLAGS_IPV4;
if (unlikely(skb->no_fcs))
tx_flags |= E1000_TX_FLAGS_NO_FCS;
/* if count is 0 then mapping error has occurred */
count = e1000_tx_map(tx_ring, skb, first, adapter->tx_fifo_limit,
nr_frags); if (count) { if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
(adapter->flags & FLAG_HAS_HW_TIMESTAMP)) { if (!adapter->tx_hwtstamp_skb) {
skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
tx_flags |= E1000_TX_FLAGS_HWTSTAMP;
adapter->tx_hwtstamp_skb = skb_get(skb);
adapter->tx_hwtstamp_start = jiffies;
schedule_work(&adapter->tx_hwtstamp_work);
} else {
adapter->tx_hwtstamp_skipped++;
}
}
skb_tx_timestamp(skb);
netdev_sent_queue(netdev, skb->len);
e1000_tx_queue(tx_ring, tx_flags, count); /* Make sure there is space in the ring for the next send. */
e1000_maybe_stop_tx(tx_ring,
((MAX_SKB_FRAGS + 1) *
DIV_ROUND_UP(PAGE_SIZE,
adapter->tx_fifo_limit) + 4));
/** * e1000e_get_stats64 - Get System Network Statistics * @netdev: network interface device structure * @stats: rtnl_link_stats64 pointer * * Returns the address of the device statistics structure.
**/ void e1000e_get_stats64(struct net_device *netdev, struct rtnl_link_stats64 *stats)
{ struct e1000_adapter *adapter = netdev_priv(netdev);
spin_lock(&adapter->stats64_lock);
e1000e_update_stats(adapter); /* Fill out the OS statistics structure */
stats->rx_bytes = adapter->stats.gorc;
stats->rx_packets = adapter->stats.gprc;
stats->tx_bytes = adapter->stats.gotc;
stats->tx_packets = adapter->stats.gptc;
stats->multicast = adapter->stats.mprc;
stats->collisions = adapter->stats.colc;
/* Rx Errors */
/* RLEC on some newer hardware can be incorrect so build * our own version based on RUC and ROC
*/
stats->rx_errors = adapter->stats.rxerrc +
adapter->stats.crcerrs + adapter->stats.algnerrc +
adapter->stats.ruc + adapter->stats.roc + adapter->stats.cexterr;
stats->rx_length_errors = adapter->stats.ruc + adapter->stats.roc;
stats->rx_crc_errors = adapter->stats.crcerrs;
stats->rx_frame_errors = adapter->stats.algnerrc;
stats->rx_missed_errors = adapter->stats.mpc;
/** * e1000_change_mtu - Change the Maximum Transfer Unit * @netdev: network interface device structure * @new_mtu: new value for maximum frame size * * Returns 0 on success, negative on failure
**/ staticint e1000_change_mtu(struct net_device *netdev, int new_mtu)
{ struct e1000_adapter *adapter = netdev_priv(netdev); int max_frame = new_mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
/* Jumbo frame support */ if ((new_mtu > ETH_DATA_LEN) &&
!(adapter->flags & FLAG_HAS_JUMBO_FRAMES)) {
e_err("Jumbo Frames not supported.\n"); return -EINVAL;
}
/* Jumbo frame workaround on 82579 and newer requires CRC be stripped */ if ((adapter->hw.mac.type >= e1000_pch2lan) &&
!(adapter->flags2 & FLAG2_CRC_STRIPPING) &&
(new_mtu > ETH_DATA_LEN)) {
e_err("Jumbo Frames not supported on this device when CRC stripping is disabled.\n"); return -EINVAL;
}
while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
usleep_range(1000, 1100); /* e1000e_down -> e1000e_reset dependent on max_frame_size & mtu */
adapter->max_frame_size = max_frame;
netdev_dbg(netdev, "changing MTU from %d to %d\n",
netdev->mtu, new_mtu);
WRITE_ONCE(netdev->mtu, new_mtu);
pm_runtime_get_sync(netdev->dev.parent);
if (netif_running(netdev))
e1000e_down(adapter, true);
/* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN * means we reserve 2 more, this pushes us to allocate from the next * larger slab size. * i.e. RXBUFFER_2048 --> size-4096 slab * However with the new *_jumbo_rx* routines, jumbo receives will use * fragmented skbs
*/
/* adjust allocation if LPE protects us, and we aren't using SBP */ if (max_frame <= (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN))
adapter->rx_buffer_len = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN;
if (netif_running(netdev))
e1000e_up(adapter); else
e1000e_reset(adapter);
if (adapter->hw.phy.media_type != e1000_media_type_copper) return -EOPNOTSUPP;
switch (cmd) { case SIOCGMIIPHY:
data->phy_id = adapter->hw.phy.addr; break; case SIOCGMIIREG:
e1000_phy_read_status(adapter);
switch (data->reg_num & 0x1F) { case MII_BMCR:
data->val_out = adapter->phy_regs.bmcr; break; case MII_BMSR:
data->val_out = adapter->phy_regs.bmsr; break; case MII_PHYSID1:
data->val_out = (adapter->hw.phy.id >> 16); break; case MII_PHYSID2:
data->val_out = (adapter->hw.phy.id & 0xFFFF); break; case MII_ADVERTISE:
data->val_out = adapter->phy_regs.advertise; break; case MII_LPA:
data->val_out = adapter->phy_regs.lpa; break; case MII_EXPANSION:
data->val_out = adapter->phy_regs.expansion; break; case MII_CTRL1000:
data->val_out = adapter->phy_regs.ctrl1000; break; case MII_STAT1000:
data->val_out = adapter->phy_regs.stat1000; break; case MII_ESTATUS:
data->val_out = adapter->phy_regs.estatus; break; default: return -EIO;
} break; case SIOCSMIIREG: default: return -EOPNOTSUPP;
} return 0;
}
/** * e1000e_hwtstamp_set - control hardware time stamping * @netdev: network interface device structure * @config: timestamp configuration * @extack: netlink extended ACK report * * Outgoing time stamping can be enabled and disabled. Play nice and * disable it when requested, although it shouldn't cause any overhead * when no packet needs it. At most one packet in the queue may be * marked for time stamping, otherwise it would be impossible to tell * for sure to which packet the hardware time stamp belongs. * * Incoming time stamping has to be configured via the hardware filters. * Not all combinations are supported, in particular event type has to be * specified. Matching the kind of event packet is not supported, with the * exception of "all V2 events regardless of level 2 or 4".
**/ staticint e1000e_hwtstamp_set(struct net_device *netdev, struct kernel_hwtstamp_config *config, struct netlink_ext_ack *extack)
{ struct e1000_adapter *adapter = netdev_priv(netdev); int ret_val;
ret_val = e1000e_config_hwtstamp(adapter, config, extack); if (ret_val) return ret_val;
switch (config->rx_filter) { case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: case HWTSTAMP_FILTER_PTP_V2_SYNC: case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: /* With V2 type filters which specify a Sync or Delay Request, * Path Delay Request/Response messages are also time stamped * by hardware so notify the caller the requested packets plus * some others are time stamped.
*/
config->rx_filter = HWTSTAMP_FILTER_SOME; break; default: break;
}
/* copy MAC RARs to PHY RARs */
e1000_copy_rx_addrs_to_phy_ich8lan(hw);
retval = hw->phy.ops.acquire(hw); if (retval) {
e_err("Could not acquire PHY\n"); return retval;
}
/* Enable access to wakeup registers on and set page to BM_WUC_PAGE */
retval = e1000_enable_phy_wakeup_reg_access_bm(hw, &wuc_enable); if (retval) goto release;
/* copy MAC MTA to PHY MTA - only needed for pchlan */ for (i = 0; i < adapter->hw.mac.mta_reg_count; i++) {
mac_reg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i);
hw->phy.ops.write_reg_page(hw, BM_MTA(i),
(u16)(mac_reg & 0xFFFF));
hw->phy.ops.write_reg_page(hw, BM_MTA(i) + 1,
(u16)((mac_reg >> 16) & 0xFFFF));
}
/* configure PHY Rx Control register */
hw->phy.ops.read_reg_page(&adapter->hw, BM_RCTL, &phy_reg);
mac_reg = er32(RCTL); if (mac_reg & E1000_RCTL_UPE)
phy_reg |= BM_RCTL_UPE; if (mac_reg & E1000_RCTL_MPE)
phy_reg |= BM_RCTL_MPE;
phy_reg &= ~(BM_RCTL_MO_MASK); if (mac_reg & E1000_RCTL_MO_3)
phy_reg |= (FIELD_GET(E1000_RCTL_MO_3, mac_reg)
<< BM_RCTL_MO_SHIFT); if (mac_reg & E1000_RCTL_BAM)
phy_reg |= BM_RCTL_BAM; if (mac_reg & E1000_RCTL_PMCF)
phy_reg |= BM_RCTL_PMCF;
mac_reg = er32(CTRL); if (mac_reg & E1000_CTRL_RFCE)
phy_reg |= BM_RCTL_RFCE;
hw->phy.ops.write_reg_page(&adapter->hw, BM_RCTL, phy_reg);
if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID &&
hw->mac.type >= e1000_pch_adp) { /* Request ME configure the device for S0ix */
mac_data = er32(H2ME);
mac_data |= E1000_H2ME_START_DPG;
mac_data &= ~E1000_H2ME_EXIT_DPG;
trace_e1000e_trace_mac_register(mac_data);
ew32(H2ME, mac_data);
} else { /* Request driver configure the device to S0ix */ /* Disable the periodic inband message, * don't request PCIe clock in K1 page770_17[10:9] = 10b
*/
e1e_rphy(hw, HV_PM_CTRL, &phy_data);
phy_data &= ~HV_PM_CTRL_K1_CLK_REQ;
phy_data |= BIT(10);
e1e_wphy(hw, HV_PM_CTRL, phy_data);
/* Make sure we don't exit K1 every time a new packet arrives * 772_29[5] = 1 CS_Mode_Stay_In_K1
*/
e1e_rphy(hw, I217_CGFREG, &phy_data);
phy_data |= BIT(5);
e1e_wphy(hw, I217_CGFREG, phy_data);
/* Change the MAC/PHY interface to SMBus * Force the SMBus in PHY page769_23[0] = 1 * Force the SMBus in MAC CTRL_EXT[11] = 1
*/
e1e_rphy(hw, CV_SMB_CTRL, &phy_data);
phy_data |= CV_SMB_CTRL_FORCE_SMBUS;
e1e_wphy(hw, CV_SMB_CTRL, phy_data);
mac_data = er32(CTRL_EXT);
mac_data |= E1000_CTRL_EXT_FORCE_SMBUS;
ew32(CTRL_EXT, mac_data);
/* Disable disconnected cable conditioning for Power Gating */
mac_data = er32(DPGFR);
mac_data |= BIT(2);
ew32(DPGFR, mac_data);
/* Enable the Dynamic Clock Gating in the DMA and MAC */
mac_data = er32(CTRL_EXT);
mac_data |= E1000_CTRL_EXT_DMA_DYN_CLK_EN;
ew32(CTRL_EXT, mac_data);
}
/* Enable the Dynamic Power Gating in the MAC */
mac_data = er32(FEXTNVM7);
mac_data |= BIT(22);
ew32(FEXTNVM7, mac_data);
/* Don't wake from dynamic Power Gating with clock request */
mac_data = er32(FEXTNVM12);
mac_data |= BIT(12);
ew32(FEXTNVM12, mac_data);
/* Enable K1 off to enable mPHY Power Gating */
mac_data = er32(FEXTNVM6);
mac_data |= BIT(31);
ew32(FEXTNVM6, mac_data);
/* Enable mPHY power gating for any link and speed */
mac_data = er32(FEXTNVM8);
mac_data |= BIT(9);
ew32(FEXTNVM8, mac_data);
/* No MAC DPG gating SLP_S0 in modern standby * Switch the logic of the lanphypc to use PMC counter
*/
mac_data = er32(FEXTNVM5);
mac_data |= BIT(7);
ew32(FEXTNVM5, mac_data);
/* Disable the time synchronization clock */
mac_data = er32(FEXTNVM7);
mac_data |= BIT(31);
mac_data &= ~BIT(0);
ew32(FEXTNVM7, mac_data);
if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID &&
hw->mac.type >= e1000_pch_adp) { /* Keep the GPT clock enabled for CSME */
mac_data = er32(FEXTNVM);
mac_data |= BIT(3);
ew32(FEXTNVM, mac_data); /* Request ME unconfigure the device from S0ix */
mac_data = er32(H2ME);
mac_data &= ~E1000_H2ME_START_DPG;
mac_data |= E1000_H2ME_EXIT_DPG;
trace_e1000e_trace_mac_register(mac_data);
ew32(H2ME, mac_data);
/* Poll up to 2.5 seconds for ME to unconfigure DPG. * If this takes more than 1 second, show a warning indicating a * firmware bug
*/ while (!(er32(EXFWSM) & E1000_EXFWSM_DPG_EXIT_DONE)) { if (i > 100 && !firmware_bug)
firmware_bug = true;
if (i++ == 250) {
e_dbg("Timeout (firmware bug): %d msec\n",
i * 10); break;
}
usleep_range(10000, 11000);
} if (firmware_bug)
e_warn("DPG_EXIT_DONE took %d msec. This is a firmware bug\n",
i * 10); else
e_dbg("DPG_EXIT_DONE cleared after %d msec\n", i * 10);
} else { /* Request driver unconfigure the device from S0ix */
/* Cancel disable disconnected cable conditioning * for Power Gating
*/
mac_data = er32(DPGFR);
mac_data &= ~BIT(2);
ew32(DPGFR, mac_data);
/* Disable the Dynamic Clock Gating in the DMA and MAC */
mac_data = er32(CTRL_EXT);
mac_data &= 0xFFF7FFFF;
ew32(CTRL_EXT, mac_data);
/* Cancel not waking from dynamic * Power Gating with clock request
*/
mac_data = er32(FEXTNVM12);
mac_data &= ~BIT(12);
ew32(FEXTNVM12, mac_data);
/* Revert the lanphypc logic to use the internal Gbe counter * and not the PMC counter
*/
mac_data = er32(FEXTNVM5);
mac_data &= 0xFFFFFF7F;
ew32(FEXTNVM5, mac_data);
}
/* Runtime suspend should only enable wakeup for link changes */ if (runtime)
wufc = E1000_WUFC_LNKC; elseif (device_may_wakeup(&pdev->dev))
wufc = adapter->wol; else
wufc = 0;
status = er32(STATUS); if (status & E1000_STATUS_LU)
wufc &= ~E1000_WUFC_LNKC;
if (wufc) {
e1000_setup_rctl(adapter);
e1000e_set_rx_mode(netdev);
/* turn on all-multi mode if wake on multicast is enabled */ if (wufc & E1000_WUFC_MC) {
rctl = er32(RCTL);
rctl |= E1000_RCTL_MPE;
ew32(RCTL, rctl);
}
if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
adapter->hw.phy.media_type ==
e1000_media_type_internal_serdes) { /* keep the laser running in D3 */
ctrl_ext = er32(CTRL_EXT);
ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA;
ew32(CTRL_EXT, ctrl_ext);
}
if (!runtime)
e1000e_power_up_phy(adapter);
if (adapter->flags & FLAG_IS_ICH)
e1000_suspend_workarounds_ich8lan(&adapter->hw);
if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) { /* enable wakeup by the PHY */
retval = e1000_init_phy_wakeup(adapter, wufc); if (retval) {
e_err("Failed to enable wakeup\n"); goto skip_phy_configurations;
}
} else { /* enable wakeup by the MAC */
ew32(WUFC, wufc);
ew32(WUC, E1000_WUC_PME_EN);
}
} else {
ew32(WUC, 0);
ew32(WUFC, 0);
e1000_power_down_phy(adapter);
}
if (adapter->hw.phy.type == e1000_phy_igp_3) {
e1000e_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw);
} elseif (hw->mac.type >= e1000_pch_lpt) { if (wufc && !(wufc & (E1000_WUFC_EX | E1000_WUFC_MC | E1000_WUFC_BC))) { /* ULP does not support wake from unicast, multicast * or broadcast.
*/
retval = e1000_enable_ulp_lpt_lp(hw, !runtime); if (retval) {
e_err("Failed to enable ULP\n"); goto skip_phy_configurations;
}
}
}
/* Ensure that the appropriate bits are set in LPI_CTRL * for EEE in Sx
*/ if ((hw->phy.type >= e1000_phy_i217) &&
adapter->eee_advert && hw->dev_spec.ich8lan.eee_lp_ability) {
u16 lpi_ctrl = 0;
retval = hw->phy.ops.acquire(hw); if (!retval) {
retval = e1e_rphy_locked(hw, I82579_LPI_CTRL,
&lpi_ctrl); if (!retval) { if (adapter->eee_advert &
hw->dev_spec.ich8lan.eee_lp_ability &
I82579_EEE_100_SUPPORTED)
lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE; if (adapter->eee_advert &
hw->dev_spec.ich8lan.eee_lp_ability &
I82579_EEE_1000_SUPPORTED)
lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;
skip_phy_configurations: /* Release control of h/w to f/w. If f/w is AMT enabled, this * would have already happened in close and is redundant.
*/
e1000e_release_hw_control(adapter);
pci_clear_master(pdev);
/* The pci-e switch on some quad port adapters will report a * correctable error when the MAC transitions from D0 to D3. To * prevent this we need to mask off the correctable errors on the * downstream port of the pci-e switch. * * We don't have the associated upstream bridge while assigning * the PCI device into guest. For example, the KVM on power is * one of the cases.
*/ if (adapter->flags & FLAG_IS_QUAD_PORT) { struct pci_dev *us_dev = pdev->bus->self;
u16 devctl;
if (parent) {
pcie_capability_read_word(parent, PCI_EXP_LNKCTL,
&parent_aspmc);
parent_aspmc &= PCI_EXP_LNKCTL_ASPMC;
}
/* Nothing to do if the ASPM states to be disabled already are */ if (!(pdev_aspmc & aspm_dis_mask) &&
(!parent || !(parent_aspmc & aspm_dis_mask))) return;
#ifdef CONFIG_PCIEASPM if (locked)
pci_disable_link_state_locked(pdev, state); else
pci_disable_link_state(pdev, state);
/* Double-check ASPM control. If not disabled by the above, the * BIOS is preventing that from happening (or CONFIG_PCIEASPM is * not enabled); override by writing PCI config space directly.
*/
pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &pdev_aspmc);
pdev_aspmc &= PCI_EXP_LNKCTL_ASPMC;
if (!(aspm_dis_mask & pdev_aspmc)) return; #endif
/* Both device and parent should have the same ASPM setting. * Disable ASPM in downstream component first and then upstream.
*/
pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL, aspm_dis_mask);
if (parent)
pcie_capability_clear_word(parent, PCI_EXP_LNKCTL,
aspm_dis_mask);
}
/** * e1000e_disable_aspm - Disable ASPM states. * @pdev: pointer to PCI device struct * @state: bit-mask of ASPM states to disable * * This function acquires the pci_bus_sem! * Some devices *must* have certain ASPM states disabled per hardware errata.
**/ staticvoid e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
{
__e1000e_disable_aspm(pdev, state, 0);
}
/** * e1000e_disable_aspm_locked - Disable ASPM states. * @pdev: pointer to PCI device struct * @state: bit-mask of ASPM states to disable * * This function must be called with pci_bus_sem acquired! * Some devices *must* have certain ASPM states disabled per hardware errata.
**/ staticvoid e1000e_disable_aspm_locked(struct pci_dev *pdev, u16 state)
{
__e1000e_disable_aspm(pdev, state, 1);
}
/* If the controller has AMT, do not set DRV_LOAD until the interface * is up. For all other cases, let the f/w know that the h/w is now * under the control of the driver.
*/ if (!(adapter->flags & FLAG_HAS_AMT))
e1000e_get_hw_control(adapter);
vector++;
msix_irq = adapter->msix_entries[vector].vector; if (disable_hardirq(msix_irq))
e1000_intr_msix_tx(msix_irq, netdev);
enable_irq(msix_irq);
vector++;
msix_irq = adapter->msix_entries[vector].vector; if (disable_hardirq(msix_irq))
e1000_msix_other(msix_irq, netdev);
enable_irq(msix_irq);
}
return IRQ_HANDLED;
}
/** * e1000_netpoll * @netdev: network interface device structure * * Polling 'interrupt' - used by things like netconsole to send skbs * without having to re-enable interrupts. It's not called while * the interrupt routine is executing.
*/ staticvoid e1000_netpoll(struct net_device *netdev)
{ struct e1000_adapter *adapter = netdev_priv(netdev);
switch (adapter->int_mode) { case E1000E_INT_MODE_MSIX:
e1000_intr_msix(adapter->pdev->irq, netdev); break; case E1000E_INT_MODE_MSI: if (disable_hardirq(adapter->pdev->irq))
e1000_intr_msi(adapter->pdev->irq, netdev);
enable_irq(adapter->pdev->irq); break; default: /* E1000E_INT_MODE_LEGACY */ if (disable_hardirq(adapter->pdev->irq))
e1000_intr(adapter->pdev->irq, netdev);
enable_irq(adapter->pdev->irq); break;
}
} #endif
/** * e1000_io_error_detected - called when PCI error is detected * @pdev: Pointer to PCI device * @state: The current pci connection state * * This function is called after a PCI bus error affecting * this device has been detected.
*/ static pci_ers_result_t e1000_io_error_detected(struct pci_dev *pdev,
pci_channel_state_t state)
{
e1000e_pm_freeze(&pdev->dev);
if (state == pci_channel_io_perm_failure) return PCI_ERS_RESULT_DISCONNECT;
pci_disable_device(pdev);
/* Request a slot reset. */ return PCI_ERS_RESULT_NEED_RESET;
}
/** * e1000_io_slot_reset - called after the pci bus has been reset. * @pdev: Pointer to PCI device * * Restart the card from scratch, as if from a cold-boot. Implementation * resembles the first-half of the e1000e_pm_resume routine.
*/ static pci_ers_result_t e1000_io_slot_reset(struct pci_dev *pdev)
{ struct net_device *netdev = pci_get_drvdata(pdev); struct e1000_adapter *adapter = netdev_priv(netdev); struct e1000_hw *hw = &adapter->hw;
u16 aspm_disable_flag = 0; int err;
pci_ers_result_t result;
if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S)
aspm_disable_flag = PCIE_LINK_STATE_L0S; if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1)
aspm_disable_flag |= PCIE_LINK_STATE_L1; if (aspm_disable_flag)
e1000e_disable_aspm_locked(pdev, aspm_disable_flag);
err = pci_enable_device_mem(pdev); if (err) {
dev_err(&pdev->dev, "Cannot re-enable PCI device after reset.\n");
result = PCI_ERS_RESULT_DISCONNECT;
} else {
pdev->state_saved = true;
pci_restore_state(pdev);
pci_set_master(pdev);
e1000e_reset(adapter);
ew32(WUS, ~0);
result = PCI_ERS_RESULT_RECOVERED;
}
return result;
}
/** * e1000_io_resume - called when traffic can start flowing again. * @pdev: Pointer to PCI device * * This callback is called when the error recovery driver tells us that * its OK to resume normal operation. Implementation resembles the * second-half of the e1000e_pm_resume routine.
*/ staticvoid e1000_io_resume(struct pci_dev *pdev)
{ struct net_device *netdev = pci_get_drvdata(pdev); struct e1000_adapter *adapter = netdev_priv(netdev);
e1000_init_manageability_pt(adapter);
e1000e_pm_thaw(&pdev->dev);
/* If the controller has AMT, do not set DRV_LOAD until the interface * is up. For all other cases, let the f/w know that the h/w is now * under the control of the driver.
*/ if (!(adapter->flags & FLAG_HAS_AMT))
e1000e_get_hw_control(adapter);
}
/* Jumbo frame workaround on 82579 and newer requires CRC be stripped */ if ((hw->mac.type >= e1000_pch2lan) && (netdev->mtu > ETH_DATA_LEN))
features &= ~NETIF_F_RXFCS;
/* Since there is no support for separate Rx/Tx vlan accel * enable/disable make sure Tx flag is always in same state as Rx.
*/ if (features & NETIF_F_HW_VLAN_CTAG_RX)
features |= NETIF_F_HW_VLAN_CTAG_TX; else
features &= ~NETIF_F_HW_VLAN_CTAG_TX;
if (changed & NETIF_F_RXFCS) { if (features & NETIF_F_RXFCS) {
adapter->flags2 &= ~FLAG2_CRC_STRIPPING;
} else { /* We need to take it back to defaults, which might mean * stripping is still disabled at the adapter level.
*/ if (adapter->flags2 & FLAG2_DFLT_CRC_STRIPPING)
adapter->flags2 |= FLAG2_CRC_STRIPPING; else
adapter->flags2 &= ~FLAG2_CRC_STRIPPING;
}
}
netdev->features = features;
if (netif_running(netdev))
e1000e_reinit_locked(adapter); else
e1000e_reset(adapter);
if (e1000e_enable_mng_pass_thru(&adapter->hw))
adapter->flags |= FLAG_MNG_PT_ENABLED;
/* before reading the NVM, reset the controller to * put the device in a known good starting state
*/
adapter->hw.mac.ops.reset_hw(&adapter->hw);
/* systems with ASPM and others may see the checksum fail on the first * attempt. Let's give it a few tries
*/ for (i = 0;; i++) { if (e1000_validate_nvm_checksum(&adapter->hw) >= 0) break; if (i == 2) {
dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
err = -EIO; goto err_eeprom;
}
}
e1000_eeprom_checks(adapter);
/* copy the MAC address */ if (e1000e_read_mac_addr(&adapter->hw))
dev_err(&pdev->dev, "NVM Read Error while reading MAC address\n");
eth_hw_addr_set(netdev, adapter->hw.mac.addr);
if (!is_valid_ether_addr(netdev->dev_addr)) {
dev_err(&pdev->dev, "Invalid MAC Address: %pM\n",
netdev->dev_addr);
err = -EIO; goto err_eeprom;
}
/* Initialize link parameters. User can change them with ethtool */
adapter->hw.mac.autoneg = 1;
adapter->fc_autoneg = true;
adapter->hw.fc.requested_mode = e1000_fc_default;
adapter->hw.fc.current_mode = e1000_fc_default;
adapter->hw.phy.autoneg_advertised = 0x2f;
/* Initial Wake on LAN setting - If APM wake is enabled in * the EEPROM, enable the ACPI Magic Packet filter
*/ if (adapter->flags & FLAG_APME_IN_WUC) { /* APME bit in EEPROM is mapped to WUC.APME */
eeprom_data = er32(WUC);
eeprom_apme_mask = E1000_WUC_APME; if ((hw->mac.type > e1000_ich10lan) &&
(eeprom_data & E1000_WUC_PHY_WAKE))
adapter->flags2 |= FLAG2_HAS_PHY_WAKEUP;
} elseif (adapter->flags & FLAG_APME_IN_CTRL3) { if (adapter->flags & FLAG_APME_CHECK_PORT_B &&
(adapter->hw.bus.func == 1))
ret_val = e1000_read_nvm(&adapter->hw,
NVM_INIT_CONTROL3_PORT_B,
1, &eeprom_data); else
ret_val = e1000_read_nvm(&adapter->hw,
NVM_INIT_CONTROL3_PORT_A,
1, &eeprom_data);
}
/* fetch WoL from EEPROM */ if (ret_val)
e_dbg("NVM read error getting WoL initial values: %d\n", ret_val); elseif (eeprom_data & eeprom_apme_mask)
adapter->eeprom_wol |= E1000_WUFC_MAG;
/* now that we have the eeprom settings, apply the special cases * where the eeprom may be wrong or the board simply won't support * wake on lan on a particular port
*/ if (!(adapter->flags & FLAG_HAS_WOL))
adapter->eeprom_wol = 0;
/* initialize the wol settings based on the eeprom settings */
adapter->wol = adapter->eeprom_wol;
/* make sure adapter isn't asleep if manageability is enabled */ if (adapter->wol || (adapter->flags & FLAG_MNG_PT_ENABLED) ||
(hw->mac.ops.check_mng_mode(hw)))
device_wakeup_enable(&pdev->dev);
/* save off EEPROM version number */
ret_val = e1000_read_nvm(&adapter->hw, 5, 1, &adapter->eeprom_vers);
/* reset the hardware with the new settings */
e1000e_reset(adapter);
/* If the controller has AMT, do not set DRV_LOAD until the interface * is up. For all other cases, let the f/w know that the h/w is now * under the control of the driver.
*/ if (!(adapter->flags & FLAG_HAS_AMT))
e1000e_get_hw_control(adapter);
if (hw->mac.type >= e1000_pch_cnp)
adapter->flags2 |= FLAG2_ENABLE_S0IX_FLOWS;
strscpy(netdev->name, "eth%d", sizeof(netdev->name));
err = register_netdev(netdev); if (err) goto err_register;
/* carrier off reporting is important to ethtool even BEFORE open */
netif_carrier_off(netdev);
/** * e1000_remove - Device Removal Routine * @pdev: PCI device information struct * * e1000_remove is called by the PCI subsystem to alert the driver * that it should release a PCI device. This could be caused by a * Hot-Plug event, or because the driver is going to be removed from * memory.
**/ staticvoid e1000_remove(struct pci_dev *pdev)
{ struct net_device *netdev = pci_get_drvdata(pdev); struct e1000_adapter *adapter = netdev_priv(netdev);
e1000e_ptp_remove(adapter);
/* The timers may be rescheduled, so explicitly disable them * from being rescheduled.
*/
set_bit(__E1000_DOWN, &adapter->state);
timer_delete_sync(&adapter->watchdog_timer);
timer_delete_sync(&adapter->phy_info_timer);
if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) {
cancel_work_sync(&adapter->tx_hwtstamp_work); if (adapter->tx_hwtstamp_skb) {
dev_consume_skb_any(adapter->tx_hwtstamp_skb);
adapter->tx_hwtstamp_skb = NULL;
}
}
unregister_netdev(netdev);
if (pci_dev_run_wake(pdev))
pm_runtime_get_noresume(&pdev->dev);
/* Release control of h/w to f/w. If f/w is AMT enabled, this * would have already happened in close and is redundant.
*/
e1000e_release_hw_control(adapter);
/** * e1000_init_module - Driver Registration Routine * * e1000_init_module is the first routine called when the driver is * loaded. All it does is register with the PCI subsystem.
**/ staticint __init e1000_init_module(void)
{
pr_info("Intel(R) PRO/1000 Network Driver\n");
pr_info("Copyright(c) 1999 - 2015 Intel Corporation.\n");
/** * e1000_exit_module - Driver Exit Cleanup Routine * * e1000_exit_module is called just before the driver is removed * from memory.
**/ staticvoid __exit e1000_exit_module(void)
{
pci_unregister_driver(&e1000_driver);
}
module_exit(e1000_exit_module);
¤ Die Informationen auf dieser Webseite wurden
nach bestem Wissen sorgfältig zusammengestellt. Es wird jedoch weder Vollständigkeit, noch Richtigkeit,
noch Qualität der bereit gestellten Informationen zugesichert.0.150Bemerkung:
(vorverarbeitet am 2026-04-28)
¤
Die Informationen auf dieser Webseite wurden
nach bestem Wissen sorgfältig zusammengestellt. Es wird jedoch weder Vollständigkeit, noch Richtigkeit,
noch Qualität der bereit gestellten Informationen zugesichert.
Bemerkung:
Die farbliche Syntaxdarstellung und die Messung sind noch experimentell.
