// SPDX-License-Identifier: GPL-2.0-only /* * Copyright ( c ) 2024 AIROHA Inc * Author : Lorenzo Bianconi < lorenzo @ kernel . org > #include <linux/of.h>#include <linux/of_net.h>#include <linux/of_reserved_mem.h>#include <linux/platform_device.h>#include <linux/tcp.h>#include <linux/u64_stats_sync.h>#include <net/dst_metadata.h>#include <net/page_pool/helpers.h>#include <net/pkt_cls.h>#include <uapi/linux/ppp_defs.h>#include "airoha_regs.h" #include "airoha_eth.h" void __iomem *base, u32 offset)return readl(base + offset);void airoha_wr(void __iomem *base, u32 offset, u32 val)void __iomem *base, u32 offset, u32 mask, u32 val)return val;static void airoha_qdma_set_irqmask(struct airoha_irq_bank *irq_bank,int index, u32 clear, u32 set)struct airoha_qdma *qdma = irq_bank->qdma;int bank = irq_bank - &qdma->irq_banks[0 ];unsigned long flags;if (WARN_ON_ONCE(index >= ARRAY_SIZE(irq_bank->irqmask)))return ;/* Read irq_enable register in order to guarantee the update above * completes in the spinlock critical section . static void airoha_qdma_irq_enable(struct airoha_irq_bank *irq_bank,int index, u32 mask)0 , mask);static void airoha_qdma_irq_disable(struct airoha_irq_bank *irq_bank,int index, u32 mask)0 );static void airoha_set_macaddr(struct airoha_gdm_port *port, const u8 *addr)struct airoha_eth *eth = port->qdma->eth;0 ] << 16 ) | (addr[1 ] << 8 ) | addr[2 ];3 ] << 16 ) | (addr[4 ] << 8 ) | addr[5 ];static void airoha_set_gdm_port_fwd_cfg(struct airoha_eth *eth, u32 addr,static int airoha_set_vip_for_gdm_port(struct airoha_gdm_port *port,bool enable)struct airoha_eth *eth = port->qdma->eth;switch (port->id) {case 3 :/* FIXME: handle XSI_PCIE1_PORT */ break ;case 4 :/* FIXME: handle XSI_USB_PORT */ break ;default :return 0 ;if (enable) {else {return 0 ;static void airoha_fe_maccr_init(struct airoha_eth *eth)int p;for (p = 1 ; p <= ARRAY_SIZE(eth->ports); p++)0 x8100));static void airoha_fe_vip_setup(struct airoha_eth *eth)3 ), ETH_P_PPP_DISC);3 ), PATN_FCPU_EN_MASK | PATN_EN_MASK);4 ), PPP_LCP);4 ),1 ) |6 ), PPP_IPCP);6 ),1 ) |7 ), PPP_CHAP);7 ),1 ) |/* BOOTP (0x43) */ 8 ), 0 x43);8 ),4 ) | PATN_EN_MASK);/* BOOTP (0x44) */ 9 ), 0 x44);9 ),4 ) | PATN_EN_MASK);/* ISAKMP */ 10 ), 0 x1f401f4);10 ),4 ) | PATN_EN_MASK);11 ), PPP_IPV6CP);11 ),1 ) |/* DHCPv6 */ 12 ), 0 x2220223);12 ),4 ) | PATN_EN_MASK);19 ), PPP_PAP);19 ),1 ) |/* ETH->ETH_P_1905 (0x893a) */ 20 ), 0 x893a);20 ),21 ), ETH_P_LLDP);21 ),static u32 airoha_fe_get_pse_queue_rsv_pages(struct airoha_eth *eth,return FIELD_GET(PSE_CFG_OQ_RSV_MASK, val);static void airoha_fe_set_pse_queue_rsv_pages(struct airoha_eth *eth,static u32 airoha_fe_get_pse_all_rsv(struct airoha_eth *eth)return FIELD_GET(PSE_ALLRSV_MASK, val);static int airoha_fe_set_pse_oq_rsv(struct airoha_eth *eth,/* modify all rsv */ /* modify hthd */ 0 x20;0 x100;3 * tmp) >> 2 ;return 0 ;static void airoha_fe_pse_ports_init(struct airoha_eth *eth)const u32 pse_port_num_queues[] = {6 ,6 ,32 ,6 ,4 ,6 ,8 ,10 ,4 ,2 ,2 ,int q;/* hw misses PPE2 oq rsv */ /* CMD1 */ for (q = 0 ; q < pse_port_num_queues[FE_PSE_PORT_CDM1]; q++)/* GMD1 */ for (q = 0 ; q < pse_port_num_queues[FE_PSE_PORT_GDM1]; q++)/* GMD2 */ for (q = 6 ; q < pse_port_num_queues[FE_PSE_PORT_GDM2]; q++)0 );/* GMD3 */ for (q = 0 ; q < pse_port_num_queues[FE_PSE_PORT_GDM3]; q++)/* PPE1 */ for (q = 0 ; q < pse_port_num_queues[FE_PSE_PORT_PPE1]; q++) {if (q < pse_port_num_queues[FE_PSE_PORT_PPE1])else 0 );/* CDM2 */ for (q = 0 ; q < pse_port_num_queues[FE_PSE_PORT_CDM2]; q++)/* CDM3 */ for (q = 0 ; q < pse_port_num_queues[FE_PSE_PORT_CDM3] - 1 ; q++)0 );/* CDM4 */ for (q = 4 ; q < pse_port_num_queues[FE_PSE_PORT_CDM4]; q++)/* PPE2 */ for (q = 0 ; q < pse_port_num_queues[FE_PSE_PORT_PPE2]; q++) {if (q < pse_port_num_queues[FE_PSE_PORT_PPE2] / 2 )else 0 );/* GMD4 */ for (q = 0 ; q < pse_port_num_queues[FE_PSE_PORT_GDM4]; q++)/* CDM5 */ for (q = 0 ; q < pse_port_num_queues[FE_PSE_PORT_CDM5]; q++)static int airoha_fe_mc_vlan_clear(struct airoha_eth *eth)int i;for (i = 0 ; i < AIROHA_FE_MC_MAX_VLAN_TABLE; i++) {int err, j;0 x0);5 * USEC_PER_MSEC,false , eth, REG_MC_VLAN_CFG);if (err)return err;for (j = 0 ; j < AIROHA_FE_MC_MAX_VLAN_PORT; j++) {0 x0);5 * USEC_PER_MSEC, false , eth,if (err)return err;return 0 ;static void airoha_fe_crsn_qsel_init(struct airoha_eth *eth)/* CDM1_CRSN_QSEL */ 2 ),2 ),2 ),2 ),2 ),/* CDM2_CRSN_QSEL */ 2 ),2 ),2 ),2 ),2 ),static int airoha_fe_init(struct airoha_eth *eth)/* PSE IQ reserve */ 0 x10));0 x40) |0 x34));/* enable FE copy engine for MC/KA/DPI */ /* set vip queue selection to ring 1 */ 0 x4));0 x4));/* set GDM4 source interface offset to 8 */ 8 ) |8 ) |8 ));/* set PSE Page as 128B */ 2 ) |1000 , 2000 );/* connect RxRing1 and RxRing15 to PSE Port0 OQ-1 * connect other rings to PSE Port0 OQ - 0 4 ));28 ));4 ));28 ));15 ));/* init fragment and assemble Force Port */ /* NPU Core-3, NPU Bridge Channel-3 */ 6 ) |3 ));/* QDMA LAN, RX Ring-22 */ 0 ) |22 ));/* default aging mode for mbi unlock issue */ 3 ) |3 ));/* disable IFC by default */ 0 ),7 ), FE_PSE_PORT_CDM1) |6 ), FE_PSE_PORT_CDM1) |5 ), FE_PSE_PORT_CDM1) |4 ), FE_PSE_PORT_CDM1) |3 ), FE_PSE_PORT_CDM1) |2 ), FE_PSE_PORT_CDM1) |1 ), FE_PSE_PORT_CDM1) |0 ), FE_PSE_PORT_CDM1));1 ),7 ), FE_PSE_PORT_CDM2) |6 ), FE_PSE_PORT_CDM2) |5 ), FE_PSE_PORT_CDM2) |4 ), FE_PSE_PORT_CDM2) |3 ), FE_PSE_PORT_CDM2) |2 ), FE_PSE_PORT_CDM2) |1 ), FE_PSE_PORT_CDM2) |0 ), FE_PSE_PORT_CDM2));/* enable 1:N vlan action, init vlan table */ return airoha_fe_mc_vlan_clear(eth);static int airoha_qdma_fill_rx_queue(struct airoha_queue *q)struct airoha_qdma *qdma = q->qdma;int qid = q - &qdma->q_rx[0 ];int nframes = 0 ;while (q->queued < q->ndesc - 1 ) {struct airoha_queue_entry *e = &q->entry[q->head];struct airoha_qdma_desc *desc = &q->desc[q->head];struct page *page;int offset;if (!page)break ;1 ) % q->ndesc;0 );0 );0 );0 );return nframes;static int airoha_qdma_get_gdm_port(struct airoha_eth *eth,struct airoha_qdma_desc *desc)switch (sport) {case 0 x10 ... 0 x14:0 ;break ;case 0 x2 ... 0 x4:1 ;break ;default :return -EINVAL;return port >= ARRAY_SIZE(eth->ports) ? -EINVAL : port;static int airoha_qdma_rx_process(struct airoha_queue *q, int budget)enum dma_data_direction dir = page_pool_get_dma_dir(q->page_pool);struct airoha_qdma *qdma = q->qdma;struct airoha_eth *eth = qdma->eth;int qid = q - &qdma->q_rx[0 ];int done = 0 ;while (done < budget) {struct airoha_queue_entry *e = &q->entry[q->tail];struct airoha_qdma_desc *desc = &q->desc[q->tail];struct page *page = virt_to_head_page(e->buf);struct airoha_gdm_port *port;int data_len, len, p;if (!(desc_ctrl & QDMA_DESC_DONE_MASK))break ;1 ) % q->ndesc;if (!len || data_len < len)goto free_frag;if (p < 0 || !eth->ports[p])goto free_frag;if (!q->skb) { /* first buffer */ if (!q->skb)goto free_frag;else { /* scattered frame */ struct skb_shared_info *shinfo = skb_shinfo(q->skb);int nr_frags = shinfo->nr_frags;if (nr_frags >= ARRAY_SIZE(shinfo->frags))goto free_frag;if (FIELD_GET(QDMA_DESC_MORE_MASK, desc_ctrl))continue ;if (netdev_uses_dsa(port->dev)) {/* PPE module requires untagged packets to work * properly and it provides DSA port index via the * DMA descriptor . Report DSA tag to the DSA stack * via skb dst info . if (sptag < ARRAY_SIZE(port->dsa_meta) &&if (hash != AIROHA_RXD4_FOE_ENTRY)0 ),if (reason == PPE_CPU_REASON_HIT_UNBIND_RATE_REACHED)continue ;if (q->skb) {else {true );return done;static int airoha_qdma_rx_napi_poll(struct napi_struct *napi, int budget)struct airoha_queue *q = container_of(napi, struct airoha_queue, napi);int cur, done = 0 ;do {while (cur && done < budget);if (done < budget && napi_complete(napi)) {struct airoha_qdma *qdma = q->qdma;int i, qid = q - &qdma->q_rx[0 ];int intr_reg = qid < RX_DONE_HIGH_OFFSET ? QDMA_INT_REG_IDX1for (i = 0 ; i < ARRAY_SIZE(qdma->irq_banks); i++) {if (!(BIT(qid) & RX_IRQ_BANK_PIN_MASK(i)))continue ;return done;static int airoha_qdma_init_rx_queue(struct airoha_queue *q,struct airoha_qdma *qdma, int ndesc)const struct page_pool_params pp_params = {0 ,256 ,struct airoha_eth *eth = qdma->eth;int qid = q - &qdma->q_rx[0 ], thr;2 ;sizeof (*q->entry),if (!q->entry)return -ENOMEM;if (IS_ERR(q->page_pool)) {int err = PTR_ERR(q->page_pool);return err;sizeof (*q->desc),if (!q->desc)return -ENOMEM;3 , 1 , 32 );return 0 ;static void airoha_qdma_cleanup_rx_queue(struct airoha_queue *q)struct airoha_eth *eth = q->qdma->eth;while (q->queued) {struct airoha_queue_entry *e = &q->entry[q->tail];struct page *page = virt_to_head_page(e->buf);false );1 ) % q->ndesc;static int airoha_qdma_init_rx(struct airoha_qdma *qdma)int i;for (i = 0 ; i < ARRAY_SIZE(qdma->q_rx); i++) {int err;if (!(RX_DONE_INT_MASK & BIT(i))) {/* rx-queue not binded to irq */ continue ;if (err)return err;return 0 ;static int airoha_qdma_tx_napi_poll(struct napi_struct *napi, int budget)struct airoha_tx_irq_queue *irq_q;int id, done = 0 , irq_queued;struct airoha_qdma *qdma;struct airoha_eth *eth;struct airoha_tx_irq_queue, napi);0 ];while (irq_queued > 0 && done < budget) {struct airoha_qdma_desc *desc;struct airoha_queue_entry *e;struct airoha_queue *q;struct sk_buff *skb;if (val == 0 xff)break ;0 xff; /* mark as done */ 1 ) % irq_q->size;if (qid >= ARRAY_SIZE(qdma->q_tx))continue ;if (!q->ndesc)continue ;if (index >= q->ndesc)continue ;if (!q->queued)goto unlock;if (!(desc_ctrl & QDMA_DESC_DONE_MASK) &&goto unlock;0 , sizeof (*e));0 );0 );/* completion ring can report out-of-order indexes if hw QoS * is enabled and packets with different priority are queued * to same DMA ring . Take into account possible out - of - order * reports incrementing DMA ring tail pointer while (q->tail != q->head && !q->entry[q->tail].dma_addr)1 ) % q->ndesc;if (skb) {struct netdev_queue *txq;1 , skb->len);if (netif_tx_queue_stopped(txq) &&if (done) {int i, len = done >> 7 ;for (i = 0 ; i < len; i++)0 x80);0 x7f));if (done < budget && napi_complete(napi))0 ], QDMA_INT_REG_IDX0,return done;static int airoha_qdma_init_tx_queue(struct airoha_queue *q,struct airoha_qdma *qdma, int size)struct airoha_eth *eth = qdma->eth;int i, qid = q - &qdma->q_tx[0 ];1 + MAX_SKB_FRAGS;sizeof (*q->entry),if (!q->entry)return -ENOMEM;sizeof (*q->desc),if (!q->desc)return -ENOMEM;for (i = 0 ; i < q->ndesc; i++) {1 );/* xmit ring drop default setting */ return 0 ;static int airoha_qdma_tx_irq_init(struct airoha_tx_irq_queue *irq_q,struct airoha_qdma *qdma, int size)int id = irq_q - &qdma->q_tx_irq[0 ];struct airoha_eth *eth = qdma->eth;sizeof (u32),if (!irq_q->q)return -ENOMEM;0 xff, size * sizeof (u32));1 ));return 0 ;static int airoha_qdma_init_tx(struct airoha_qdma *qdma)int i, err;for (i = 0 ; i < ARRAY_SIZE(qdma->q_tx_irq); i++) {if (err)return err;for (i = 0 ; i < ARRAY_SIZE(qdma->q_tx); i++) {if (err)return err;return 0 ;static void airoha_qdma_cleanup_tx_queue(struct airoha_queue *q)struct airoha_eth *eth = q->qdma->eth;while (q->queued) {struct airoha_queue_entry *e = &q->entry[q->tail];1 ) % q->ndesc;static int airoha_qdma_init_hfwd_queues(struct airoha_qdma *qdma)int size, index, num_desc = HW_DSCP_NUM;struct airoha_eth *eth = qdma->eth;int id = qdma - ð->qdma[0 ];const char *name;"qdma%d-buf" , id);if (!name)return -ENOMEM;2 : AIROHA_MAX_PACKET_SIZE;"memory-region-names" , name);if (index >= 0 ) {struct reserved_mem *rmem;struct device_node *np;/* Consume reserved memory for hw forwarding buffers queue if * available in the DTS "memory-region" ,if (!np)return -ENODEV;/* Compute the number of hw descriptors according to the * reserved memory size and the payload buffer size else {if (!dmam_alloc_coherent(eth->dev, size, &dma_addr,return -ENOMEM;sizeof (struct airoha_qdma_fwd_desc);if (!dmam_alloc_coherent(eth->dev, size, &dma_addr, GFP_KERNEL))return -ENOMEM;/* QDMA0: 2KB. QDMA1: 1KB */ 128 ));return read_poll_timeout(airoha_qdma_rr, status,30 * USEC_PER_MSEC, true , qdma,static void airoha_qdma_init_qos(struct airoha_qdma *qdma)/* 2047us x 31 = 63.457ms */ 0 x1f));0 x7ff));/* ratelimit init */ /* fast-tick 25us */ 25 ));40 ));25 ));40 ));125 ));8 ));25 ));40 ));static void airoha_qdma_init_qos_stats(struct airoha_qdma *qdma)int i;for (i = 0 ; i < AIROHA_NUM_QOS_CHANNELS; i++) {/* Tx-cpu transferred count */ 1 ), 0 );1 ),/* Tx-fwd transferred count */ 1 ) + 1 ), 0 );1 ),1 ) |static int airoha_qdma_hw_init(struct airoha_qdma *qdma)int i;for (i = 0 ; i < ARRAY_SIZE(qdma->irq_banks); i++) {/* clear pending irqs */ 0 xffffffff);/* setup rx irqs */ /* setup tx irqs */ 0 ], QDMA_INT_REG_IDX0,0 ], QDMA_INT_REG_IDX4,/* setup irq binding */ for (i = 0 ; i < ARRAY_SIZE(qdma->q_tx); i++) {if (!qdma->q_tx[i].ndesc)continue ;if (TX_RING_IRQ_BLOCKING_MAP_MASK & BIT(i))else 3 ) |2 ));/* disable qdma rx delay interrupt */ for (i = 0 ; i < ARRAY_SIZE(qdma->q_rx); i++) {if (!qdma->q_rx[i].ndesc)continue ;return 0 ;static irqreturn_t airoha_irq_handler(int irq, void *dev_instance)struct airoha_irq_bank *irq_bank = dev_instance;struct airoha_qdma *qdma = irq_bank->qdma;0 , rx_intr1, rx_intr2;int i;for (i = 0 ; i < ARRAY_SIZE(intr); i++) {if (!test_bit(DEV_STATE_INITIALIZED, &qdma->eth->state))return IRQ_NONE;1 ] & RX_DONE_LOW_INT_MASK;if (rx_intr1) {2 ] & RX_DONE_HIGH_INT_MASK;if (rx_intr2) {16 );for (i = 0 ; rx_intr_mask && i < ARRAY_SIZE(qdma->q_rx); i++) {if (!qdma->q_rx[i].ndesc)continue ;if (rx_intr_mask & BIT(i))if (intr[0 ] & INT_TX_MASK) {for (i = 0 ; i < ARRAY_SIZE(qdma->q_tx_irq); i++) {if (!(intr[0 ] & TX_DONE_INT_MASK(i)))continue ;return IRQ_HANDLED;static int airoha_qdma_init_irq_banks(struct platform_device *pdev,struct airoha_qdma *qdma)struct airoha_eth *eth = qdma->eth;int i, id = qdma - ð->qdma[0 ];for (i = 0 ; i < ARRAY_SIZE(qdma->irq_banks); i++) {struct airoha_irq_bank *irq_bank = &qdma->irq_banks[i];int err, irq_index = 4 * id + i;const char *name;if (irq_bank->irq < 0 )return irq_bank->irq;".%d" , irq_index);if (!name)return -ENOMEM;if (err)return err;return 0 ;static int airoha_qdma_init(struct platform_device *pdev,struct airoha_eth *eth,struct airoha_qdma *qdma)int err, id = qdma - ð->qdma[0 ];const char *res;"qdma%d" , id);if (!res)return -ENOMEM;if (IS_ERR(qdma->regs))return dev_err_probe(eth->dev, PTR_ERR(qdma->regs),"failed to iomap qdma%d regs\n" , id);if (err)return err;if (err)return err;if (err)return err;if (err)return err;return airoha_qdma_hw_init(qdma);static int airoha_hw_init(struct platform_device *pdev,struct airoha_eth *eth)int err, i;/* disable xsi */ if (err)return err;if (err)return err;20 );if (err)return err;20 );if (err)return err;for (i = 0 ; i < ARRAY_SIZE(eth->qdma); i++) {if (err)return err;if (err)return err;return 0 ;static void airoha_hw_cleanup(struct airoha_qdma *qdma)int i;for (i = 0 ; i < ARRAY_SIZE(qdma->q_rx); i++) {if (!qdma->q_rx[i].ndesc)continue ;if (qdma->q_rx[i].page_pool)for (i = 0 ; i < ARRAY_SIZE(qdma->q_tx_irq); i++)for (i = 0 ; i < ARRAY_SIZE(qdma->q_tx); i++) {if (!qdma->q_tx[i].ndesc)continue ;static void airoha_qdma_start_napi(struct airoha_qdma *qdma)int i;for (i = 0 ; i < ARRAY_SIZE(qdma->q_tx_irq); i++)for (i = 0 ; i < ARRAY_SIZE(qdma->q_rx); i++) {if (!qdma->q_rx[i].ndesc)continue ;static void airoha_qdma_stop_napi(struct airoha_qdma *qdma)int i;for (i = 0 ; i < ARRAY_SIZE(qdma->q_tx_irq); i++)for (i = 0 ; i < ARRAY_SIZE(qdma->q_rx); i++) {if (!qdma->q_rx[i].ndesc)continue ;static void airoha_update_hw_stats(struct airoha_gdm_port *port)struct airoha_eth *eth = port->qdma->eth;0 ;/* TX */ 32 );32 );32 );32 );32 );32 );32 );32 );/* RX */ 32 );32 );0 ;32 );32 );32 );32 );32 );32 );/* reset mib counters */ static int airoha_dev_open(struct net_device *dev)int err, len = ETH_HLEN + dev->mtu + ETH_FCS_LEN;struct airoha_gdm_port *port = netdev_priv(dev);struct airoha_qdma *qdma = port->qdma;true );if (err)return err;if (netdev_uses_dsa(dev))else 60 ) |return 0 ;static int airoha_dev_stop(struct net_device *dev)struct airoha_gdm_port *port = netdev_priv(dev);struct airoha_qdma *qdma = port->qdma;int i, err;false );if (err)return err;for (i = 0 ; i < ARRAY_SIZE(qdma->q_tx); i++)if (atomic_dec_and_test(&qdma->users)) {for (i = 0 ; i < ARRAY_SIZE(qdma->q_tx); i++) {if (!qdma->q_tx[i].ndesc)continue ;return 0 ;static int airoha_dev_set_macaddr(struct net_device *dev, void *p)struct airoha_gdm_port *port = netdev_priv(dev);int err;if (err)return err;return 0 ;static void airhoha_set_gdm2_loopback(struct airoha_gdm_port *port)3 ? FE_PSE_PORT_GDM3 : FE_PSE_PORT_GDM4;struct airoha_eth *eth = port->qdma->eth;3 ? 4 : 0 ;/* Forward the traffic to the proper GDM port */ 2 ), pse_port);2 ), GDM_STRIP_CRC);/* Enable GDM2 loopback */ 2 ), 0 xffffffff);2 ), 0 xffff);2 ),2 ),60 ) |/* Disable VIP and IFC for GDM2 */ 2 ));2 ));if (port->id == 3 ) {/* FIXME: handle XSI_PCE1_PORT */ 3 ),else {/* FIXME: handle XSI_USB_PORT */ 2 ));3 ),static int airoha_dev_init(struct net_device *dev)struct airoha_gdm_port *port = netdev_priv(dev);struct airoha_eth *eth = port->qdma->eth;switch (port->id) {case 3 :case 4 :/* If GDM2 is active we can't enable loopback */ if (!eth->ports[1 ])case 2 :break ;default :break ;return 0 ;static void airoha_dev_get_stats64(struct net_device *dev,struct rtnl_link_stats64 *storage)struct airoha_gdm_port *port = netdev_priv(dev);unsigned int start;do {while (u64_stats_fetch_retry(&port->stats.syncp, start));static int airoha_dev_change_mtu(struct net_device *dev, int mtu)struct airoha_gdm_port *port = netdev_priv(dev);struct airoha_eth *eth = port->qdma->eth;return 0 ;static u16 airoha_dev_select_queue(struct net_device *dev, struct sk_buff *skb,struct net_device *sb_dev)struct airoha_gdm_port *port = netdev_priv(dev);int queue, channel;/* For dsa device select QoS channel according to the dsa user port * index , rely on port id otherwise . Select QoS queue based on the * skb priority . 1 ) % AIROHA_NUM_QOS_QUEUES; /* QoS queue */ return queue < dev->num_tx_queues ? queue : 0 ;static u32 airoha_get_dsa_tag(struct sk_buff *skb, struct net_device *dev)#if IS_ENABLED(CONFIG_NET_DSA)struct ethhdr *ehdr;if (!netdev_uses_dsa(dev))return 0 ;if (dev->dsa_ptr->tag_ops->proto != DSA_TAG_PROTO_MTK)return 0 ;if (skb_cow_head(skb, 0 ))return 0 ;struct ethhdr *)skb->data;8 ;switch (xmit_tpid) {case MTK_HDR_XMIT_TAGGED_TPID_8100:8 );break ;case MTK_HDR_XMIT_TAGGED_TPID_88A8:8 );break ;default :/* PPE module requires untagged DSA packets to work properly, * so move DSA tag to DMA descriptor . 2 * ETH_ALEN);break ;return tag;#else return 0 ;#endif static bool airoha_dev_tx_queue_busy(struct airoha_queue *q, u32 nr_frags)/* completion napi can free out-of-order tx descriptors if hw QoS is * enabled and packets with different priorities are queued to the same * DMA ring . Take into account possible out - of - order reports checking * if the tx queue is full using circular buffer head / tail pointers * instead of the number of queued packets . return index >= tail;static netdev_tx_t airoha_dev_xmit(struct sk_buff *skb,struct net_device *dev)struct airoha_gdm_port *port = netdev_priv(dev);struct airoha_qdma *qdma = port->qdma;struct netdev_queue *txq;struct airoha_queue *q;void *data;int i, qid;if (skb->ip_summed == CHECKSUM_PARTIAL)1 ) |1 ) |1 );/* TSO: fill MSS info in tcp checksum field */ if (skb_is_gso(skb)) {if (skb_cow_head(skb, 0 ))goto error;if (skb_shinfo(skb)->gso_type & (SKB_GSO_TCPV4 |1 );4 ? FE_PSE_PORT_GDM4 : port->id;0 x7f);if (WARN_ON_ONCE(!q->ndesc))goto error;1 + skb_shinfo(skb)->nr_frags;if (airoha_dev_tx_queue_busy(q, nr_frags)) {/* not enough space in the queue */ return NETDEV_TX_BUSY;for (i = 0 ; i < nr_frags; i++) {struct airoha_qdma_desc *desc = &q->desc[index];struct airoha_queue_entry *e = &q->entry[index];if (unlikely(dma_mapping_error(dev->dev.parent, addr)))goto error_unmap;1 ) % q->ndesc;if (i < nr_frags - 1 )1 );0 xffff));if (netif_xmit_stopped(txq) || !netdev_xmit_more())if (q->ndesc - q->queued < q->free_thr)return NETDEV_TX_OK;for (i--; i >= 0 ; i--) {return NETDEV_TX_OK;static void airoha_ethtool_get_drvinfo(struct net_device *dev,struct ethtool_drvinfo *info)struct airoha_gdm_port *port = netdev_priv(dev);struct airoha_eth *eth = port->qdma->eth;sizeof (info->driver));sizeof (info->bus_info));static void airoha_ethtool_get_mac_stats(struct net_device *dev,struct ethtool_eth_mac_stats *stats)struct airoha_gdm_port *port = netdev_priv(dev);unsigned int start;do {while (u64_stats_fetch_retry(&port->stats.syncp, start));static const struct ethtool_rmon_hist_range airoha_ethtool_rmon_ranges[] = {0 , 64 },65 , 127 },128 , 255 },256 , 511 },512 , 1023 },1024 , 1518 },1519 , 10239 },static void struct net_device *dev,struct ethtool_rmon_stats *stats,const struct ethtool_rmon_hist_range **ranges)struct airoha_gdm_port *port = netdev_priv(dev);struct airoha_hw_stats *hw_stats = &port->stats;unsigned int start;1 );1 );do {int i;for (i = 0 ; i < ARRAY_SIZE(airoha_ethtool_rmon_ranges) - 1 ;while (u64_stats_fetch_retry(&port->stats.syncp, start));static int airoha_qdma_set_chan_tx_sched(struct airoha_gdm_port *port,int channel, enum tx_sched_mode mode,const u16 *weights, u8 n_weights)int i;for (i = 0 ; i < AIROHA_NUM_TX_RING; i++)for (i = 0 ; i < n_weights; i++) {int err;10 * USEC_PER_MSEC,true , port->qdma,if (err)return err;3 ),return 0 ;static int airoha_qdma_set_tx_prio_sched(struct airoha_gdm_port *port,int channel)static const u16 w[AIROHA_NUM_QOS_QUEUES] = {};return airoha_qdma_set_chan_tx_sched(port, channel, TC_SCH_SP, w,static int airoha_qdma_set_tx_ets_sched(struct airoha_gdm_port *port,int channel,struct tc_ets_qopt_offload *opt)struct tc_ets_qopt_offload_replace_params *p = &opt->replace_params;enum tx_sched_mode mode = TC_SCH_SP;int i, nstrict = 0 ;if (p->bands > AIROHA_NUM_QOS_QUEUES)return -EINVAL;for (i = 0 ; i < p->bands; i++) {if (!p->quanta[i])/* this configuration is not supported by the hw */ if (nstrict == AIROHA_NUM_QOS_QUEUES - 1 )return -EINVAL;/* EN7581 SoC supports fixed QoS band priority where WRR queues have * lowest priorities with respect to SP ones . * e . g : WRR0 , WRR1 , . . , WRRm , SP0 , SP1 , . . , SPn for (i = 0 ; i < nstrict; i++) {if (p->priomap[p->bands - i - 1 ] != i)return -EINVAL;for (i = 0 ; i < p->bands - nstrict; i++) {if (p->priomap[i] != nstrict + i)return -EINVAL;if (!nstrict)else if (nstrict < AIROHA_NUM_QOS_QUEUES - 1 )1 ;return airoha_qdma_set_chan_tx_sched(port, channel, mode, w,static int airoha_qdma_get_tx_ets_stats(struct airoha_gdm_port *port,int channel,struct tc_ets_qopt_offload *opt)1 ));1 ) + 1 ));0 , tx_packets);return 0 ;static int airoha_tc_setup_qdisc_ets(struct airoha_gdm_port *port,struct tc_ets_qopt_offload *opt)int channel;if (opt->parent == TC_H_ROOT)return -EINVAL;16 ;switch (opt->command) {case TC_ETS_REPLACE:return airoha_qdma_set_tx_ets_sched(port, channel, opt);case TC_ETS_DESTROY:/* PRIO is default qdisc scheduler */ return airoha_qdma_set_tx_prio_sched(port, channel);case TC_ETS_STATS:return airoha_qdma_get_tx_ets_stats(port, channel, opt);default :return -EOPNOTSUPP;static int airoha_qdma_get_rl_param(struct airoha_qdma *qdma, int queue_id,enum trtcm_param_type param,if (read_poll_timeout(airoha_qdma_rr, val,10 * USEC_PER_MSEC, true , qdma,return -ETIMEDOUT;if (val_high)return 0 ;static int airoha_qdma_set_rl_param(struct airoha_qdma *qdma, int queue_id,enum trtcm_param_type param,return read_poll_timeout(airoha_qdma_rr, val,10 * USEC_PER_MSEC, true ,static int airoha_qdma_set_rl_config(struct airoha_qdma *qdma, int queue_id,bool enable, u32 enable_mask)int err;if (err)return err;return airoha_qdma_set_rl_param(qdma, queue_id, addr, TRTCM_MISC_MODE,static int airoha_qdma_set_rl_token_bucket(struct airoha_qdma *qdma,int queue_id, u32 rate_val,int err;if (err)return err;if (config & TRTCM_TICK_SEL)if (!tick)return -EINVAL;1000000 / tick : 8000 / tick;if (!unit)return -EINVAL;if (err)return err;if (!(config & TRTCM_PKT_MODE))return airoha_qdma_set_rl_param(qdma, queue_id, REG_INGRESS_TRTCM_CFG,static int airoha_qdma_init_rl_config(struct airoha_qdma *qdma, int queue_id,bool enable, enum trtcm_unit_type unit)bool tick_sel = queue_id == 0 || queue_id == 2 || queue_id == 8 ;enum trtcm_param mode = TRTCM_METER_MODE;int err;0 ;if (err)return err;return airoha_qdma_set_rl_config(qdma, queue_id, REG_INGRESS_TRTCM_CFG,static int airoha_qdma_get_trtcm_param(struct airoha_qdma *qdma, int channel,enum trtcm_param_type param,enum trtcm_mode_type mode,if (read_poll_timeout(airoha_qdma_rr, val,10 * USEC_PER_MSEC, true ,return -ETIMEDOUT;if (val_high)return 0 ;static int airoha_qdma_set_trtcm_param(struct airoha_qdma *qdma, int channel,enum trtcm_param_type param,enum trtcm_mode_type mode, u32 val)return read_poll_timeout(airoha_qdma_rr, val,10 * USEC_PER_MSEC, true ,static int airoha_qdma_set_trtcm_config(struct airoha_qdma *qdma, int channel,enum trtcm_mode_type mode,bool enable, u32 enable_mask)if (airoha_qdma_get_trtcm_param(qdma, channel, addr, TRTCM_MISC_MODE,return -EINVAL;return airoha_qdma_set_trtcm_param(qdma, channel, addr, TRTCM_MISC_MODE,static int airoha_qdma_set_trtcm_token_bucket(struct airoha_qdma *qdma,int channel, u32 addr,enum trtcm_mode_type mode,int err;if (airoha_qdma_get_trtcm_param(qdma, channel, addr, TRTCM_MISC_MODE,return -EINVAL;if (config & TRTCM_TICK_SEL)if (!tick)return -EINVAL;1000000 / tick : 8000 / tick;if (!unit)return -EINVAL;if (err)return err;return airoha_qdma_set_trtcm_param(qdma, channel, addr,static int airoha_qdma_set_tx_rate_limit(struct airoha_gdm_port *port,int channel, u32 rate,int i, err;for (i = 0 ; i <= TRTCM_PEAK_MODE; i++) {if (err)return err;if (err)return err;return 0 ;static int airoha_tc_htb_alloc_leaf_queue(struct airoha_gdm_port *port,struct tc_htb_qopt_offload *opt)1000 ) << 3 ; /* kbps */ struct net_device *dev = port->dev;int num_tx_queues = dev->real_num_tx_queues;int err;if (opt->parent_classid != TC_HTB_CLASSID_ROOT) {"invalid parent classid" );return -EINVAL;if (err) {"failed configuring htb offload" );return err;if (opt->command == TC_HTB_NODE_MODIFY)return 0 ;1 );if (err) {0 , opt->quantum);"failed setting real_num_tx_queues" );return err;return 0 ;static int airoha_qdma_set_rx_meter(struct airoha_gdm_port *port,enum trtcm_unit_type unit_type)struct airoha_qdma *qdma = port->qdma;int i;for (i = 0 ; i < ARRAY_SIZE(qdma->q_rx); i++) {int err;if (!qdma->q_rx[i].ndesc)continue ;if (err)return err;if (err)return err;return 0 ;static int airoha_tc_matchall_act_validate(struct tc_cls_matchall_offload *f)const struct flow_action *actions = &f->rule->action;const struct flow_action_entry *act;if (!flow_action_has_entries(actions)) {"filter run with no actions" );return -EINVAL;if (!flow_offload_has_one_action(actions)) {"only once action per filter is supported" );return -EOPNOTSUPP;0 ];if (act->id != FLOW_ACTION_POLICE) {"unsupported action" );return -EOPNOTSUPP;if (act->police.exceed.act_id != FLOW_ACTION_DROP) {"invalid exceed action id" );return -EOPNOTSUPP;if (act->police.notexceed.act_id != FLOW_ACTION_ACCEPT) {"invalid notexceed action id" );return -EOPNOTSUPP;if (act->police.notexceed.act_id == FLOW_ACTION_ACCEPT &&"action accept must be last" );return -EOPNOTSUPP;if (act->police.peakrate_bytes_ps || act->police.avrate ||"peakrate/avrate/overhead/mtu unsupported" );return -EOPNOTSUPP;return 0 ;static int airoha_dev_tc_matchall(struct net_device *dev,struct tc_cls_matchall_offload *f)enum trtcm_unit_type unit_type = TRTCM_BYTE_UNIT;struct airoha_gdm_port *port = netdev_priv(dev);0 , bucket_size = 0 ;switch (f->command) {case TC_CLSMATCHALL_REPLACE: {const struct flow_action_entry *act;int err;if (err)return err;0 ];if (act->police.rate_pkt_ps) {else {1000 );3 ; /* Kbps */ case TC_CLSMATCHALL_DESTROY:return airoha_qdma_set_rx_meter(port, rate, bucket_size,default :return -EOPNOTSUPP;static int airoha_dev_setup_tc_block_cb(enum tc_setup_type type,void *type_data, void *cb_priv)struct net_device *dev = cb_priv;if (!tc_can_offload(dev))return -EOPNOTSUPP;switch (type) {case TC_SETUP_CLSFLOWER:return airoha_ppe_setup_tc_block_cb(dev, type_data);case TC_SETUP_CLSMATCHALL:return airoha_dev_tc_matchall(dev, type_data);default :return -EOPNOTSUPP;static int airoha_dev_setup_tc_block(struct airoha_gdm_port *port,struct flow_block_offload *f)static LIST_HEAD(block_cb_list);struct flow_block_cb *block_cb;if (f->binder_type != FLOW_BLOCK_BINDER_TYPE_CLSACT_INGRESS)return -EOPNOTSUPP;switch (f->command) {case FLOW_BLOCK_BIND:if (block_cb) {return 0 ;if (IS_ERR(block_cb))return PTR_ERR(block_cb);return 0 ;case FLOW_BLOCK_UNBIND:if (!block_cb)return -ENOENT;if (!flow_block_cb_decref(block_cb)) {return 0 ;default :return -EOPNOTSUPP;static void airoha_tc_remove_htb_queue(struct airoha_gdm_port *port, int queue)struct net_device *dev = port->dev;1 );1 , 0 , 0 );static int airoha_tc_htb_delete_leaf_queue(struct airoha_gdm_port *port,struct tc_htb_qopt_offload *opt)if (!test_bit(channel, port->qos_sq_bmap)) {"invalid queue id" );return -EINVAL;return 0 ;static int airoha_tc_htb_destroy(struct airoha_gdm_port *port)int q;return 0 ;static int airoha_tc_get_htb_get_leaf_queue(struct airoha_gdm_port *port,struct tc_htb_qopt_offload *opt)if (!test_bit(channel, port->qos_sq_bmap)) {"invalid queue id" );return -EINVAL;return 0 ;static int airoha_tc_setup_qdisc_htb(struct airoha_gdm_port *port,struct tc_htb_qopt_offload *opt)switch (opt->command) {case TC_HTB_CREATE:break ;case TC_HTB_DESTROY:return airoha_tc_htb_destroy(port);case TC_HTB_NODE_MODIFY:case TC_HTB_LEAF_ALLOC_QUEUE:return airoha_tc_htb_alloc_leaf_queue(port, opt);case TC_HTB_LEAF_DEL:case TC_HTB_LEAF_DEL_LAST:case TC_HTB_LEAF_DEL_LAST_FORCE:return airoha_tc_htb_delete_leaf_queue(port, opt);case TC_HTB_LEAF_QUERY_QUEUE:return airoha_tc_get_htb_get_leaf_queue(port, opt);default :return -EOPNOTSUPP;return 0 ;static int airoha_dev_tc_setup(struct net_device *dev, enum tc_setup_type type,void *type_data)struct airoha_gdm_port *port = netdev_priv(dev);switch (type) {case TC_SETUP_QDISC_ETS:return airoha_tc_setup_qdisc_ets(port, type_data);case TC_SETUP_QDISC_HTB:return airoha_tc_setup_qdisc_htb(port, type_data);case TC_SETUP_BLOCK:case TC_SETUP_FT:return airoha_dev_setup_tc_block(port, type_data);default :return -EOPNOTSUPP;static const struct net_device_ops airoha_netdev_ops = {static const struct ethtool_ops airoha_ethtool_ops = {static int airoha_metadata_dst_alloc(struct airoha_gdm_port *port)int i;for (i = 0 ; i < ARRAY_SIZE(port->dsa_meta); i++) {struct metadata_dst *md_dst;0 , METADATA_HW_PORT_MUX,if (!md_dst)return -ENOMEM;return 0 ;static void airoha_metadata_dst_free(struct airoha_gdm_port *port)int i;for (i = 0 ; i < ARRAY_SIZE(port->dsa_meta); i++) {if (!port->dsa_meta[i])continue ;bool airoha_is_valid_gdm_port(struct airoha_eth *eth,struct airoha_gdm_port *port)int i;for (i = 0 ; i < ARRAY_SIZE(eth->ports); i++) {if (eth->ports[i] == port)return true ;return false ;static int airoha_alloc_gdm_port(struct airoha_eth *eth,struct device_node *np, int index)const __be32 *id_ptr = of_get_property(np, "reg" , NULL);struct airoha_gdm_port *port;struct airoha_qdma *qdma;struct net_device *dev;int err, p;if (!id_ptr) {"missing gdm port id\n" );return -EINVAL;1 ;if (!id || id > ARRAY_SIZE(eth->ports)) {"invalid gdm port id: %d\n" , id);return -EINVAL;if (eth->ports[p]) {"duplicate gdm port id: %d\n" , id);return -EINVAL;sizeof (*port),if (!dev) {"alloc_etherdev failed\n" );return -ENOMEM;5 * HZ;0 ].irq;/* reserve hw queues for HTB offloading */ if (err)return err;if (err) {if (err == -EPROBE_DEFER)return err;"generated random MAC address %pM\n" ,if (err)return err;if (err)goto free_metadata_dst;return 0 ;return err;static int airoha_probe(struct platform_device *pdev)struct device_node *np;struct airoha_eth *eth;int i, err;sizeof (*eth), GFP_KERNEL);if (!eth)return -ENOMEM;32 ));if (err) {"failed configuring DMA mask\n" );return err;"fe" );if (IS_ERR(eth->fe_regs))return dev_err_probe(eth->dev, PTR_ERR(eth->fe_regs),"failed to iomap fe regs\n" );0 ].id = "fe" ;1 ].id = "pdma" ;2 ].id = "qdma" ;if (err) {"failed to get bulk reset lines\n" );return err;0 ].id = "xsi-mac" ;1 ].id = "hsi0-mac" ;2 ].id = "hsi1-mac" ;3 ].id = "hsi-mac" ;4 ].id = "xfp-mac" ;if (err) {"failed to get bulk xsi reset lines\n" );return err;0 );if (!eth->napi_dev)return -ENOMEM;/* Enable threaded NAPI by default */ true ;"qdma_eth" , sizeof (eth->napi_dev->name));if (err)goto error_hw_cleanup;for (i = 0 ; i < ARRAY_SIZE(eth->qdma); i++)0 ;if (!of_device_is_compatible(np, "airoha,eth-mac" ))continue ;if (!of_device_is_available(np))continue ;if (err) {goto error_napi_stop;return 0 ;for (i = 0 ; i < ARRAY_SIZE(eth->qdma); i++)for (i = 0 ; i < ARRAY_SIZE(eth->qdma); i++)for (i = 0 ; i < ARRAY_SIZE(eth->ports); i++) {struct airoha_gdm_port *port = eth->ports[i];if (port && port->dev->reg_state == NETREG_REGISTERED) {return err;static void airoha_remove(struct platform_device *pdev)struct airoha_eth *eth = platform_get_drvdata(pdev);int i;for (i = 0 ; i < ARRAY_SIZE(eth->qdma); i++) {for (i = 0 ; i < ARRAY_SIZE(eth->ports); i++) {struct airoha_gdm_port *port = eth->ports[i];if (!port)continue ;static const struct of_device_id of_airoha_match[] = {"airoha,en7581-eth" },/* sentinel */ } static struct platform_driver airoha_driver = {"GPL" );"Lorenzo Bianconi <lorenzo@kernel.org>" );"Ethernet driver for Airoha SoC" );
Messung V0.5 in Prozent C=97 H=92 G=94
¤ Dauer der Verarbeitung: 0.32 Sekunden
(vorverarbeitet am 2026-09-29)
¤ *© Formatika GbR, Deutschland
