// SPDX-License-Identifier: GPL-2.0-only /* * st_spi_fsm . c - ST Fast Sequence Mode ( FSM ) Serial Flash Controller * * Author : Angus Clark < angus . clark @ st . com > * * Copyright ( C ) 2010 - 2014 STMicroelectronics Limited * * JEDEC probe based on drivers / mtd / devices / m25p80 . c #include <linux/kernel.h>#include <linux/module.h>#include <linux/regmap.h>#include <linux/platform_device.h>#include <linux/mfd/syscon.h>#include <linux/mtd/mtd.h>#include <linux/mtd/partitions.h>#include <linux/mtd/spi-nor.h>#include <linux/sched.h>#include <linux/delay.h>#include <linux/io.h>#include <linux/of.h>#include <linux/clk.h>#include "serial_flash_cmds.h" /* * FSM SPI Controller Registers #define SPI_CLOCKDIV 0 x0010#define SPI_MODESELECT 0 x0018#define SPI_CONFIGDATA 0 x0020#define SPI_STA_MODE_CHANGE 0 x0028#define SPI_FAST_SEQ_TRANSFER_SIZE 0 x0100#define SPI_FAST_SEQ_ADD1 0 x0104#define SPI_FAST_SEQ_ADD2 0 x0108#define SPI_FAST_SEQ_ADD_CFG 0 x010c#define SPI_FAST_SEQ_OPC1 0 x0110#define SPI_FAST_SEQ_OPC2 0 x0114#define SPI_FAST_SEQ_OPC3 0 x0118#define SPI_FAST_SEQ_OPC4 0 x011c#define SPI_FAST_SEQ_OPC5 0 x0120#define SPI_MODE_BITS 0 x0124#define SPI_DUMMY_BITS 0 x0128#define SPI_FAST_SEQ_FLASH_STA_DATA 0 x012c#define SPI_FAST_SEQ_1 0 x0130#define SPI_FAST_SEQ_2 0 x0134#define SPI_FAST_SEQ_3 0 x0138#define SPI_FAST_SEQ_4 0 x013c#define SPI_FAST_SEQ_CFG 0 x0140#define SPI_FAST_SEQ_STA 0 x0144#define SPI_QUAD_BOOT_SEQ_INIT_1 0 x0148#define SPI_QUAD_BOOT_SEQ_INIT_2 0 x014c#define SPI_QUAD_BOOT_READ_SEQ_1 0 x0150#define SPI_QUAD_BOOT_READ_SEQ_2 0 x0154#define SPI_PROGRAM_ERASE_TIME 0 x0158#define SPI_MULT_PAGE_REPEAT_SEQ_1 0 x015c#define SPI_MULT_PAGE_REPEAT_SEQ_2 0 x0160#define SPI_STATUS_WR_TIME_REG 0 x0164#define SPI_FAST_SEQ_DATA_REG 0 x0300/* * Register : SPI_MODESELECT #define SPI_MODESELECT_CONTIG 0 x01#define SPI_MODESELECT_FASTREAD 0 x02#define SPI_MODESELECT_DUALIO 0 x04#define SPI_MODESELECT_FSM 0 x08#define SPI_MODESELECT_QUADBOOT 0 x10/* * Register : SPI_CONFIGDATA #define SPI_CFG_DEVICE_ST 0 x1#define SPI_CFG_DEVICE_ATMEL 0 x4#define SPI_CFG_MIN_CS_HIGH(x) (((x) & 0 xfff) << 4 )#define SPI_CFG_CS_SETUPHOLD(x) (((x) & 0 xff) << 16 )#define SPI_CFG_DATA_HOLD(x) (((x) & 0 xff) << 24 )#define SPI_CFG_DEFAULT_MIN_CS_HIGH SPI_CFG_MIN_CS_HIGH(0 x0AA)#define SPI_CFG_DEFAULT_CS_SETUPHOLD SPI_CFG_CS_SETUPHOLD(0 xA0)#define SPI_CFG_DEFAULT_DATA_HOLD SPI_CFG_DATA_HOLD(0 x00)/* * Register : SPI_FAST_SEQ_TRANSFER_SIZE #define TRANSFER_SIZE(x) ((x) * 8 )/* * Register : SPI_FAST_SEQ_ADD_CFG #define ADR_CFG_CYCLES_ADD1(x) ((x) << 0 )#define ADR_CFG_PADS_1_ADD1 (0 x0 << 6 )#define ADR_CFG_PADS_2_ADD1 (0 x1 << 6 )#define ADR_CFG_PADS_4_ADD1 (0 x3 << 6 )#define ADR_CFG_CSDEASSERT_ADD1 (1 << 8 )#define ADR_CFG_CYCLES_ADD2(x) ((x) << (0 +16 ))#define ADR_CFG_PADS_1_ADD2 (0 x0 << (6 +16 ))#define ADR_CFG_PADS_2_ADD2 (0 x1 << (6 +16 ))#define ADR_CFG_PADS_4_ADD2 (0 x3 << (6 +16 ))#define ADR_CFG_CSDEASSERT_ADD2 (1 << (8 +16 ))/* * Register : SPI_FAST_SEQ_n #define SEQ_OPC_OPCODE(x) ((x) << 0 )#define SEQ_OPC_CYCLES(x) ((x) << 8 )#define SEQ_OPC_PADS_1 (0 x0 << 14 )#define SEQ_OPC_PADS_2 (0 x1 << 14 )#define SEQ_OPC_PADS_4 (0 x3 << 14 )#define SEQ_OPC_CSDEASSERT (1 << 16 )/* * Register : SPI_FAST_SEQ_CFG #define SEQ_CFG_STARTSEQ (1 << 0 )#define SEQ_CFG_SWRESET (1 << 5 )#define SEQ_CFG_CSDEASSERT (1 << 6 )#define SEQ_CFG_READNOTWRITE (1 << 7 )#define SEQ_CFG_ERASE (1 << 8 )#define SEQ_CFG_PADS_1 (0 x0 << 16 )#define SEQ_CFG_PADS_2 (0 x1 << 16 )#define SEQ_CFG_PADS_4 (0 x3 << 16 )/* * Register : SPI_MODE_BITS #define MODE_DATA(x) (x & 0 xff)#define MODE_CYCLES(x) ((x & 0 x3f) << 16 )#define MODE_PADS_1 (0 x0 << 22 )#define MODE_PADS_2 (0 x1 << 22 )#define MODE_PADS_4 (0 x3 << 22 )#define DUMMY_CSDEASSERT (1 << 24 )/* * Register : SPI_DUMMY_BITS #define DUMMY_CYCLES(x) ((x & 0 x3f) << 16 )#define DUMMY_PADS_1 (0 x0 << 22 )#define DUMMY_PADS_2 (0 x1 << 22 )#define DUMMY_PADS_4 (0 x3 << 22 )#define DUMMY_CSDEASSERT (1 << 24 )/* * Register : SPI_FAST_SEQ_FLASH_STA_DATA #define STA_DATA_BYTE1(x) ((x & 0 xff) << 0 )#define STA_DATA_BYTE2(x) ((x & 0 xff) << 8 )#define STA_PADS_1 (0 x0 << 16 )#define STA_PADS_2 (0 x1 << 16 )#define STA_PADS_4 (0 x3 << 16 )#define STA_CSDEASSERT (0 x1 << 20 )#define STA_RDNOTWR (0 x1 << 21 )/* * FSM SPI Instruction Opcodes #define STFSM_OPC_CMD 0 x1#define STFSM_OPC_ADD 0 x2#define STFSM_OPC_STA 0 x3#define STFSM_OPC_MODE 0 x4#define STFSM_OPC_DUMMY 0 x5#define STFSM_OPC_DATA 0 x6#define STFSM_OPC_WAIT 0 x7#define STFSM_OPC_JUMP 0 x8#define STFSM_OPC_GOTO 0 x9#define STFSM_OPC_STOP 0 xF/* * FSM SPI Instructions ( = = opcode + operand ) . #define STFSM_INSTR(cmd, op) ((cmd) | ((op) << 4 ))#define STFSM_INST_CMD1 STFSM_INSTR(STFSM_OPC_CMD, 1 )#define STFSM_INST_CMD2 STFSM_INSTR(STFSM_OPC_CMD, 2 )#define STFSM_INST_CMD3 STFSM_INSTR(STFSM_OPC_CMD, 3 )#define STFSM_INST_CMD4 STFSM_INSTR(STFSM_OPC_CMD, 4 )#define STFSM_INST_CMD5 STFSM_INSTR(STFSM_OPC_CMD, 5 )#define STFSM_INST_ADD1 STFSM_INSTR(STFSM_OPC_ADD, 1 )#define STFSM_INST_ADD2 STFSM_INSTR(STFSM_OPC_ADD, 2 )#define STFSM_INST_DATA_WRITE STFSM_INSTR(STFSM_OPC_DATA, 1 )#define STFSM_INST_DATA_READ STFSM_INSTR(STFSM_OPC_DATA, 2 )#define STFSM_INST_STA_RD1 STFSM_INSTR(STFSM_OPC_STA, 0 x1)#define STFSM_INST_STA_WR1 STFSM_INSTR(STFSM_OPC_STA, 0 x1)#define STFSM_INST_STA_RD2 STFSM_INSTR(STFSM_OPC_STA, 0 x2)#define STFSM_INST_STA_WR1_2 STFSM_INSTR(STFSM_OPC_STA, 0 x3)#define STFSM_INST_MODE STFSM_INSTR(STFSM_OPC_MODE, 0 )#define STFSM_INST_DUMMY STFSM_INSTR(STFSM_OPC_DUMMY, 0 )#define STFSM_INST_WAIT STFSM_INSTR(STFSM_OPC_WAIT, 0 )#define STFSM_INST_STOP STFSM_INSTR(STFSM_OPC_STOP, 0 )#define STFSM_DEFAULT_EMI_FREQ 100000000 UL /* 100 MHz */ #define STFSM_DEFAULT_WR_TIME (STFSM_DEFAULT_EMI_FREQ * (15 /1000 )) /* 15ms */ #define STFSM_FLASH_SAFE_FREQ 10000000 UL /* 10 MHz */ #define STFSM_MAX_WAIT_SEQ_MS 1000 /* FSM execution time */ /* S25FLxxxS commands */ #define S25FL_CMD_WRITE4_1_1_4 0 x34#define S25FL_CMD_SE4 0 xdc#define S25FL_CMD_CLSR 0 x30#define S25FL_CMD_DYBWR 0 xe1#define S25FL_CMD_DYBRD 0 xe0#define S25FL_CMD_WRITE4 0 x12 /* Note, opcode clashes with * ' SPINOR_OP_WRITE_1_4_4 ' /* Status register */ #define FLASH_STATUS_BUSY 0 x01#define FLASH_STATUS_WEL 0 x02#define FLASH_STATUS_BP0 0 x04#define FLASH_STATUS_BP1 0 x08#define FLASH_STATUS_BP2 0 x10#define FLASH_STATUS_SRWP0 0 x80#define FLASH_STATUS_TIMEOUT 0 xff/* S25FL Error Flags */ #define S25FL_STATUS_E_ERR 0 x20#define S25FL_STATUS_P_ERR 0 x40#define N25Q_CMD_WRVCR 0 x81#define N25Q_CMD_RDVCR 0 x85#define N25Q_CMD_RDVECR 0 x65#define N25Q_CMD_RDNVCR 0 xb5#define N25Q_CMD_WRNVCR 0 xb1#define FLASH_PAGESIZE 256 /* In Bytes */ #define FLASH_PAGESIZE_32 (FLASH_PAGESIZE / 4 ) /* In uint32_t */ #define FLASH_MAX_BUSY_WAIT (300 * HZ) /* Maximum 'CHIPERASE' time */ /* * Flags to tweak operation of default read / write / erase routines #define CFG_READ_TOGGLE_32BIT_ADDR 0 x00000001#define CFG_WRITE_TOGGLE_32BIT_ADDR 0 x00000002#define CFG_ERASESEC_TOGGLE_32BIT_ADDR 0 x00000008#define CFG_S25FL_CHECK_ERROR_FLAGS 0 x00000010struct stfsm_seq {5 ];16 ];4 );struct stfsm {struct device *dev;void __iomem *base;struct mtd_info mtd;struct mutex lock;struct flash_info *info;struct clk *clk;bool booted_from_spi;bool reset_signal;bool reset_por;struct stfsm_seq stfsm_seq_read;struct stfsm_seq stfsm_seq_write;struct stfsm_seq stfsm_seq_en_32bit_addr;/* Parameters to configure a READ or WRITE FSM sequence */ struct seq_rw_config {/* flags to support config */ /* FLASH command */ int write; /* Write Sequence */ /* No. of addr pads (MODE & DUMMY) */ /* No. of data pads */ /* MODE data */ /* No. of MODE cycles */ /* No. of DUMMY cycles */ /* SPI Flash Device Table */ struct flash_info {char *name;/* * JEDEC id zero means " no ID " ( most older chips ) ; otherwise it has * a high byte of zero plus three data bytes : the manufacturer id , * then a two byte device id . /* * The size listed here is what works with SPINOR_OP_SE , which isn ' t * necessarily called a " sector " by the vendor . unsigned sector_size;/* * Note , where FAST_READ is supported , freq_max specifies the * FAST_READ frequency , not the READ frequency . int (*config)(struct stfsm *);static int stfsm_n25q_config(struct stfsm *fsm);static int stfsm_mx25_config(struct stfsm *fsm);static int stfsm_s25fl_config(struct stfsm *fsm);static int stfsm_w25q_config(struct stfsm *fsm);static struct flash_info flash_types[] = {/* * ST Microelectronics / Numonyx - - * ( newer production versions may have feature updates * ( eg faster operating frequency ) #define M25P_FLAG (FLASH_FLAG_READ_WRITE | FLASH_FLAG_READ_FAST)"m25p40" , 0 x202013, 0 , 64 * 1024 , 8 , M25P_FLAG, 25 , NULL },"m25p80" , 0 x202014, 0 , 64 * 1024 , 16 , M25P_FLAG, 25 , NULL },"m25p16" , 0 x202015, 0 , 64 * 1024 , 32 , M25P_FLAG, 25 , NULL },"m25p32" , 0 x202016, 0 , 64 * 1024 , 64 , M25P_FLAG, 50 , NULL },"m25p64" , 0 x202017, 0 , 64 * 1024 , 128 , M25P_FLAG, 50 , NULL },"m25p128" , 0 x202018, 0 , 256 * 1024 , 64 , M25P_FLAG, 50 , NULL },#define M25PX_FLAG (FLASH_FLAG_READ_WRITE | \"m25px32" , 0 x207116, 0 , 64 * 1024 , 64 , M25PX_FLAG, 75 , NULL },"m25px64" , 0 x207117, 0 , 64 * 1024 , 128 , M25PX_FLAG, 75 , NULL },/* Macronix MX25xxx * - Support for ' FLASH_FLAG_WRITE_1_4_4 ' is omitted for devices * where operating frequency must be reduced . #define MX25_FLAG (FLASH_FLAG_READ_WRITE | \"mx25l3255e" , 0 xc29e16, 0 , 64 * 1024 , 64 ,86 ,"mx25l25635e" , 0 xc22019, 0 , 64 *1024 , 512 ,70 ,"mx25l25655e" , 0 xc22619, 0 , 64 *1024 , 512 ,70 ,#define N25Q_FLAG (FLASH_FLAG_READ_WRITE | \"n25q128" , 0 x20ba18, 0 , 64 * 1024 , 256 , N25Q_FLAG, 108 ,"n25q256" , 0 x20ba19, 0 , 64 * 1024 , 512 ,108 , stfsm_n25q_config },/* * Spansion S25FLxxxP * - 256 KiB and 64 KiB sector variants ( identified by ext . JEDEC ) #define S25FLXXXP_FLAG (FLASH_FLAG_READ_WRITE | \"s25fl032p" , 0 x010215, 0 x4d00, 64 * 1024 , 64 , S25FLXXXP_FLAG, 80 ,"s25fl129p0" , 0 x012018, 0 x4d00, 256 * 1024 , 64 , S25FLXXXP_FLAG, 80 ,"s25fl129p1" , 0 x012018, 0 x4d01, 64 * 1024 , 256 , S25FLXXXP_FLAG, 80 ,/* * Spansion S25FLxxxS * - 256 KiB and 64 KiB sector variants ( identified by ext . JEDEC ) * - RESET # signal supported by die but not bristled out on all * package types . The package type is a function of board design , * so this information is captured in the board ' s flags . * - Supports ' DYB ' sector protection . Depending on variant , sectors * may default to locked state on power - on . #define S25FLXXXS_FLAG (S25FLXXXP_FLAG | \"s25fl128s0" , 0 x012018, 0 x0300, 256 * 1024 , 64 , S25FLXXXS_FLAG, 80 ,"s25fl128s1" , 0 x012018, 0 x0301, 64 * 1024 , 256 , S25FLXXXS_FLAG, 80 ,"s25fl256s0" , 0 x010219, 0 x4d00, 256 * 1024 , 128 ,80 , stfsm_s25fl_config },"s25fl256s1" , 0 x010219, 0 x4d01, 64 * 1024 , 512 ,80 , stfsm_s25fl_config },/* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */ #define W25X_FLAG (FLASH_FLAG_READ_WRITE | \"w25x40" , 0 xef3013, 0 , 64 * 1024 , 8 , W25X_FLAG, 75 , NULL },"w25x80" , 0 xef3014, 0 , 64 * 1024 , 16 , W25X_FLAG, 75 , NULL },"w25x16" , 0 xef3015, 0 , 64 * 1024 , 32 , W25X_FLAG, 75 , NULL },"w25x32" , 0 xef3016, 0 , 64 * 1024 , 64 , W25X_FLAG, 75 , NULL },"w25x64" , 0 xef3017, 0 , 64 * 1024 , 128 , W25X_FLAG, 75 , NULL },/* Winbond -- w25q "blocks" are 64K, "sectors" are 4KiB */ #define W25Q_FLAG (FLASH_FLAG_READ_WRITE | \"w25q80" , 0 xef4014, 0 , 64 * 1024 , 16 , W25Q_FLAG, 80 ,"w25q16" , 0 xef4015, 0 , 64 * 1024 , 32 , W25Q_FLAG, 80 ,"w25q32" , 0 xef4016, 0 , 64 * 1024 , 64 , W25Q_FLAG, 80 ,"w25q64" , 0 xef4017, 0 , 64 * 1024 , 128 , W25Q_FLAG, 80 ,/* Sentinel */ 0 x000000, 0 , 0 , 0 , 0 , 0 , NULL },/* * FSM message sequence configurations : * * All configs are presented in order of preference /* Default READ configurations, in order of preference */ static struct seq_rw_config default_read_configs[] = {0 , 4 , 4 , 0 x00, 2 , 4 },0 , 1 , 4 , 0 x00, 4 , 0 },0 , 2 , 2 , 0 x00, 4 , 0 },0 , 1 , 2 , 0 x00, 0 , 8 },0 , 1 , 1 , 0 x00, 0 , 8 },0 , 1 , 1 , 0 x00, 0 , 0 },0 x00, 0 , 0 , 0 , 0 , 0 x00, 0 , 0 },/* Default WRITE configurations */ static struct seq_rw_config default_write_configs[] = {1 , 4 , 4 , 0 x00, 0 , 0 },1 , 1 , 4 , 0 x00, 0 , 0 },1 , 2 , 2 , 0 x00, 0 , 0 },1 , 1 , 2 , 0 x00, 0 , 0 },1 , 1 , 1 , 0 x00, 0 , 0 },0 x00, 0 , 0 , 0 , 0 , 0 x00, 0 , 0 },/* * [ N25Qxxx ] Configuration #define N25Q_VCR_DUMMY_CYCLES(x) (((x) & 0 xf) << 4 )#define N25Q_VCR_XIP_DISABLED ((uint8_t)0 x1 << 3 )#define N25Q_VCR_WRAP_CONT 0 x3/* N25Q 3-byte Address READ configurations * - ' FAST ' variants configured for 8 dummy cycles . * * Note , the number of dummy cycles used for ' FAST ' READ operations is * configurable and would normally be tuned according to the READ command and * operating frequency . However , this applies universally to all ' FAST ' READ * commands , including those used by the SPIBoot controller , and remains in * force until the device is power - cycled . Since the SPIBoot controller is * hard - wired to use 8 dummy cycles , we must configure the device to also use 8 * cycles . static struct seq_rw_config n25q_read3_configs[] = {0 , 4 , 4 , 0 x00, 0 , 8 },0 , 1 , 4 , 0 x00, 0 , 8 },0 , 2 , 2 , 0 x00, 0 , 8 },0 , 1 , 2 , 0 x00, 0 , 8 },0 , 1 , 1 , 0 x00, 0 , 8 },0 , 1 , 1 , 0 x00, 0 , 0 },0 x00, 0 , 0 , 0 , 0 , 0 x00, 0 , 0 },/* N25Q 4-byte Address READ configurations * - use special 4 - byte address READ commands ( reduces overheads , and * reduces risk of hitting watchdog reset issues ) . * - ' FAST ' variants configured for 8 dummy cycles ( see note above . ) static struct seq_rw_config n25q_read4_configs[] = {0 , 4 , 4 , 0 x00, 0 , 8 },0 , 1 , 4 , 0 x00, 0 , 8 },0 , 2 , 2 , 0 x00, 0 , 8 },0 , 1 , 2 , 0 x00, 0 , 8 },0 , 1 , 1 , 0 x00, 0 , 8 },0 , 1 , 1 , 0 x00, 0 , 0 },0 x00, 0 , 0 , 0 , 0 , 0 x00, 0 , 0 },/* * [ MX25xxx ] Configuration #define MX25_STATUS_QE (0 x1 << 6 )static int stfsm_mx25_en_32bit_addr_seq(struct stfsm_seq *seq)0 ] = (SEQ_OPC_PADS_1 |8 ) |0 ] = STFSM_INST_CMD1;1 ] = STFSM_INST_WAIT;2 ] = STFSM_INST_STOP;return 0 ;/* * [ S25FLxxx ] Configuration #define STFSM_S25FL_CONFIG_QE (0 x1 << 1 )/* * S25FLxxxS devices provide three ways of supporting 32 - bit addressing : Bank * Register , Extended Address Modes , and a 32 - bit address command set . The * 32 - bit address command set is used here , since it avoids any problems with * entering a state that is incompatible with the SPIBoot Controller . static struct seq_rw_config stfsm_s25fl_read4_configs[] = {0 , 4 , 4 , 0 x00, 2 , 4 },0 , 1 , 4 , 0 x00, 0 , 8 },0 , 2 , 2 , 0 x00, 4 , 0 },0 , 1 , 2 , 0 x00, 0 , 8 },0 , 1 , 1 , 0 x00, 0 , 8 },0 , 1 , 1 , 0 x00, 0 , 0 },0 x00, 0 , 0 , 0 , 0 , 0 x00, 0 , 0 },static struct seq_rw_config stfsm_s25fl_write4_configs[] = {1 , 1 , 4 , 0 x00, 0 , 0 },1 , 1 , 1 , 0 x00, 0 , 0 },0 x00, 0 , 0 , 0 , 0 , 0 x00, 0 , 0 },/* * [ W25Qxxx ] Configuration #define W25Q_STATUS_QE (0 x1 << 1 )static struct stfsm_seq stfsm_seq_read_jedec = {8 ),0 ] = (SEQ_OPC_PADS_1 |8 ) |static struct stfsm_seq stfsm_seq_read_status_fifo = {4 ),0 ] = (SEQ_OPC_PADS_1 |8 ) |static struct stfsm_seq stfsm_seq_erase_sector = {/* 'addr_cfg' configured during initialisation */ 8 ) |8 ) |static struct stfsm_seq stfsm_seq_erase_chip = {8 ) |8 ) |static struct stfsm_seq stfsm_seq_write_status = {0 ] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8 ) |1 ] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8 ) |/* Dummy sequence to read one byte of data from flash into the FIFO */ static const struct stfsm_seq stfsm_seq_load_fifo_byte = {1 ),0 ] = (SEQ_OPC_PADS_1 |8 ) |static int stfsm_n25q_en_32bit_addr_seq(struct stfsm_seq *seq)0 ] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8 ) |1 ] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8 ) |0 ] = STFSM_INST_CMD2;1 ] = STFSM_INST_CMD1;2 ] = STFSM_INST_WAIT;3 ] = STFSM_INST_STOP;return 0 ;static inline int stfsm_is_idle(struct stfsm *fsm)return readl(fsm->base + SPI_FAST_SEQ_STA) & 0 x10;static inline uint32_t stfsm_fifo_available(struct stfsm *fsm)return (readl(fsm->base + SPI_FAST_SEQ_STA) >> 5 ) & 0 x7f;static inline void stfsm_load_seq(struct stfsm *fsm,const struct stfsm_seq *seq)void __iomem *dst = fsm->base + SPI_FAST_SEQ_TRANSFER_SIZE;const uint32_t *src = (const uint32_t *)seq;int words = sizeof (*seq) / sizeof (*src);while (words--) {4 ;static void stfsm_wait_seq(struct stfsm *fsm)unsigned long deadline;int timeout = 0 ;while (!timeout) {if (time_after_eq(jiffies, deadline))1 ;if (stfsm_is_idle(fsm))return ;"timeout on sequence completion\n" );static void stfsm_read_fifo(struct stfsm *fsm, uint32_t *buf, uint32_t size)2 ;"Reading %d bytes from FIFO\n" , size);0 x3) || (size & 0 x3));while (remaining) {for (;;) {if (avail)break ;1 );/* * Clear the data FIFO * * Typically , this is only required during driver initialisation , where no * assumptions can be made regarding the state of the FIFO . * * The process of clearing the FIFO is complicated by fact that while it is * possible for the FIFO to contain an arbitrary number of bytes [ 1 ] , the * SPI_FAST_SEQ_STA register only reports the number of complete 32 - bit words * present . Furthermore , data can only be drained from the FIFO by reading * complete 32 - bit words . * * With this in mind , a two stage process is used to the clear the FIFO : * * 1 . Read any complete 32 - bit words from the FIFO , as reported by the * SPI_FAST_SEQ_STA register . * * 2 . Mop up any remaining bytes . At this point , it is not known if there * are 0 , 1 , 2 , or 3 bytes in the FIFO . To handle all cases , a dummy FSM * sequence is used to load one byte at a time , until a complete 32 - bit * word is formed ; at most , 4 bytes will need to be loaded . * * [ 1 ] It is theoretically possible for the FIFO to contain an arbitrary number * of bits . However , since there are no known use - cases that leave * incomplete bytes in the FIFO , only words and bytes are considered here . static void stfsm_clear_fifo(struct stfsm *fsm)const struct stfsm_seq *seq = &stfsm_seq_load_fifo_byte;/* 1. Clear any 32-bit words */ if (words) {for (i = 0 ; i < words; i++)"cleared %d words from FIFO\n" , words);/* * 2 . Clear any remaining bytes * - Load the FIFO , one byte at a time , until a complete 32 - bit word * is available . for (i = 0 , words = 0 ; i < 4 && !words; i++) {/* - A single word must be available now */ if (words != 1 ) {"failed to clear bytes from the data FIFO\n" );return ;/* - Read the 32-bit word */ "cleared %d byte(s) from the data FIFO\n" , 4 - i);static int stfsm_write_fifo(struct stfsm *fsm, const uint32_t *buf,2 ;"writing %d bytes to FIFO\n" , size);0 x3) || (size & 0 x3));return size;static int stfsm_enter_32bit_addr(struct stfsm *fsm, int enter)struct stfsm_seq *seq = &fsm->stfsm_seq_en_32bit_addr;0 ] = (SEQ_OPC_PADS_1 |8 ) |return 0 ;static uint8_t stfsm_wait_busy(struct stfsm *fsm)struct stfsm_seq *seq = &stfsm_seq_read_status_fifo;unsigned long deadline;int timeout = 0 ;/* Use RDRS1 */ 0 ] = (SEQ_OPC_PADS_1 |8 ) |/* Load read_status sequence */ /* * Repeat until busy bit is deasserted , or timeout , or error ( S25FLxxxS ) while (!timeout) {if (time_after_eq(jiffies, deadline))1 ;4 );if ((status & FLASH_STATUS_BUSY) == 0 )return 0 ;if ((fsm->configuration & CFG_S25FL_CHECK_ERROR_FLAGS) &&return (uint8_t)(status & 0 xff);if (!timeout)/* Restart */ "timeout on wait_busy\n" );return FLASH_STATUS_TIMEOUT;static int stfsm_read_status(struct stfsm *fsm, uint8_t cmd,int bytes)struct stfsm_seq *seq = &stfsm_seq_read_status_fifo;int i;"read 'status' register [0x%02x], %d byte(s)\n" ,1 && bytes != 2 );0 ] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8 ) |4 );for (i = 0 ; i < bytes; i++)return 0 ;static int stfsm_write_status(struct stfsm *fsm, uint8_t cmd,int bytes, int wait_busy)struct stfsm_seq *seq = &stfsm_seq_write_status;"write 'status' register [0x%02x], %d byte(s), 0x%04x\n" " %s wait-busy\n" , cmd, bytes, data, wait_busy ? "with" : "no" );1 && bytes != 2 );1 ] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8 ) |2 ] = (bytes == 1 ) ? STFSM_INST_STA_WR1 : STFSM_INST_STA_WR1_2;if (wait_busy)return 0 ;/* * SoC reset on ' boot - from - spi ' systems * * Certain modes of operation cause the Flash device to enter a particular state * for a period of time ( e . g . ' Erase Sector ' , ' Quad Enable ' , and ' Enter 32 - bit * Addr ' commands ) . On boot - from - spi systems , it is important to consider what * happens if a warm reset occurs during this period . The SPIBoot controller * assumes that Flash device is in its default reset state , 24 - bit address mode , * and ready to accept commands . This can be achieved using some form of * on - board logic / controller to force a device POR in response to a SoC - level * reset or by making use of the device reset signal if available ( limited * number of devices only ) . * * Failure to take such precautions can cause problems following a warm reset . * For some operations ( e . g . ERASE ) , there is little that can be done . For * other modes of operation ( e . g . 32 - bit addressing ) , options are often * available that can help minimise the window in which a reset could cause a * problem . * static bool stfsm_can_handle_soc_reset(struct stfsm *fsm)/* Reset signal is available on the board and supported by the device */ if (fsm->reset_signal && fsm->info->flags & FLASH_FLAG_RESET)return true ;/* Board-level logic forces a power-on-reset */ if (fsm->reset_por)return true ;/* Reset is not properly handled and may result in failure to reboot */ return false ;/* Configure 'addr_cfg' according to addressing mode */ static void stfsm_prepare_erasesec_seq(struct stfsm *fsm,struct stfsm_seq *seq)int addr1_cycles = fsm->info->flags & FLASH_FLAG_32BIT_ADDR ? 16 : 8 ;16 ) |/* Search for preferred configuration based on available flags */ static struct seq_rw_config *struct stfsm *fsm,struct seq_rw_config cfgs[])struct seq_rw_config *config;int flags = fsm->info->flags;for (config = cfgs; config->cmd != 0 ; config++)if ((config->flags & flags) == config->flags)return config;return NULL;/* Prepare a READ/WRITE sequence according to configuration parameters */ static void stfsm_prepare_rw_seq(struct stfsm *fsm,struct stfsm_seq *seq,struct seq_rw_config *cfg)int addr1_cycles, addr2_cycles;int i = 0 ;0 , sizeof (*seq));/* Add READ/WRITE OPC */ 8 ) |/* Add WREN OPC for a WRITE sequence */ if (cfg->write)8 ) |/* Address configuration (24 or 32-bit addresses) */ 16 : 8 ;16 / cfg->addr_pads;0 x3f) << 0 | /* ADD1 cycles */ 1 ) << 6 | /* ADD1 pads */ 0 x3f) << 16 | /* ADD2 cycles */ 1 ) << 22 )); /* ADD2 pads */ /* Data/Sequence configuration */ 1 ) << 16 |if (!cfg->write)/* Mode configuration (no. of pads taken from addr cfg) */ 0 xff) << 0 | /* data */ 0 x3f) << 16 | /* cycles */ 1 ) << 22 ); /* pads */ /* Dummy configuration (no. of pads taken from addr cfg) */ 0 x3f) << 16 | /* cycles */ 1 ) << 22 ); /* pads */ /* Instruction sequence */ 0 ;if (cfg->write)if (cfg->mode_cycles)if (cfg->dummy_cycles)static int stfsm_search_prepare_rw_seq(struct stfsm *fsm,struct stfsm_seq *seq,struct seq_rw_config *cfgs)struct seq_rw_config *config;if (!config) {"failed to find suitable config\n" );return -EINVAL;return 0 ;/* Prepare a READ/WRITE/ERASE 'default' sequences */ static int stfsm_prepare_rwe_seqs_default(struct stfsm *fsm)int ret;/* Configure 'READ' sequence */ if (ret) {"failed to prep READ sequence with flags [0x%08x]\n" ,return ret;/* Configure 'WRITE' sequence */ if (ret) {"failed to prep WRITE sequence with flags [0x%08x]\n" ,return ret;/* Configure 'ERASE_SECTOR' sequence */ return 0 ;static int stfsm_mx25_config(struct stfsm *fsm)int ret;bool soc_reset;/* * Use default READ / WRITE sequences if (ret)return ret;/* * Configure 32 - bit Address Support if (flags & FLASH_FLAG_32BIT_ADDR) {/* Configure 'enter_32bitaddr' FSM sequence */ if (soc_reset || !fsm->booted_from_spi)/* If we can handle SoC resets, we enable 32-bit address 1 );else /* Else, enable/disable 32-bit addressing before/after /* Check status of 'QE' bit, update if required. */ 1 );16 ) & 0 x3) + 1 ;if (data_pads == 4 ) {if (!(sta & MX25_STATUS_QE)) {/* Set 'QE' */ 1 , 1 );else {if (sta & MX25_STATUS_QE) {/* Clear 'QE' */ 1 , 1 );return 0 ;static int stfsm_n25q_config(struct stfsm *fsm)int ret = 0 ;bool soc_reset;/* Configure 'READ' sequence */ if (flags & FLASH_FLAG_32BIT_ADDR)else if (ret) {"failed to prepare READ sequence with flags [0x%08x]\n" ,return ret;/* Configure 'WRITE' sequence (default configs) */ if (ret) {"preparing WRITE sequence using flags [0x%08x] failed\n" ,return ret;/* * Configure 'ERASE_SECTOR' sequence */ /* Configure 32-bit address support */ if (flags & FLASH_FLAG_32BIT_ADDR) {if (soc_reset || !fsm->booted_from_spi) {/* * If we can handle SoC resets , we enable 32 - bit * address mode pervasively 1 );else {/* * If not , enable / disable for WRITE and ERASE * operations ( READ uses special commands ) /* * Configure device to use 8 dummy cycles 8 ) | N25Q_VCR_XIP_DISABLED |1 , 0 );return 0 ;static void stfsm_s25fl_prepare_erasesec_seq_32(struct stfsm_seq *seq)1 ] = (SEQ_OPC_PADS_1 |8 ) |16 ) |16 ) |static void stfsm_s25fl_read_dyb(struct stfsm *fsm, uint32_t offs, uint8_t *dby)struct stfsm_seq seq = {4 ),0 ] = (SEQ_OPC_PADS_1 |8 ) |16 ) |16 ) |16 ) & 0 xffff,0 xffff,4 );24 );static void stfsm_s25fl_write_dyb(struct stfsm *fsm, uint32_t offs, uint8_t dby)struct stfsm_seq seq = {0 ] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8 ) |1 ] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8 ) |16 ) |16 ) |16 ) & 0 xffff,0 xffff,static int stfsm_s25fl_clear_status_reg(struct stfsm *fsm)struct stfsm_seq seq = {0 ] = (SEQ_OPC_PADS_1 |8 ) |1 ] = (SEQ_OPC_PADS_1 |8 ) |return 0 ;static int stfsm_s25fl_config(struct stfsm *fsm)struct flash_info *info = fsm->info;int update_sr = 0 ;int ret;if (flags & FLASH_FLAG_32BIT_ADDR) {/* * Prepare Read / Write / Erase sequences according to S25FLxxx * 32 - bit address command set if (ret)return ret;if (ret)return ret;else {/* Use default configurations for 24-bit addressing */ if (ret)return ret;/* * For devices that support ' DYB ' sector locking , check lock status and * unlock sectors if necessary ( some variants power - on with sectors * locked by default ) if (flags & FLASH_FLAG_DYB_LOCKING) {0 ;for (offs = 0 ; offs < info->sector_size * info->n_sectors;) {if (dyb == 0 x00)0 xff);/* Handle bottom/top 4KiB parameter sectors */ if ((offs < info->sector_size * 2 ) ||4 )))0 x1000;else 0 x10000;/* Check status of 'QE' bit, update if required. */ 1 );16 ) & 0 x3) + 1 ;if (data_pads == 4 ) {if (!(cr1 & STFSM_S25FL_CONFIG_QE)) {/* Set 'QE' */ 1 ;else {if (cr1 & STFSM_S25FL_CONFIG_QE) {/* Clear 'QE' */ 1 ;if (update_sr) {1 );8 ) | sr1;2 , 1 );/* * S25FLxxx devices support Program and Error error flags . * Configure driver to check flags and clear if necessary . return 0 ;static int stfsm_w25q_config(struct stfsm *fsm)int update_sr = 0 ;int ret;if (ret)return ret;/* Check status of 'QE' bit, update if required. */ 1 );16 ) & 0 x3) + 1 ;if (data_pads == 4 ) {if (!(sr2 & W25Q_STATUS_QE)) {/* Set 'QE' */ 1 ;else {if (sr2 & W25Q_STATUS_QE) {/* Clear 'QE' */ 1 ;if (update_sr) {/* Write status register */ 1 );8 ) | sr1;2 , 1 );return 0 ;static int stfsm_read(struct stfsm *fsm, uint8_t *buf, uint32_t size,struct stfsm_seq *seq = &fsm->stfsm_seq_read;4 ];"reading %d bytes from 0x%08x\n" , size, offset);/* Enter 32-bit address mode, if required */ if (fsm->configuration & CFG_READ_TOGGLE_32BIT_ADDR)1 );/* Must read in multiples of 32 cycles (or 32*pads/8 Bytes) */ 16 ) & 0 x3) + 1 ;2 ) - 1 ;/* Handle non-aligned buf */ 0 x3) ? (uint8_t *)page_buf : buf;/* Handle non-aligned size */ 16 ) & 0 xffff;0 xffff;if (size_lb)if (size_mop) {1 );/* Handle non-aligned buf */ if ((uintptr_t)buf & 0 x3)/* Wait for sequence to finish */ /* Exit 32-bit address mode, if required */ if (fsm->configuration & CFG_READ_TOGGLE_32BIT_ADDR)0 );return 0 ;static int stfsm_write(struct stfsm *fsm, const uint8_t *buf,struct stfsm_seq *seq = &fsm->stfsm_seq_write;4 ];const uint8_t *p;int ret;"writing %d bytes to 0x%08x\n" , size, offset);/* Enter 32-bit address mode, if required */ if (fsm->configuration & CFG_WRITE_TOGGLE_32BIT_ADDR)1 );/* Must write in multiples of 32 cycles (or 32*pads/8 bytes) */ 16 ) & 0 x3) + 1 ;2 ) - 1 ;/* Handle non-aligned buf */ if ((uintptr_t)buf & 0 x3) {else {/* Handle non-aligned size */ 16 ) & 0 xffff;0 xffff;/* Need to set FIFO to write mode, before writing data to FIFO (see * GNBvb79594 ) 0 x00040000, fsm->base + SPI_FAST_SEQ_CFG);/* * Before writing data to the FIFO , apply a small delay to allow a * potential change of FIFO direction to complete . if (fsm->fifo_dir_delay == 0 )else /* Write data to FIFO, before starting sequence (see GNBvd79593) */ if (size_lb) {/* Handle non-aligned size */ if (size_mop) {0 xff, write_mask + 1 ); /* fill with 0xff's */ for (i = 0 ; i < size_mop; i++)1 );/* Start sequence */ /* Wait for sequence to finish */ /* Wait for completion */ if (ret && fsm->configuration & CFG_S25FL_CHECK_ERROR_FLAGS)/* Exit 32-bit address mode, if required */ if (fsm->configuration & CFG_WRITE_TOGGLE_32BIT_ADDR)0 );return 0 ;/* * Read an address range from the flash chip . The address range * may be any size provided it is within the physical boundaries . static int stfsm_mtd_read(struct mtd_info *mtd, loff_t from, size_t len,struct stfsm *fsm = dev_get_drvdata(mtd->dev.parent);"%s from 0x%08x, len %zd\n" ,while (len > 0 ) {return 0 ;static int stfsm_erase_sector(struct stfsm *fsm, uint32_t offset)struct stfsm_seq *seq = &stfsm_seq_erase_sector;int ret;"erasing sector at 0x%08x\n" , offset);/* Enter 32-bit address mode, if required */ if (fsm->configuration & CFG_ERASESEC_TOGGLE_32BIT_ADDR)1 );16 ) & 0 xffff;0 xffff;/* Wait for completion */ if (ret && fsm->configuration & CFG_S25FL_CHECK_ERROR_FLAGS)/* Exit 32-bit address mode, if required */ if (fsm->configuration & CFG_ERASESEC_TOGGLE_32BIT_ADDR)0 );return ret;static int stfsm_erase_chip(struct stfsm *fsm)const struct stfsm_seq *seq = &stfsm_seq_erase_chip;"erasing chip\n" );return stfsm_wait_busy(fsm);/* * Write an address range to the flash chip . Data must be written in * FLASH_PAGESIZE chunks . The address range may be any size provided * it is within the physical boundaries . static int stfsm_mtd_write(struct mtd_info *mtd, loff_t to, size_t len,const u_char *buf)struct stfsm *fsm = dev_get_drvdata(mtd->dev.parent);int ret = 0 ;"%s to 0x%08x, len %zd\n" , __func__, (u32)to, len);/* Offset within page */ while (len) {/* Write up to page boundary */ if (ret)goto out1;/* We are now page-aligned */ 0 ;return ret;/* * Erase an address range on the flash chip . The address range may extend * one or more erase sectors . Return an error is there is a problem erasing . static int stfsm_mtd_erase(struct mtd_info *mtd, struct erase_info *instr)struct stfsm *fsm = dev_get_drvdata(mtd->dev.parent);int ret;"%s at 0x%llx, len %lld\n" , __func__,long long )instr->addr, (long long )instr->len);/* Whole-chip erase? */ if (len == mtd->size) {if (ret)goto out1;else {while (len) {if (ret)goto out1;return 0 ;return ret;static void stfsm_read_jedec(struct stfsm *fsm, uint8_t *jedec)const struct stfsm_seq *seq = &stfsm_seq_read_jedec;2 ];8 );5 );static struct flash_info *stfsm_jedec_probe(struct stfsm *fsm)struct flash_info *info;5 ];0 ] << 16 | id[1 ] << 8 | id[2 ];/* * JEDEC also defines an optional " extended device information " * string for after vendor - specific data , after the three bytes * we use here . Supporting some chips might require using it . 3 ] << 8 | id[4 ];"JEDEC = 0x%08x [%5ph]\n" , jedec, id);for (info = flash_types; info->name; info++) {if (info->jedec_id == jedec) {if (info->ext_id && info->ext_id != ext_jedec)continue ;return info;"Unrecognized JEDEC id %06x\n" , jedec);return NULL;static int stfsm_set_mode(struct stfsm *fsm, uint32_t mode)int ret, timeout = 10 ;/* Wait for controller to accept mode change */ while (--timeout) {if (ret & 0 x1)break ;1 );if (!timeout)return -EBUSY;return 0 ;static void stfsm_set_freq(struct stfsm *fsm, uint32_t spi_freq)/* * Calculate clk_div - values between 2 and 128 * Multiple of 2 , rounded up 2 * DIV_ROUND_UP(emi_freq, 2 * spi_freq);if (clk_div < 2 )2 ;else if (clk_div > 128 )128 ;/* * Determine a suitable delay for the IP to complete a change of * direction of the FIFO . The required delay is related to the clock * divider used . The following heuristics are based on empirical tests , * using a 100 MHz EMI clock . if (clk_div <= 4 )0 ;else if (clk_div <= 10 )1 ;else 10 );"emi_clk = %uHZ, spi_freq = %uHZ, clk_div = %u\n" ,static int stfsm_init(struct stfsm *fsm)int ret;/* Perform a soft reset of the FSM controller */ 1 );0 , fsm->base + SPI_FAST_SEQ_CFG);/* Set clock to 'safe' frequency initially */ /* Switch to FSM */ if (ret)return ret;/* Set timing parameters */ /* * Set the FSM ' WAIT ' delay to the minimum workable value . Note , for * our purposes , the WAIT instruction is used purely to achieve * " sequence validity " rather than actually implement a delay . 0 x00000001, fsm->base + SPI_PROGRAM_ERASE_TIME);/* Clear FIFO, just in case */ return 0 ;static void stfsm_fetch_platform_configs(struct platform_device *pdev)struct stfsm *fsm = platform_get_drvdata(pdev);struct device_node *np = pdev->dev.of_node;struct regmap *regmap;/* Value we read from *boot_device_reg */ int ret;/* Booting from SPI NOR Flash is the default */ true ;"st,syscfg" );if (IS_ERR(regmap))goto boot_device_fail;"st,reset-signal" );"st,reset-por" );/* Where in the syscon the boot device information lives */ "st,boot-device-reg" , &boot_device_reg);if (ret)goto boot_device_fail;/* Boot device value when booted from SPI NOR */ "st,boot-device-spi" , &boot_device_spi);if (ret)goto boot_device_fail;if (ret)goto boot_device_fail;if (boot_device != boot_device_spi)false ;return ;"failed to fetch boot device, assuming boot from SPI\n" );static int stfsm_probe(struct platform_device *pdev)struct device_node *np = pdev->dev.of_node;struct flash_info *info;struct stfsm *fsm;int ret;if (!np) {"No DT found\n" );return -EINVAL;sizeof (*fsm), GFP_KERNEL);if (!fsm)return -ENOMEM;0 );if (IS_ERR(fsm->base))return PTR_ERR(fsm->base);if (IS_ERR(fsm->clk)) {"Couldn't find EMI clock.\n" );return PTR_ERR(fsm->clk);if (ret) {"Failed to initialise FSM Controller\n" );return ret;/* Detect SPI FLASH device */ if (!info)return -ENODEV;/* Use device size to determine address width */ if (info->sector_size * info->n_sectors > 0 x1000000)/* * Configure READ / WRITE / ERASE sequences according to platform and * device flags . if (info->config)else if (ret)return ret;4 ;"Found serial flash device: %s\n" " size = %llx (%lldMiB) erasesize = 0x%08x (%uKiB)\n" ,long long )fsm->mtd.size, (long long )(fsm->mtd.size >> 20 ),10 ));return mtd_device_register(&fsm->mtd, NULL, 0 );static void stfsm_remove(struct platform_device *pdev)struct stfsm *fsm = platform_get_drvdata(pdev);static int stfsmfsm_suspend(struct device *dev)struct stfsm *fsm = dev_get_drvdata(dev);return 0 ;static int stfsmfsm_resume(struct device *dev)struct stfsm *fsm = dev_get_drvdata(dev);return clk_prepare_enable(fsm->clk);static DEFINE_SIMPLE_DEV_PM_OPS(stfsm_pm_ops, stfsmfsm_suspend, stfsmfsm_resume);static const struct of_device_id stfsm_match[] = {"st,spi-fsm" , },static struct platform_driver stfsm_driver = {"st-spi-fsm" ,"Angus Clark <angus.clark@st.com>" );"ST SPI FSM driver" );"GPL" );
Messung V0.5 in Prozent C=93 H=91 G=91
¤ Dauer der Verarbeitung: 0.32 Sekunden
(vorverarbeitet am 2026-09-29)
¤ *© Formatika GbR, Deutschland
