Quelle sdhci-msm.c
Sprache: C
// SPDX-License-Identifier: GPL-2.0-only /* * drivers / mmc / host / sdhci - msm . c - Qualcomm SDHCI Platform driver * * Copyright ( c ) 2013 - 2014 , The Linux Foundation . All rights reserved . #include <linux/module.h>#include <linux/delay.h>#include <linux/mmc/mmc.h>#include <linux/pm_runtime.h>#include <linux/pm_opp.h>#include <linux/slab.h>#include <linux/iopoll.h>#include <linux/regulator/consumer.h>#include <linux/interconnect.h>#include <linux/of.h>#include <linux/pinctrl/consumer.h>#include <linux/reset.h>#include <soc/qcom/ice.h>#include "sdhci-cqhci.h" #include "sdhci-pltfm.h" #include "cqhci.h" #define CORE_MCI_VERSION 0 x50#define CORE_VERSION_MAJOR_SHIFT 28 #define CORE_VERSION_MAJOR_MASK (0 xf << CORE_VERSION_MAJOR_SHIFT)#define CORE_VERSION_MINOR_MASK 0 xff#define CORE_MCI_GENERICS 0 x70#define SWITCHABLE_SIGNALING_VOLTAGE BIT(29 )#define HC_MODE_EN 0 x1#define CORE_POWER 0 x0#define CORE_SW_RST BIT(7 )#define FF_CLK_SW_RST_DIS BIT(13 )#define CORE_PWRCTL_BUS_OFF BIT(0 )#define CORE_PWRCTL_BUS_ON BIT(1 )#define CORE_PWRCTL_IO_LOW BIT(2 )#define CORE_PWRCTL_IO_HIGH BIT(3 )#define CORE_PWRCTL_BUS_SUCCESS BIT(0 )#define CORE_PWRCTL_BUS_FAIL BIT(1 )#define CORE_PWRCTL_IO_SUCCESS BIT(2 )#define CORE_PWRCTL_IO_FAIL BIT(3 )#define REQ_BUS_OFF BIT(0 )#define REQ_BUS_ON BIT(1 )#define REQ_IO_LOW BIT(2 )#define REQ_IO_HIGH BIT(3 )#define INT_MASK 0 xf#define MAX_PHASES 16 #define CORE_DLL_LOCK BIT(7 )#define CORE_DDR_DLL_LOCK BIT(11 )#define CORE_DLL_EN BIT(16 )#define CORE_CDR_EN BIT(17 )#define CORE_CK_OUT_EN BIT(18 )#define CORE_CDR_EXT_EN BIT(19 )#define CORE_DLL_PDN BIT(29 )#define CORE_DLL_RST BIT(30 )#define CORE_CMD_DAT_TRACK_SEL BIT(0 )#define CORE_DDR_CAL_EN BIT(0 )#define CORE_FLL_CYCLE_CNT BIT(18 )#define CORE_DLL_CLOCK_DISABLE BIT(21 )#define DLL_USR_CTL_POR_VAL 0 x10800#define ENABLE_DLL_LOCK_STATUS BIT(26 )#define FINE_TUNE_MODE_EN BIT(27 )#define BIAS_OK_SIGNAL BIT(29 )#define DLL_CONFIG_3_LOW_FREQ_VAL 0 x08#define DLL_CONFIG_3_HIGH_FREQ_VAL 0 x10#define CORE_VENDOR_SPEC_POR_VAL 0 xa9c#define CORE_CLK_PWRSAVE BIT(1 )#define CORE_HC_MCLK_SEL_DFLT (2 << 8 )#define CORE_HC_MCLK_SEL_HS400 (3 << 8 )#define CORE_HC_MCLK_SEL_MASK (3 << 8 )#define CORE_IO_PAD_PWR_SWITCH_EN BIT(15 )#define CORE_IO_PAD_PWR_SWITCH BIT(16 )#define CORE_HC_SELECT_IN_EN BIT(18 )#define CORE_HC_SELECT_IN_SDR50 (4 << 19 )#define CORE_HC_SELECT_IN_HS400 (6 << 19 )#define CORE_HC_SELECT_IN_MASK (7 << 19 )#define CORE_3_0V_SUPPORT BIT(25 )#define CORE_1_8V_SUPPORT BIT(26 )#define CORE_VOLT_SUPPORT (CORE_3_0V_SUPPORT | CORE_1_8V_SUPPORT)#define CORE_CSR_CDC_CTLR_CFG0 0 x130#define CORE_SW_TRIG_FULL_CALIB BIT(16 )#define CORE_HW_AUTOCAL_ENA BIT(17 )#define CORE_CSR_CDC_CTLR_CFG1 0 x134#define CORE_CSR_CDC_CAL_TIMER_CFG0 0 x138#define CORE_TIMER_ENA BIT(16 )#define CORE_CSR_CDC_CAL_TIMER_CFG1 0 x13C#define CORE_CSR_CDC_REFCOUNT_CFG 0 x140#define CORE_CSR_CDC_COARSE_CAL_CFG 0 x144#define CORE_CDC_OFFSET_CFG 0 x14C#define CORE_CSR_CDC_DELAY_CFG 0 x150#define CORE_CDC_SLAVE_DDA_CFG 0 x160#define CORE_CSR_CDC_STATUS0 0 x164#define CORE_CALIBRATION_DONE BIT(0 )#define CORE_CDC_ERROR_CODE_MASK 0 x7000000#define CORE_CSR_CDC_GEN_CFG 0 x178#define CORE_CDC_SWITCH_BYPASS_OFF BIT(0 )#define CORE_CDC_SWITCH_RC_EN BIT(1 )#define CORE_CDC_T4_DLY_SEL BIT(0 )#define CORE_CMDIN_RCLK_EN BIT(1 )#define CORE_START_CDC_TRAFFIC BIT(6 )#define CORE_PWRSAVE_DLL BIT(3 )#define DDR_CONFIG_POR_VAL 0 x80040873#define INVALID_TUNING_PHASE -1 #define SDHCI_MSM_MIN_CLOCK 400000 #define CORE_FREQ_100MHZ (100 * 1000 * 1000 )#define CDR_SELEXT_SHIFT 20 #define CDR_SELEXT_MASK (0 xf << CDR_SELEXT_SHIFT)#define CMUX_SHIFT_PHASE_SHIFT 24 #define CMUX_SHIFT_PHASE_MASK (7 << CMUX_SHIFT_PHASE_SHIFT)#define MSM_MMC_AUTOSUSPEND_DELAY_MS 50 /* Timeout value to avoid infinite waiting for pwr_irq */ #define MSM_PWR_IRQ_TIMEOUT_MS 5000 /* Max load for eMMC Vdd supply */ #define MMC_VMMC_MAX_LOAD_UA 570000 /* Max load for eMMC Vdd-io supply */ #define MMC_VQMMC_MAX_LOAD_UA 325000 /* Max load for SD Vdd supply */ #define SD_VMMC_MAX_LOAD_UA 800000 /* Max load for SD Vdd-io supply */ #define SD_VQMMC_MAX_LOAD_UA 22000 #define msm_host_readl(msm_host, host, offset) \#define msm_host_writel(msm_host, val, host, offset) \/* CQHCI vendor specific registers */ #define CQHCI_VENDOR_CFG1 0 xA00#define CQHCI_VENDOR_DIS_RST_ON_CQ_EN (0 x3 << 13 )struct sdhci_msm_offset {/* Applicable to sdcc minor ver < 0x49 */ /* Present on SDCC5.1 onwards */ static const struct sdhci_msm_offset sdhci_msm_v5_offset = {0 x35c,0 x324,0 x308,0 x318,0 x320,0 x32c,3 ,1 << 31 ),1 << 3 ),0 x240,0 x244,0 x248,0 x24c,0 x358,0 x200,0 x208,0 x20c,0 x214,0 x218,0 x210,0 x21c,0 x224,0 x250,0 x254,0 x258,0 x25c,0 x388,static const struct sdhci_msm_offset sdhci_msm_mci_offset = {0 x78,0 x30,0 x34,0 x44,0 x050,0 x70,0 x0cc,4 ,1 << 3 ),1 << 4 ),0 xdc,0 xe0,0 xe4,0 xe8,0 x124,0 x100,0 x108,0 x10c,0 x114,0 x118,0 x110,0 x11c,0 x184,0 x1b0,0 x1b4,0 x1b8,0 x1bc,struct sdhci_msm_variant_ops {struct sdhci_host *host, u32 offset);void (*msm_writel_relaxed)(u32 val, struct sdhci_host *host,/* * From V5 , register spaces have changed . Wrap this info in a structure * and choose the data_structure based on version info mentioned in DT . struct sdhci_msm_variant_info {bool mci_removed;bool restore_dll_config;const struct sdhci_msm_variant_ops *var_ops;const struct sdhci_msm_offset *offset;struct sdhci_msm_host {struct platform_device *pdev;void __iomem *core_mem; /* MSM SDCC mapped address */ int pwr_irq; /* power irq */ struct clk *bus_clk; /* SDHC bus voter clock */ struct clk *xo_clk; /* TCXO clk needed for FLL feature of cm_dll*/ /* core, iface, cal and sleep clocks */ struct clk_bulk_data bulk_clks[4 ];#ifdef CONFIG_MMC_CRYPTOstruct qcom_ice *ice;#endif unsigned long clk_rate;struct mmc_host *mmc;bool use_14lpp_dll_reset;bool tuning_done;bool calibration_done;bool use_cdclp533;bool pwr_irq_flag;bool mci_removed;bool restore_dll_config;const struct sdhci_msm_variant_ops *var_ops;const struct sdhci_msm_offset *offset;bool use_cdr;bool updated_ddr_cfg;bool uses_tassadar_dll;bool vqmmc_enabled;static const struct sdhci_msm_offset *sdhci_priv_msm_offset(struct sdhci_host *host)struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);return msm_host->offset;/* * APIs to read / write to vendor specific registers which were there in the * core_mem region before MCI was removed . static u32 sdhci_msm_mci_variant_readl_relaxed(struct sdhci_host *host,struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);return readl_relaxed(msm_host->core_mem + offset);static u32 sdhci_msm_v5_variant_readl_relaxed(struct sdhci_host *host,return readl_relaxed(host->ioaddr + offset);static void sdhci_msm_mci_variant_writel_relaxed(u32 val,struct sdhci_host *host, u32 offset)struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);static void sdhci_msm_v5_variant_writel_relaxed(u32 val,struct sdhci_host *host, u32 offset)static unsigned int msm_get_clock_mult_for_bus_mode(struct sdhci_host *host)struct mmc_ios ios = host->mmc->ios;/* * The SDHC requires internal clock frequency to be double the * actual clock that will be set for DDR mode . The controller * uses the faster clock ( 100 / 400 MHz ) for some of its parts and * send the actual required clock ( 50 / 200 MHz ) to the card . if (ios.timing == MMC_TIMING_UHS_DDR50 ||return 2 ;return 1 ;static void msm_set_clock_rate_for_bus_mode(struct sdhci_host *host,unsigned int clock)struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);struct mmc_ios curr_ios = host->mmc->ios;struct clk *core_clk = msm_host->bulk_clks[0 ].clk;unsigned long achieved_rate;unsigned int desired_rate;unsigned int mult;int rc;if (rc) {"%s: Failed to set clock at rate %u at timing %d\n" ,return ;/* * Qualcomm clock drivers by default round clock _ up_ if they can ' t * make the requested rate . This is not good for SD . Yell if we * encounter it . if (achieved_rate > desired_rate)"%s: Card appears overclocked; req %u Hz, actual %lu Hz\n" ,/* Stash the rate we requested to use in sdhci_msm_runtime_resume() */ "%s: Setting clock at rate %lu at timing %d\n" ,/* Platform specific tuning */ static inline int msm_dll_poll_ck_out_en(struct sdhci_host *host, u8 poll)50 ;struct mmc_host *mmc = host->mmc;const struct sdhci_msm_offset *msm_offset =/* Poll for CK_OUT_EN bit. max. poll time = 50us */ while (ck_out_en != poll) {if (--wait_cnt == 0 ) {"%s: CK_OUT_EN bit is not %d\n" ,return -ETIMEDOUT;1 );return 0 ;static int msm_config_cm_dll_phase(struct sdhci_host *host, u8 phase)int rc;static const u8 grey_coded_phase_table[] = {0 x0, 0 x1, 0 x3, 0 x2, 0 x6, 0 x7, 0 x5, 0 x4,0 xc, 0 xd, 0 xf, 0 xe, 0 xa, 0 xb, 0 x9, 0 x8unsigned long flags;struct mmc_host *mmc = host->mmc;const struct sdhci_msm_offset *msm_offset =if (phase > 0 xf)return -EINVAL;/* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '0' */ 0 );if (rc)goto err_out;/* * Write the selected DLL clock output phase ( 0 . . . 15 ) * to CDR_SELEXT bit field of DLL_CONFIG register . /* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '1' */ 1 );if (rc)goto err_out;goto out;"%s: Failed to set DLL phase: %d\n" ,return rc;/* * Find out the greatest range of consecuitive selected * DLL clock output phases that can be used as sampling * setting for SD3 . 0 UHS - I card read operation ( in SDR104 * timing mode ) or for eMMC4 . 5 card read operation ( in * HS400 / HS200 timing mode ) . * Select the 3 / 4 of the range and configure the DLL with the * selected DLL clock output phase . static int msm_find_most_appropriate_phase(struct sdhci_host *host,int ret;0 }, {0 } };0 };int row_index = 0 , col_index = 0 , selected_row_index = 0 , curr_max = 0 ;int i, cnt, phase_0_raw_index = 0 , phase_15_raw_index = 0 ;bool phase_0_found = false , phase_15_found = false ;struct mmc_host *mmc = host->mmc;if (!total_phases || (total_phases > MAX_PHASES)) {"%s: Invalid argument: total_phases=%d\n" ,return -EINVAL;for (cnt = 0 ; cnt < total_phases; cnt++) {1 ;if ((cnt + 1 ) == total_phases) {continue ;/* check if next phase in phase_table is consecutive or not */ else if ((phase_table[cnt] + 1 ) != phase_table[cnt + 1 ]) {0 ;if (row_index >= MAX_PHASES)return -EINVAL;/* Check if phase-0 is present in first valid window? */ if (!ranges[0 ][0 ]) {true ;0 ;/* Check if cycle exist between 2 valid windows */ for (cnt = 1 ; cnt <= row_index; cnt++) {if (phases_per_row[cnt]) {for (i = 0 ; i < phases_per_row[cnt]; i++) {if (ranges[cnt][i] == 15 ) {true ;break ;/* If 2 valid windows form cycle then merge them as single window */ if (phase_0_found && phase_15_found) {/* number of phases in raw where phase 0 is present */ /* number of phases in raw where phase 15 is present */ if (phases_0 + phases_15 >= MAX_PHASES)/* * If there are more than 1 phase windows then total * number of phases in both the windows should not be * more than or equal to MAX_PHASES . return -EINVAL;/* Merge 2 cyclic windows */ for (cnt = 0 ; cnt < phases_0; cnt++) {if (++i >= MAX_PHASES)break ;0 ;for (cnt = 0 ; cnt <= row_index; cnt++) {if (phases_per_row[cnt] > curr_max) {3 ) / 4 ;if (i)if (ret >= MAX_PHASES) {"%s: Invalid phase selected=%d\n" ,return ret;static inline void msm_cm_dll_set_freq(struct sdhci_host *host)0 , config;const struct sdhci_msm_offset *msm_offset =/* Program the MCLK value to MCLK_FREQ bit field */ if (host->clock <= 112000000 )0 ;else if (host->clock <= 125000000 )1 ;else if (host->clock <= 137000000 )2 ;else if (host->clock <= 150000000 )3 ;else if (host->clock <= 162000000 )4 ;else if (host->clock <= 175000000 )5 ;else if (host->clock <= 187000000 )6 ;else if (host->clock <= 200000000 )7 ;/* Initialize the DLL (Programmable Delay Line) */ static int msm_init_cm_dll(struct sdhci_host *host)struct mmc_host *mmc = host->mmc;struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);int wait_cnt = 50 ;unsigned long flags, xo_clk = 0 ;const struct sdhci_msm_offset *msm_offset =if (msm_host->use_14lpp_dll_reset && !IS_ERR_OR_NULL(msm_host->xo_clk))/* * Make sure that clock is always enabled when DLL * tuning is in progress . Keeping PWRSAVE ON may * turn off the clock . if (msm_host->dll_config)if (msm_host->use_14lpp_dll_reset) {if (!msm_host->dll_config)if (msm_host->use_14lpp_dll_reset &&0 ;if (config)8 ),else 4 ),0 xFF << 10 );10 ;/* wait for 5us before enabling DLL clock */ 5 );if (msm_host->use_14lpp_dll_reset) {if (!msm_host->dll_config)/* * Configure DLL user control register to enable DLL status . * This setting is applicable to SDCC v5 . 1 onwards only . if (msm_host->uses_tassadar_dll) {0 xFF;if (msm_host->clk_rate < 150000000 )else /* Wait until DLL_LOCK bit of DLL_STATUS register becomes '1' */ while (!(readl_relaxed(host->ioaddr + msm_offset->core_dll_status) &/* max. wait for 50us sec for LOCK bit to be set */ if (--wait_cnt == 0 ) {"%s: DLL failed to LOCK\n" ,return -ETIMEDOUT;1 );return 0 ;static void msm_hc_select_default(struct sdhci_host *host)struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);const struct sdhci_msm_offset *msm_offset =if (!msm_host->use_cdclp533) {/* * Disable HC_SELECT_IN to be able to use the UHS mode select * configuration from Host Control2 register for all other * modes . * Write 0 to HC_SELECT_IN and HC_SELECT_IN_EN field * in VENDOR_SPEC_FUNC /* * Make sure above writes impacting free running MCLK are completed * before changing the clk_rate at GCC . static void msm_hc_select_hs400(struct sdhci_host *host)struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);struct mmc_ios ios = host->mmc->ios;int rc;const struct sdhci_msm_offset *msm_offset =/* Select the divided clock (free running MCLK/2) */ /* * Select HS400 mode using the HC_SELECT_IN from VENDOR SPEC * register if ((msm_host->tuning_done || ios.enhanced_strobe) &&if (!msm_host->clk_rate && !msm_host->use_cdclp533) {/* * Poll on DLL_LOCK or DDR_DLL_LOCK bits in * core_dll_status to be set . This should get set * within 15 us at 200 MHz . 10 ,1000 );if (rc == -ETIMEDOUT)"%s: Unable to get DLL_LOCK/DDR_DLL_LOCK, dll_status: 0x%08x\n" ,/* * Make sure above writes impacting free running MCLK are completed * before changing the clk_rate at GCC . /* * sdhci_msm_hc_select_mode : - In general all timing modes are * controlled via UHS mode select in Host Control2 register . * eMMC specific HS200 / HS400 doesn ' t have their respective modes * defined here , hence we use these values . * * HS200 - SDR104 ( Since they both are equivalent in functionality ) * HS400 - This involves multiple configurations * Initially SDR104 - when tuning is required as HS200 * Then when switching to DDR @ 400 MHz ( HS400 ) we use * the vendor specific HC_SELECT_IN to control the mode . * * In addition to controlling the modes we also need to select the * correct input clock for DLL depending on the mode . * * HS400 - divided clock ( free running MCLK / 2 ) * All other modes - default ( free running MCLK ) static void sdhci_msm_hc_select_mode(struct sdhci_host *host)struct mmc_ios ios = host->mmc->ios;if (ios.timing == MMC_TIMING_MMC_HS400 ||else static int sdhci_msm_cdclp533_calibration(struct sdhci_host *host)struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);int ret;const struct sdhci_msm_offset *msm_offset ="%s: %s: Enter\n" , mmc_hostname(host->mmc), __func__);/* * Retuning in HS400 ( DDR mode ) will fail , just reset the * tuning block and restore the saved tuning phase . if (ret)goto out;/* Set the selected phase in delay line hw block */ if (ret)goto out;/* Perform CDC Register Initialization Sequence */ 0 x11800EC, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);0 x3011111, host->ioaddr + CORE_CSR_CDC_CTLR_CFG1);0 x1201000, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0);0 x4, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG1);0 xCB732020, host->ioaddr + CORE_CSR_CDC_REFCOUNT_CFG);0 xB19, host->ioaddr + CORE_CSR_CDC_COARSE_CAL_CFG);0 x4E2, host->ioaddr + CORE_CSR_CDC_DELAY_CFG);0 x0, host->ioaddr + CORE_CDC_OFFSET_CFG);0 x16334, host->ioaddr + CORE_CDC_SLAVE_DDA_CFG);/* CDC HW Calibration */ 1 , 50 );if (ret == -ETIMEDOUT) {"%s: %s: CDC calibration was not completed\n" ,goto out;if (ret) {"%s: %s: CDC error code %d\n" ,goto out;"%s: %s: Exit, ret %d\n" , mmc_hostname(host->mmc),return ret;static int sdhci_msm_cm_dll_sdc4_calibration(struct sdhci_host *host)struct mmc_host *mmc = host->mmc;int ret;struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);const struct sdhci_msm_offset *msm_offset ="%s: %s: Enter\n" , mmc_hostname(host->mmc), __func__);/* * Currently the core_ddr_config register defaults to desired * configuration on reset . Currently reprogramming the power on * reset ( POR ) value in case it might have been modified by * bootloaders . In the future , if this changes , then the desired * values will need to be programmed appropriately . if (msm_host->updated_ddr_cfg)else if (mmc->ios.enhanced_strobe) {10 , 1000 );if (ret == -ETIMEDOUT) {"%s: %s: CM_DLL_SDC4 calibration was not completed\n" ,goto out;/* * Set CORE_PWRSAVE_DLL bit in CORE_VENDOR_SPEC3 . * When MCLK is gated OFF , it is not gated for less than 0 . 5 us * and MCLK must be switched on for at - least 1 us before DATA * starts coming . Controllers with 14 lpp and later tech DLL cannot * guarantee above requirement . So PWRSAVE_DLL should not be * turned on for host controllers using this DLL . if (!msm_host->use_14lpp_dll_reset) {/* * Drain writebuffer to ensure above DLL calibration * and PWRSAVE DLL is enabled . "%s: %s: Exit, ret %d\n" , mmc_hostname(host->mmc),return ret;static int sdhci_msm_hs400_dll_calibration(struct sdhci_host *host)struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);struct mmc_host *mmc = host->mmc;int ret;const struct sdhci_msm_offset *msm_offset ="%s: %s: Enter\n" , mmc_hostname(host->mmc), __func__);/* * Retuning in HS400 ( DDR mode ) will fail , just reset the * tuning block and restore the saved tuning phase . if (ret)goto out;if (!mmc->ios.enhanced_strobe) {/* Set the selected phase in delay line hw block */ if (ret)goto out;if (msm_host->use_cdclp533)else "%s: %s: Exit, ret %d\n" , mmc_hostname(host->mmc),return ret;static bool sdhci_msm_is_tuning_needed(struct sdhci_host *host)struct mmc_ios *ios = &host->mmc->ios;if (ios->timing == MMC_TIMING_UHS_SDR50 &&return true ;/* * Tuning is required for SDR104 , HS200 and HS400 cards and * if clock frequency is greater than 100 MHz in these modes . if (host->clock <= CORE_FREQ_100MHZ ||return false ;return true ;static int sdhci_msm_restore_sdr_dll_config(struct sdhci_host *host)struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);int ret;/* * SDR DLL comes into picture only for timing modes which needs * tuning . if (!sdhci_msm_is_tuning_needed(host))return 0 ;/* Reset the tuning block */ if (ret)return ret;/* Restore the tuning block */ return ret;static void sdhci_msm_set_cdr(struct sdhci_host *host, bool enable)const struct sdhci_msm_offset *msm_offset = sdhci_priv_msm_offset(host);if (enable) {else {if (config != oldconfig) {static int sdhci_msm_execute_tuning(struct mmc_host *mmc, u32 opcode)struct sdhci_host *host = mmc_priv(mmc);int tuning_seq_cnt = 10 ;16 ], tuned_phase_cnt = 0 ;int rc;struct mmc_ios ios = host->mmc->ios;struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);const struct sdhci_msm_offset *msm_offset = msm_host->offset;if (!sdhci_msm_is_tuning_needed(host)) {false ;false );return 0 ;/* Clock-Data-Recovery used to dynamically adjust RX sampling point */ true ;/* * Clear tuning_done flag before tuning to ensure proper * HS400 settings . 0 ;if (ios.timing == MMC_TIMING_UHS_SDR50 &&/* * For HS400 tuning in HS200 timing requires : * - select MCLK / 2 in VENDOR_SPEC * - program MCLK to 400 MHz ( or nearest supported ) in GCC if (host->flags & SDHCI_HS400_TUNING) {/* First of all reset the tuning block */ if (rc)return rc;0 ;do {/* Set the phase in delay line hw block */ if (rc)return rc;if (!rc) {/* Tuning is successful at this tuning point */ "%s: Found good phase = %d\n" ,while (++phase < ARRAY_SIZE(tuned_phases));if (tuned_phase_cnt) {if (tuned_phase_cnt == ARRAY_SIZE(tuned_phases)) {/* * All phases valid is _ almost_ as bad as no phases * valid . Probably all phases are not really reliable * but we didn ' t detect where the unreliable place is . * That means we ' ll essentially be guessing and hoping * we get a good phase . Better to try a few times . "%s: All phases valid; try again\n" ,if (--tuning_seq_cnt) {0 ;goto retry;if (rc < 0 )return rc;else /* * Finally set the selected phase in delay * line hw block . if (rc)return rc;"%s: Setting the tuning phase to %d\n" ,else {if (--tuning_seq_cnt)goto retry;/* Tuning failed */ "%s: No tuning point found\n" ,if (!rc)true ;return rc;/* * sdhci_msm_hs400 - Calibrate the DLL for HS400 bus speed mode operation . * This needs to be done for both tuning and enhanced_strobe mode . * DLL operation is only needed for clock > 100 MHz . For clock < = 100 MHz * fixed feedback clock is used . static void sdhci_msm_hs400(struct sdhci_host *host, struct mmc_ios *ios)struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);int ret;if (host->clock > CORE_FREQ_100MHZ &&if (!ret)true ;else "%s: Failed to calibrate DLL for hs400 mode (%d)\n" ,static void sdhci_msm_set_uhs_signaling(struct sdhci_host *host,unsigned int uhs)struct mmc_host *mmc = host->mmc;struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);const struct sdhci_msm_offset *msm_offset =/* Select Bus Speed Mode for host */ switch (uhs) {case MMC_TIMING_UHS_SDR12:break ;case MMC_TIMING_UHS_SDR25:break ;case MMC_TIMING_UHS_SDR50:break ;case MMC_TIMING_MMC_HS400:case MMC_TIMING_MMC_HS200:case MMC_TIMING_UHS_SDR104:break ;case MMC_TIMING_UHS_DDR50:case MMC_TIMING_MMC_DDR52:break ;/* * When clock frequency is less than 100 MHz , the feedback clock must be * provided and DLL must not be used so that tuning can be skipped . To * provide feedback clock , the mode selection can be any value less * than 3 ' b011 in bits [ 2 : 0 ] of HOST CONTROL2 register . if (host->clock <= CORE_FREQ_100MHZ) {if (uhs == MMC_TIMING_MMC_HS400 ||/* * DLL is not required for clock < = 100 MHz * Thus , make sure DLL it is disabled when not required /* * The DLL needs to be restored and CDCLP533 recalibrated * when the clock frequency is set back to 400 MHz . false ;"%s: clock=%u uhs=%u ctrl_2=0x%x\n" ,if (mmc->ios.timing == MMC_TIMING_MMC_HS400)static int sdhci_msm_set_pincfg(struct sdhci_msm_host *msm_host, bool level)struct platform_device *pdev = msm_host->pdev;int ret;if (level)else return ret;static void msm_config_vmmc_regulator(struct mmc_host *mmc, bool hpm)int load;if (!hpm)0 ;else if (!mmc->card)else if (mmc_card_mmc(mmc->card))else if (mmc_card_sd(mmc->card))else return ;static void msm_config_vqmmc_regulator(struct mmc_host *mmc, bool hpm)int load;if (!hpm)0 ;else if (!mmc->card)else if (mmc_card_sd(mmc->card))else return ;static int sdhci_msm_set_vmmc(struct sdhci_msm_host *msm_host,struct mmc_host *mmc, bool hpm)if (IS_ERR(mmc->supply.vmmc))return 0 ;return mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, mmc->ios.vdd);static int msm_toggle_vqmmc(struct sdhci_msm_host *msm_host,struct mmc_host *mmc, bool level)int ret;struct mmc_ios ios;if (msm_host->vqmmc_enabled == level)return 0 ;if (level) {/* Set the IO voltage regulator to default voltage level */ if (msm_host->caps_0 & CORE_3_0V_SUPPORT)else if (msm_host->caps_0 & CORE_1_8V_SUPPORT)if (msm_host->caps_0 & CORE_VOLT_SUPPORT) {if (ret < 0 ) {"%s: vqmmc set volgate failed: %d\n" ,goto out;else {if (ret)"%s: vqmm %sable failed: %d\n" ,"en" :"dis" , ret);else return ret;static int msm_config_vqmmc_mode(struct sdhci_msm_host *msm_host,struct mmc_host *mmc, bool hpm)int load, ret;0 ;if (ret)"%s: vqmmc set load failed: %d\n" ,return ret;static int sdhci_msm_set_vqmmc(struct sdhci_msm_host *msm_host,struct mmc_host *mmc, bool level)int ret;bool always_on;if (IS_ERR(mmc->supply.vqmmc) ||return 0 ;/* * For eMMC don ' t turn off Vqmmc , Instead just configure it in LPM * and HPM modes by setting the corresponding load . * * Till eMMC is initialized ( i . e . always_on = = 0 ) , just turn on / off * Vqmmc . Vqmmc gets turned off only if init fails and mmc_power_off * gets invoked . Once eMMC is initialized ( i . e . always_on = = 1 ) , * Vqmmc should remain ON , So just set the load instead of turning it * off / on . if (always_on)else return ret;static inline void sdhci_msm_init_pwr_irq_wait(struct sdhci_msm_host *msm_host)static inline void sdhci_msm_complete_pwr_irq_wait(struct sdhci_msm_host *msm_host)/* * sdhci_msm_check_power_status API should be called when registers writes * which can toggle sdhci IO bus ON / OFF or change IO lines HIGH / LOW happens . * To what state the register writes will change the IO lines should be passed * as the argument req_type . This API will check whether the IO line ' s state * is already the expected state and will wait for power irq only if * power irq is expected to be triggered based on the current IO line state * and expected IO line state . static void sdhci_msm_check_power_status(struct sdhci_host *host, u32 req_type)struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);struct mmc_host *mmc = host->mmc;bool done = false ;const struct sdhci_msm_offset *msm_offset ="%s: %s: request %d curr_pwr_state %x curr_io_level %x\n" ,/* * The power interrupt will not be generated for signal voltage * switches if SWITCHABLE_SIGNALING_VOLTAGE in MCI_GENERICS is not set . * Since sdhci - msm - v5 , this bit has been removed and SW must consider * it as always set . if (!msm_host->mci_removed)if ((req_type & REQ_IO_HIGH || req_type & REQ_IO_LOW) &&return ;/* * The IRQ for request type IO High / LOW will be generated when - * there is a state change in 1 . 8 V enable bit ( bit 3 ) of * SDHCI_HOST_CONTROL2 register . The reset state of that bit is 0 * which indicates 3 . 3 V IO voltage . So , when MMC core layer tries * to set it to 3 . 3 V before card detection happens , the * IRQ doesn ' t get triggered as there is no state change in this bit . * The driver already handles this case by changing the IO voltage * level to high as part of controller power up sequence . Hence , check * for host - > pwr to handle a case where IO voltage high request is * issued even before controller power up . if ((req_type & REQ_IO_HIGH) && !host->pwr) {"%s: do not wait for power IRQ that never comes, req_type: %d\n" ,return ;if ((req_type & msm_host->curr_pwr_state) ||true ;/* * This is needed here to handle cases where register writes will * not change the current bus state or io level of the controller . * In this case , no power irq will be triggerred and we should * not wait . if (!done) {if (!wait_event_timeout(msm_host->pwr_irq_wait,"%s: pwr_irq for req: (%d) timed out\n" ,if ((req_type & REQ_BUS_ON) && mmc->card && !mmc->ops->get_cd(mmc)) {0 , SDHCI_POWER_CONTROL);0 ;"%s: %s: request %d done\n" , mmc_hostname(host->mmc),static void sdhci_msm_dump_pwr_ctrl_regs(struct sdhci_host *host)struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);const struct sdhci_msm_offset *msm_offset ="%s: PWRCTL_STATUS: 0x%08x | PWRCTL_MASK: 0x%08x | PWRCTL_CTL: 0x%08x\n" ,static void sdhci_msm_handle_pwr_irq(struct sdhci_host *host, int irq)struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);struct mmc_host *mmc = host->mmc;0 ;int retry = 10 , ret;0 , io_level = 0 ;const struct sdhci_msm_offset *msm_offset = msm_host->offset;/* * There is a rare HW scenario where the first clear pulse could be * lost when actual reset and clear / read of status register is * happening at a time . Hence , retry for at least 10 times to make * sure status register is cleared . Otherwise , this will result in * a spurious power IRQ resulting in system instability . while (irq_status & msm_host_readl(msm_host, host,if (retry == 0 ) {"%s: Timedout clearing (0x%x) pwrctl status register\n" ,1 );break ;10 );if ((irq_status & CORE_PWRCTL_BUS_ON) && mmc->card &&return ;/* Handle BUS ON/OFF*/ if (irq_status & CORE_PWRCTL_BUS_ON) {if (irq_status & CORE_PWRCTL_BUS_OFF) {if (pwr_state) {if (!ret)if (!ret)if (!ret)else /* Handle IO LOW/HIGH */ if (irq_status & CORE_PWRCTL_IO_LOW)if (irq_status & CORE_PWRCTL_IO_HIGH)if (io_level)if (io_level && !IS_ERR(mmc->supply.vqmmc) && !pwr_state) {if (ret < 0 ) {"%s: IO_level setting failed(%d). signal_voltage: %d, vdd: %d irq_status: 0x%08x\n" ,/* * The driver has to acknowledge the interrupt , switch voltages and * report back if it succeded or not to this register . The voltage * switches are handled by the sdhci core , so just report success . /* * If we don ' t have info regarding the voltage levels supported by * regulators , don ' t change the IO PAD PWR SWITCH . if (msm_host->caps_0 & CORE_VOLT_SUPPORT) {/* * We should unset IO PAD PWR switch only if the register write * can set IO lines high and the regulator also switches to 3 V . * Else , we should keep the IO PAD PWR switch set . * This is applicable to certain targets where eMMC vccq supply * is only 1 . 8 V . In such targets , even during REQ_IO_HIGH , the * IO PAD PWR switch must be kept set to reflect actual * regulator voltage . This way , during initialization of * controllers with only 1 . 8 V , we will set the IO PAD bit * without waiting for a REQ_IO_LOW . if ((io_level & REQ_IO_HIGH) &&else if ((io_level & REQ_IO_LOW) ||if (config ^ new_config)if (pwr_state)if (io_level)"%s: %s: Handled IRQ(%d), irq_status=0x%x, ack=0x%x\n" ,static irqreturn_t sdhci_msm_pwr_irq(int irq, void *data)struct sdhci_host *host = (struct sdhci_host *)data;struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);1 ;return IRQ_HANDLED;static unsigned int sdhci_msm_get_max_clock(struct sdhci_host *host)struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);struct clk *core_clk = msm_host->bulk_clks[0 ].clk;return clk_round_rate(core_clk, ULONG_MAX);static unsigned int sdhci_msm_get_min_clock(struct sdhci_host *host)return SDHCI_MSM_MIN_CLOCK;/* * _ _ sdhci_msm_set_clock - sdhci_msm clock control . * * Description : * MSM controller does not use internal divider and * instead directly control the GCC clock as per * HW recommendation . static void __sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)0 , SDHCI_CLOCK_CONTROL);if (clock == 0 )return ;/* * MSM controller do not use clock divider . * Thus read SDHCI_CLOCK_CONTROL and only enable * clock with no divider value programmed . /* sdhci_msm_set_clock - Called with (host->lock) spinlock held. */ static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);if (!clock) {0 ;goto out;/*****************************************************************************\ * * * Inline Crypto Engine ( ICE ) support * * * #ifdef CONFIG_MMC_CRYPTOstatic const struct blk_crypto_ll_ops sdhci_msm_crypto_ops; /* forward decl */ static int sdhci_msm_ice_init(struct sdhci_msm_host *msm_host,struct cqhci_host *cq_host)struct mmc_host *mmc = msm_host->mmc;struct blk_crypto_profile *profile = &mmc->crypto_profile;struct device *dev = mmc_dev(mmc);struct qcom_ice *ice;union cqhci_crypto_capabilities caps;union cqhci_crypto_cap_entry cap;int err;int i;if (!(cqhci_readl(cq_host, CQHCI_CAP) & CQHCI_CAP_CS))return 0 ;if (ice == ERR_PTR(-EOPNOTSUPP)) {"Disabling inline encryption support\n" );if (IS_ERR_OR_NULL(ice))return PTR_ERR_OR_ZERO(ice);if (qcom_ice_get_supported_key_type(ice) != BLK_CRYPTO_KEY_TYPE_RAW) {"Wrapped keys not supported. Disabling inline encryption support.\n" );return 0 ;/* Initialize the blk_crypto_profile */ /* The number of keyslots supported is (CFGC+1) */ 1 );if (err)return err;4 ;/* * Currently this driver only supports AES - 256 - XTS . All known versions * of ICE support it , but to be safe make sure it is really declared in * the crypto capability registers . The crypto capability registers * also give the supported data unit size ( s ) . for (i = 0 ; i < caps.num_crypto_cap; i++) {sizeof (__le32)));if (cap.algorithm_id == CQHCI_CRYPTO_ALG_AES_XTS &&512 ;return 0 ;static void sdhci_msm_ice_enable(struct sdhci_msm_host *msm_host)if (msm_host->mmc->caps2 & MMC_CAP2_CRYPTO)static __maybe_unused int sdhci_msm_ice_resume(struct sdhci_msm_host *msm_host)if (msm_host->mmc->caps2 & MMC_CAP2_CRYPTO)return qcom_ice_resume(msm_host->ice);return 0 ;static __maybe_unused int sdhci_msm_ice_suspend(struct sdhci_msm_host *msm_host)if (msm_host->mmc->caps2 & MMC_CAP2_CRYPTO)return qcom_ice_suspend(msm_host->ice);return 0 ;static inline struct sdhci_msm_host *struct blk_crypto_profile *profile)struct mmc_host *mmc = mmc_from_crypto_profile(profile);struct sdhci_host *host = mmc_priv(mmc);struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);return msm_host;/* * Program a key into a QC ICE keyslot . QC ICE requires a QC - specific SCM call * for this ; it doesn ' t support the standard way . static int sdhci_msm_ice_keyslot_program(struct blk_crypto_profile *profile,const struct blk_crypto_key *key,unsigned int slot)struct sdhci_msm_host *msm_host =return qcom_ice_program_key(msm_host->ice, slot, key);static int sdhci_msm_ice_keyslot_evict(struct blk_crypto_profile *profile,const struct blk_crypto_key *key,unsigned int slot)struct sdhci_msm_host *msm_host =return qcom_ice_evict_key(msm_host->ice, slot);static const struct blk_crypto_ll_ops sdhci_msm_crypto_ops = {#else /* CONFIG_MMC_CRYPTO */ static inline int sdhci_msm_ice_init(struct sdhci_msm_host *msm_host,struct cqhci_host *cq_host)return 0 ;static inline void sdhci_msm_ice_enable(struct sdhci_msm_host *msm_host)static inline __maybe_unused int struct sdhci_msm_host *msm_host)return 0 ;static inline __maybe_unused int struct sdhci_msm_host *msm_host)return 0 ;#endif /* !CONFIG_MMC_CRYPTO */ /*****************************************************************************\ * * * MSM Command Queue Engine ( CQE ) * * * static u32 sdhci_msm_cqe_irq(struct sdhci_host *host, u32 intmask)int cmd_error = 0 ;int data_error = 0 ;if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))return intmask;return 0 ;static void sdhci_msm_cqe_enable(struct mmc_host *mmc)struct sdhci_host *host = mmc_priv(mmc);struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);static void sdhci_msm_cqe_disable(struct mmc_host *mmc, bool recovery)struct sdhci_host *host = mmc_priv(mmc);unsigned long flags;/* * When CQE is halted , the legacy SDHCI path operates only * on 16 - byte descriptors in 64 bit mode . if (host->flags & SDHCI_USE_64_BIT_DMA)16 ;/* * During CQE command transfers , command complete bit gets latched . * So s / w should clear command complete interrupt status when CQE is * either halted or disabled . Otherwise unexpected SDCHI legacy * interrupt gets triggered when CQE is halted / disabled . static void sdhci_msm_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)15 ;/* * Update software timeout value if its value is less than hardware data * timeout value . Qcom SoC hardware data timeout value was calculated * using 4 * MCLK * 2 ^ ( count + 13 ) . where MCLK = 1 / host - > clock . if (cmd && cmd->data && host->clock > 400000 &&50000000 &&1 << (count + start)) > (10 * host->clock)))22 LL * NSEC_PER_SEC;static const struct cqhci_host_ops sdhci_msm_cqhci_ops = {#ifdef CONFIG_MMC_CRYPTOtrue ,#endif static int sdhci_msm_cqe_add_host(struct sdhci_host *host,struct platform_device *pdev)struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);struct cqhci_host *cq_host;bool dma64;int ret;/* * When CQE is halted , SDHC operates only on 16 byte ADMA descriptors . * So ensure ADMA table is allocated for 16 byte descriptors . if (host->caps & SDHCI_CAN_64BIT)16 ;if (ret)return ret;if (IS_ERR(cq_host)) {"cqhci-pltfm init: failed: %d\n" , ret);goto cleanup;if (ret)goto cleanup;if (ret) {"%s: CQE init: failed (%d)\n" ,goto cleanup;/* Disable cqe reset due to cqe enable signal */ /* * SDHC expects 12 byte ADMA descriptors till CQE is enabled . * So limit desc_sz to 12 so that the data commands that are sent * during card initialization ( before CQE gets enabled ) would * get executed without any issues . if (host->flags & SDHCI_USE_64_BIT_DMA)12 ;if (ret)goto cleanup;"%s: CQE init: success\n" ,return ret;return ret;/* * Platform specific register write functions . This is so that , if any * register write needs to be followed up by platform specific actions , * they can be added here . These functions can go to sleep when writes * to certain registers are done . * These functions are relying on sdhci_set_ios not using spinlock . static int __sdhci_msm_check_write(struct sdhci_host *host, u16 val, int reg)struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);0 ;switch (reg) {case SDHCI_HOST_CONTROL2:break ;case SDHCI_SOFTWARE_RESET:if (host->pwr && (val & SDHCI_RESET_ALL))break ;case SDHCI_POWER_CONTROL:break ;case SDHCI_TRANSFER_MODE:break ;case SDHCI_COMMAND:if (!msm_host->use_cdr)break ;if ((msm_host->transfer_mode & SDHCI_TRNS_READ) &&true );else false );break ;if (req_type) {0 ;/* * Since this register write may trigger a power irq , ensure * all previous register writes are complete by this point . return req_type;/* This function may sleep*/ static void sdhci_msm_writew(struct sdhci_host *host, u16 val, int reg)0 ;if (req_type)/* This function may sleep*/ static void sdhci_msm_writeb(struct sdhci_host *host, u8 val, int reg)0 ;if (req_type)static void sdhci_msm_set_regulator_caps(struct sdhci_msm_host *msm_host)struct mmc_host *mmc = msm_host->mmc;struct regulator *supply = mmc->supply.vqmmc;0 , config;struct sdhci_host *host = mmc_priv(mmc);const struct sdhci_msm_offset *msm_offset = msm_host->offset;if (!IS_ERR(mmc->supply.vqmmc)) {if (regulator_is_supported_voltage(supply, 1700000 , 1950000 ))if (regulator_is_supported_voltage(supply, 2700000 , 3600000 ))if (!caps)"%s: 1.8/3V not supported for vqmmc\n" ,if (caps) {/* * Set the PAD_PWR_SWITCH_EN bit so that the PAD_PWR_SWITCH * bit can be used as required later on . if ((io_level & REQ_IO_HIGH) && (caps & CORE_3_0V_SUPPORT))else if ((io_level & REQ_IO_LOW) || (caps & CORE_1_8V_SUPPORT))"%s: supported caps: 0x%08x\n" , mmc_hostname(mmc), caps);static int sdhci_msm_register_vreg(struct sdhci_msm_host *msm_host)int ret;if (ret)return ret;return 0 ;static int sdhci_msm_start_signal_voltage_switch(struct mmc_host *mmc,struct mmc_ios *ios)struct sdhci_host *host = mmc_priv(mmc);/* * Signal Voltage Switching is only applicable for Host Controllers * v3 . 00 and above . if (host->version < SDHCI_SPEC_300)return 0 ;switch (ios->signal_voltage) {case MMC_SIGNAL_VOLTAGE_330:if (!(host->flags & SDHCI_SIGNALING_330))return -EINVAL;/* Set 1.8V Signal Enable in the Host Control2 register to 0 */ break ;case MMC_SIGNAL_VOLTAGE_180:if (!(host->flags & SDHCI_SIGNALING_180))return -EINVAL;/* Enable 1.8V Signal Enable in the Host Control2 register */ break ;default :return -EINVAL;/* Wait for 5ms */ 5000 , 5500 );/* regulator output should be stable within 5 ms */ if ((ctrl & SDHCI_CTRL_VDD_180) == status)return 0 ;"%s: Regulator output did not became stable\n" ,return -EAGAIN;#define DRIVER_NAME "sdhci_msm" #define SDHCI_MSM_DUMP(f, x...) \"%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)static void sdhci_msm_dump_vendor_regs(struct sdhci_host *host)struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);const struct sdhci_msm_offset *msm_offset = msm_host->offset;"----------- VENDOR REGISTER DUMP -----------\n" );"DLL sts: 0x%08x | DLL cfg: 0x%08x | DLL cfg2: 0x%08x\n" ,"DLL cfg3: 0x%08x | DLL usr ctl: 0x%08x | DDR cfg: 0x%08x\n" ,"Vndr func: 0x%08x | Vndr func2 : 0x%08x Vndr func3: 0x%08x\n" ,static const struct sdhci_msm_variant_ops mci_var_ops = {static const struct sdhci_msm_variant_ops v5_var_ops = {static const struct sdhci_msm_variant_info sdhci_msm_mci_var = {static const struct sdhci_msm_variant_info sdhci_msm_v5_var = {true ,static const struct sdhci_msm_variant_info sdm845_sdhci_var = {true ,true ,static const struct of_device_id sdhci_msm_dt_match[] = {/* * Do not add new variants to the driver which are compatible with * generic ones , unless they need customization . "qcom,sdhci-msm-v4" , .data = &sdhci_msm_mci_var},"qcom,sdhci-msm-v5" , .data = &sdhci_msm_v5_var},"qcom,sdm670-sdhci" , .data = &sdm845_sdhci_var},"qcom,sdm845-sdhci" , .data = &sdm845_sdhci_var},"qcom,sc7180-sdhci" , .data = &sdm845_sdhci_var},static const struct sdhci_ops sdhci_msm_ops = {static const struct sdhci_pltfm_data sdhci_msm_pdata = {static inline void sdhci_msm_get_of_property(struct platform_device *pdev,struct sdhci_host *host)struct device_node *node = pdev->dev.of_node;struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);if (of_property_read_u32(node, "qcom,ddr-config" ,"qcom,dll-config" , &msm_host->dll_config);if (of_device_is_compatible(node, "qcom,msm8916-sdhci" ))static int sdhci_msm_gcc_reset(struct device *dev, struct sdhci_host *host)struct reset_control *reset;int ret = 0 ;if (IS_ERR(reset))return dev_err_probe(dev, PTR_ERR(reset),"unable to acquire core_reset\n" );if (!reset)return ret;if (ret) {return dev_err_probe(dev, ret, "core_reset assert failed\n" );/* * The hardware requirement for delay between assert / deassert * is at least 3 - 4 sleep clock ( 32 . 7 KHz ) cycles , which comes to * ~ 125 us ( 4 / 32768 ) . To be on the safe side add 200 us delay . 200 , 210 );if (ret) {return dev_err_probe(dev, ret, "core_reset deassert failed\n" );200 , 210 );return ret;static int sdhci_msm_probe(struct platform_device *pdev)struct sdhci_host *host;struct sdhci_pltfm_host *pltfm_host;struct sdhci_msm_host *msm_host;struct clk *clk;int ret;const struct sdhci_msm_offset *msm_offset;const struct sdhci_msm_variant_info *var_info;struct device_node *node = pdev->dev.of_node;sizeof (*msm_host));if (IS_ERR(host))return PTR_ERR(host);0 ;if (ret)return ret;/* * Based on the compatible string , load the required msm host info from * the data associated with the version info . if (ret)return ret;/* Setup SDCC bus voter clock. */ "bus" );if (!IS_ERR(msm_host->bus_clk)) {/* Vote for max. clk rate for max. performance */ if (ret)return ret;if (ret)return ret;/* Setup main peripheral bus clock */ "iface" );if (IS_ERR(clk)) {"Peripheral clk setup failed (%d)\n" , ret);goto bus_clk_disable;1 ].clk = clk;/* Setup SDC MMC clock */ "core" );if (IS_ERR(clk)) {"SDC MMC clk setup failed (%d)\n" , ret);goto bus_clk_disable;0 ].clk = clk;/* Check for optional interconnect paths */ if (ret)goto bus_clk_disable;"core" );if (ret)goto bus_clk_disable;/* OPP table is optional */ if (ret && ret != -ENODEV) {"Invalid OPP table in Device tree\n" );goto bus_clk_disable;/* Vote for maximum clock rate for maximum performance */ if (ret)"core clock boost failed\n" );"cal" );if (IS_ERR(clk))2 ].clk = clk;"sleep" );if (IS_ERR(clk))3 ].clk = clk;if (ret)goto bus_clk_disable;/* * xo clock is needed for FLL feature of cm_dll . * In case if xo clock is not mentioned in DT , warn and proceed . "xo" );if (IS_ERR(msm_host->xo_clk)) {"TCXO clk not present (%d)\n" , ret);if (!msm_host->mci_removed) {1 );if (IS_ERR(msm_host->core_mem)) {goto clk_disable;/* Reset the vendor spec register to power on reset state */ if (!msm_host->mci_removed) {/* Set HC_MODE_EN bit in HC_MODE register */ "Host Version: 0x%x Vendor Version 0x%x\n" ,"MCI Version: 0x%08x, major: 0x%04x, minor: 0x%02x\n" ,if (core_major == 1 && core_minor >= 0 x42)true ;/* * SDCC 5 controller with major version 1 , minor version 0 x34 and later * with HS 400 mode support will use CM DLL instead of CDC LP 533 DLL . if (core_major == 1 && core_minor < 0 x34)true ;/* * Support for some capabilities is not advertised by newer * controller versions and must be explicitly enabled . if (core_major >= 1 && core_minor != 0 x11 && core_minor != 0 x12) {if (core_major == 1 && core_minor >= 0 x49)true ;if (core_major == 1 && core_minor >= 0 x71)true ;if (ret)goto clk_disable;/* * Power on reset state may trigger power irq if previous status of * PWRCTL was either BUS_ON or IO_HIGH_V . So before enabling pwr irq * interrupt in GIC , any pending power irq interrupt should be * acknowledged . Otherwise power irq interrupt handler would be * fired prematurely . 0 );/* * Ensure that above writes are propagated before interrupt enablement * in GIC . /* Setup IRQ for handling power/voltage tasks with PMIC */ "pwr_irq" );if (msm_host->pwr_irq < 0 ) {goto clk_disable;/* Enable pwr irq interrupts */ if (ret) {"Request IRQ failed (%d)\n" , ret);goto clk_disable;/* Set the timeout value to max possible */ 0 xF;if (of_property_read_bool(node, "supports-cqe" ))else if (ret)goto pm_runtime_disable;return 0 ;if (!IS_ERR(msm_host->bus_clk))return ret;static void sdhci_msm_remove(struct platform_device *pdev)struct sdhci_host *host = platform_get_drvdata(pdev);struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);int dead = (readl_relaxed(host->ioaddr + SDHCI_INT_STATUS) ==0 xffffffff);if (!IS_ERR(msm_host->bus_clk))static __maybe_unused int sdhci_msm_runtime_suspend(struct device *dev)struct sdhci_host *host = dev_get_drvdata(dev);struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);unsigned long flags;true ;/* Drop the performance vote */ 0 );return sdhci_msm_ice_suspend(msm_host);static __maybe_unused int sdhci_msm_runtime_resume(struct device *dev)struct sdhci_host *host = dev_get_drvdata(dev);struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);unsigned long flags;int ret;if (ret)return ret;/* * Whenever core - clock is gated dynamically , it ' s needed to * restore the SDR DLL settings when the clock is ungated . if (msm_host->restore_dll_config && msm_host->clk_rate) {if (ret)return ret;if (ret)return ret;false ;return ret;static const struct dev_pm_ops sdhci_msm_pm_ops = {static struct platform_driver sdhci_msm_driver = {"sdhci_msm" ,"Qualcomm Secure Digital Host Controller Interface driver" );"GPL v2" );
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(vorverarbeitet am 2026-09-28)
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2026-10-10
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