// SPDX-License-Identifier: GPL-2.0-only /* * lpc_ich . c - LPC interface for Intel ICH * * LPC bridge function of the Intel ICH contains many other * functional units , such as Interrupt controllers , Timers , * Power Management , System Management , GPIO , RTC , and LPC * Configuration Registers . * * This driver is derived from lpc_sch . * * Copyright ( c ) 2017 , 2021 - 2022 Intel Corporation * Copyright ( c ) 2011 Extreme Engineering Solution , Inc . * Author : Aaron Sierra < asierra @ xes - inc . com > * * This driver supports the following I / O Controller hubs : * ( See the intel documentation on http : //developer.intel.com.) * document number 290655 - 003 , 290677 - 014 : 82801 AA ( ICH ) , 82801 AB ( ICHO ) * document number 290687 - 002 , 298242 - 027 : 82801 BA ( ICH2 ) * document number 290733 - 003 , 290739 - 013 : 82801 CA ( ICH3 - S ) * document number 290716 - 001 , 290718 - 007 : 82801 CAM ( ICH3 - M ) * document number 290744 - 001 , 290745 - 025 : 82801 DB ( ICH4 ) * document number 252337 - 001 , 252663 - 008 : 82801 DBM ( ICH4 - M ) * document number 273599 - 001 , 273645 - 002 : 82801 E ( C - ICH ) * document number 252516 - 001 , 252517 - 028 : 82801 EB ( ICH5 ) , 82801 ER ( ICH5R ) * document number 300641 - 004 , 300884 - 013 : 6300 ESB * document number 301473 - 002 , 301474 - 026 : 82801 F ( ICH6 ) * document number 313082 - 001 , 313075 - 006 : 631 xESB , 632 xESB * document number 307013 - 003 , 307014 - 024 : 82801 G ( ICH7 ) * document number 322896 - 001 , 322897 - 001 : NM10 * document number 313056 - 003 , 313057 - 017 : 82801 H ( ICH8 ) * document number 316972 - 004 , 316973 - 012 : 82801 I ( ICH9 ) * document number 319973 - 002 , 319974 - 002 : 82801 J ( ICH10 ) * document number 322169 - 001 , 322170 - 003 : 5 Series , 3400 Series ( PCH ) * document number 320066 - 003 , 320257 - 008 : EP80597 ( IICH ) * document number 324645 - 001 , 324646 - 001 : Cougar Point ( CPT ) #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt#include <linux/align.h>#include <linux/kernel.h>#include <linux/module.h>#include <linux/errno.h>#include <linux/acpi.h>#include <linux/pci.h>#include <linux/pinctrl/pinctrl.h>#include <linux/mfd/core.h>#include <linux/mfd/lpc_ich.h>#include <linux/platform_data/itco_wdt.h>#include <linux/platform_data/x86/p2sb.h>#define ACPIBASE 0 x40#define ACPIBASE_GPE_OFF 0 x28#define ACPIBASE_GPE_END 0 x2f#define ACPIBASE_SMI_OFF 0 x30#define ACPIBASE_SMI_END 0 x33#define ACPIBASE_PMC_OFF 0 x08#define ACPIBASE_PMC_END 0 x0c#define ACPIBASE_TCO_OFF 0 x60#define ACPIBASE_TCO_END 0 x7f#define ACPICTRL_PMCBASE 0 x44#define ACPIBASE_GCS_OFF 0 x3410#define ACPIBASE_GCS_END 0 x3414#define SPIBASE_BYT 0 x54#define SPIBASE_BYT_SZ 512 #define SPIBASE_BYT_EN BIT(1 )#define BYT_BCR 0 xfc#define BYT_BCR_WPD BIT(0 )#define SPIBASE_LPT 0 x3800#define SPIBASE_LPT_SZ 512 #define BCR 0 xdc#define BCR_WPD BIT(0 )#define GPIOBASE_ICH0 0 x58#define GPIOCTRL_ICH0 0 x5C#define GPIOBASE_ICH6 0 x48#define GPIOCTRL_ICH6 0 x4C#define RCBABASE 0 xf0#define wdt_io_res(i) wdt_res(0 , i)#define wdt_mem_res(i) wdt_res(ICH_RES_MEM_OFF, i)#define wdt_res(b, i) (&wdt_ich_res[(b) + (i)])static struct resource wdt_ich_res[] = {/* ACPI - TCO */ /* ACPI - SMI */ /* GCS or PMC */ static struct resource gpio_ich_res[] = {/* GPIO */ /* ACPI - GPE0 */ static struct resource intel_spi_res[] = {static struct mfd_cell lpc_ich_wdt_cell = {"iTCO_wdt" ,true ,static struct mfd_cell lpc_ich_gpio_cell = {"gpio_ich" ,true ,#define INTEL_GPIO_RESOURCE_SIZE 0 x1000struct lpc_ich_gpio_info {const char *hid;const struct mfd_cell *devices;struct resource **resources;const resource_size_t *offsets;#define APL_GPIO_NORTH 0 #define APL_GPIO_NORTHWEST 1 #define APL_GPIO_WEST 2 #define APL_GPIO_SOUTHWEST 3 #define APL_GPIO_NR_DEVICES 4 #define APL_GPIO_NR_RESOURCES 4 /* Offset data for Apollo Lake GPIO controllers */ static const resource_size_t apl_gpio_offsets[APL_GPIO_NR_RESOURCES] = {0 xc50000,0 xc40000,0 xc70000,0 xc00000,#define APL_GPIO_IRQ 14 static struct resource apl_gpio_resources[APL_GPIO_NR_DEVICES][2 ] = {0 , 0 ),0 , 0 ),0 , 0 ),0 , 0 ),static struct resource *apl_gpio_mem_resources[APL_GPIO_NR_RESOURCES] = {0 ],0 ],0 ],0 ],static const struct mfd_cell apl_gpio_devices[APL_GPIO_NR_DEVICES] = {"apollolake-pinctrl" ,true ,"apollolake-pinctrl" ,true ,"apollolake-pinctrl" ,true ,"apollolake-pinctrl" ,true ,static const struct lpc_ich_gpio_info apl_gpio_info = {"INT3452" ,#define DNV_GPIO_NORTH 0 #define DNV_GPIO_SOUTH 1 #define DNV_GPIO_NR_DEVICES 1 #define DNV_GPIO_NR_RESOURCES 2 /* Offset data for Denverton GPIO controllers */ static const resource_size_t dnv_gpio_offsets[DNV_GPIO_NR_RESOURCES] = {0 xc20000,0 xc50000,#define DNV_GPIO_IRQ 14 static struct resource dnv_gpio_resources[DNV_GPIO_NR_RESOURCES + 1 ] = {0 , 0 ),0 , 0 ),static struct resource *dnv_gpio_mem_resources[DNV_GPIO_NR_RESOURCES] = {static const struct mfd_cell dnv_gpio_devices[DNV_GPIO_NR_DEVICES] = {"denverton-pinctrl" ,true ,static const struct lpc_ich_gpio_info dnv_gpio_info = {"INTC3000" ,static struct mfd_cell lpc_ich_spi_cell = {"intel-spi" ,true ,/* chipset related info */ enum lpc_chipsets {0 , /* ICH */ /* ICH0 */ /* ICH2 */ /* ICH2-M */ /* ICH3-S */ /* ICH3-M */ /* ICH4 */ /* ICH4-M */ /* C-ICH */ /* ICH5 & ICH5R */ /* 6300ESB */ /* ICH6 & ICH6R */ /* ICH6-M */ /* ICH6W & ICH6RW */ /* 631xESB/632xESB */ /* ICH7 & ICH7R */ /* ICH7DH */ /* ICH7-M & ICH7-U */ /* ICH7-M DH */ /* NM10 */ /* ICH8 & ICH8R */ /* ICH8DH */ /* ICH8DO */ /* ICH8M */ /* ICH8M-E */ /* ICH9 */ /* ICH9R */ /* ICH9DH */ /* ICH9DO */ /* ICH9M */ /* ICH9M-E */ /* ICH10 */ /* ICH10R */ /* ICH10D */ /* ICH10DO */ /* PCH Desktop Full Featured */ /* PCH Mobile Full Featured */ /* P55 */ /* PM55 */ /* H55 */ /* QM57 */ /* H57 */ /* HM55 */ /* Q57 */ /* HM57 */ /* PCH Mobile SFF Full Featured */ /* QS57 */ /* 3400 */ /* 3420 */ /* 3450 */ /* EP80579 */ /* Cougar Point */ /* Cougar Point Desktop */ /* Cougar Point Mobile */ /* Patsburg */ /* DH89xxCC */ /* Panther Point */ /* Lynx Point */ /* Lynx Point-LP */ /* Wellsburg */ /* Avoton SoC */ /* Bay Trail SoC */ /* Coleto Creek */ /* Wildcat Point-LP */ /* Braswell SoC */ /* Lewisburg */ /* 9 Series */ /* Apollo Lake SoC */ /* Denverton SoC */ /* Gemini Lake SoC */ /* Cougar Mountain SoC*/ struct lpc_ich_priv {enum lpc_chipsets chipset;int abase; /* ACPI base */ int actrl_pbase; /* ACPI control or PMC base */ int gbase; /* GPIO base */ int gctrl; /* GPIO control */ int abase_save; /* Cached ACPI base value */ int actrl_pbase_save; /* Cached ACPI control or PMC base value */ int gctrl_save; /* Cached GPIO control value */ static struct lpc_ich_info lpc_chipset_info[] = {"ICH" ,1 ,"ICH0" ,1 ,"ICH2" ,1 ,"ICH2-M" ,1 ,"ICH3-S" ,1 ,"ICH3-M" ,1 ,"ICH4" ,1 ,"ICH4-M" ,1 ,"C-ICH" ,1 ,"ICH5 or ICH5R" ,1 ,"6300ESB" ,1 ,"ICH6 or ICH6R" ,2 ,"ICH6-M" ,2 ,"ICH6W or ICH6RW" ,2 ,"631xESB/632xESB" ,2 ,"ICH7 or ICH7R" ,2 ,"ICH7DH" ,2 ,"ICH7-M or ICH7-U" ,2 ,"ICH7-M DH" ,2 ,"NM10" ,2 ,"ICH8 or ICH8R" ,2 ,"ICH8DH" ,2 ,"ICH8DO" ,2 ,"ICH8M" ,2 ,"ICH8M-E" ,2 ,"ICH9" ,2 ,"ICH9R" ,2 ,"ICH9DH" ,2 ,"ICH9DO" ,2 ,"ICH9M" ,2 ,"ICH9M-E" ,2 ,"ICH10" ,2 ,"ICH10R" ,2 ,"ICH10D" ,2 ,"ICH10DO" ,2 ,"PCH Desktop Full Featured" ,2 ,"PCH Mobile Full Featured" ,2 ,"P55" ,2 ,"PM55" ,2 ,"H55" ,2 ,"QM57" ,2 ,"H57" ,2 ,"HM55" ,2 ,"Q57" ,2 ,"HM57" ,2 ,"PCH Mobile SFF Full Featured" ,2 ,"QS57" ,2 ,"3400" ,2 ,"3420" ,2 ,"3450" ,2 ,"EP80579" ,2 ,"Cougar Point" ,2 ,"Cougar Point Desktop" ,2 ,"Cougar Point Mobile" ,2 ,"Patsburg" ,2 ,"DH89xxCC" ,2 ,"Panther Point" ,2 ,"Lynx Point" ,2 ,"Lynx Point_LP" ,2 ,"Wellsburg" ,2 ,"Avoton SoC" ,3 ,"Bay Trail SoC" ,3 ,"Coleto Creek" ,2 ,"Wildcat Point_LP" ,2 ,"Braswell SoC" ,3 ,"Lewisburg" ,2 ,"9 Series" ,2 ,"Apollo Lake SoC" ,5 ,"Denverton SoC" ,"Gemini Lake SoC" ,"Cougar Mountain SoC" ,3 ,/* * This data only exists for exporting the supported PCI ids * via MODULE_DEVICE_TABLE . We do not actually register a * pci_driver , because the I / O Controller Hub has also other * functions that probably will be registered by other drivers . static const struct pci_device_id lpc_ich_ids[] = {0 x0f1c), LPC_BAYTRAIL},0 x19dc), LPC_DNV},0 x1c41), LPC_CPT},0 x1c42), LPC_CPTD},0 x1c43), LPC_CPTM},0 x1c44), LPC_CPT},0 x1c45), LPC_CPT},0 x1c46), LPC_CPT},0 x1c47), LPC_CPT},0 x1c48), LPC_CPT},0 x1c49), LPC_CPT},0 x1c4a), LPC_CPT},0 x1c4b), LPC_CPT},0 x1c4c), LPC_CPT},0 x1c4d), LPC_CPT},0 x1c4e), LPC_CPT},0 x1c4f), LPC_CPT},0 x1c50), LPC_CPT},0 x1c51), LPC_CPT},0 x1c52), LPC_CPT},0 x1c53), LPC_CPT},0 x1c54), LPC_CPT},0 x1c55), LPC_CPT},0 x1c56), LPC_CPT},0 x1c57), LPC_CPT},0 x1c58), LPC_CPT},0 x1c59), LPC_CPT},0 x1c5a), LPC_CPT},0 x1c5b), LPC_CPT},0 x1c5c), LPC_CPT},0 x1c5d), LPC_CPT},0 x1c5e), LPC_CPT},0 x1c5f), LPC_CPT},0 x1d40), LPC_PBG},0 x1d41), LPC_PBG},0 x1e40), LPC_PPT},0 x1e41), LPC_PPT},0 x1e42), LPC_PPT},0 x1e43), LPC_PPT},0 x1e44), LPC_PPT},0 x1e45), LPC_PPT},0 x1e46), LPC_PPT},0 x1e47), LPC_PPT},0 x1e48), LPC_PPT},0 x1e49), LPC_PPT},0 x1e4a), LPC_PPT},0 x1e4b), LPC_PPT},0 x1e4c), LPC_PPT},0 x1e4d), LPC_PPT},0 x1e4e), LPC_PPT},0 x1e4f), LPC_PPT},0 x1e50), LPC_PPT},0 x1e51), LPC_PPT},0 x1e52), LPC_PPT},0 x1e53), LPC_PPT},0 x1e54), LPC_PPT},0 x1e55), LPC_PPT},0 x1e56), LPC_PPT},0 x1e57), LPC_PPT},0 x1e58), LPC_PPT},0 x1e59), LPC_PPT},0 x1e5a), LPC_PPT},0 x1e5b), LPC_PPT},0 x1e5c), LPC_PPT},0 x1e5d), LPC_PPT},0 x1e5e), LPC_PPT},0 x1e5f), LPC_PPT},0 x1f38), LPC_AVN},0 x1f39), LPC_AVN},0 x1f3a), LPC_AVN},0 x1f3b), LPC_AVN},0 x229c), LPC_BRASWELL},0 x2310), LPC_DH89XXCC},0 x2390), LPC_COLETO},0 x2410), LPC_ICH},0 x2420), LPC_ICH0},0 x2440), LPC_ICH2},0 x244c), LPC_ICH2M},0 x2450), LPC_CICH},0 x2480), LPC_ICH3},0 x248c), LPC_ICH3M},0 x24c0), LPC_ICH4},0 x24cc), LPC_ICH4M},0 x24d0), LPC_ICH5},0 x25a1), LPC_6300ESB},0 x2640), LPC_ICH6},0 x2641), LPC_ICH6M},0 x2642), LPC_ICH6W},0 x2670), LPC_631XESB},0 x2671), LPC_631XESB},0 x2672), LPC_631XESB},0 x2673), LPC_631XESB},0 x2674), LPC_631XESB},0 x2675), LPC_631XESB},0 x2676), LPC_631XESB},0 x2677), LPC_631XESB},0 x2678), LPC_631XESB},0 x2679), LPC_631XESB},0 x267a), LPC_631XESB},0 x267b), LPC_631XESB},0 x267c), LPC_631XESB},0 x267d), LPC_631XESB},0 x267e), LPC_631XESB},0 x267f), LPC_631XESB},0 x27b0), LPC_ICH7DH},0 x27b8), LPC_ICH7},0 x27b9), LPC_ICH7M},0 x27bc), LPC_NM10},0 x27bd), LPC_ICH7MDH},0 x2810), LPC_ICH8},0 x2811), LPC_ICH8ME},0 x2812), LPC_ICH8DH},0 x2814), LPC_ICH8DO},0 x2815), LPC_ICH8M},0 x2912), LPC_ICH9DH},0 x2914), LPC_ICH9DO},0 x2916), LPC_ICH9R},0 x2917), LPC_ICH9ME},0 x2918), LPC_ICH9},0 x2919), LPC_ICH9M},0 x2b9c), LPC_COUGARMOUNTAIN},0 x3197), LPC_GLK},0 x31e8), LPC_GLK},0 x3a14), LPC_ICH10DO},0 x3a16), LPC_ICH10R},0 x3a18), LPC_ICH10},0 x3a1a), LPC_ICH10D},0 x3b00), LPC_PCH},0 x3b01), LPC_PCHM},0 x3b02), LPC_P55},0 x3b03), LPC_PM55},0 x3b06), LPC_H55},0 x3b07), LPC_QM57},0 x3b08), LPC_H57},0 x3b09), LPC_HM55},0 x3b0a), LPC_Q57},0 x3b0b), LPC_HM57},0 x3b0d), LPC_PCHMSFF},0 x3b0f), LPC_QS57},0 x3b12), LPC_3400},0 x3b14), LPC_3420},0 x3b16), LPC_3450},0 x5031), LPC_EP80579},0 x5ae8), LPC_APL},0 x8c40), LPC_LPT},0 x8c41), LPC_LPT},0 x8c42), LPC_LPT},0 x8c43), LPC_LPT},0 x8c44), LPC_LPT},0 x8c45), LPC_LPT},0 x8c46), LPC_LPT},0 x8c47), LPC_LPT},0 x8c48), LPC_LPT},0 x8c49), LPC_LPT},0 x8c4a), LPC_LPT},0 x8c4b), LPC_LPT},0 x8c4c), LPC_LPT},0 x8c4d), LPC_LPT},0 x8c4e), LPC_LPT},0 x8c4f), LPC_LPT},0 x8c50), LPC_LPT},0 x8c51), LPC_LPT},0 x8c52), LPC_LPT},0 x8c53), LPC_LPT},0 x8c54), LPC_LPT},0 x8c55), LPC_LPT},0 x8c56), LPC_LPT},0 x8c57), LPC_LPT},0 x8c58), LPC_LPT},0 x8c59), LPC_LPT},0 x8c5a), LPC_LPT},0 x8c5b), LPC_LPT},0 x8c5c), LPC_LPT},0 x8c5d), LPC_LPT},0 x8c5e), LPC_LPT},0 x8c5f), LPC_LPT},0 x8cc1), LPC_9S},0 x8cc2), LPC_9S},0 x8cc3), LPC_9S},0 x8cc4), LPC_9S},0 x8cc6), LPC_9S},0 x8d40), LPC_WBG},0 x8d41), LPC_WBG},0 x8d42), LPC_WBG},0 x8d43), LPC_WBG},0 x8d44), LPC_WBG},0 x8d45), LPC_WBG},0 x8d46), LPC_WBG},0 x8d47), LPC_WBG},0 x8d48), LPC_WBG},0 x8d49), LPC_WBG},0 x8d4a), LPC_WBG},0 x8d4b), LPC_WBG},0 x8d4c), LPC_WBG},0 x8d4d), LPC_WBG},0 x8d4e), LPC_WBG},0 x8d4f), LPC_WBG},0 x8d50), LPC_WBG},0 x8d51), LPC_WBG},0 x8d52), LPC_WBG},0 x8d53), LPC_WBG},0 x8d54), LPC_WBG},0 x8d55), LPC_WBG},0 x8d56), LPC_WBG},0 x8d57), LPC_WBG},0 x8d58), LPC_WBG},0 x8d59), LPC_WBG},0 x8d5a), LPC_WBG},0 x8d5b), LPC_WBG},0 x8d5c), LPC_WBG},0 x8d5d), LPC_WBG},0 x8d5e), LPC_WBG},0 x8d5f), LPC_WBG},0 x9c40), LPC_LPT_LP},0 x9c41), LPC_LPT_LP},0 x9c42), LPC_LPT_LP},0 x9c43), LPC_LPT_LP},0 x9c44), LPC_LPT_LP},0 x9c45), LPC_LPT_LP},0 x9c46), LPC_LPT_LP},0 x9c47), LPC_LPT_LP},0 x9cc1), LPC_WPT_LP},0 x9cc2), LPC_WPT_LP},0 x9cc3), LPC_WPT_LP},0 x9cc5), LPC_WPT_LP},0 x9cc6), LPC_WPT_LP},0 x9cc7), LPC_WPT_LP},0 x9cc9), LPC_WPT_LP},0 xa1c1), LPC_LEWISBURG},0 xa1c2), LPC_LEWISBURG},0 xa1c3), LPC_LEWISBURG},0 xa1c4), LPC_LEWISBURG},0 xa1c5), LPC_LEWISBURG},0 xa1c6), LPC_LEWISBURG},0 xa1c7), LPC_LEWISBURG},0 xa242), LPC_LEWISBURG},0 xa243), LPC_LEWISBURG},0 , }, /* End of list */ static void lpc_ich_restore_config_space(struct pci_dev *dev)struct lpc_ich_priv *priv = pci_get_drvdata(dev);if (priv->abase_save >= 0 ) {1 ;if (priv->actrl_pbase_save >= 0 ) {1 ;if (priv->gctrl_save >= 0 ) {1 ;static void lpc_ich_enable_acpi_space(struct pci_dev *dev)struct lpc_ich_priv *priv = pci_get_drvdata(dev);switch (lpc_chipset_info[priv->chipset].iTCO_version) {case 3 :/* * Some chipsets ( eg Avoton ) enable the ACPI space in the * ACPI BASE register . 0 x2);break ;default :/* * Most chipsets enable the ACPI space in the ACPI control * register . 0 x80);break ;static void lpc_ich_enable_gpio_space(struct pci_dev *dev)struct lpc_ich_priv *priv = pci_get_drvdata(dev);0 x10);static void lpc_ich_enable_pmc_space(struct pci_dev *dev)struct lpc_ich_priv *priv = pci_get_drvdata(dev);0 x2);static int lpc_ich_finalize_wdt_cell(struct pci_dev *dev)struct itco_wdt_platform_data *pdata;struct lpc_ich_priv *priv = pci_get_drvdata(dev);struct lpc_ich_info *info;struct mfd_cell *cell = &lpc_ich_wdt_cell;sizeof (*pdata), GFP_KERNEL);if (!pdata)return -ENOMEM;sizeof (pdata->name));sizeof (*pdata);return 0 ;static void lpc_ich_finalize_gpio_cell(struct pci_dev *dev)struct lpc_ich_priv *priv = pci_get_drvdata(dev);struct mfd_cell *cell = &lpc_ich_gpio_cell;sizeof (struct lpc_ich_info);/* * We don ' t check for resource conflict globally . There are 2 or 3 independent * GPIO groups and it ' s enough to have access to one of these to instantiate * the device . static int lpc_ich_check_conflict_gpio(struct resource *res)int ret;0 ;if (resource_size(res) >= 0 x50 &&0 x40, 0 x10, "LPC ICH GPIO3" ))1 << 2 ;if (!acpi_check_region(res->start + 0 x30, 0 x10, "LPC ICH GPIO2" ))1 << 1 ;0 x00, 0 x30, "LPC ICH GPIO1" );if (!ret)1 << 0 ;return use_gpio ? use_gpio : ret;static int lpc_ich_init_gpio(struct pci_dev *dev)struct lpc_ich_priv *priv = pci_get_drvdata(dev);int ret;bool acpi_conflict = false ;struct resource *res;/* Setup power management base register */ 0 x0000ff80;if (!base_addr) {"I/O space for ACPI uninitialized\n" );goto gpe0_done;if (ret) {/* * This isn ' t fatal for the GPIO , but we have to make sure that * the platform_device subsystem doesn ' t see this resource * or it will register an invalid region . true ;else {/* Setup GPIO base register */ 0 x0000ff80;if (!base_addr) {"I/O space for GPIO uninitialized\n" );goto gpio_done;/* Older devices provide fewer GPIO and have a smaller resource size. */ switch (lpc_chipset_info[priv->chipset].gpio_version) {case ICH_V5_GPIO:case ICH_V10CORP_GPIO:128 - 1 ;break ;default :64 - 1 ;break ;if (ret < 0 ) {/* this isn't necessarily fatal for the GPIO */ true ;goto gpio_done;1 , NULL, 0 , NULL);if (acpi_conflict)"Resource conflict(s) found affecting %s\n" ,return ret;static int lpc_ich_init_wdt(struct pci_dev *dev)struct lpc_ich_priv *priv = pci_get_drvdata(dev);int ret;struct resource *res;/* If we have ACPI based watchdog use that instead */ if (acpi_has_watchdog())return -ENODEV;/* Setup power management base register */ 0 x0000ff80;if (!base_addr) {"I/O space for ACPI uninitialized\n" );goto wdt_done;/* * iTCO v2 : * Get the Memory - Mapped GCS register . To get access to it * we have to read RCBA from PCI Config space 0 xf0 and use * it as base . GCS = RCBA + ICH6_GCS ( 0 x3410 ) . * * iTCO v3 : * Get the Power Management Configuration register . To get access * to it we have to read the PMC BASE from config space and address * the register at offset 0 x8 . if (lpc_chipset_info[priv->chipset].iTCO_version == 1 ) {/* Don't register iomem for TCO ver 1 */ else if (lpc_chipset_info[priv->chipset].iTCO_version == 2 ) {0 xffffc000;if (!(base_addr_cfg & 1 )) {"RCBA is disabled by " "hardware/BIOS, device disabled\n" );goto wdt_done;else if (lpc_chipset_info[priv->chipset].iTCO_version == 3 ) {0 xfffffe00;if (ret)goto wdt_done;1 , NULL, 0 , NULL);return ret;static int lpc_ich_init_pinctrl(struct pci_dev *dev)struct lpc_ich_priv *priv = pci_get_drvdata(dev);const struct lpc_ich_gpio_info *info = lpc_chipset_info[priv->chipset].gpio_info;struct resource base;unsigned int i;int ret;/* Check, if GPIO has been exported as an ACPI device */ if (acpi_dev_present(info->hid, NULL, -1 ))return -EEXIST;0 , &base);if (ret)return ret;for (i = 0 ; i < info->nr_resources; i++) {struct resource *mem = info->resources[i];/* Fill MEM resource */ 1 ;return mfd_add_devices(&dev->dev, 0 , info->devices, info->nr_devices,0 , NULL);static bool lpc_ich_byt_set_writeable(void __iomem *base, void *data)if (!(val & BYT_BCR_WPD)) {return val & BYT_BCR_WPD;static bool lpc_ich_set_writeable(struct pci_bus *bus, unsigned int devfn)if (!(bcr & BCR_WPD)) {return bcr & BCR_WPD;static bool lpc_ich_lpt_set_writeable(void __iomem *base, void *data)struct pci_dev *pdev = data;return lpc_ich_set_writeable(pdev->bus, pdev->devfn);static bool lpc_ich_bxt_set_writeable(void __iomem *base, void *data)struct pci_dev *pdev = data;return lpc_ich_set_writeable(pdev->bus, PCI_DEVFN(13 , 2 ));static int lpc_ich_init_spi(struct pci_dev *dev)struct lpc_ich_priv *priv = pci_get_drvdata(dev);struct resource *res = &intel_spi_res[0 ];struct intel_spi_boardinfo *info;int ret;sizeof (*info), GFP_KERNEL);if (!info)return -ENOMEM;switch (info->type) {case INTEL_SPI_BYT:if (spi_base & SPIBASE_BYT_EN) {1 ;break ;case INTEL_SPI_LPT:if (rcba & 1 ) {1 ;break ;case INTEL_SPI_BXT:/* * The P2SB is hidden by BIOS and we need to unhide it in * order to read BAR of the SPI flash device . Once that is * done we hide it again . 13 , 2 ), res);if (ret)return ret;break ;default :return -EINVAL;if (!res->start)return -ENODEV;sizeof (*info);return mfd_add_devices(&dev->dev, PLATFORM_DEVID_NONE,1 , NULL, 0 , NULL);static int lpc_ich_probe(struct pci_dev *dev,const struct pci_device_id *id)struct lpc_ich_priv *priv;int ret;bool cell_added = false ;sizeof (struct lpc_ich_priv), GFP_KERNEL);if (!priv)return -ENOMEM;1 ;1 ;1 ;if (priv->chipset <= LPC_ICH5) {else {if (lpc_chipset_info[priv->chipset].iTCO_version) {if (!ret)true ;if (lpc_chipset_info[priv->chipset].gpio_version) {if (!ret)true ;if (lpc_chipset_info[priv->chipset].gpio_info) {if (!ret)true ;if (lpc_chipset_info[priv->chipset].spi_type) {if (!ret)true ;/* * We only care if at least one or none of the cells registered * successfully . if (!cell_added) {"No MFD cells added\n" );return -ENODEV;return 0 ;static void lpc_ich_remove(struct pci_dev *dev)static struct pci_driver lpc_ich_driver = {"lpc_ich" ,"Aaron Sierra <asierra@xes-inc.com>" );"LPC interface for Intel ICH" );"GPL" );
Messung V0.5 in Prozent C=93 H=95 G=93
¤ Dauer der Verarbeitung: 0.27 Sekunden
(vorverarbeitet am 2026-09-28)
¤ *© Formatika GbR, Deutschland
