/* Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of Trident Microsystems nor Hauppauge Computer Works nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. /* *********************************************************************************************************************** * WARNING - THIS FILE HAS BEEN GENERATED - DO NOT CHANGE * * Filename: drxj_map.h * Generated on: Mon Jan 18 12:09:24 2010 * Generated by: IDF:x 1.3.0 * Generated from: reg_map * Output start: [entry point] * * filename last modified re-use * ----------------------------------------------------- * reg_map.1.tmp Mon Jan 18 12:09:24 2010 - * #ifndef __DRXJ_MAP__H__#define __DRXJ_MAP__H__ INCLUDED#ifdef _REGISTERTABLE_#include <registertable.h>extern register_table_t drxj_map[];extern register_table_info_t drxj_map_info[];#endif #define ATV_COMM_EXEC__A 0 xC00000#define ATV_COMM_EXEC__W 2 #define ATV_COMM_EXEC__M 0 x3#define ATV_COMM_EXEC__PRE 0 x0#define ATV_COMM_EXEC_STOP 0 x0#define ATV_COMM_EXEC_ACTIVE 0 x1#define ATV_COMM_EXEC_HOLD 0 x2#define ATV_COMM_STATE__A 0 xC00001#define ATV_COMM_STATE__W 16 #define ATV_COMM_STATE__M 0 xFFFF#define ATV_COMM_STATE__PRE 0 x0#define ATV_COMM_MB__A 0 xC00002#define ATV_COMM_MB__W 16 #define ATV_COMM_MB__M 0 xFFFF#define ATV_COMM_MB__PRE 0 x0#define ATV_COMM_INT_REQ__A 0 xC00003#define ATV_COMM_INT_REQ__W 16 #define ATV_COMM_INT_REQ__M 0 xFFFF#define ATV_COMM_INT_REQ__PRE 0 x0#define ATV_COMM_INT_REQ_COMM_INT_REQ__B 0 #define ATV_COMM_INT_REQ_COMM_INT_REQ__W 1 #define ATV_COMM_INT_REQ_COMM_INT_REQ__M 0 x1#define ATV_COMM_INT_REQ_COMM_INT_REQ__PRE 0 x0#define ATV_COMM_INT_STA__A 0 xC00005#define ATV_COMM_INT_STA__W 16 #define ATV_COMM_INT_STA__M 0 xFFFF#define ATV_COMM_INT_STA__PRE 0 x0#define ATV_COMM_INT_MSK__A 0 xC00006#define ATV_COMM_INT_MSK__W 16 #define ATV_COMM_INT_MSK__M 0 xFFFF#define ATV_COMM_INT_MSK__PRE 0 x0#define ATV_COMM_INT_STM__A 0 xC00007#define ATV_COMM_INT_STM__W 16 #define ATV_COMM_INT_STM__M 0 xFFFF#define ATV_COMM_INT_STM__PRE 0 x0#define ATV_COMM_KEY__A 0 xC0000F#define ATV_COMM_KEY__W 16 #define ATV_COMM_KEY__M 0 xFFFF#define ATV_COMM_KEY__PRE 0 x0#define ATV_COMM_KEY_KEY 0 xFABA#define ATV_COMM_KEY_MIN 0 x0#define ATV_COMM_KEY_MAX 0 xFFFF#define ATV_TOP_COMM_EXEC__A 0 xC10000#define ATV_TOP_COMM_EXEC__W 2 #define ATV_TOP_COMM_EXEC__M 0 x3#define ATV_TOP_COMM_EXEC__PRE 0 x0#define ATV_TOP_COMM_EXEC_STOP 0 x0#define ATV_TOP_COMM_EXEC_ACTIVE 0 x1#define ATV_TOP_COMM_EXEC_HOLD 0 x2#define ATV_TOP_COMM_STATE__A 0 xC10001#define ATV_TOP_COMM_STATE__W 16 #define ATV_TOP_COMM_STATE__M 0 xFFFF#define ATV_TOP_COMM_STATE__PRE 0 x0#define ATV_TOP_COMM_STATE_STATE__B 0 #define ATV_TOP_COMM_STATE_STATE__W 16 #define ATV_TOP_COMM_STATE_STATE__M 0 xFFFF#define ATV_TOP_COMM_STATE_STATE__PRE 0 x0#define ATV_TOP_COMM_MB__A 0 xC10002#define ATV_TOP_COMM_MB__W 16 #define ATV_TOP_COMM_MB__M 0 xFFFF#define ATV_TOP_COMM_MB__PRE 0 x0#define ATV_TOP_COMM_MB_CTL__B 0 #define ATV_TOP_COMM_MB_CTL__W 1 #define ATV_TOP_COMM_MB_CTL__M 0 x1#define ATV_TOP_COMM_MB_CTL__PRE 0 x0#define ATV_TOP_COMM_MB_OBS__B 1 #define ATV_TOP_COMM_MB_OBS__W 1 #define ATV_TOP_COMM_MB_OBS__M 0 x2#define ATV_TOP_COMM_MB_OBS__PRE 0 x0#define ATV_TOP_COMM_MB_MUX_CTRL__B 2 #define ATV_TOP_COMM_MB_MUX_CTRL__W 4 #define ATV_TOP_COMM_MB_MUX_CTRL__M 0 x3C#define ATV_TOP_COMM_MB_MUX_CTRL__PRE 0 x0#define ATV_TOP_COMM_MB_MUX_CTRL_PEAK_S 0 x0#define ATV_TOP_COMM_MB_MUX_CTRL_VID_GAIN 0 x4#define ATV_TOP_COMM_MB_MUX_CTRL_CORR_O 0 x8#define ATV_TOP_COMM_MB_MUX_CTRL_CR_ROT_O 0 xC#define ATV_TOP_COMM_MB_MUX_CTRL_CR_IIR_IQ 0 x10#define ATV_TOP_COMM_MB_MUX_CTRL_VIDEO_O 0 x14#define ATV_TOP_COMM_MB_MUX_CTRL_SIF_O 0 x18#define ATV_TOP_COMM_MB_MUX_CTRL_SIF2025_O 0 x1C#define ATV_TOP_COMM_MB_MUX_CTRL_POST_S 0 x20#define ATV_TOP_COMM_MB_MUX_OBS__B 6 #define ATV_TOP_COMM_MB_MUX_OBS__W 4 #define ATV_TOP_COMM_MB_MUX_OBS__M 0 x3C0#define ATV_TOP_COMM_MB_MUX_OBS__PRE 0 x0#define ATV_TOP_COMM_MB_MUX_OBS_PEAK_S 0 x0#define ATV_TOP_COMM_MB_MUX_OBS_VID_GAIN 0 x40#define ATV_TOP_COMM_MB_MUX_OBS_CORR_O 0 x80#define ATV_TOP_COMM_MB_MUX_OBS_CR_ROT_O 0 xC0#define ATV_TOP_COMM_MB_MUX_OBS_CR_IIR_IQ 0 x100#define ATV_TOP_COMM_MB_MUX_OBS_VIDEO_O 0 x140#define ATV_TOP_COMM_MB_MUX_OBS_SIF_O 0 x180#define ATV_TOP_COMM_MB_MUX_OBS_SIF2025_O 0 x1C0#define ATV_TOP_COMM_MB_MUX_OBS_POST_S 0 x200#define ATV_TOP_COMM_INT_REQ__A 0 xC10003#define ATV_TOP_COMM_INT_REQ__W 16 #define ATV_TOP_COMM_INT_REQ__M 0 xFFFF#define ATV_TOP_COMM_INT_REQ__PRE 0 x0#define ATV_TOP_COMM_INT_STA__A 0 xC10005#define ATV_TOP_COMM_INT_STA__W 16 #define ATV_TOP_COMM_INT_STA__M 0 xFFFF#define ATV_TOP_COMM_INT_STA__PRE 0 x0#define ATV_TOP_COMM_INT_STA_FAGC_STA__B 0 #define ATV_TOP_COMM_INT_STA_FAGC_STA__W 1 #define ATV_TOP_COMM_INT_STA_FAGC_STA__M 0 x1#define ATV_TOP_COMM_INT_STA_FAGC_STA__PRE 0 x0#define ATV_TOP_COMM_INT_STA_OVM_STA__B 1 #define ATV_TOP_COMM_INT_STA_OVM_STA__W 1 #define ATV_TOP_COMM_INT_STA_OVM_STA__M 0 x2#define ATV_TOP_COMM_INT_STA_OVM_STA__PRE 0 x0#define ATV_TOP_COMM_INT_STA_AMPTH_STA__B 2 #define ATV_TOP_COMM_INT_STA_AMPTH_STA__W 1 #define ATV_TOP_COMM_INT_STA_AMPTH_STA__M 0 x4#define ATV_TOP_COMM_INT_STA_AMPTH_STA__PRE 0 x0#define ATV_TOP_COMM_INT_MSK__A 0 xC10006#define ATV_TOP_COMM_INT_MSK__W 16 #define ATV_TOP_COMM_INT_MSK__M 0 xFFFF#define ATV_TOP_COMM_INT_MSK__PRE 0 x0#define ATV_TOP_COMM_INT_MSK_FAGC_MSK__B 0 #define ATV_TOP_COMM_INT_MSK_FAGC_MSK__W 1 #define ATV_TOP_COMM_INT_MSK_FAGC_MSK__M 0 x1#define ATV_TOP_COMM_INT_MSK_FAGC_MSK__PRE 0 x0#define ATV_TOP_COMM_INT_MSK_OVM_MSK__B 1 #define ATV_TOP_COMM_INT_MSK_OVM_MSK__W 1 #define ATV_TOP_COMM_INT_MSK_OVM_MSK__M 0 x2#define ATV_TOP_COMM_INT_MSK_OVM_MSK__PRE 0 x0#define ATV_TOP_COMM_INT_MSK_AMPTH_MSK__B 2 #define ATV_TOP_COMM_INT_MSK_AMPTH_MSK__W 1 #define ATV_TOP_COMM_INT_MSK_AMPTH_MSK__M 0 x4#define ATV_TOP_COMM_INT_MSK_AMPTH_MSK__PRE 0 x0#define ATV_TOP_COMM_INT_STM__A 0 xC10007#define ATV_TOP_COMM_INT_STM__W 16 #define ATV_TOP_COMM_INT_STM__M 0 xFFFF#define ATV_TOP_COMM_INT_STM__PRE 0 x0#define ATV_TOP_COMM_INT_STM_FAGC_STM__B 0 #define ATV_TOP_COMM_INT_STM_FAGC_STM__W 1 #define ATV_TOP_COMM_INT_STM_FAGC_STM__M 0 x1#define ATV_TOP_COMM_INT_STM_FAGC_STM__PRE 0 x0#define ATV_TOP_COMM_INT_STM_OVM_STM__B 1 #define ATV_TOP_COMM_INT_STM_OVM_STM__W 1 #define ATV_TOP_COMM_INT_STM_OVM_STM__M 0 x2#define ATV_TOP_COMM_INT_STM_OVM_STM__PRE 0 x0#define ATV_TOP_COMM_INT_STM_AMPTH_STM__B 2 #define ATV_TOP_COMM_INT_STM_AMPTH_STM__W 1 #define ATV_TOP_COMM_INT_STM_AMPTH_STM__M 0 x4#define ATV_TOP_COMM_INT_STM_AMPTH_STM__PRE 0 x0#define ATV_TOP_COMM_KEY__A 0 xC1000F#define ATV_TOP_COMM_KEY__W 16 #define ATV_TOP_COMM_KEY__M 0 xFFFF#define ATV_TOP_COMM_KEY__PRE 0 x0#define ATV_TOP_COMM_KEY_KEY__B 0 #define ATV_TOP_COMM_KEY_KEY__W 16 #define ATV_TOP_COMM_KEY_KEY__M 0 xFFFF#define ATV_TOP_COMM_KEY_KEY__PRE 0 x0#define ATV_TOP_COMM_KEY_KEY_KEY 0 xFABA#define ATV_TOP_COMM_KEY_KEY_MIN 0 x0#define ATV_TOP_COMM_KEY_KEY_MAX 0 xFFFF#define ATV_TOP_CR_AMP_TH__A 0 xC10010#define ATV_TOP_CR_AMP_TH__W 8 #define ATV_TOP_CR_AMP_TH__M 0 xFF#define ATV_TOP_CR_AMP_TH__PRE 0 x8#define ATV_TOP_CR_AMP_TH_MN 0 x8#define ATV_TOP_CR_CONT__A 0 xC10011#define ATV_TOP_CR_CONT__W 9 #define ATV_TOP_CR_CONT__M 0 x1FF#define ATV_TOP_CR_CONT__PRE 0 x9C#define ATV_TOP_CR_CONT_CR_P__B 0 #define ATV_TOP_CR_CONT_CR_P__W 3 #define ATV_TOP_CR_CONT_CR_P__M 0 x7#define ATV_TOP_CR_CONT_CR_P__PRE 0 x4#define ATV_TOP_CR_CONT_CR_P_MN 0 x4#define ATV_TOP_CR_CONT_CR_P_FM 0 x0#define ATV_TOP_CR_CONT_CR_D__B 3 #define ATV_TOP_CR_CONT_CR_D__W 3 #define ATV_TOP_CR_CONT_CR_D__M 0 x38#define ATV_TOP_CR_CONT_CR_D__PRE 0 x18#define ATV_TOP_CR_CONT_CR_D_MN 0 x18#define ATV_TOP_CR_CONT_CR_D_FM 0 x0#define ATV_TOP_CR_CONT_CR_I__B 6 #define ATV_TOP_CR_CONT_CR_I__W 3 #define ATV_TOP_CR_CONT_CR_I__M 0 x1C0#define ATV_TOP_CR_CONT_CR_I__PRE 0 x80#define ATV_TOP_CR_CONT_CR_I_MN 0 x80#define ATV_TOP_CR_CONT_CR_I_FM 0 x0#define ATV_TOP_CR_OVM_TH__A 0 xC10012#define ATV_TOP_CR_OVM_TH__W 8 #define ATV_TOP_CR_OVM_TH__M 0 xFF#define ATV_TOP_CR_OVM_TH__PRE 0 xA0#define ATV_TOP_CR_OVM_TH_MN 0 xA0#define ATV_TOP_CR_OVM_TH_FM 0 x0#define ATV_TOP_NOISE_TH__A 0 xC10013#define ATV_TOP_NOISE_TH__W 4 #define ATV_TOP_NOISE_TH__M 0 xF#define ATV_TOP_NOISE_TH__PRE 0 x8#define ATV_TOP_NOISE_TH_MN 0 x8#define ATV_TOP_EQU0__A 0 xC10014#define ATV_TOP_EQU0__W 9 #define ATV_TOP_EQU0__M 0 x1FF#define ATV_TOP_EQU0__PRE 0 x1FB#define ATV_TOP_EQU0_EQU_C0__B 0 #define ATV_TOP_EQU0_EQU_C0__W 9 #define ATV_TOP_EQU0_EQU_C0__M 0 x1FF#define ATV_TOP_EQU0_EQU_C0__PRE 0 x1FB#define ATV_TOP_EQU0_EQU_C0_MN 0 xFB#define ATV_TOP_EQU1__A 0 xC10015#define ATV_TOP_EQU1__W 9 #define ATV_TOP_EQU1__M 0 x1FF#define ATV_TOP_EQU1__PRE 0 x1CE#define ATV_TOP_EQU1_EQU_C1__B 0 #define ATV_TOP_EQU1_EQU_C1__W 9 #define ATV_TOP_EQU1_EQU_C1__M 0 x1FF#define ATV_TOP_EQU1_EQU_C1__PRE 0 x1CE#define ATV_TOP_EQU1_EQU_C1_MN 0 xCE#define ATV_TOP_EQU2__A 0 xC10016#define ATV_TOP_EQU2__W 9 #define ATV_TOP_EQU2__M 0 x1FF#define ATV_TOP_EQU2__PRE 0 xD2#define ATV_TOP_EQU2_EQU_C2__B 0 #define ATV_TOP_EQU2_EQU_C2__W 9 #define ATV_TOP_EQU2_EQU_C2__M 0 x1FF#define ATV_TOP_EQU2_EQU_C2__PRE 0 xD2#define ATV_TOP_EQU2_EQU_C2_MN 0 xD2#define ATV_TOP_EQU3__A 0 xC10017#define ATV_TOP_EQU3__W 9 #define ATV_TOP_EQU3__M 0 x1FF#define ATV_TOP_EQU3__PRE 0 x160#define ATV_TOP_EQU3_EQU_C3__B 0 #define ATV_TOP_EQU3_EQU_C3__W 9 #define ATV_TOP_EQU3_EQU_C3__M 0 x1FF#define ATV_TOP_EQU3_EQU_C3__PRE 0 x160#define ATV_TOP_EQU3_EQU_C3_MN 0 x60#define ATV_TOP_ROT_MODE__A 0 xC10018#define ATV_TOP_ROT_MODE__W 1 #define ATV_TOP_ROT_MODE__M 0 x1#define ATV_TOP_ROT_MODE__PRE 0 x0#define ATV_TOP_ROT_MODE_AMPTH_DEPEND 0 x0#define ATV_TOP_ROT_MODE_ALWAYS 0 x1#define ATV_TOP_MOD_CONTROL__A 0 xC10019#define ATV_TOP_MOD_CONTROL__W 12 #define ATV_TOP_MOD_CONTROL__M 0 xFFF#define ATV_TOP_MOD_CONTROL__PRE 0 x5B1#define ATV_TOP_MOD_CONTROL_MOD_IR__B 0 #define ATV_TOP_MOD_CONTROL_MOD_IR__W 3 #define ATV_TOP_MOD_CONTROL_MOD_IR__M 0 x7#define ATV_TOP_MOD_CONTROL_MOD_IR__PRE 0 x1#define ATV_TOP_MOD_CONTROL_MOD_IR_MN 0 x1#define ATV_TOP_MOD_CONTROL_MOD_IR_FM 0 x0#define ATV_TOP_MOD_CONTROL_MOD_IF__B 3 #define ATV_TOP_MOD_CONTROL_MOD_IF__W 4 #define ATV_TOP_MOD_CONTROL_MOD_IF__M 0 x78#define ATV_TOP_MOD_CONTROL_MOD_IF__PRE 0 x30#define ATV_TOP_MOD_CONTROL_MOD_IF_MN 0 x30#define ATV_TOP_MOD_CONTROL_MOD_IF_FM 0 x0#define ATV_TOP_MOD_CONTROL_MOD_MODE__B 7 #define ATV_TOP_MOD_CONTROL_MOD_MODE__W 1 #define ATV_TOP_MOD_CONTROL_MOD_MODE__M 0 x80#define ATV_TOP_MOD_CONTROL_MOD_MODE__PRE 0 x80#define ATV_TOP_MOD_CONTROL_MOD_MODE_RISE 0 x0#define ATV_TOP_MOD_CONTROL_MOD_MODE_RISE_FALL 0 x80#define ATV_TOP_MOD_CONTROL_MOD_TH__B 8 #define ATV_TOP_MOD_CONTROL_MOD_TH__W 4 #define ATV_TOP_MOD_CONTROL_MOD_TH__M 0 xF00#define ATV_TOP_MOD_CONTROL_MOD_TH__PRE 0 x500#define ATV_TOP_MOD_CONTROL_MOD_TH_MN 0 x500#define ATV_TOP_MOD_CONTROL_MOD_TH_FM 0 x0#define ATV_TOP_STD__A 0 xC1001A#define ATV_TOP_STD__W 2 #define ATV_TOP_STD__M 0 x3#define ATV_TOP_STD__PRE 0 x0#define ATV_TOP_STD_MODE__B 0 #define ATV_TOP_STD_MODE__W 1 #define ATV_TOP_STD_MODE__M 0 x1#define ATV_TOP_STD_MODE__PRE 0 x0#define ATV_TOP_STD_MODE_MN 0 x0#define ATV_TOP_STD_MODE_FM 0 x1#define ATV_TOP_STD_VID_POL__B 1 #define ATV_TOP_STD_VID_POL__W 1 #define ATV_TOP_STD_VID_POL__M 0 x2#define ATV_TOP_STD_VID_POL__PRE 0 x0#define ATV_TOP_STD_VID_POL_NEG 0 x0#define ATV_TOP_STD_VID_POL_POS 0 x2#define ATV_TOP_VID_AMP__A 0 xC1001B#define ATV_TOP_VID_AMP__W 12 #define ATV_TOP_VID_AMP__M 0 xFFF#define ATV_TOP_VID_AMP__PRE 0 x380#define ATV_TOP_VID_AMP_MN 0 x380#define ATV_TOP_VID_AMP_FM 0 x0#define ATV_TOP_VID_PEAK__A 0 xC1001C#define ATV_TOP_VID_PEAK__W 5 #define ATV_TOP_VID_PEAK__M 0 x1F#define ATV_TOP_VID_PEAK__PRE 0 x1#define ATV_TOP_FAGC_TH__A 0 xC1001D#define ATV_TOP_FAGC_TH__W 11 #define ATV_TOP_FAGC_TH__M 0 x7FF#define ATV_TOP_FAGC_TH__PRE 0 x2B2#define ATV_TOP_FAGC_TH_MN 0 x2B2#define ATV_TOP_SYNC_SLICE__A 0 xC1001E#define ATV_TOP_SYNC_SLICE__W 11 #define ATV_TOP_SYNC_SLICE__M 0 x7FF#define ATV_TOP_SYNC_SLICE__PRE 0 x243#define ATV_TOP_SYNC_SLICE_MN 0 x243#define ATV_TOP_SIF_GAIN__A 0 xC1001F#define ATV_TOP_SIF_GAIN__W 11 #define ATV_TOP_SIF_GAIN__M 0 x7FF#define ATV_TOP_SIF_GAIN__PRE 0 x0#define ATV_TOP_SIF_TP__A 0 xC10020#define ATV_TOP_SIF_TP__W 6 #define ATV_TOP_SIF_TP__M 0 x3F#define ATV_TOP_SIF_TP__PRE 0 x0#define ATV_TOP_MOD_ACCU__A 0 xC10021#define ATV_TOP_MOD_ACCU__W 10 #define ATV_TOP_MOD_ACCU__M 0 x3FF#define ATV_TOP_MOD_ACCU__PRE 0 x0#define ATV_TOP_CR_FREQ__A 0 xC10022#define ATV_TOP_CR_FREQ__W 8 #define ATV_TOP_CR_FREQ__M 0 xFF#define ATV_TOP_CR_FREQ__PRE 0 x0#define ATV_TOP_CR_PHAD__A 0 xC10023#define ATV_TOP_CR_PHAD__W 12 #define ATV_TOP_CR_PHAD__M 0 xFFF#define ATV_TOP_CR_PHAD__PRE 0 x0#define ATV_TOP_AF_SIF_ATT__A 0 xC10024#define ATV_TOP_AF_SIF_ATT__W 2 #define ATV_TOP_AF_SIF_ATT__M 0 x3#define ATV_TOP_AF_SIF_ATT__PRE 0 x0#define ATV_TOP_AF_SIF_ATT_0DB 0 x0#define ATV_TOP_AF_SIF_ATT_M3DB 0 x1#define ATV_TOP_AF_SIF_ATT_M6DB 0 x2#define ATV_TOP_AF_SIF_ATT_M9DB 0 x3#define ATV_TOP_STDBY__A 0 xC10025#define ATV_TOP_STDBY__W 2 #define ATV_TOP_STDBY__M 0 x3#define ATV_TOP_STDBY__PRE 0 x1#define ATV_TOP_STDBY_SIF_STDBY__B 0 #define ATV_TOP_STDBY_SIF_STDBY__W 1 #define ATV_TOP_STDBY_SIF_STDBY__M 0 x1#define ATV_TOP_STDBY_SIF_STDBY__PRE 0 x1#define ATV_TOP_STDBY_SIF_STDBY_ACTIVE 0 x0#define ATV_TOP_STDBY_SIF_STDBY_STANDBY 0 x1#define ATV_TOP_STDBY_CVBS_STDBY__B 1 #define ATV_TOP_STDBY_CVBS_STDBY__W 1 #define ATV_TOP_STDBY_CVBS_STDBY__M 0 x2#define ATV_TOP_STDBY_CVBS_STDBY__PRE 0 x0#define ATV_TOP_STDBY_CVBS_STDBY_A1_ACTIVE 0 x0#define ATV_TOP_STDBY_CVBS_STDBY_A1_STANDBY 0 x2#define ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE 0 x2#define ATV_TOP_STDBY_CVBS_STDBY_A2_STANDBY 0 x0#define ATV_TOP_OVERRIDE_SFR__A 0 xC10026#define ATV_TOP_OVERRIDE_SFR__W 1 #define ATV_TOP_OVERRIDE_SFR__M 0 x1#define ATV_TOP_OVERRIDE_SFR__PRE 0 x0#define ATV_TOP_OVERRIDE_SFR_ACTIVE 0 x0#define ATV_TOP_OVERRIDE_SFR_OVERRIDE 0 x1#define ATV_TOP_SFR_VID_GAIN__A 0 xC10027#define ATV_TOP_SFR_VID_GAIN__W 16 #define ATV_TOP_SFR_VID_GAIN__M 0 xFFFF#define ATV_TOP_SFR_VID_GAIN__PRE 0 x0#define ATV_TOP_SFR_AGC_RES__A 0 xC10028#define ATV_TOP_SFR_AGC_RES__W 5 #define ATV_TOP_SFR_AGC_RES__M 0 x1F#define ATV_TOP_SFR_AGC_RES__PRE 0 x0#define ATV_TOP_OVM_COMP__A 0 xC10029#define ATV_TOP_OVM_COMP__W 12 #define ATV_TOP_OVM_COMP__M 0 xFFF#define ATV_TOP_OVM_COMP__PRE 0 x0#define ATV_TOP_OUT_CONF__A 0 xC1002A#define ATV_TOP_OUT_CONF__W 5 #define ATV_TOP_OUT_CONF__M 0 x1F#define ATV_TOP_OUT_CONF__PRE 0 x0#define ATV_TOP_OUT_CONF_CVBS_DAC_SIGN__B 0 #define ATV_TOP_OUT_CONF_CVBS_DAC_SIGN__W 1 #define ATV_TOP_OUT_CONF_CVBS_DAC_SIGN__M 0 x1#define ATV_TOP_OUT_CONF_CVBS_DAC_SIGN__PRE 0 x0#define ATV_TOP_OUT_CONF_CVBS_DAC_SIGN_UNSIGNED 0 x0#define ATV_TOP_OUT_CONF_CVBS_DAC_SIGN_SIGNED 0 x1#define ATV_TOP_OUT_CONF_SIF_DAC_SIGN__B 1 #define ATV_TOP_OUT_CONF_SIF_DAC_SIGN__W 1 #define ATV_TOP_OUT_CONF_SIF_DAC_SIGN__M 0 x2#define ATV_TOP_OUT_CONF_SIF_DAC_SIGN__PRE 0 x0#define ATV_TOP_OUT_CONF_SIF_DAC_SIGN_UNSIGNED 0 x0#define ATV_TOP_OUT_CONF_SIF_DAC_SIGN_SIGNED 0 x2#define ATV_TOP_OUT_CONF_SIF20_SIGN__B 2 #define ATV_TOP_OUT_CONF_SIF20_SIGN__W 1 #define ATV_TOP_OUT_CONF_SIF20_SIGN__M 0 x4#define ATV_TOP_OUT_CONF_SIF20_SIGN__PRE 0 x0#define ATV_TOP_OUT_CONF_SIF20_SIGN_UNSIGNED 0 x0#define ATV_TOP_OUT_CONF_SIF20_SIGN_SIGNED 0 x4#define ATV_TOP_OUT_CONF_CVBS_DAC_BR__B 3 #define ATV_TOP_OUT_CONF_CVBS_DAC_BR__W 1 #define ATV_TOP_OUT_CONF_CVBS_DAC_BR__M 0 x8#define ATV_TOP_OUT_CONF_CVBS_DAC_BR__PRE 0 x0#define ATV_TOP_OUT_CONF_CVBS_DAC_BR_NORMAL 0 x0#define ATV_TOP_OUT_CONF_CVBS_DAC_BR_BITREVERSED 0 x8#define ATV_TOP_OUT_CONF_SIF_DAC_BR__B 4 #define ATV_TOP_OUT_CONF_SIF_DAC_BR__W 1 #define ATV_TOP_OUT_CONF_SIF_DAC_BR__M 0 x10#define ATV_TOP_OUT_CONF_SIF_DAC_BR__PRE 0 x0#define ATV_TOP_OUT_CONF_SIF_DAC_BR_NORMAL 0 x0#define ATV_TOP_OUT_CONF_SIF_DAC_BR_BITREVERSED 0 x10#define ATV_AFT_COMM_EXEC__A 0 xFF0000#define ATV_AFT_COMM_EXEC__W 2 #define ATV_AFT_COMM_EXEC__M 0 x3#define ATV_AFT_COMM_EXEC__PRE 0 x0#define ATV_AFT_COMM_EXEC_STOP 0 x0#define ATV_AFT_COMM_EXEC_ACTIVE 0 x1#define ATV_AFT_COMM_EXEC_HOLD 0 x2#define ATV_AFT_TST__A 0 xFF0010#define ATV_AFT_TST__W 4 #define ATV_AFT_TST__M 0 xF#define ATV_AFT_TST__PRE 0 x0#define AUD_COMM_EXEC__A 0 x1000000#define AUD_COMM_EXEC__W 2 #define AUD_COMM_EXEC__M 0 x3#define AUD_COMM_EXEC__PRE 0 x0#define AUD_COMM_EXEC_STOP 0 x0#define AUD_COMM_EXEC_ACTIVE 0 x1#define AUD_COMM_MB__A 0 x1000002#define AUD_COMM_MB__W 16 #define AUD_COMM_MB__M 0 xFFFF#define AUD_COMM_MB__PRE 0 x0#define AUD_TOP_COMM_EXEC__A 0 x1010000#define AUD_TOP_COMM_EXEC__W 2 #define AUD_TOP_COMM_EXEC__M 0 x3#define AUD_TOP_COMM_EXEC__PRE 0 x0#define AUD_TOP_COMM_EXEC_STOP 0 x0#define AUD_TOP_COMM_EXEC_ACTIVE 0 x1#define AUD_TOP_COMM_MB__A 0 x1010002#define AUD_TOP_COMM_MB__W 16 #define AUD_TOP_COMM_MB__M 0 xFFFF#define AUD_TOP_COMM_MB__PRE 0 x0#define AUD_TOP_COMM_MB_CTL__B 0 #define AUD_TOP_COMM_MB_CTL__W 1 #define AUD_TOP_COMM_MB_CTL__M 0 x1#define AUD_TOP_COMM_MB_CTL__PRE 0 x0#define AUD_TOP_COMM_MB_CTL_CTR_OFF 0 x0#define AUD_TOP_COMM_MB_CTL_CTR_ON 0 x1#define AUD_TOP_COMM_MB_OBS__B 1 #define AUD_TOP_COMM_MB_OBS__W 1 #define AUD_TOP_COMM_MB_OBS__M 0 x2#define AUD_TOP_COMM_MB_OBS__PRE 0 x0#define AUD_TOP_COMM_MB_OBS_OBS_OFF 0 x0#define AUD_TOP_COMM_MB_OBS_OBS_ON 0 x2#define AUD_TOP_COMM_MB_MUX_CTRL__B 2 #define AUD_TOP_COMM_MB_MUX_CTRL__W 4 #define AUD_TOP_COMM_MB_MUX_CTRL__M 0 x3C#define AUD_TOP_COMM_MB_MUX_CTRL__PRE 0 x0#define AUD_TOP_COMM_MB_MUX_CTRL_DEMOD_TBO 0 x0#define AUD_TOP_COMM_MB_MUX_CTRL_XDFP_IRQS 0 x4#define AUD_TOP_COMM_MB_MUX_CTRL_OBSERVEPC 0 x8#define AUD_TOP_COMM_MB_MUX_CTRL_SAOUT 0 xC#define AUD_TOP_COMM_MB_MUX_CTRL_XDFP_SCHEQ 0 x10#define AUD_TOP_COMM_MB_MUX_OBS__B 6 #define AUD_TOP_COMM_MB_MUX_OBS__W 4 #define AUD_TOP_COMM_MB_MUX_OBS__M 0 x3C0#define AUD_TOP_COMM_MB_MUX_OBS__PRE 0 x0#define AUD_TOP_COMM_MB_MUX_OBS_DEMOD_TBO 0 x0#define AUD_TOP_COMM_MB_MUX_OBS_XDFP_IRQS 0 x40#define AUD_TOP_COMM_MB_MUX_OBS_OBSERVEPC 0 x80#define AUD_TOP_COMM_MB_MUX_OBS_SAOUT 0 xC0#define AUD_TOP_COMM_MB_MUX_OBS_XDFP_SCHEQ 0 x100#define AUD_TOP_TR_MDE__A 0 x1010010#define AUD_TOP_TR_MDE__W 5 #define AUD_TOP_TR_MDE__M 0 x1F#define AUD_TOP_TR_MDE__PRE 0 x18#define AUD_TOP_TR_MDE_FIFO_SIZE__B 0 #define AUD_TOP_TR_MDE_FIFO_SIZE__W 4 #define AUD_TOP_TR_MDE_FIFO_SIZE__M 0 xF#define AUD_TOP_TR_MDE_FIFO_SIZE__PRE 0 x8#define AUD_TOP_TR_MDE_RD_LOCK__B 4 #define AUD_TOP_TR_MDE_RD_LOCK__W 1 #define AUD_TOP_TR_MDE_RD_LOCK__M 0 x10#define AUD_TOP_TR_MDE_RD_LOCK__PRE 0 x10#define AUD_TOP_TR_MDE_RD_LOCK_NORMAL 0 x0#define AUD_TOP_TR_MDE_RD_LOCK_LOCK 0 x10#define AUD_TOP_TR_CTR__A 0 x1010011#define AUD_TOP_TR_CTR__W 4 #define AUD_TOP_TR_CTR__M 0 xF#define AUD_TOP_TR_CTR__PRE 0 x0#define AUD_TOP_TR_CTR_FIFO_RD_RDY__B 0 #define AUD_TOP_TR_CTR_FIFO_RD_RDY__W 1 #define AUD_TOP_TR_CTR_FIFO_RD_RDY__M 0 x1#define AUD_TOP_TR_CTR_FIFO_RD_RDY__PRE 0 x0#define AUD_TOP_TR_CTR_FIFO_RD_RDY_NOT_READY 0 x0#define AUD_TOP_TR_CTR_FIFO_RD_RDY_READY 0 x1#define AUD_TOP_TR_CTR_FIFO_EMPTY__B 1 #define AUD_TOP_TR_CTR_FIFO_EMPTY__W 1 #define AUD_TOP_TR_CTR_FIFO_EMPTY__M 0 x2#define AUD_TOP_TR_CTR_FIFO_EMPTY__PRE 0 x0#define AUD_TOP_TR_CTR_FIFO_EMPTY_NOT_EMPTY 0 x0#define AUD_TOP_TR_CTR_FIFO_EMPTY_EMPTY 0 x2#define AUD_TOP_TR_CTR_FIFO_LOCK__B 2 #define AUD_TOP_TR_CTR_FIFO_LOCK__W 1 #define AUD_TOP_TR_CTR_FIFO_LOCK__M 0 x4#define AUD_TOP_TR_CTR_FIFO_LOCK__PRE 0 x0#define AUD_TOP_TR_CTR_FIFO_LOCK_UNLOCKED 0 x0#define AUD_TOP_TR_CTR_FIFO_LOCK_LOCKED 0 x4#define AUD_TOP_TR_CTR_FIFO_FULL__B 3 #define AUD_TOP_TR_CTR_FIFO_FULL__W 1 #define AUD_TOP_TR_CTR_FIFO_FULL__M 0 x8#define AUD_TOP_TR_CTR_FIFO_FULL__PRE 0 x0#define AUD_TOP_TR_CTR_FIFO_FULL_EMPTY 0 x0#define AUD_TOP_TR_CTR_FIFO_FULL_FULL 0 x8#define AUD_TOP_TR_RD_REG__A 0 x1010012#define AUD_TOP_TR_RD_REG__W 16 #define AUD_TOP_TR_RD_REG__M 0 xFFFF#define AUD_TOP_TR_RD_REG__PRE 0 x0#define AUD_TOP_TR_RD_REG_RESULT__B 0 #define AUD_TOP_TR_RD_REG_RESULT__W 16 #define AUD_TOP_TR_RD_REG_RESULT__M 0 xFFFF#define AUD_TOP_TR_RD_REG_RESULT__PRE 0 x0#define AUD_TOP_TR_TIMER__A 0 x1010013#define AUD_TOP_TR_TIMER__W 16 #define AUD_TOP_TR_TIMER__M 0 xFFFF#define AUD_TOP_TR_TIMER__PRE 0 x0#define AUD_TOP_TR_TIMER_CYCLES__B 0 #define AUD_TOP_TR_TIMER_CYCLES__W 16 #define AUD_TOP_TR_TIMER_CYCLES__M 0 xFFFF#define AUD_TOP_TR_TIMER_CYCLES__PRE 0 x0#define AUD_TOP_DEMOD_TBO_SEL__A 0 x1010014#define AUD_TOP_DEMOD_TBO_SEL__W 5 #define AUD_TOP_DEMOD_TBO_SEL__M 0 x1F#define AUD_TOP_DEMOD_TBO_SEL__PRE 0 x0#define AUD_DEM_WR_MODUS__A 0 x1030030#define AUD_DEM_WR_MODUS__W 16 #define AUD_DEM_WR_MODUS__M 0 xFFFF#define AUD_DEM_WR_MODUS__PRE 0 x0#define AUD_DEM_WR_MODUS_MOD_ASS__B 0 #define AUD_DEM_WR_MODUS_MOD_ASS__W 1 #define AUD_DEM_WR_MODUS_MOD_ASS__M 0 x1#define AUD_DEM_WR_MODUS_MOD_ASS__PRE 0 x0#define AUD_DEM_WR_MODUS_MOD_ASS_OFF 0 x0#define AUD_DEM_WR_MODUS_MOD_ASS_ON 0 x1#define AUD_DEM_WR_MODUS_MOD_STATINTERR__B 1 #define AUD_DEM_WR_MODUS_MOD_STATINTERR__W 1 #define AUD_DEM_WR_MODUS_MOD_STATINTERR__M 0 x2#define AUD_DEM_WR_MODUS_MOD_STATINTERR__PRE 0 x0#define AUD_DEM_WR_MODUS_MOD_STATINTERR_DISABLE 0 x0#define AUD_DEM_WR_MODUS_MOD_STATINTERR_ENABLE 0 x2#define AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG__B 2 #define AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG__W 1 #define AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG__M 0 x4#define AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG__PRE 0 x0#define AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG_ENABLED 0 x0#define AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG_DISABLED 0 x4#define AUD_DEM_WR_MODUS_MOD_HDEV_A__B 8 #define AUD_DEM_WR_MODUS_MOD_HDEV_A__W 1 #define AUD_DEM_WR_MODUS_MOD_HDEV_A__M 0 x100#define AUD_DEM_WR_MODUS_MOD_HDEV_A__PRE 0 x0#define AUD_DEM_WR_MODUS_MOD_HDEV_A_NORMAL 0 x0#define AUD_DEM_WR_MODUS_MOD_HDEV_A_HIGH_DEVIATION 0 x100#define AUD_DEM_WR_MODUS_MOD_CM_A__B 9 #define AUD_DEM_WR_MODUS_MOD_CM_A__W 1 #define AUD_DEM_WR_MODUS_MOD_CM_A__M 0 x200#define AUD_DEM_WR_MODUS_MOD_CM_A__PRE 0 x0#define AUD_DEM_WR_MODUS_MOD_CM_A_MUTE 0 x0#define AUD_DEM_WR_MODUS_MOD_CM_A_NOISE 0 x200#define AUD_DEM_WR_MODUS_MOD_CM_B__B 10 #define AUD_DEM_WR_MODUS_MOD_CM_B__W 1 #define AUD_DEM_WR_MODUS_MOD_CM_B__M 0 x400#define AUD_DEM_WR_MODUS_MOD_CM_B__PRE 0 x0#define AUD_DEM_WR_MODUS_MOD_CM_B_MUTE 0 x0#define AUD_DEM_WR_MODUS_MOD_CM_B_NOISE 0 x400#define AUD_DEM_WR_MODUS_MOD_FMRADIO__B 11 #define AUD_DEM_WR_MODUS_MOD_FMRADIO__W 1 #define AUD_DEM_WR_MODUS_MOD_FMRADIO__M 0 x800#define AUD_DEM_WR_MODUS_MOD_FMRADIO__PRE 0 x0#define AUD_DEM_WR_MODUS_MOD_FMRADIO_US_75U 0 x0#define AUD_DEM_WR_MODUS_MOD_FMRADIO_EU_50U 0 x800#define AUD_DEM_WR_MODUS_MOD_6_5MHZ__B 12 #define AUD_DEM_WR_MODUS_MOD_6_5MHZ__W 1 #define AUD_DEM_WR_MODUS_MOD_6_5MHZ__M 0 x1000#define AUD_DEM_WR_MODUS_MOD_6_5MHZ__PRE 0 x0#define AUD_DEM_WR_MODUS_MOD_6_5MHZ_SECAM 0 x0#define AUD_DEM_WR_MODUS_MOD_6_5MHZ_D_K 0 x1000#define AUD_DEM_WR_MODUS_MOD_4_5MHZ__B 13 #define AUD_DEM_WR_MODUS_MOD_4_5MHZ__W 2 #define AUD_DEM_WR_MODUS_MOD_4_5MHZ__M 0 x6000#define AUD_DEM_WR_MODUS_MOD_4_5MHZ__PRE 0 x0#define AUD_DEM_WR_MODUS_MOD_4_5MHZ_M_KOREA 0 x0#define AUD_DEM_WR_MODUS_MOD_4_5MHZ_M_BTSC 0 x2000#define AUD_DEM_WR_MODUS_MOD_4_5MHZ_M_EIAJ 0 x4000#define AUD_DEM_WR_MODUS_MOD_4_5MHZ_CHROMA 0 x6000#define AUD_DEM_WR_MODUS_MOD_BTSC__B 15 #define AUD_DEM_WR_MODUS_MOD_BTSC__W 1 #define AUD_DEM_WR_MODUS_MOD_BTSC__M 0 x8000#define AUD_DEM_WR_MODUS_MOD_BTSC__PRE 0 x0#define AUD_DEM_WR_MODUS_MOD_BTSC_BTSC_STEREO 0 x0#define AUD_DEM_WR_MODUS_MOD_BTSC_BTSC_SAP 0 x8000#define AUD_DEM_WR_STANDARD_SEL__A 0 x1030020#define AUD_DEM_WR_STANDARD_SEL__W 16 #define AUD_DEM_WR_STANDARD_SEL__M 0 xFFFF#define AUD_DEM_WR_STANDARD_SEL__PRE 0 x0#define AUD_DEM_WR_STANDARD_SEL_STD_SEL__B 0 #define AUD_DEM_WR_STANDARD_SEL_STD_SEL__W 12 #define AUD_DEM_WR_STANDARD_SEL_STD_SEL__M 0 xFFF#define AUD_DEM_WR_STANDARD_SEL_STD_SEL__PRE 0 x0#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_AUTO 0 x1#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_M_KOREA 0 x2#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_BG_FM 0 x3#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_D_K1 0 x4#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_D_K2 0 x5#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_D_K3 0 x7#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_BG_NICAM_FM 0 x8#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_L_NICAM_AM 0 x9#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_I_NICAM_FM 0 xA#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_D_K_NICAM_FM 0 xB#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_BTSC_STEREO 0 x20#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_BTSC_SAP 0 x21#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_EIA_J 0 x30#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_FM_RADIO 0 x40#define AUD_DEM_RD_STANDARD_RES__A 0 x102007E#define AUD_DEM_RD_STANDARD_RES__W 16 #define AUD_DEM_RD_STANDARD_RES__M 0 xFFFF#define AUD_DEM_RD_STANDARD_RES__PRE 0 x0#define AUD_DEM_RD_STANDARD_RES_STD_RESULT__B 0 #define AUD_DEM_RD_STANDARD_RES_STD_RESULT__W 16 #define AUD_DEM_RD_STANDARD_RES_STD_RESULT__M 0 xFFFF#define AUD_DEM_RD_STANDARD_RES_STD_RESULT__PRE 0 x0#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_NO_SOUND_STANDARD 0 x0#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_NTSC_M_DUAL_CARRIER_FM 0 x2#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_B_G_DUAL_CARRIER_FM 0 x3#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_D_K1_DUAL_CARRIER_FM 0 x4#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_D_K2_DUAL_CARRIER_FM 0 x5#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_D_K3_DUAL_CARRIER_FM 0 x7#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_B_G_NICAM_FM 0 x8#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_L_NICAM_AM 0 x9#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_I_NICAM_FM 0 xA#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_D_K_NICAM_FM 0 xB#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_BTSC_STEREO 0 x20#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_BTSC_MONO_SAP 0 x21#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_NTSC_EIA_J 0 x30#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_FM_RADIO 0 x40#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_DETECTION_STILL_ACTIVE 0 x7FF#define AUD_DEM_RD_STATUS__A 0 x1020200#define AUD_DEM_RD_STATUS__W 16 #define AUD_DEM_RD_STATUS__M 0 xFFFF#define AUD_DEM_RD_STATUS__PRE 0 x0#define AUD_DEM_RD_STATUS_STAT_NEW_RDS__B 0 #define AUD_DEM_RD_STATUS_STAT_NEW_RDS__W 1 #define AUD_DEM_RD_STATUS_STAT_NEW_RDS__M 0 x1#define AUD_DEM_RD_STATUS_STAT_NEW_RDS__PRE 0 x0#define AUD_DEM_RD_STATUS_STAT_NEW_RDS_NO_RDS_DATA 0 x0#define AUD_DEM_RD_STATUS_STAT_NEW_RDS_NEW_RDS_DATA 0 x1#define AUD_DEM_RD_STATUS_STAT_CARR_A__B 1 #define AUD_DEM_RD_STATUS_STAT_CARR_A__W 1 #define AUD_DEM_RD_STATUS_STAT_CARR_A__M 0 x2#define AUD_DEM_RD_STATUS_STAT_CARR_A__PRE 0 x0#define AUD_DEM_RD_STATUS_STAT_CARR_A_DETECTED 0 x0#define AUD_DEM_RD_STATUS_STAT_CARR_A_NOT_DETECTED 0 x2#define AUD_DEM_RD_STATUS_STAT_CARR_B__B 2 #define AUD_DEM_RD_STATUS_STAT_CARR_B__W 1 #define AUD_DEM_RD_STATUS_STAT_CARR_B__M 0 x4#define AUD_DEM_RD_STATUS_STAT_CARR_B__PRE 0 x0#define AUD_DEM_RD_STATUS_STAT_CARR_B_DETECTED 0 x0#define AUD_DEM_RD_STATUS_STAT_CARR_B_NOT_DETECTED 0 x4#define AUD_DEM_RD_STATUS_STAT_NICAM__B 5 #define AUD_DEM_RD_STATUS_STAT_NICAM__W 1 #define AUD_DEM_RD_STATUS_STAT_NICAM__M 0 x20#define AUD_DEM_RD_STATUS_STAT_NICAM__PRE 0 x0#define AUD_DEM_RD_STATUS_STAT_NICAM_NO_NICAM 0 x0#define AUD_DEM_RD_STATUS_STAT_NICAM_NICAM_DETECTED 0 x20#define AUD_DEM_RD_STATUS_STAT_STEREO__B 6 #define AUD_DEM_RD_STATUS_STAT_STEREO__W 1 #define AUD_DEM_RD_STATUS_STAT_STEREO__M 0 x40#define AUD_DEM_RD_STATUS_STAT_STEREO__PRE 0 x0#define AUD_DEM_RD_STATUS_STAT_STEREO_NO_STEREO 0 x0#define AUD_DEM_RD_STATUS_STAT_STEREO_STEREO 0 x40#define AUD_DEM_RD_STATUS_STAT_INDEP_MONO__B 7 #define AUD_DEM_RD_STATUS_STAT_INDEP_MONO__W 1 #define AUD_DEM_RD_STATUS_STAT_INDEP_MONO__M 0 x80#define AUD_DEM_RD_STATUS_STAT_INDEP_MONO__PRE 0 x0#define AUD_DEM_RD_STATUS_STAT_INDEP_MONO_DEPENDENT_FM_MONO_PROGRAM 0 x0#define AUD_DEM_RD_STATUS_STAT_INDEP_MONO_INDEPENDENT_FM_MONO_PROGRAM 0 x80#define AUD_DEM_RD_STATUS_STAT_BIL_OR_SAP__B 8 #define AUD_DEM_RD_STATUS_STAT_BIL_OR_SAP__W 1 #define AUD_DEM_RD_STATUS_STAT_BIL_OR_SAP__M 0 x100#define AUD_DEM_RD_STATUS_STAT_BIL_OR_SAP__PRE 0 x0#define AUD_DEM_RD_STATUS_STAT_BIL_OR_SAP_NO_SAP 0 x0#define AUD_DEM_RD_STATUS_STAT_BIL_OR_SAP_SAP 0 x100#define AUD_DEM_RD_STATUS_BAD_NICAM__B 9 #define AUD_DEM_RD_STATUS_BAD_NICAM__W 1 #define AUD_DEM_RD_STATUS_BAD_NICAM__M 0 x200#define AUD_DEM_RD_STATUS_BAD_NICAM__PRE 0 x0#define AUD_DEM_RD_STATUS_BAD_NICAM_OK 0 x0#define AUD_DEM_RD_STATUS_BAD_NICAM_BAD 0 x200#define AUD_DEM_RD_RDS_ARRAY_CNT__A 0 x102020F#define AUD_DEM_RD_RDS_ARRAY_CNT__W 12 #define AUD_DEM_RD_RDS_ARRAY_CNT__M 0 xFFF#define AUD_DEM_RD_RDS_ARRAY_CNT__PRE 0 x0#define AUD_DEM_RD_RDS_ARRAY_CNT_RDS_ARRAY_CT__B 0 #define AUD_DEM_RD_RDS_ARRAY_CNT_RDS_ARRAY_CT__W 12 #define AUD_DEM_RD_RDS_ARRAY_CNT_RDS_ARRAY_CT__M 0 xFFF#define AUD_DEM_RD_RDS_ARRAY_CNT_RDS_ARRAY_CT__PRE 0 x0#define AUD_DEM_RD_RDS_ARRAY_CNT_RDS_ARRAY_CT_RDS_DATA_NOT_VALID 0 xFFF#define AUD_DEM_RD_RDS_DATA__A 0 x1020210#define AUD_DEM_RD_RDS_DATA__W 12 #define AUD_DEM_RD_RDS_DATA__M 0 xFFF#define AUD_DEM_RD_RDS_DATA__PRE 0 x0#define AUD_DSP_WR_FM_PRESC__A 0 x105000E#define AUD_DSP_WR_FM_PRESC__W 16 #define AUD_DSP_WR_FM_PRESC__M 0 xFFFF#define AUD_DSP_WR_FM_PRESC__PRE 0 x0#define AUD_DSP_WR_FM_PRESC_FM_AM_PRESC__B 8 #define AUD_DSP_WR_FM_PRESC_FM_AM_PRESC__W 8 #define AUD_DSP_WR_FM_PRESC_FM_AM_PRESC__M 0 xFF00#define AUD_DSP_WR_FM_PRESC_FM_AM_PRESC__PRE 0 x0#define AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_28_KHZ_FM_DEVIATION 0 x7F00#define AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_50_KHZ_FM_DEVIATION 0 x4800#define AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_75_KHZ_FM_DEVIATION 0 x3000#define AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_100_KHZ_FM_DEVIATION 0 x2400#define AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_150_KHZ_FM_DEVIATION 0 x1800#define AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_180_KHZ_FM_DEVIATION 0 x1300#define AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_380_KHZ_FM_DEVIATION 0 x900#define AUD_DSP_WR_NICAM_PRESC__A 0 x1050010#define AUD_DSP_WR_NICAM_PRESC__W 16 #define AUD_DSP_WR_NICAM_PRESC__M 0 xFFFF#define AUD_DSP_WR_NICAM_PRESC__PRE 0 x0#define AUD_DSP_WR_VOLUME__A 0 x1050000#define AUD_DSP_WR_VOLUME__W 16 #define AUD_DSP_WR_VOLUME__M 0 xFFFF#define AUD_DSP_WR_VOLUME__PRE 0 x0#define AUD_DSP_WR_VOLUME_VOL_MAIN__B 8 #define AUD_DSP_WR_VOLUME_VOL_MAIN__W 8 #define AUD_DSP_WR_VOLUME_VOL_MAIN__M 0 xFF00#define AUD_DSP_WR_VOLUME_VOL_MAIN__PRE 0 x0#define AUD_DSP_WR_SRC_I2S_MATR__A 0 x1050038#define AUD_DSP_WR_SRC_I2S_MATR__W 16 #define AUD_DSP_WR_SRC_I2S_MATR__M 0 xFFFF#define AUD_DSP_WR_SRC_I2S_MATR__PRE 0 x0#define AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S__B 8 #define AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S__W 8 #define AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S__M 0 xFF00#define AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S__PRE 0 x0#define AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_MONO 0 x0#define AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_STEREO_AB 0 x100#define AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_STEREO_A 0 x300#define AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_STEREO_B 0 x400#define AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S__B 0 #define AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S__W 8 #define AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S__M 0 xFF#define AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S__PRE 0 x0#define AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_SOUND_A 0 x0#define AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_SOUND_B 0 x10#define AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_STEREO 0 x20#define AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_MONO 0 x30#define AUD_DSP_WR_AVC__A 0 x1050029#define AUD_DSP_WR_AVC__W 16 #define AUD_DSP_WR_AVC__M 0 xFFFF#define AUD_DSP_WR_AVC__PRE 0 x0#define AUD_DSP_WR_AVC_AVC_ON__B 14 #define AUD_DSP_WR_AVC_AVC_ON__W 2 #define AUD_DSP_WR_AVC_AVC_ON__M 0 xC000#define AUD_DSP_WR_AVC_AVC_ON__PRE 0 x0#define AUD_DSP_WR_AVC_AVC_ON_OFF 0 x0#define AUD_DSP_WR_AVC_AVC_ON_ON 0 xC000#define AUD_DSP_WR_AVC_AVC_DECAY__B 8 #define AUD_DSP_WR_AVC_AVC_DECAY__W 4 #define AUD_DSP_WR_AVC_AVC_DECAY__M 0 xF00#define AUD_DSP_WR_AVC_AVC_DECAY__PRE 0 x0#define AUD_DSP_WR_AVC_AVC_DECAY_8_SEC 0 x800#define AUD_DSP_WR_AVC_AVC_DECAY_4_SEC 0 x400#define AUD_DSP_WR_AVC_AVC_DECAY_2_SEC 0 x200#define AUD_DSP_WR_AVC_AVC_DECAY_20_MSEC 0 x100#define AUD_DSP_WR_AVC_AVC_REF_LEV__B 4 #define AUD_DSP_WR_AVC_AVC_REF_LEV__W 4 #define AUD_DSP_WR_AVC_AVC_REF_LEV__M 0 xF0#define AUD_DSP_WR_AVC_AVC_REF_LEV__PRE 0 x0#define AUD_DSP_WR_AVC_AVC_MAX_ATT__B 2 #define AUD_DSP_WR_AVC_AVC_MAX_ATT__W 2 #define AUD_DSP_WR_AVC_AVC_MAX_ATT__M 0 xC#define AUD_DSP_WR_AVC_AVC_MAX_ATT__PRE 0 x0#define AUD_DSP_WR_AVC_AVC_MAX_ATT_24DB 0 x0#define AUD_DSP_WR_AVC_AVC_MAX_ATT_18DB 0 x4#define AUD_DSP_WR_AVC_AVC_MAX_ATT_12DB 0 x8#define AUD_DSP_WR_AVC_AVC_MAX_GAIN__B 0 #define AUD_DSP_WR_AVC_AVC_MAX_GAIN__W 2 #define AUD_DSP_WR_AVC_AVC_MAX_GAIN__M 0 x3#define AUD_DSP_WR_AVC_AVC_MAX_GAIN__PRE 0 x0#define AUD_DSP_WR_AVC_AVC_MAX_GAIN_6DB 0 x0#define AUD_DSP_WR_AVC_AVC_MAX_GAIN_12DB 0 x1#define AUD_DSP_WR_AVC_AVC_MAX_GAIN_0DB 0 x3#define AUD_DSP_WR_QPEAK__A 0 x105000C#define AUD_DSP_WR_QPEAK__W 16 #define AUD_DSP_WR_QPEAK__M 0 xFFFF#define AUD_DSP_WR_QPEAK__PRE 0 x0#define AUD_DSP_WR_QPEAK_SRC_QP__B 8 #define AUD_DSP_WR_QPEAK_SRC_QP__W 8 #define AUD_DSP_WR_QPEAK_SRC_QP__M 0 xFF00#define AUD_DSP_WR_QPEAK_SRC_QP__PRE 0 x0#define AUD_DSP_WR_QPEAK_SRC_QP_MONO 0 x0#define AUD_DSP_WR_QPEAK_SRC_QP_STEREO_AB 0 x100#define AUD_DSP_WR_QPEAK_SRC_QP_STEREO_A 0 x300#define AUD_DSP_WR_QPEAK_SRC_QP_STEREO_B 0 x400#define AUD_DSP_WR_QPEAK_MAT_QP__B 0 #define AUD_DSP_WR_QPEAK_MAT_QP__W 8 #define AUD_DSP_WR_QPEAK_MAT_QP__M 0 xFF#define AUD_DSP_WR_QPEAK_MAT_QP__PRE 0 x0#define AUD_DSP_WR_QPEAK_MAT_QP_SOUND_A 0 x0#define AUD_DSP_WR_QPEAK_MAT_QP_SOUND_B 0 x10#define AUD_DSP_WR_QPEAK_MAT_QP_STEREO 0 x20#define AUD_DSP_WR_QPEAK_MAT_QP_MONO 0 x30#define AUD_DSP_RD_QPEAK_L__A 0 x1040019#define AUD_DSP_RD_QPEAK_L__W 16 #define AUD_DSP_RD_QPEAK_L__M 0 xFFFF#define AUD_DSP_RD_QPEAK_L__PRE 0 x0#define AUD_DSP_RD_QPEAK_R__A 0 x104001A#define AUD_DSP_RD_QPEAK_R__W 16 #define AUD_DSP_RD_QPEAK_R__M 0 xFFFF#define AUD_DSP_RD_QPEAK_R__PRE 0 x0#define AUD_DSP_WR_BEEPER__A 0 x1050014#define AUD_DSP_WR_BEEPER__W 16 #define AUD_DSP_WR_BEEPER__M 0 xFFFF#define AUD_DSP_WR_BEEPER__PRE 0 x0#define AUD_DSP_WR_BEEPER_BEEP_VOLUME__B 8 #define AUD_DSP_WR_BEEPER_BEEP_VOLUME__W 7 #define AUD_DSP_WR_BEEPER_BEEP_VOLUME__M 0 x7F00#define AUD_DSP_WR_BEEPER_BEEP_VOLUME__PRE 0 x0#define AUD_DSP_WR_BEEPER_BEEP_FREQUENCY__B 0 #define AUD_DSP_WR_BEEPER_BEEP_FREQUENCY__W 7 #define AUD_DSP_WR_BEEPER_BEEP_FREQUENCY__M 0 x7F#define AUD_DSP_WR_BEEPER_BEEP_FREQUENCY__PRE 0 x0#define AUD_DEM_WR_I2S_CONFIG2__A 0 x1030050#define AUD_DEM_WR_I2S_CONFIG2__W 16 #define AUD_DEM_WR_I2S_CONFIG2__M 0 xFFFF#define AUD_DEM_WR_I2S_CONFIG2__PRE 0 x0#define AUD_DEM_WR_I2S_CONFIG2_I2S_CL_POL__B 6 #define AUD_DEM_WR_I2S_CONFIG2_I2S_CL_POL__W 1 #define AUD_DEM_WR_I2S_CONFIG2_I2S_CL_POL__M 0 x40#define AUD_DEM_WR_I2S_CONFIG2_I2S_CL_POL__PRE 0 x0#define AUD_DEM_WR_I2S_CONFIG2_I2S_CL_POL_NORMAL 0 x0#define AUD_DEM_WR_I2S_CONFIG2_I2S_CL_POL_INVERTED 0 x40#define AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE__B 4 #define AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE__W 1 #define AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE__M 0 x10#define AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE__PRE 0 x0#define AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE_DISABLE 0 x0#define AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE_ENABLE 0 x10#define AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST__B 3 #define AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST__W 1 #define AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST__M 0 x8#define AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST__PRE 0 x0#define AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST_MASTER 0 x0#define AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST_SLAVE 0 x8#define AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL__B 2 #define AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL__W 1 #define AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL__M 0 x4#define AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL__PRE 0 x0#define AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL_LEFT_LOW 0 x0#define AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL_LEFT_HIGH 0 x4#define AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE__B 1 #define AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE__W 1 #define AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE__M 0 x2#define AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE__PRE 0 x0#define AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE_NO_DELAY 0 x0#define AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE_DELAY 0 x2#define AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN__B 0 #define AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN__W 1 #define AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN__M 0 x1#define AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN__PRE 0 x0#define AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN_BIT_32 0 x0#define AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN_BIT_16 0 x1#define AUD_DSP_WR_I2S_OUT_FS__A 0 x105002A#define AUD_DSP_WR_I2S_OUT_FS__W 16 #define AUD_DSP_WR_I2S_OUT_FS__M 0 xFFFF#define AUD_DSP_WR_I2S_OUT_FS__PRE 0 x0#define AUD_DSP_WR_I2S_OUT_FS_FS_OUT__B 0 #define AUD_DSP_WR_I2S_OUT_FS_FS_OUT__W 16 #define AUD_DSP_WR_I2S_OUT_FS_FS_OUT__M 0 xFFFF#define AUD_DSP_WR_I2S_OUT_FS_FS_OUT__PRE 0 x0#define AUD_DSP_WR_AV_SYNC__A 0 x105002B#define AUD_DSP_WR_AV_SYNC__W 16 #define AUD_DSP_WR_AV_SYNC__M 0 xFFFF#define AUD_DSP_WR_AV_SYNC__PRE 0 x0#define AUD_DSP_WR_AV_SYNC_AV_ON__B 15 #define AUD_DSP_WR_AV_SYNC_AV_ON__W 1 #define AUD_DSP_WR_AV_SYNC_AV_ON__M 0 x8000#define AUD_DSP_WR_AV_SYNC_AV_ON__PRE 0 x0#define AUD_DSP_WR_AV_SYNC_AV_ON_DISABLE 0 x0#define AUD_DSP_WR_AV_SYNC_AV_ON_ENABLE 0 x8000#define AUD_DSP_WR_AV_SYNC_AV_AUTO_FREQ__B 14 #define AUD_DSP_WR_AV_SYNC_AV_AUTO_FREQ__W 1 #define AUD_DSP_WR_AV_SYNC_AV_AUTO_FREQ__M 0 x4000#define AUD_DSP_WR_AV_SYNC_AV_AUTO_FREQ__PRE 0 x0#define AUD_DSP_WR_AV_SYNC_AV_AUTO_FREQ_MONOCHROME 0 x0#define AUD_DSP_WR_AV_SYNC_AV_AUTO_FREQ_NTSC 0 x4000#define AUD_DSP_WR_AV_SYNC_AV_STD_SEL__B 0 #define AUD_DSP_WR_AV_SYNC_AV_STD_SEL__W 2 #define AUD_DSP_WR_AV_SYNC_AV_STD_SEL__M 0 x3#define AUD_DSP_WR_AV_SYNC_AV_STD_SEL__PRE 0 x0#define AUD_DSP_WR_AV_SYNC_AV_STD_SEL_AUTO 0 x0#define AUD_DSP_WR_AV_SYNC_AV_STD_SEL_PAL_SECAM 0 x1#define AUD_DSP_WR_AV_SYNC_AV_STD_SEL_NTSC 0 x2#define AUD_DSP_WR_AV_SYNC_AV_STD_SEL_MONOCHROME 0 x3#define AUD_DSP_RD_STATUS2__A 0 x104007B#define AUD_DSP_RD_STATUS2__W 16 #define AUD_DSP_RD_STATUS2__M 0 xFFFF#define AUD_DSP_RD_STATUS2__PRE 0 x0#define AUD_DSP_RD_STATUS2_AV_ACTIVE__B 15 #define AUD_DSP_RD_STATUS2_AV_ACTIVE__W 1 #define AUD_DSP_RD_STATUS2_AV_ACTIVE__M 0 x8000#define AUD_DSP_RD_STATUS2_AV_ACTIVE__PRE 0 x0#define AUD_DSP_RD_STATUS2_AV_ACTIVE_NO_SYNC 0 x0#define AUD_DSP_RD_STATUS2_AV_ACTIVE_SYNC_ACTIVE 0 x8000#define AUD_DSP_RD_XDFP_FW__A 0 x104001D#define AUD_DSP_RD_XDFP_FW__W 16 #define AUD_DSP_RD_XDFP_FW__M 0 xFFFF#define AUD_DSP_RD_XDFP_FW__PRE 0 x344#define AUD_DSP_RD_XDFP_FW_DSP_FW_REV__B 0 #define AUD_DSP_RD_XDFP_FW_DSP_FW_REV__W 16 #define AUD_DSP_RD_XDFP_FW_DSP_FW_REV__M 0 xFFFF#define AUD_DSP_RD_XDFP_FW_DSP_FW_REV__PRE 0 x344#define AUD_DSP_RD_XFP_FW__A 0 x10404B8#define AUD_DSP_RD_XFP_FW__W 16 #define AUD_DSP_RD_XFP_FW__M 0 xFFFF#define AUD_DSP_RD_XFP_FW__PRE 0 x42#define AUD_DSP_RD_XFP_FW_FP_FW_REV__B 0 #define AUD_DSP_RD_XFP_FW_FP_FW_REV__W 16 #define AUD_DSP_RD_XFP_FW_FP_FW_REV__M 0 xFFFF#define AUD_DSP_RD_XFP_FW_FP_FW_REV__PRE 0 x42#define AUD_DEM_WR_DCO_B_HI__A 0 x103009B#define AUD_DEM_WR_DCO_B_HI__W 16 #define AUD_DEM_WR_DCO_B_HI__M 0 xFFFF#define AUD_DEM_WR_DCO_B_HI__PRE 0 x0#define AUD_DEM_WR_DCO_B_LO__A 0 x1030093#define AUD_DEM_WR_DCO_B_LO__W 16 #define AUD_DEM_WR_DCO_B_LO__M 0 xFFFF#define AUD_DEM_WR_DCO_B_LO__PRE 0 x0#define AUD_DEM_WR_DCO_A_HI__A 0 x10300AB#define AUD_DEM_WR_DCO_A_HI__W 16 #define AUD_DEM_WR_DCO_A_HI__M 0 xFFFF#define AUD_DEM_WR_DCO_A_HI__PRE 0 x0#define AUD_DEM_WR_DCO_A_LO__A 0 x10300A3#define AUD_DEM_WR_DCO_A_LO__W 16 #define AUD_DEM_WR_DCO_A_LO__M 0 xFFFF#define AUD_DEM_WR_DCO_A_LO__PRE 0 x0#define AUD_DEM_WR_NICAM_THRSHLD__A 0 x1030021#define AUD_DEM_WR_NICAM_THRSHLD__W 16 #define AUD_DEM_WR_NICAM_THRSHLD__M 0 xFFFF#define AUD_DEM_WR_NICAM_THRSHLD__PRE 0 x2BC#define AUD_DEM_WR_NICAM_THRSHLD_NICAM_THLD__B 0 #define AUD_DEM_WR_NICAM_THRSHLD_NICAM_THLD__W 12 #define AUD_DEM_WR_NICAM_THRSHLD_NICAM_THLD__M 0 xFFF#define AUD_DEM_WR_NICAM_THRSHLD_NICAM_THLD__PRE 0 x2BC#define AUD_DEM_WR_A2_THRSHLD__A 0 x1030022#define AUD_DEM_WR_A2_THRSHLD__W 16 #define AUD_DEM_WR_A2_THRSHLD__M 0 xFFFF#define AUD_DEM_WR_A2_THRSHLD__PRE 0 x190#define AUD_DEM_WR_A2_THRSHLD_A2_THLD__B 0 #define AUD_DEM_WR_A2_THRSHLD_A2_THLD__W 12 #define AUD_DEM_WR_A2_THRSHLD_A2_THLD__M 0 xFFF#define AUD_DEM_WR_A2_THRSHLD_A2_THLD__PRE 0 x190#define AUD_DEM_WR_BTSC_THRSHLD__A 0 x1030023#define AUD_DEM_WR_BTSC_THRSHLD__W 16 #define AUD_DEM_WR_BTSC_THRSHLD__M 0 xFFFF#define AUD_DEM_WR_BTSC_THRSHLD__PRE 0 xC#define AUD_DEM_WR_BTSC_THRSHLD_BTSC_THLD__B 0 #define AUD_DEM_WR_BTSC_THRSHLD_BTSC_THLD__W 12 #define AUD_DEM_WR_BTSC_THRSHLD_BTSC_THLD__M 0 xFFF#define AUD_DEM_WR_BTSC_THRSHLD_BTSC_THLD__PRE 0 xC#define AUD_DEM_WR_CM_A_THRSHLD__A 0 x1030024#define AUD_DEM_WR_CM_A_THRSHLD__W 16 #define AUD_DEM_WR_CM_A_THRSHLD__M 0 xFFFF#define AUD_DEM_WR_CM_A_THRSHLD__PRE 0 x2A#define AUD_DEM_WR_CM_A_THRSHLD_CM_A_THLD__B 0 #define AUD_DEM_WR_CM_A_THRSHLD_CM_A_THLD__W 12 #define AUD_DEM_WR_CM_A_THRSHLD_CM_A_THLD__M 0 xFFF#define AUD_DEM_WR_CM_A_THRSHLD_CM_A_THLD__PRE 0 x2A#define AUD_DEM_WR_CM_B_THRSHLD__A 0 x1030025#define AUD_DEM_WR_CM_B_THRSHLD__W 16 #define AUD_DEM_WR_CM_B_THRSHLD__M 0 xFFFF#define AUD_DEM_WR_CM_B_THRSHLD__PRE 0 x2A#define AUD_DEM_WR_CM_B_THRSHLD_CM_B_THLD__B 0 #define AUD_DEM_WR_CM_B_THRSHLD_CM_B_THLD__W 12 #define AUD_DEM_WR_CM_B_THRSHLD_CM_B_THLD__M 0 xFFF#define AUD_DEM_WR_CM_B_THRSHLD_CM_B_THLD__PRE 0 x2A#define AUD_DEM_RD_NIC_C_AD_BITS__A 0 x1020023#define AUD_DEM_RD_NIC_C_AD_BITS__W 16 #define AUD_DEM_RD_NIC_C_AD_BITS__M 0 xFFFF#define AUD_DEM_RD_NIC_C_AD_BITS__PRE 0 x0#define AUD_DEM_RD_NIC_C_AD_BITS_NICAM_SYNC__B 0 #define AUD_DEM_RD_NIC_C_AD_BITS_NICAM_SYNC__W 1 #define AUD_DEM_RD_NIC_C_AD_BITS_NICAM_SYNC__M 0 x1#define AUD_DEM_RD_NIC_C_AD_BITS_NICAM_SYNC__PRE 0 x0#define AUD_DEM_RD_NIC_C_AD_BITS_NICAM_SYNC_NOT_SYNCED 0 x0#define AUD_DEM_RD_NIC_C_AD_BITS_NICAM_SYNC_SYNCED 0 x1#define AUD_DEM_RD_NIC_C_AD_BITS_C__B 1 #define AUD_DEM_RD_NIC_C_AD_BITS_C__W 4 #define AUD_DEM_RD_NIC_C_AD_BITS_C__M 0 x1E#define AUD_DEM_RD_NIC_C_AD_BITS_C__PRE 0 x0#define AUD_DEM_RD_NIC_C_AD_BITS_ADD_BIT_LO__B 5 #define AUD_DEM_RD_NIC_C_AD_BITS_ADD_BIT_LO__W 3 #define AUD_DEM_RD_NIC_C_AD_BITS_ADD_BIT_LO__M 0 xE0#define AUD_DEM_RD_NIC_C_AD_BITS_ADD_BIT_LO__PRE 0 x0#define AUD_DEM_RD_NIC_ADD_BITS_HI__A 0 x1020038#define AUD_DEM_RD_NIC_ADD_BITS_HI__W 16 #define AUD_DEM_RD_NIC_ADD_BITS_HI__M 0 xFFFF#define AUD_DEM_RD_NIC_ADD_BITS_HI__PRE 0 x0#define AUD_DEM_RD_NIC_ADD_BITS_HI_ADD_BIT_HI__B 0 #define AUD_DEM_RD_NIC_ADD_BITS_HI_ADD_BIT_HI__W 8 #define AUD_DEM_RD_NIC_ADD_BITS_HI_ADD_BIT_HI__M 0 xFF#define AUD_DEM_RD_NIC_ADD_BITS_HI_ADD_BIT_HI__PRE 0 x0#define AUD_DEM_RD_NIC_CIB__A 0 x1020038#define AUD_DEM_RD_NIC_CIB__W 16 #define AUD_DEM_RD_NIC_CIB__M 0 xFFFF#define AUD_DEM_RD_NIC_CIB__PRE 0 x0#define AUD_DEM_RD_NIC_CIB_CIB2__B 0 #define AUD_DEM_RD_NIC_CIB_CIB2__W 1 #define AUD_DEM_RD_NIC_CIB_CIB2__M 0 x1#define AUD_DEM_RD_NIC_CIB_CIB2__PRE 0 x0#define AUD_DEM_RD_NIC_CIB_CIB1__B 1 #define AUD_DEM_RD_NIC_CIB_CIB1__W 1 #define AUD_DEM_RD_NIC_CIB_CIB1__M 0 x2#define AUD_DEM_RD_NIC_CIB_CIB1__PRE 0 x0#define AUD_DEM_RD_NIC_ERROR_RATE__A 0 x1020057#define AUD_DEM_RD_NIC_ERROR_RATE__W 16 #define AUD_DEM_RD_NIC_ERROR_RATE__M 0 xFFFF#define AUD_DEM_RD_NIC_ERROR_RATE__PRE 0 x0#define AUD_DEM_RD_NIC_ERROR_RATE_ERROR_RATE__B 0 #define AUD_DEM_RD_NIC_ERROR_RATE_ERROR_RATE__W 12 #define AUD_DEM_RD_NIC_ERROR_RATE_ERROR_RATE__M 0 xFFF#define AUD_DEM_RD_NIC_ERROR_RATE_ERROR_RATE__PRE 0 x0#define AUD_DEM_WR_FM_DEEMPH__A 0 x103000F#define AUD_DEM_WR_FM_DEEMPH__W 16 #define AUD_DEM_WR_FM_DEEMPH__M 0 xFFFF#define AUD_DEM_WR_FM_DEEMPH__PRE 0 x0#define AUD_DEM_WR_FM_DEEMPH_50US 0 x0#define AUD_DEM_WR_FM_DEEMPH_75US 0 x1#define AUD_DEM_WR_FM_DEEMPH_OFF 0 x3F#define AUD_DEM_WR_FM_MATRIX__A 0 x103006F#define AUD_DEM_WR_FM_MATRIX__W 16 #define AUD_DEM_WR_FM_MATRIX__M 0 xFFFF#define AUD_DEM_WR_FM_MATRIX__PRE 0 x0#define AUD_DEM_WR_FM_MATRIX_NO_MATRIX 0 x0#define AUD_DEM_WR_FM_MATRIX_GERMAN_MATRIX 0 x1#define AUD_DEM_WR_FM_MATRIX_KOREAN_MATRIX 0 x2#define AUD_DEM_WR_FM_MATRIX_SOUND_A 0 x3#define AUD_DEM_WR_FM_MATRIX_SOUND_B 0 x4#define AUD_DSP_RD_FM_IDENT_VALUE__A 0 x1040018#define AUD_DSP_RD_FM_IDENT_VALUE__W 16 #define AUD_DSP_RD_FM_IDENT_VALUE__M 0 xFFFF#define AUD_DSP_RD_FM_IDENT_VALUE__PRE 0 x0#define AUD_DSP_RD_FM_IDENT_VALUE_FM_IDENT__B 8 #define AUD_DSP_RD_FM_IDENT_VALUE_FM_IDENT__W 8 #define AUD_DSP_RD_FM_IDENT_VALUE_FM_IDENT__M 0 xFF00#define AUD_DSP_RD_FM_IDENT_VALUE_FM_IDENT__PRE 0 x0#define AUD_DSP_RD_FM_DC_LEVEL_A__A 0 x104001B#define AUD_DSP_RD_FM_DC_LEVEL_A__W 16 #define AUD_DSP_RD_FM_DC_LEVEL_A__M 0 xFFFF#define AUD_DSP_RD_FM_DC_LEVEL_A__PRE 0 x0#define AUD_DSP_RD_FM_DC_LEVEL_A_FM_DC_LEV_A__B 0 #define AUD_DSP_RD_FM_DC_LEVEL_A_FM_DC_LEV_A__W 16 #define AUD_DSP_RD_FM_DC_LEVEL_A_FM_DC_LEV_A__M 0 xFFFF#define AUD_DSP_RD_FM_DC_LEVEL_A_FM_DC_LEV_A__PRE 0 x0#define AUD_DSP_RD_FM_DC_LEVEL_B__A 0 x104001C#define AUD_DSP_RD_FM_DC_LEVEL_B__W 16 #define AUD_DSP_RD_FM_DC_LEVEL_B__M 0 xFFFF#define AUD_DSP_RD_FM_DC_LEVEL_B__PRE 0 x0#define AUD_DSP_RD_FM_DC_LEVEL_B_FM_DC_LEV_B__B 0 #define AUD_DSP_RD_FM_DC_LEVEL_B_FM_DC_LEV_B__W 16 #define AUD_DSP_RD_FM_DC_LEVEL_B_FM_DC_LEV_B__M 0 xFFFF#define AUD_DSP_RD_FM_DC_LEVEL_B_FM_DC_LEV_B__PRE 0 x0#define AUD_DEM_WR_FM_DC_NOTCH_SW__A 0 x1030017#define AUD_DEM_WR_FM_DC_NOTCH_SW__W 16 #define AUD_DEM_WR_FM_DC_NOTCH_SW__M 0 xFFFF#define AUD_DEM_WR_FM_DC_NOTCH_SW__PRE 0 x0#define AUD_DEM_WR_FM_DC_NOTCH_SW_FM_DC_NO_SW__B 0 #define AUD_DEM_WR_FM_DC_NOTCH_SW_FM_DC_NO_SW__W 16 #define AUD_DEM_WR_FM_DC_NOTCH_SW_FM_DC_NO_SW__M 0 xFFFF#define AUD_DEM_WR_FM_DC_NOTCH_SW_FM_DC_NO_SW__PRE 0 x0#define AUD_DEM_WR_FM_DC_NOTCH_SW_FM_DC_NO_SW_ON 0 x0#define AUD_DEM_WR_FM_DC_NOTCH_SW_FM_DC_NO_SW_OFF 0 x3F#define AUD_DSP_WR_SYNC_OUT__A 0 x1050026#define AUD_DSP_WR_SYNC_OUT__W 16 #define AUD_DSP_WR_SYNC_OUT__M 0 xFFFF#define AUD_DSP_WR_SYNC_OUT__PRE 0 x0#define AUD_DSP_WR_SYNC_OUT_OFF 0 x0#define AUD_DSP_WR_SYNC_OUT_SYNCHRONOUS 0 x1#define AUD_XFP_DRAM_1K__A 0 x1060000#define AUD_XFP_DRAM_1K__W 16 #define AUD_XFP_DRAM_1K__M 0 xFFFF#define AUD_XFP_DRAM_1K__PRE 0 x0#define AUD_XFP_DRAM_1K_D__B 0 #define AUD_XFP_DRAM_1K_D__W 16 #define AUD_XFP_DRAM_1K_D__M 0 xFFFF#define AUD_XFP_DRAM_1K_D__PRE 0 x0#define AUD_XFP_PRAM_4K__A 0 x1070000#define AUD_XFP_PRAM_4K__W 16 #define AUD_XFP_PRAM_4K__M 0 xFFFF#define AUD_XFP_PRAM_4K__PRE 0 x0#define AUD_XFP_PRAM_4K_D__B 0 #define AUD_XFP_PRAM_4K_D__W 16 #define AUD_XFP_PRAM_4K_D__M 0 xFFFF#define AUD_XFP_PRAM_4K_D__PRE 0 x0#define AUD_XDFP_DRAM_1K__A 0 x1080000#define AUD_XDFP_DRAM_1K__W 16 #define AUD_XDFP_DRAM_1K__M 0 xFFFF#define AUD_XDFP_DRAM_1K__PRE 0 x0#define AUD_XDFP_DRAM_1K_D__B 0 #define AUD_XDFP_DRAM_1K_D__W 16 #define AUD_XDFP_DRAM_1K_D__M 0 xFFFF#define AUD_XDFP_DRAM_1K_D__PRE 0 x0#define AUD_XDFP_PRAM_4K__A 0 x1090000#define AUD_XDFP_PRAM_4K__W 16 #define AUD_XDFP_PRAM_4K__M 0 xFFFF#define AUD_XDFP_PRAM_4K__PRE 0 x0#define AUD_XDFP_PRAM_4K_D__B 0 #define AUD_XDFP_PRAM_4K_D__W 16 #define AUD_XDFP_PRAM_4K_D__M 0 xFFFF#define AUD_XDFP_PRAM_4K_D__PRE 0 x0#define FEC_COMM_EXEC__A 0 x2400000#define FEC_COMM_EXEC__W 2 #define FEC_COMM_EXEC__M 0 x3#define FEC_COMM_EXEC__PRE 0 x0#define FEC_COMM_EXEC_STOP 0 x0#define FEC_COMM_EXEC_ACTIVE 0 x1#define FEC_COMM_EXEC_HOLD 0 x2#define FEC_COMM_MB__A 0 x2400002#define FEC_COMM_MB__W 16 #define FEC_COMM_MB__M 0 xFFFF#define FEC_COMM_MB__PRE 0 x0#define FEC_COMM_INT_REQ__A 0 x2400003#define FEC_COMM_INT_REQ__W 16 #define FEC_COMM_INT_REQ__M 0 xFFFF#define FEC_COMM_INT_REQ__PRE 0 x0#define FEC_COMM_INT_REQ_OC_REQ__B 0 #define FEC_COMM_INT_REQ_OC_REQ__W 1 #define FEC_COMM_INT_REQ_OC_REQ__M 0 x1#define FEC_COMM_INT_REQ_OC_REQ__PRE 0 x0#define FEC_COMM_INT_REQ_RS_REQ__B 1 #define FEC_COMM_INT_REQ_RS_REQ__W 1 #define FEC_COMM_INT_REQ_RS_REQ__M 0 x2#define FEC_COMM_INT_REQ_RS_REQ__PRE 0 x0#define FEC_COMM_INT_REQ_DI_REQ__B 2 #define FEC_COMM_INT_REQ_DI_REQ__W 1 #define FEC_COMM_INT_REQ_DI_REQ__M 0 x4#define FEC_COMM_INT_REQ_DI_REQ__PRE 0 x0#define FEC_COMM_INT_STA__A 0 x2400005#define FEC_COMM_INT_STA__W 16 #define FEC_COMM_INT_STA__M 0 xFFFF#define FEC_COMM_INT_STA__PRE 0 x0#define FEC_COMM_INT_MSK__A 0 x2400006#define FEC_COMM_INT_MSK__W 16 #define FEC_COMM_INT_MSK__M 0 xFFFF#define FEC_COMM_INT_MSK__PRE 0 x0#define FEC_COMM_INT_STM__A 0 x2400007#define FEC_COMM_INT_STM__W 16 #define FEC_COMM_INT_STM__M 0 xFFFF#define FEC_COMM_INT_STM__PRE 0 x0#define FEC_TOP_COMM_EXEC__A 0 x2410000#define FEC_TOP_COMM_EXEC__W 2 #define FEC_TOP_COMM_EXEC__M 0 x3#define FEC_TOP_COMM_EXEC__PRE 0 x0#define FEC_TOP_COMM_EXEC_STOP 0 x0#define FEC_TOP_COMM_EXEC_ACTIVE 0 x1#define FEC_TOP_COMM_EXEC_HOLD 0 x2#define FEC_TOP_ANNEX__A 0 x2410010#define FEC_TOP_ANNEX__W 2 #define FEC_TOP_ANNEX__M 0 x3#define FEC_TOP_ANNEX__PRE 0 x0#define FEC_TOP_ANNEX_A 0 x0#define FEC_TOP_ANNEX_B 0 x1#define FEC_TOP_ANNEX_C 0 x2#define FEC_TOP_ANNEX_D 0 x3#define FEC_DI_COMM_EXEC__A 0 x2420000#define FEC_DI_COMM_EXEC__W 2 #define FEC_DI_COMM_EXEC__M 0 x3#define FEC_DI_COMM_EXEC__PRE 0 x0#define FEC_DI_COMM_EXEC_STOP 0 x0#define FEC_DI_COMM_EXEC_ACTIVE 0 x1#define FEC_DI_COMM_EXEC_HOLD 0 x2#define FEC_DI_COMM_MB__A 0 x2420002#define FEC_DI_COMM_MB__W 2 #define FEC_DI_COMM_MB__M 0 x3#define FEC_DI_COMM_MB__PRE 0 x0#define FEC_DI_COMM_MB_CTL__B 0 #define FEC_DI_COMM_MB_CTL__W 1 #define FEC_DI_COMM_MB_CTL__M 0 x1#define FEC_DI_COMM_MB_CTL__PRE 0 x0#define FEC_DI_COMM_MB_CTL_OFF 0 x0#define FEC_DI_COMM_MB_CTL_ON 0 x1#define FEC_DI_COMM_MB_OBS__B 1 #define FEC_DI_COMM_MB_OBS__W 1 #define FEC_DI_COMM_MB_OBS__M 0 x2#define FEC_DI_COMM_MB_OBS__PRE 0 x0#define FEC_DI_COMM_MB_OBS_OFF 0 x0#define FEC_DI_COMM_MB_OBS_ON 0 x2#define FEC_DI_COMM_INT_REQ__A 0 x2420003#define FEC_DI_COMM_INT_REQ__W 1 #define FEC_DI_COMM_INT_REQ__M 0 x1#define FEC_DI_COMM_INT_REQ__PRE 0 x0#define FEC_DI_COMM_INT_STA__A 0 x2420005#define FEC_DI_COMM_INT_STA__W 2 #define FEC_DI_COMM_INT_STA__M 0 x3#define FEC_DI_COMM_INT_STA__PRE 0 x0#define FEC_DI_COMM_INT_STA_STAT_INT__B 0 #define FEC_DI_COMM_INT_STA_STAT_INT__W 1 #define FEC_DI_COMM_INT_STA_STAT_INT__M 0 x1#define FEC_DI_COMM_INT_STA_STAT_INT__PRE 0 x0#define FEC_DI_COMM_INT_STA_TIMEOUT_INT__B 1 #define FEC_DI_COMM_INT_STA_TIMEOUT_INT__W 1 #define FEC_DI_COMM_INT_STA_TIMEOUT_INT__M 0 x2#define FEC_DI_COMM_INT_STA_TIMEOUT_INT__PRE 0 x0#define FEC_DI_COMM_INT_MSK__A 0 x2420006#define FEC_DI_COMM_INT_MSK__W 2 #define FEC_DI_COMM_INT_MSK__M 0 x3#define FEC_DI_COMM_INT_MSK__PRE 0 x0#define FEC_DI_COMM_INT_MSK_STAT_INT__B 0 #define FEC_DI_COMM_INT_MSK_STAT_INT__W 1 #define FEC_DI_COMM_INT_MSK_STAT_INT__M 0 x1#define FEC_DI_COMM_INT_MSK_STAT_INT__PRE 0 x0#define FEC_DI_COMM_INT_MSK_TIMEOUT_INT__B 1 #define FEC_DI_COMM_INT_MSK_TIMEOUT_INT__W 1 #define FEC_DI_COMM_INT_MSK_TIMEOUT_INT__M 0 x2#define FEC_DI_COMM_INT_MSK_TIMEOUT_INT__PRE 0 x0#define FEC_DI_COMM_INT_STM__A 0 x2420007#define FEC_DI_COMM_INT_STM__W 2 #define FEC_DI_COMM_INT_STM__M 0 x3#define FEC_DI_COMM_INT_STM__PRE 0 x0#define FEC_DI_COMM_INT_STM_STAT_INT__B 0 #define FEC_DI_COMM_INT_STM_STAT_INT__W 1 #define FEC_DI_COMM_INT_STM_STAT_INT__M 0 x1#define FEC_DI_COMM_INT_STM_STAT_INT__PRE 0 x0#define FEC_DI_COMM_INT_STM_TIMEOUT_INT__B 1 #define FEC_DI_COMM_INT_STM_TIMEOUT_INT__W 1 #define FEC_DI_COMM_INT_STM_TIMEOUT_INT__M 0 x2#define FEC_DI_COMM_INT_STM_TIMEOUT_INT__PRE 0 x0#define FEC_DI_STATUS__A 0 x2420010#define FEC_DI_STATUS__W 1 #define FEC_DI_STATUS__M 0 x1#define FEC_DI_STATUS__PRE 0 x0#define FEC_DI_MODE__A 0 x2420011#define FEC_DI_MODE__W 3 #define FEC_DI_MODE__M 0 x7#define FEC_DI_MODE__PRE 0 x0#define FEC_DI_MODE_NO_SYNC__B 0 #define FEC_DI_MODE_NO_SYNC__W 1 #define FEC_DI_MODE_NO_SYNC__M 0 x1#define FEC_DI_MODE_NO_SYNC__PRE 0 x0#define FEC_DI_MODE_IGNORE_LOST_SYNC__B 1 #define FEC_DI_MODE_IGNORE_LOST_SYNC__W 1 #define FEC_DI_MODE_IGNORE_LOST_SYNC__M 0 x2#define FEC_DI_MODE_IGNORE_LOST_SYNC__PRE 0 x0#define FEC_DI_MODE_IGNORE_TIMEOUT__B 2 #define FEC_DI_MODE_IGNORE_TIMEOUT__W 1 #define FEC_DI_MODE_IGNORE_TIMEOUT__M 0 x4#define FEC_DI_MODE_IGNORE_TIMEOUT__PRE 0 x0#define FEC_DI_CONTROL_WORD__A 0 x2420012#define FEC_DI_CONTROL_WORD__W 4 #define FEC_DI_CONTROL_WORD__M 0 xF#define FEC_DI_CONTROL_WORD__PRE 0 x0#define FEC_DI_RESTART__A 0 x2420013#define FEC_DI_RESTART__W 1 #define FEC_DI_RESTART__M 0 x1#define FEC_DI_RESTART__PRE 0 x0#define FEC_DI_TIMEOUT_LO__A 0 x2420014#define FEC_DI_TIMEOUT_LO__W 16 #define FEC_DI_TIMEOUT_LO__M 0 xFFFF#define FEC_DI_TIMEOUT_LO__PRE 0 x0#define FEC_DI_TIMEOUT_HI__A 0 x2420015#define FEC_DI_TIMEOUT_HI__W 8 #define FEC_DI_TIMEOUT_HI__M 0 xFF#define FEC_DI_TIMEOUT_HI__PRE 0 xA#define FEC_RS_COMM_EXEC__A 0 x2430000#define FEC_RS_COMM_EXEC__W 2 #define FEC_RS_COMM_EXEC__M 0 x3#define FEC_RS_COMM_EXEC__PRE 0 x0#define FEC_RS_COMM_EXEC_STOP 0 x0#define FEC_RS_COMM_EXEC_ACTIVE 0 x1#define FEC_RS_COMM_EXEC_HOLD 0 x2#define FEC_RS_COMM_MB__A 0 x2430002#define FEC_RS_COMM_MB__W 2 #define FEC_RS_COMM_MB__M 0 x3#define FEC_RS_COMM_MB__PRE 0 x0#define FEC_RS_COMM_MB_CTL__B 0 #define FEC_RS_COMM_MB_CTL__W 1 #define FEC_RS_COMM_MB_CTL__M 0 x1#define FEC_RS_COMM_MB_CTL__PRE 0 x0#define FEC_RS_COMM_MB_CTL_OFF 0 x0#define FEC_RS_COMM_MB_CTL_ON 0 x1#define FEC_RS_COMM_MB_OBS__B 1 #define FEC_RS_COMM_MB_OBS__W 1 #define FEC_RS_COMM_MB_OBS__M 0 x2#define FEC_RS_COMM_MB_OBS__PRE 0 x0#define FEC_RS_COMM_MB_OBS_OFF 0 x0#define FEC_RS_COMM_MB_OBS_ON 0 x2#define FEC_RS_COMM_INT_REQ__A 0 x2430003#define FEC_RS_COMM_INT_REQ__W 1 #define FEC_RS_COMM_INT_REQ__M 0 x1#define FEC_RS_COMM_INT_REQ__PRE 0 x0#define FEC_RS_COMM_INT_STA__A 0 x2430005#define FEC_RS_COMM_INT_STA__W 2 #define FEC_RS_COMM_INT_STA__M 0 x3#define FEC_RS_COMM_INT_STA__PRE 0 x0#define FEC_RS_COMM_INT_STA_FAILURE_INT__B 0 #define FEC_RS_COMM_INT_STA_FAILURE_INT__W 1 #define FEC_RS_COMM_INT_STA_FAILURE_INT__M 0 x1#define FEC_RS_COMM_INT_STA_FAILURE_INT__PRE 0 x0#define FEC_RS_COMM_INT_STA_MEASUREMENT_INT__B 1 #define FEC_RS_COMM_INT_STA_MEASUREMENT_INT__W 1 #define FEC_RS_COMM_INT_STA_MEASUREMENT_INT__M 0 x2#define FEC_RS_COMM_INT_STA_MEASUREMENT_INT__PRE 0 x0#define FEC_RS_COMM_INT_MSK__A 0 x2430006#define FEC_RS_COMM_INT_MSK__W 2 #define FEC_RS_COMM_INT_MSK__M 0 x3#define FEC_RS_COMM_INT_MSK__PRE 0 x0#define FEC_RS_COMM_INT_MSK_FAILURE_MSK__B 0 #define FEC_RS_COMM_INT_MSK_FAILURE_MSK__W 1 #define FEC_RS_COMM_INT_MSK_FAILURE_MSK__M 0 x1#define FEC_RS_COMM_INT_MSK_FAILURE_MSK__PRE 0 x0#define FEC_RS_COMM_INT_MSK_MEASUREMENT_MSK__B 1 #define FEC_RS_COMM_INT_MSK_MEASUREMENT_MSK__W 1 #define FEC_RS_COMM_INT_MSK_MEASUREMENT_MSK__M 0 x2#define FEC_RS_COMM_INT_MSK_MEASUREMENT_MSK__PRE 0 x0#define FEC_RS_COMM_INT_STM__A 0 x2430007#define FEC_RS_COMM_INT_STM__W 2 #define FEC_RS_COMM_INT_STM__M 0 x3#define FEC_RS_COMM_INT_STM__PRE 0 x0#define FEC_RS_COMM_INT_STM_FAILURE_MSK__B 0 #define FEC_RS_COMM_INT_STM_FAILURE_MSK__W 1 #define FEC_RS_COMM_INT_STM_FAILURE_MSK__M 0 x1#define FEC_RS_COMM_INT_STM_FAILURE_MSK__PRE 0 x0#define FEC_RS_COMM_INT_STM_MEASUREMENT_MSK__B 1 #define FEC_RS_COMM_INT_STM_MEASUREMENT_MSK__W 1 #define FEC_RS_COMM_INT_STM_MEASUREMENT_MSK__M 0 x2#define FEC_RS_COMM_INT_STM_MEASUREMENT_MSK__PRE 0 x0#define FEC_RS_STATUS__A 0 x2430010#define FEC_RS_STATUS__W 1 #define FEC_RS_STATUS__M 0 x1#define FEC_RS_STATUS__PRE 0 x0#define FEC_RS_MODE__A 0 x2430011#define FEC_RS_MODE__W 1 #define FEC_RS_MODE__M 0 x1#define FEC_RS_MODE__PRE 0 x0#define FEC_RS_MODE_BYPASS__B 0 #define FEC_RS_MODE_BYPASS__W 1 #define FEC_RS_MODE_BYPASS__M 0 x1#define FEC_RS_MODE_BYPASS__PRE 0 x0#define FEC_RS_MEASUREMENT_PERIOD__A 0 x2430012#define FEC_RS_MEASUREMENT_PERIOD__W 16 #define FEC_RS_MEASUREMENT_PERIOD__M 0 xFFFF#define FEC_RS_MEASUREMENT_PERIOD__PRE 0 x1171#define FEC_RS_MEASUREMENT_PERIOD_PERIOD__B 0 #define FEC_RS_MEASUREMENT_PERIOD_PERIOD__W 16 #define FEC_RS_MEASUREMENT_PERIOD_PERIOD__M 0 xFFFF#define FEC_RS_MEASUREMENT_PERIOD_PERIOD__PRE 0 x1171#define FEC_RS_MEASUREMENT_PRESCALE__A 0 x2430013#define FEC_RS_MEASUREMENT_PRESCALE__W 16 #define FEC_RS_MEASUREMENT_PRESCALE__M 0 xFFFF#define FEC_RS_MEASUREMENT_PRESCALE__PRE 0 x1#define FEC_RS_MEASUREMENT_PRESCALE_PRESCALE__B 0 #define FEC_RS_MEASUREMENT_PRESCALE_PRESCALE__W 16 #define FEC_RS_MEASUREMENT_PRESCALE_PRESCALE__M 0 xFFFF#define FEC_RS_MEASUREMENT_PRESCALE_PRESCALE__PRE 0 x1#define FEC_RS_NR_BIT_ERRORS__A 0 x2430014#define FEC_RS_NR_BIT_ERRORS__W 16 #define FEC_RS_NR_BIT_ERRORS__M 0 xFFFF#define FEC_RS_NR_BIT_ERRORS__PRE 0 xFFFF#define FEC_RS_NR_BIT_ERRORS_FIXED_MANT__B 0 #define FEC_RS_NR_BIT_ERRORS_FIXED_MANT__W 12 #define FEC_RS_NR_BIT_ERRORS_FIXED_MANT__M 0 xFFF#define FEC_RS_NR_BIT_ERRORS_FIXED_MANT__PRE 0 xFFF#define FEC_RS_NR_BIT_ERRORS_EXP__B 12 #define FEC_RS_NR_BIT_ERRORS_EXP__W 4 #define FEC_RS_NR_BIT_ERRORS_EXP__M 0 xF000#define FEC_RS_NR_BIT_ERRORS_EXP__PRE 0 xF000#define FEC_RS_NR_SYMBOL_ERRORS__A 0 x2430015#define FEC_RS_NR_SYMBOL_ERRORS__W 16 #define FEC_RS_NR_SYMBOL_ERRORS__M 0 xFFFF#define FEC_RS_NR_SYMBOL_ERRORS__PRE 0 xFFFF#define FEC_RS_NR_SYMBOL_ERRORS_FIXED_MANT__B 0 #define FEC_RS_NR_SYMBOL_ERRORS_FIXED_MANT__W 12 #define FEC_RS_NR_SYMBOL_ERRORS_FIXED_MANT__M 0 xFFF#define FEC_RS_NR_SYMBOL_ERRORS_FIXED_MANT__PRE 0 xFFF#define FEC_RS_NR_SYMBOL_ERRORS_EXP__B 12 #define FEC_RS_NR_SYMBOL_ERRORS_EXP__W 4 #define FEC_RS_NR_SYMBOL_ERRORS_EXP__M 0 xF000#define FEC_RS_NR_SYMBOL_ERRORS_EXP__PRE 0 xF000#define FEC_RS_NR_PACKET_ERRORS__A 0 x2430016#define FEC_RS_NR_PACKET_ERRORS__W 16 #define FEC_RS_NR_PACKET_ERRORS__M 0 xFFFF#define FEC_RS_NR_PACKET_ERRORS__PRE 0 xFFFF#define FEC_RS_NR_PACKET_ERRORS_FIXED_MANT__B 0 #define FEC_RS_NR_PACKET_ERRORS_FIXED_MANT__W 12 #define FEC_RS_NR_PACKET_ERRORS_FIXED_MANT__M 0 xFFF#define FEC_RS_NR_PACKET_ERRORS_FIXED_MANT__PRE 0 xFFF#define FEC_RS_NR_PACKET_ERRORS_EXP__B 12 #define FEC_RS_NR_PACKET_ERRORS_EXP__W 4 #define FEC_RS_NR_PACKET_ERRORS_EXP__M 0 xF000#define FEC_RS_NR_PACKET_ERRORS_EXP__PRE 0 xF000#define FEC_RS_NR_FAILURES__A 0 x2430017#define FEC_RS_NR_FAILURES__W 16 #define FEC_RS_NR_FAILURES__M 0 xFFFF#define FEC_RS_NR_FAILURES__PRE 0 x0#define FEC_RS_NR_FAILURES_FIXED_MANT__B 0 #define FEC_RS_NR_FAILURES_FIXED_MANT__W 12 #define FEC_RS_NR_FAILURES_FIXED_MANT__M 0 xFFF#define FEC_RS_NR_FAILURES_FIXED_MANT__PRE 0 x0#define FEC_RS_NR_FAILURES_EXP__B 12 #define FEC_RS_NR_FAILURES_EXP__W 4 #define FEC_RS_NR_FAILURES_EXP__M 0 xF000#define FEC_RS_NR_FAILURES_EXP__PRE 0 x0#define FEC_OC_COMM_EXEC__A 0 x2440000#define FEC_OC_COMM_EXEC__W 2 #define FEC_OC_COMM_EXEC__M 0 x3#define FEC_OC_COMM_EXEC__PRE 0 x0#define FEC_OC_COMM_EXEC_STOP 0 x0#define FEC_OC_COMM_EXEC_ACTIVE 0 x1#define FEC_OC_COMM_EXEC_HOLD 0 x2#define FEC_OC_COMM_MB__A 0 x2440002#define FEC_OC_COMM_MB__W 2 #define FEC_OC_COMM_MB__M 0 x3#define FEC_OC_COMM_MB__PRE 0 x0#define FEC_OC_COMM_MB_CTL__B 0 #define FEC_OC_COMM_MB_CTL__W 1 #define FEC_OC_COMM_MB_CTL__M 0 x1#define FEC_OC_COMM_MB_CTL__PRE 0 x0#define FEC_OC_COMM_MB_CTL_OFF 0 x0#define FEC_OC_COMM_MB_CTL_ON 0 x1#define FEC_OC_COMM_MB_OBS__B 1 #define FEC_OC_COMM_MB_OBS__W 1 #define FEC_OC_COMM_MB_OBS__M 0 x2#define FEC_OC_COMM_MB_OBS__PRE 0 x0#define FEC_OC_COMM_MB_OBS_OFF 0 x0#define FEC_OC_COMM_MB_OBS_ON 0 x2#define FEC_OC_COMM_INT_REQ__A 0 x2440003#define FEC_OC_COMM_INT_REQ__W 1 #define FEC_OC_COMM_INT_REQ__M 0 x1#define FEC_OC_COMM_INT_REQ__PRE 0 x0#define FEC_OC_COMM_INT_STA__A 0 x2440005#define FEC_OC_COMM_INT_STA__W 8 #define FEC_OC_COMM_INT_STA__M 0 xFF#define FEC_OC_COMM_INT_STA__PRE 0 x0#define FEC_OC_COMM_INT_STA_DPR_LOCK_INT__B 0 #define FEC_OC_COMM_INT_STA_DPR_LOCK_INT__W 1 #define FEC_OC_COMM_INT_STA_DPR_LOCK_INT__M 0 x1#define FEC_OC_COMM_INT_STA_DPR_LOCK_INT__PRE 0 x0#define FEC_OC_COMM_INT_STA_SNC_LOCK_INT__B 1 #define FEC_OC_COMM_INT_STA_SNC_LOCK_INT__W 1 #define FEC_OC_COMM_INT_STA_SNC_LOCK_INT__M 0 x2#define FEC_OC_COMM_INT_STA_SNC_LOCK_INT__PRE 0 x0#define FEC_OC_COMM_INT_STA_SNC_LOST_INT__B 2 #define FEC_OC_COMM_INT_STA_SNC_LOST_INT__W 1 #define FEC_OC_COMM_INT_STA_SNC_LOST_INT__M 0 x4#define FEC_OC_COMM_INT_STA_SNC_LOST_INT__PRE 0 x0#define FEC_OC_COMM_INT_STA_SNC_PAR_INT__B 3 #define FEC_OC_COMM_INT_STA_SNC_PAR_INT__W 1 #define FEC_OC_COMM_INT_STA_SNC_PAR_INT__M 0 x8#define FEC_OC_COMM_INT_STA_SNC_PAR_INT__PRE 0 x0#define FEC_OC_COMM_INT_STA_FIFO_FULL_INT__B 4 #define FEC_OC_COMM_INT_STA_FIFO_FULL_INT__W 1 #define FEC_OC_COMM_INT_STA_FIFO_FULL_INT__M 0 x10#define FEC_OC_COMM_INT_STA_FIFO_FULL_INT__PRE 0 x0#define FEC_OC_COMM_INT_STA_FIFO_EMPTY_INT__B 5 #define FEC_OC_COMM_INT_STA_FIFO_EMPTY_INT__W 1 #define FEC_OC_COMM_INT_STA_FIFO_EMPTY_INT__M 0 x20#define FEC_OC_COMM_INT_STA_FIFO_EMPTY_INT__PRE 0 x0#define FEC_OC_COMM_INT_STA_OCR_ACQ_INT__B 6 #define FEC_OC_COMM_INT_STA_OCR_ACQ_INT__W 1 #define FEC_OC_COMM_INT_STA_OCR_ACQ_INT__M 0 x40#define FEC_OC_COMM_INT_STA_OCR_ACQ_INT__PRE 0 x0#define FEC_OC_COMM_INT_STA_STAT_CHG_INT__B 7 #define FEC_OC_COMM_INT_STA_STAT_CHG_INT__W 1 #define FEC_OC_COMM_INT_STA_STAT_CHG_INT__M 0 x80#define FEC_OC_COMM_INT_STA_STAT_CHG_INT__PRE 0 x0#define FEC_OC_COMM_INT_MSK__A 0 x2440006#define FEC_OC_COMM_INT_MSK__W 8 #define FEC_OC_COMM_INT_MSK__M 0 xFF#define FEC_OC_COMM_INT_MSK__PRE 0 x0#define FEC_OC_COMM_INT_MSK_DPR_LOCK_MSK__B 0 #define FEC_OC_COMM_INT_MSK_DPR_LOCK_MSK__W 1 #define FEC_OC_COMM_INT_MSK_DPR_LOCK_MSK__M 0 x1#define FEC_OC_COMM_INT_MSK_DPR_LOCK_MSK__PRE 0 x0#define FEC_OC_COMM_INT_MSK_SNC_LOCK_MSK__B 1 #define FEC_OC_COMM_INT_MSK_SNC_LOCK_MSK__W 1 #define FEC_OC_COMM_INT_MSK_SNC_LOCK_MSK__M 0 x2#define FEC_OC_COMM_INT_MSK_SNC_LOCK_MSK__PRE 0 x0#define FEC_OC_COMM_INT_MSK_SNC_LOST_MSK__B 2 #define FEC_OC_COMM_INT_MSK_SNC_LOST_MSK__W 1 #define FEC_OC_COMM_INT_MSK_SNC_LOST_MSK__M 0 x4#define FEC_OC_COMM_INT_MSK_SNC_LOST_MSK__PRE 0 x0#define FEC_OC_COMM_INT_MSK_SNC_PAR_MSK__B 3 #define FEC_OC_COMM_INT_MSK_SNC_PAR_MSK__W 1 #define FEC_OC_COMM_INT_MSK_SNC_PAR_MSK__M 0 x8#define FEC_OC_COMM_INT_MSK_SNC_PAR_MSK__PRE 0 x0#define FEC_OC_COMM_INT_MSK_FIFO_FULL_MSK__B 4 #define FEC_OC_COMM_INT_MSK_FIFO_FULL_MSK__W 1 #define FEC_OC_COMM_INT_MSK_FIFO_FULL_MSK__M 0 x10#define FEC_OC_COMM_INT_MSK_FIFO_FULL_MSK__PRE 0 x0#define FEC_OC_COMM_INT_MSK_FIFO_EMPTY_MSK__B 5 #define FEC_OC_COMM_INT_MSK_FIFO_EMPTY_MSK__W 1 #define FEC_OC_COMM_INT_MSK_FIFO_EMPTY_MSK__M 0 x20#define FEC_OC_COMM_INT_MSK_FIFO_EMPTY_MSK__PRE 0 x0#define FEC_OC_COMM_INT_MSK_OCR_ACQ_MSK__B 6 #define FEC_OC_COMM_INT_MSK_OCR_ACQ_MSK__W 1 #define FEC_OC_COMM_INT_MSK_OCR_ACQ_MSK__M 0 x40#define FEC_OC_COMM_INT_MSK_OCR_ACQ_MSK__PRE 0 x0#define FEC_OC_COMM_INT_MSK_STAT_CHG_MSK__B 7 #define FEC_OC_COMM_INT_MSK_STAT_CHG_MSK__W 1 #define FEC_OC_COMM_INT_MSK_STAT_CHG_MSK__M 0 x80#define FEC_OC_COMM_INT_MSK_STAT_CHG_MSK__PRE 0 x0#define FEC_OC_COMM_INT_STM__A 0 x2440007#define FEC_OC_COMM_INT_STM__W 8 #define FEC_OC_COMM_INT_STM__M 0 xFF#define FEC_OC_COMM_INT_STM__PRE 0 x0#define FEC_OC_COMM_INT_STM_DPR_LOCK_MSK__B 0 #define FEC_OC_COMM_INT_STM_DPR_LOCK_MSK__W 1 #define FEC_OC_COMM_INT_STM_DPR_LOCK_MSK__M 0 x1#define FEC_OC_COMM_INT_STM_DPR_LOCK_MSK__PRE 0 x0#define FEC_OC_COMM_INT_STM_SNC_LOCK_MSK__B 1 #define FEC_OC_COMM_INT_STM_SNC_LOCK_MSK__W 1 #define FEC_OC_COMM_INT_STM_SNC_LOCK_MSK__M 0 x2#define FEC_OC_COMM_INT_STM_SNC_LOCK_MSK__PRE 0 x0#define FEC_OC_COMM_INT_STM_SNC_LOST_MSK__B 2 #define FEC_OC_COMM_INT_STM_SNC_LOST_MSK__W 1 #define FEC_OC_COMM_INT_STM_SNC_LOST_MSK__M 0 x4#define FEC_OC_COMM_INT_STM_SNC_LOST_MSK__PRE 0 x0#define FEC_OC_COMM_INT_STM_SNC_PAR_MSK__B 3 #define FEC_OC_COMM_INT_STM_SNC_PAR_MSK__W 1 #define FEC_OC_COMM_INT_STM_SNC_PAR_MSK__M 0 x8#define FEC_OC_COMM_INT_STM_SNC_PAR_MSK__PRE 0 x0#define FEC_OC_COMM_INT_STM_FIFO_FULL_MSK__B 4 #define FEC_OC_COMM_INT_STM_FIFO_FULL_MSK__W 1 #define FEC_OC_COMM_INT_STM_FIFO_FULL_MSK__M 0 x10#define FEC_OC_COMM_INT_STM_FIFO_FULL_MSK__PRE 0 x0#define FEC_OC_COMM_INT_STM_FIFO_EMPTY_MSK__B 5 #define FEC_OC_COMM_INT_STM_FIFO_EMPTY_MSK__W 1 #define FEC_OC_COMM_INT_STM_FIFO_EMPTY_MSK__M 0 x20#define FEC_OC_COMM_INT_STM_FIFO_EMPTY_MSK__PRE 0 x0#define FEC_OC_COMM_INT_STM_OCR_ACQ_MSK__B 6 #define FEC_OC_COMM_INT_STM_OCR_ACQ_MSK__W 1 #define FEC_OC_COMM_INT_STM_OCR_ACQ_MSK__M 0 x40#define FEC_OC_COMM_INT_STM_OCR_ACQ_MSK__PRE 0 x0#define FEC_OC_COMM_INT_STM_STAT_CHG_MSK__B 7 #define FEC_OC_COMM_INT_STM_STAT_CHG_MSK__W 1 #define FEC_OC_COMM_INT_STM_STAT_CHG_MSK__M 0 x80#define FEC_OC_COMM_INT_STM_STAT_CHG_MSK__PRE 0 x0#define FEC_OC_STATUS__A 0 x2440010#define FEC_OC_STATUS__W 5 #define FEC_OC_STATUS__M 0 x1F#define FEC_OC_STATUS__PRE 0 x0#define FEC_OC_STATUS_DPR_STATUS__B 0 #define FEC_OC_STATUS_DPR_STATUS__W 1 #define FEC_OC_STATUS_DPR_STATUS__M 0 x1#define FEC_OC_STATUS_DPR_STATUS__PRE 0 x0#define FEC_OC_STATUS_SNC_STATUS__B 1 #define FEC_OC_STATUS_SNC_STATUS__W 2 #define FEC_OC_STATUS_SNC_STATUS__M 0 x6#define FEC_OC_STATUS_SNC_STATUS__PRE 0 x0#define FEC_OC_STATUS_FIFO_FULL__B 3 #define FEC_OC_STATUS_FIFO_FULL__W 1 #define FEC_OC_STATUS_FIFO_FULL__M 0 x8#define FEC_OC_STATUS_FIFO_FULL__PRE 0 x0#define FEC_OC_STATUS_FIFO_EMPTY__B 4 #define FEC_OC_STATUS_FIFO_EMPTY__W 1 #define FEC_OC_STATUS_FIFO_EMPTY__M 0 x10#define FEC_OC_STATUS_FIFO_EMPTY__PRE 0 x0#define FEC_OC_MODE__A 0 x2440011#define FEC_OC_MODE__W 4 #define FEC_OC_MODE__M 0 xF#define FEC_OC_MODE__PRE 0 x0#define FEC_OC_MODE_PARITY__B 0 #define FEC_OC_MODE_PARITY__W 1 #define FEC_OC_MODE_PARITY__M 0 x1#define FEC_OC_MODE_PARITY__PRE 0 x0#define FEC_OC_MODE_TRANSPARENT__B 1 #define FEC_OC_MODE_TRANSPARENT__W 1 #define FEC_OC_MODE_TRANSPARENT__M 0 x2#define FEC_OC_MODE_TRANSPARENT__PRE 0 x0#define FEC_OC_MODE_CLEAR__B 2 #define FEC_OC_MODE_CLEAR__W 1 #define FEC_OC_MODE_CLEAR__M 0 x4#define FEC_OC_MODE_CLEAR__PRE 0 x0#define FEC_OC_MODE_RETAIN_FRAMING__B 3 #define FEC_OC_MODE_RETAIN_FRAMING__W 1 #define FEC_OC_MODE_RETAIN_FRAMING__M 0 x8#define FEC_OC_MODE_RETAIN_FRAMING__PRE 0 x0#define FEC_OC_DPR_MODE__A 0 x2440012#define FEC_OC_DPR_MODE__W 2 #define FEC_OC_DPR_MODE__M 0 x3#define FEC_OC_DPR_MODE__PRE 0 x0#define FEC_OC_DPR_MODE_ERR_DISABLE__B 0 #define FEC_OC_DPR_MODE_ERR_DISABLE__W 1 #define FEC_OC_DPR_MODE_ERR_DISABLE__M 0 x1#define FEC_OC_DPR_MODE_ERR_DISABLE__PRE 0 x0#define FEC_OC_DPR_MODE_NOSYNC_ENABLE__B 1 #define FEC_OC_DPR_MODE_NOSYNC_ENABLE__W 1 #define FEC_OC_DPR_MODE_NOSYNC_ENABLE__M 0 x2#define FEC_OC_DPR_MODE_NOSYNC_ENABLE__PRE 0 x0#define FEC_OC_DPR_UNLOCK__A 0 x2440013#define FEC_OC_DPR_UNLOCK__W 1 #define FEC_OC_DPR_UNLOCK__M 0 x1#define FEC_OC_DPR_UNLOCK__PRE 0 x0#define FEC_OC_DTO_MODE__A 0 x2440014#define FEC_OC_DTO_MODE__W 3 #define FEC_OC_DTO_MODE__M 0 x7#define FEC_OC_DTO_MODE__PRE 0 x0#define FEC_OC_DTO_MODE_DYNAMIC__B 0 #define FEC_OC_DTO_MODE_DYNAMIC__W 1 #define FEC_OC_DTO_MODE_DYNAMIC__M 0 x1#define FEC_OC_DTO_MODE_DYNAMIC__PRE 0 x0#define FEC_OC_DTO_MODE_DUTY_CYCLE__B 1 #define FEC_OC_DTO_MODE_DUTY_CYCLE__W 1 #define FEC_OC_DTO_MODE_DUTY_CYCLE__M 0 x2#define FEC_OC_DTO_MODE_DUTY_CYCLE__PRE 0 x0#define FEC_OC_DTO_MODE_OFFSET_ENABLE__B 2 #define FEC_OC_DTO_MODE_OFFSET_ENABLE__W 1 #define FEC_OC_DTO_MODE_OFFSET_ENABLE__M 0 x4#define FEC_OC_DTO_MODE_OFFSET_ENABLE__PRE 0 x0#define FEC_OC_DTO_PERIOD__A 0 x2440015#define FEC_OC_DTO_PERIOD__W 8 #define FEC_OC_DTO_PERIOD__M 0 xFF#define FEC_OC_DTO_PERIOD__PRE 0 x0#define FEC_OC_DTO_RATE_LO__A 0 x2440016#define FEC_OC_DTO_RATE_LO__W 16 #define FEC_OC_DTO_RATE_LO__M 0 xFFFF#define FEC_OC_DTO_RATE_LO__PRE 0 x0#define FEC_OC_DTO_RATE_LO_RATE_LO__B 0 #define FEC_OC_DTO_RATE_LO_RATE_LO__W 16 #define FEC_OC_DTO_RATE_LO_RATE_LO__M 0 xFFFF#define FEC_OC_DTO_RATE_LO_RATE_LO__PRE 0 x0#define FEC_OC_DTO_RATE_HI__A 0 x2440017#define FEC_OC_DTO_RATE_HI__W 10 #define FEC_OC_DTO_RATE_HI__M 0 x3FF#define FEC_OC_DTO_RATE_HI__PRE 0 xC0#define FEC_OC_DTO_RATE_HI_RATE_HI__B 0 #define FEC_OC_DTO_RATE_HI_RATE_HI__W 10 #define FEC_OC_DTO_RATE_HI_RATE_HI__M 0 x3FF#define FEC_OC_DTO_RATE_HI_RATE_HI__PRE 0 xC0#define FEC_OC_DTO_BURST_LEN__A 0 x2440018#define FEC_OC_DTO_BURST_LEN__W 8 #define FEC_OC_DTO_BURST_LEN__M 0 xFF#define FEC_OC_DTO_BURST_LEN__PRE 0 xBC#define FEC_OC_DTO_BURST_LEN_BURST_LEN__B 0 #define FEC_OC_DTO_BURST_LEN_BURST_LEN__W 8 #define FEC_OC_DTO_BURST_LEN_BURST_LEN__M 0 xFF#define FEC_OC_DTO_BURST_LEN_BURST_LEN__PRE 0 xBC#define FEC_OC_FCT_MODE__A 0 x244001A#define FEC_OC_FCT_MODE__W 2 #define FEC_OC_FCT_MODE__M 0 x3#define FEC_OC_FCT_MODE__PRE 0 x0#define FEC_OC_FCT_MODE_RAT_ENA__B 0 #define FEC_OC_FCT_MODE_RAT_ENA__W 1 #define FEC_OC_FCT_MODE_RAT_ENA__M 0 x1#define FEC_OC_FCT_MODE_RAT_ENA__PRE 0 x0#define FEC_OC_FCT_MODE_VIRT_ENA__B 1 #define FEC_OC_FCT_MODE_VIRT_ENA__W 1 #define FEC_OC_FCT_MODE_VIRT_ENA__M 0 x2#define FEC_OC_FCT_MODE_VIRT_ENA__PRE 0 x0#define FEC_OC_FCT_USAGE__A 0 x244001B#define FEC_OC_FCT_USAGE__W 3 #define FEC_OC_FCT_USAGE__M 0 x7#define FEC_OC_FCT_USAGE__PRE 0 x2#define FEC_OC_FCT_USAGE_USAGE__B 0 #define FEC_OC_FCT_USAGE_USAGE__W 3 #define FEC_OC_FCT_USAGE_USAGE__M 0 x7#define FEC_OC_FCT_USAGE_USAGE__PRE 0 x2#define FEC_OC_FCT_OCCUPATION__A 0 x244001C#define FEC_OC_FCT_OCCUPATION__W 12 #define FEC_OC_FCT_OCCUPATION__M 0 xFFF#define FEC_OC_FCT_OCCUPATION__PRE 0 x0#define FEC_OC_FCT_OCCUPATION_OCCUPATION__B 0 #define FEC_OC_FCT_OCCUPATION_OCCUPATION__W 12 #define FEC_OC_FCT_OCCUPATION_OCCUPATION__M 0 xFFF#define FEC_OC_FCT_OCCUPATION_OCCUPATION__PRE 0 x0#define FEC_OC_TMD_MODE__A 0 x244001E#define FEC_OC_TMD_MODE__W 3 #define FEC_OC_TMD_MODE__M 0 x7#define FEC_OC_TMD_MODE__PRE 0 x4#define FEC_OC_TMD_MODE_MODE__B 0 #define FEC_OC_TMD_MODE_MODE__W 3 #define FEC_OC_TMD_MODE_MODE__M 0 x7#define FEC_OC_TMD_MODE_MODE__PRE 0 x4#define FEC_OC_TMD_COUNT__A 0 x244001F#define FEC_OC_TMD_COUNT__W 10 #define FEC_OC_TMD_COUNT__M 0 x3FF#define FEC_OC_TMD_COUNT__PRE 0 x1F4#define FEC_OC_TMD_COUNT_COUNT__B 0 #define FEC_OC_TMD_COUNT_COUNT__W 10 #define FEC_OC_TMD_COUNT_COUNT__M 0 x3FF#define FEC_OC_TMD_COUNT_COUNT__PRE 0 x1F4#define FEC_OC_TMD_HI_MARGIN__A 0 x2440020#define FEC_OC_TMD_HI_MARGIN__W 11 #define FEC_OC_TMD_HI_MARGIN__M 0 x7FF#define FEC_OC_TMD_HI_MARGIN__PRE 0 x200#define FEC_OC_TMD_HI_MARGIN_HI_MARGIN__B 0 #define FEC_OC_TMD_HI_MARGIN_HI_MARGIN__W 11 #define FEC_OC_TMD_HI_MARGIN_HI_MARGIN__M 0 x7FF#define FEC_OC_TMD_HI_MARGIN_HI_MARGIN__PRE 0 x200#define FEC_OC_TMD_LO_MARGIN__A 0 x2440021#define FEC_OC_TMD_LO_MARGIN__W 11 #define FEC_OC_TMD_LO_MARGIN__M 0 x7FF#define FEC_OC_TMD_LO_MARGIN__PRE 0 x100#define FEC_OC_TMD_LO_MARGIN_LO_MARGIN__B 0 #define FEC_OC_TMD_LO_MARGIN_LO_MARGIN__W 11 #define FEC_OC_TMD_LO_MARGIN_LO_MARGIN__M 0 x7FF#define FEC_OC_TMD_LO_MARGIN_LO_MARGIN__PRE 0 x100#define FEC_OC_TMD_CTL_UPD_RATE__A 0 x2440022#define FEC_OC_TMD_CTL_UPD_RATE__W 4 #define FEC_OC_TMD_CTL_UPD_RATE__M 0 xF#define FEC_OC_TMD_CTL_UPD_RATE__PRE 0 x1#define FEC_OC_TMD_CTL_UPD_RATE_RATE__B 0 #define FEC_OC_TMD_CTL_UPD_RATE_RATE__W 4 #define FEC_OC_TMD_CTL_UPD_RATE_RATE__M 0 xF#define FEC_OC_TMD_CTL_UPD_RATE_RATE__PRE 0 x1#define FEC_OC_TMD_INT_UPD_RATE__A 0 x2440023#define FEC_OC_TMD_INT_UPD_RATE__W 4 #define FEC_OC_TMD_INT_UPD_RATE__M 0 xF#define FEC_OC_TMD_INT_UPD_RATE__PRE 0 x4#define FEC_OC_TMD_INT_UPD_RATE_RATE__B 0 #define FEC_OC_TMD_INT_UPD_RATE_RATE__W 4 #define FEC_OC_TMD_INT_UPD_RATE_RATE__M 0 xF#define FEC_OC_TMD_INT_UPD_RATE_RATE__PRE 0 x4#define FEC_OC_AVR_PARM_A__A 0 x2440026#define FEC_OC_AVR_PARM_A__W 4 #define FEC_OC_AVR_PARM_A__M 0 xF#define FEC_OC_AVR_PARM_A__PRE 0 x6#define FEC_OC_AVR_PARM_A_PARM__B 0 #define FEC_OC_AVR_PARM_A_PARM__W 4 #define FEC_OC_AVR_PARM_A_PARM__M 0 xF#define FEC_OC_AVR_PARM_A_PARM__PRE 0 x6#define FEC_OC_AVR_PARM_B__A 0 x2440027#define FEC_OC_AVR_PARM_B__W 4 #define FEC_OC_AVR_PARM_B__M 0 xF#define FEC_OC_AVR_PARM_B__PRE 0 x4#define FEC_OC_AVR_PARM_B_PARM__B 0 #define FEC_OC_AVR_PARM_B_PARM__W 4 #define FEC_OC_AVR_PARM_B_PARM__M 0 xF#define FEC_OC_AVR_PARM_B_PARM__PRE 0 x4#define FEC_OC_AVR_AVG_LO__A 0 x2440028#define FEC_OC_AVR_AVG_LO__W 16 #define FEC_OC_AVR_AVG_LO__M 0 xFFFF#define FEC_OC_AVR_AVG_LO__PRE 0 x0#define FEC_OC_AVR_AVG_LO_AVG_LO__B 0 #define FEC_OC_AVR_AVG_LO_AVG_LO__W 16 #define FEC_OC_AVR_AVG_LO_AVG_LO__M 0 xFFFF#define FEC_OC_AVR_AVG_LO_AVG_LO__PRE 0 x0#define FEC_OC_AVR_AVG_HI__A 0 x2440029#define FEC_OC_AVR_AVG_HI__W 6 #define FEC_OC_AVR_AVG_HI__M 0 x3F#define FEC_OC_AVR_AVG_HI__PRE 0 x0#define FEC_OC_AVR_AVG_HI_AVG_HI__B 0 #define FEC_OC_AVR_AVG_HI_AVG_HI__W 6 #define FEC_OC_AVR_AVG_HI_AVG_HI__M 0 x3F#define FEC_OC_AVR_AVG_HI_AVG_HI__PRE 0 x0#define FEC_OC_RCN_MODE__A 0 x244002C#define FEC_OC_RCN_MODE__W 5 #define FEC_OC_RCN_MODE__M 0 x1F#define FEC_OC_RCN_MODE__PRE 0 x1F#define FEC_OC_RCN_MODE_MODE__B 0 #define FEC_OC_RCN_MODE_MODE__W 5 #define FEC_OC_RCN_MODE_MODE__M 0 x1F#define FEC_OC_RCN_MODE_MODE__PRE 0 x1F#define FEC_OC_RCN_OCC_SETTLE__A 0 x244002D#define FEC_OC_RCN_OCC_SETTLE__W 11 #define FEC_OC_RCN_OCC_SETTLE__M 0 x7FF#define FEC_OC_RCN_OCC_SETTLE__PRE 0 x180#define FEC_OC_RCN_OCC_SETTLE_LEVEL__B 0 #define FEC_OC_RCN_OCC_SETTLE_LEVEL__W 11 #define FEC_OC_RCN_OCC_SETTLE_LEVEL__M 0 x7FF#define FEC_OC_RCN_OCC_SETTLE_LEVEL__PRE 0 x180#define FEC_OC_RCN_GAIN__A 0 x244002E#define FEC_OC_RCN_GAIN__W 4 #define FEC_OC_RCN_GAIN__M 0 xF#define FEC_OC_RCN_GAIN__PRE 0 xC#define FEC_OC_RCN_GAIN_GAIN__B 0 #define FEC_OC_RCN_GAIN_GAIN__W 4 #define FEC_OC_RCN_GAIN_GAIN__M 0 xF#define FEC_OC_RCN_GAIN_GAIN__PRE 0 xC#define FEC_OC_RCN_CTL_RATE_LO__A 0 x2440030#define FEC_OC_RCN_CTL_RATE_LO__W 16 #define FEC_OC_RCN_CTL_RATE_LO__M 0 xFFFF#define FEC_OC_RCN_CTL_RATE_LO__PRE 0 x0#define FEC_OC_RCN_CTL_RATE_LO_CTL_LO__B 0 #define FEC_OC_RCN_CTL_RATE_LO_CTL_LO__W 16 #define FEC_OC_RCN_CTL_RATE_LO_CTL_LO__M 0 xFFFF#define FEC_OC_RCN_CTL_RATE_LO_CTL_LO__PRE 0 x0#define FEC_OC_RCN_CTL_RATE_HI__A 0 x2440031#define FEC_OC_RCN_CTL_RATE_HI__W 8 #define FEC_OC_RCN_CTL_RATE_HI__M 0 xFF#define FEC_OC_RCN_CTL_RATE_HI__PRE 0 xC0#define FEC_OC_RCN_CTL_RATE_HI_CTL_HI__B 0 #define FEC_OC_RCN_CTL_RATE_HI_CTL_HI__W 8 #define FEC_OC_RCN_CTL_RATE_HI_CTL_HI__M 0 xFF#define FEC_OC_RCN_CTL_RATE_HI_CTL_HI__PRE 0 xC0#define FEC_OC_RCN_CTL_STEP_LO__A 0 x2440032#define FEC_OC_RCN_CTL_STEP_LO__W 16 #define FEC_OC_RCN_CTL_STEP_LO__M 0 xFFFF#define FEC_OC_RCN_CTL_STEP_LO__PRE 0 x0#define FEC_OC_RCN_CTL_STEP_LO_CTL_LO__B 0 #define FEC_OC_RCN_CTL_STEP_LO_CTL_LO__W 16 #define FEC_OC_RCN_CTL_STEP_LO_CTL_LO__M 0 xFFFF#define FEC_OC_RCN_CTL_STEP_LO_CTL_LO__PRE 0 x0#define FEC_OC_RCN_CTL_STEP_HI__A 0 x2440033#define FEC_OC_RCN_CTL_STEP_HI__W 8 #define FEC_OC_RCN_CTL_STEP_HI__M 0 xFF#define FEC_OC_RCN_CTL_STEP_HI__PRE 0 x8#define FEC_OC_RCN_CTL_STEP_HI_CTL_HI__B 0 #define FEC_OC_RCN_CTL_STEP_HI_CTL_HI__W 8 #define FEC_OC_RCN_CTL_STEP_HI_CTL_HI__M 0 xFF#define FEC_OC_RCN_CTL_STEP_HI_CTL_HI__PRE 0 x8#define FEC_OC_RCN_DTO_OFS_LO__A 0 x2440034#define FEC_OC_RCN_DTO_OFS_LO__W 16 #define FEC_OC_RCN_DTO_OFS_LO__M 0 xFFFF#define FEC_OC_RCN_DTO_OFS_LO__PRE 0 x0#define FEC_OC_RCN_DTO_OFS_LO_OFS_LO__B 0 #define FEC_OC_RCN_DTO_OFS_LO_OFS_LO__W 16 #define FEC_OC_RCN_DTO_OFS_LO_OFS_LO__M 0 xFFFF#define FEC_OC_RCN_DTO_OFS_LO_OFS_LO__PRE 0 x0#define FEC_OC_RCN_DTO_OFS_HI__A 0 x2440035#define FEC_OC_RCN_DTO_OFS_HI__W 8 #define FEC_OC_RCN_DTO_OFS_HI__M 0 xFF#define FEC_OC_RCN_DTO_OFS_HI__PRE 0 x0#define FEC_OC_RCN_DTO_OFS_HI_OFS_HI__B 0 #define FEC_OC_RCN_DTO_OFS_HI_OFS_HI__W 8 #define FEC_OC_RCN_DTO_OFS_HI_OFS_HI__M 0 xFF#define FEC_OC_RCN_DTO_OFS_HI_OFS_HI__PRE 0 x0#define FEC_OC_RCN_DTO_RATE_LO__A 0 x2440036#define FEC_OC_RCN_DTO_RATE_LO__W 16 #define FEC_OC_RCN_DTO_RATE_LO__M 0 xFFFF#define FEC_OC_RCN_DTO_RATE_LO__PRE 0 x0#define FEC_OC_RCN_DTO_RATE_LO_OFS_LO__B 0 #define FEC_OC_RCN_DTO_RATE_LO_OFS_LO__W 16 #define FEC_OC_RCN_DTO_RATE_LO_OFS_LO__M 0 xFFFF#define FEC_OC_RCN_DTO_RATE_LO_OFS_LO__PRE 0 x0#define FEC_OC_RCN_DTO_RATE_HI__A 0 x2440037#define FEC_OC_RCN_DTO_RATE_HI__W 8 #define FEC_OC_RCN_DTO_RATE_HI__M 0 xFF#define FEC_OC_RCN_DTO_RATE_HI__PRE 0 x0#define FEC_OC_RCN_DTO_RATE_HI_OFS_HI__B 0 #define FEC_OC_RCN_DTO_RATE_HI_OFS_HI__W 8 #define FEC_OC_RCN_DTO_RATE_HI_OFS_HI__M 0 xFF#define FEC_OC_RCN_DTO_RATE_HI_OFS_HI__PRE 0 x0#define FEC_OC_RCN_RATE_CLIP_LO__A 0 x2440038#define FEC_OC_RCN_RATE_CLIP_LO__W 16 #define FEC_OC_RCN_RATE_CLIP_LO__M 0 xFFFF#define FEC_OC_RCN_RATE_CLIP_LO__PRE 0 x0#define FEC_OC_RCN_RATE_CLIP_LO_CLIP_LO__B 0 #define FEC_OC_RCN_RATE_CLIP_LO_CLIP_LO__W 16 #define FEC_OC_RCN_RATE_CLIP_LO_CLIP_LO__M 0 xFFFF#define FEC_OC_RCN_RATE_CLIP_LO_CLIP_LO__PRE 0 x0#define FEC_OC_RCN_RATE_CLIP_HI__A 0 x2440039#define FEC_OC_RCN_RATE_CLIP_HI__W 8 #define FEC_OC_RCN_RATE_CLIP_HI__M 0 xFF#define FEC_OC_RCN_RATE_CLIP_HI__PRE 0 xF0#define FEC_OC_RCN_RATE_CLIP_HI_CLIP_HI__B 0 #define FEC_OC_RCN_RATE_CLIP_HI_CLIP_HI__W 8 #define FEC_OC_RCN_RATE_CLIP_HI_CLIP_HI__M 0 xFF#define FEC_OC_RCN_RATE_CLIP_HI_CLIP_HI__PRE 0 xF0#define FEC_OC_RCN_DYN_RATE_LO__A 0 x244003A#define FEC_OC_RCN_DYN_RATE_LO__W 16 #define FEC_OC_RCN_DYN_RATE_LO__M 0 xFFFF#define FEC_OC_RCN_DYN_RATE_LO__PRE 0 x0#define FEC_OC_RCN_DYN_RATE_LO_RATE_LO__B 0 #define FEC_OC_RCN_DYN_RATE_LO_RATE_LO__W 16 #define FEC_OC_RCN_DYN_RATE_LO_RATE_LO__M 0 xFFFF#define FEC_OC_RCN_DYN_RATE_LO_RATE_LO__PRE 0 x0#define FEC_OC_RCN_DYN_RATE_HI__A 0 x244003B#define FEC_OC_RCN_DYN_RATE_HI__W 8 #define FEC_OC_RCN_DYN_RATE_HI__M 0 xFF#define FEC_OC_RCN_DYN_RATE_HI__PRE 0 x0#define FEC_OC_RCN_DYN_RATE_HI_RATE_HI__B 0 #define FEC_OC_RCN_DYN_RATE_HI_RATE_HI__W 8 #define FEC_OC_RCN_DYN_RATE_HI_RATE_HI__M 0 xFF#define FEC_OC_RCN_DYN_RATE_HI_RATE_HI__PRE 0 x0#define FEC_OC_SNC_MODE__A 0 x2440040#define FEC_OC_SNC_MODE__W 4 #define FEC_OC_SNC_MODE__M 0 xF#define FEC_OC_SNC_MODE__PRE 0 x0#define FEC_OC_SNC_MODE_UNLOCK_ENABLE__B 0 #define FEC_OC_SNC_MODE_UNLOCK_ENABLE__W 1 #define FEC_OC_SNC_MODE_UNLOCK_ENABLE__M 0 x1#define FEC_OC_SNC_MODE_UNLOCK_ENABLE__PRE 0 x0#define FEC_OC_SNC_MODE_ERROR_CTL__B 1 #define FEC_OC_SNC_MODE_ERROR_CTL__W 2 #define FEC_OC_SNC_MODE_ERROR_CTL__M 0 x6#define FEC_OC_SNC_MODE_ERROR_CTL__PRE 0 x0#define FEC_OC_SNC_MODE_CORR_DISABLE__B 3 #define FEC_OC_SNC_MODE_CORR_DISABLE__W 1 #define FEC_OC_SNC_MODE_CORR_DISABLE__M 0 x8#define FEC_OC_SNC_MODE_CORR_DISABLE__PRE 0 x0#define FEC_OC_SNC_LWM__A 0 x2440041#define FEC_OC_SNC_LWM__W 4 #define FEC_OC_SNC_LWM__M 0 xF#define FEC_OC_SNC_LWM__PRE 0 x3#define FEC_OC_SNC_LWM_MARK__B 0 #define FEC_OC_SNC_LWM_MARK__W 4 #define FEC_OC_SNC_LWM_MARK__M 0 xF#define FEC_OC_SNC_LWM_MARK__PRE 0 x3#define FEC_OC_SNC_HWM__A 0 x2440042#define FEC_OC_SNC_HWM__W 4 #define FEC_OC_SNC_HWM__M 0 xF#define FEC_OC_SNC_HWM__PRE 0 x5#define FEC_OC_SNC_HWM_MARK__B 0 #define FEC_OC_SNC_HWM_MARK__W 4 #define FEC_OC_SNC_HWM_MARK__M 0 xF#define FEC_OC_SNC_HWM_MARK__PRE 0 x5#define FEC_OC_SNC_UNLOCK__A 0 x2440043#define FEC_OC_SNC_UNLOCK__W 1 #define FEC_OC_SNC_UNLOCK__M 0 x1#define FEC_OC_SNC_UNLOCK__PRE 0 x0#define FEC_OC_SNC_UNLOCK_RESTART__B 0 #define FEC_OC_SNC_UNLOCK_RESTART__W 1 #define FEC_OC_SNC_UNLOCK_RESTART__M 0 x1#define FEC_OC_SNC_UNLOCK_RESTART__PRE 0 x0#define FEC_OC_SNC_LOCK_COUNT__A 0 x2440044#define FEC_OC_SNC_LOCK_COUNT__W 12 #define FEC_OC_SNC_LOCK_COUNT__M 0 xFFF#define FEC_OC_SNC_LOCK_COUNT__PRE 0 x0#define FEC_OC_SNC_LOCK_COUNT_COUNT__B 0 #define FEC_OC_SNC_LOCK_COUNT_COUNT__W 12 #define FEC_OC_SNC_LOCK_COUNT_COUNT__M 0 xFFF#define FEC_OC_SNC_LOCK_COUNT_COUNT__PRE 0 x0#define FEC_OC_SNC_FAIL_COUNT__A 0 x2440045#define FEC_OC_SNC_FAIL_COUNT__W 12 #define FEC_OC_SNC_FAIL_COUNT__M 0 xFFF#define FEC_OC_SNC_FAIL_COUNT__PRE 0 x0#define FEC_OC_SNC_FAIL_COUNT_COUNT__B 0 #define FEC_OC_SNC_FAIL_COUNT_COUNT__W 12 #define FEC_OC_SNC_FAIL_COUNT_COUNT__M 0 xFFF#define FEC_OC_SNC_FAIL_COUNT_COUNT__PRE 0 x0#define FEC_OC_SNC_FAIL_PERIOD__A 0 x2440046#define FEC_OC_SNC_FAIL_PERIOD__W 16 #define FEC_OC_SNC_FAIL_PERIOD__M 0 xFFFF#define FEC_OC_SNC_FAIL_PERIOD__PRE 0 x1171#define FEC_OC_SNC_FAIL_PERIOD_PERIOD__B 0 #define FEC_OC_SNC_FAIL_PERIOD_PERIOD__W 16 #define FEC_OC_SNC_FAIL_PERIOD_PERIOD__M 0 xFFFF#define FEC_OC_SNC_FAIL_PERIOD_PERIOD__PRE 0 x1171#define FEC_OC_EMS_MODE__A 0 x2440047#define FEC_OC_EMS_MODE__W 2 #define FEC_OC_EMS_MODE__M 0 x3#define FEC_OC_EMS_MODE__PRE 0 x0#define FEC_OC_EMS_MODE_MODE__B 0 #define FEC_OC_EMS_MODE_MODE__W 2 #define FEC_OC_EMS_MODE_MODE__M 0 x3#define FEC_OC_EMS_MODE_MODE__PRE 0 x0#define FEC_OC_IPR_MODE__A 0 x2440048#define FEC_OC_IPR_MODE__W 12 #define FEC_OC_IPR_MODE__M 0 xFFF#define FEC_OC_IPR_MODE__PRE 0 x0#define FEC_OC_IPR_MODE_SERIAL__B 0 #define FEC_OC_IPR_MODE_SERIAL__W 1 #define FEC_OC_IPR_MODE_SERIAL__M 0 x1#define FEC_OC_IPR_MODE_SERIAL__PRE 0 x0#define FEC_OC_IPR_MODE_REVERSE_ORDER__B 1 #define FEC_OC_IPR_MODE_REVERSE_ORDER__W 1 #define FEC_OC_IPR_MODE_REVERSE_ORDER__M 0 x2#define FEC_OC_IPR_MODE_REVERSE_ORDER__PRE 0 x0#define FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__B 2 #define FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__W 1 #define FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__M 0 x4#define FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__PRE 0 x0#define FEC_OC_IPR_MODE_MCLK_DIS_PAR__B 3 #define FEC_OC_IPR_MODE_MCLK_DIS_PAR__W 1 #define FEC_OC_IPR_MODE_MCLK_DIS_PAR__M 0 x8#define FEC_OC_IPR_MODE_MCLK_DIS_PAR__PRE 0 x0#define FEC_OC_IPR_MODE_MVAL_DIS_PAR__B 4 #define FEC_OC_IPR_MODE_MVAL_DIS_PAR__W 1 #define FEC_OC_IPR_MODE_MVAL_DIS_PAR__M 0 x10#define FEC_OC_IPR_MODE_MVAL_DIS_PAR__PRE 0 x0#define FEC_OC_IPR_MODE_MERR_DIS_PAR__B 5 #define FEC_OC_IPR_MODE_MERR_DIS_PAR__W 1 #define FEC_OC_IPR_MODE_MERR_DIS_PAR__M 0 x20#define FEC_OC_IPR_MODE_MERR_DIS_PAR__PRE 0 x0#define FEC_OC_IPR_MODE_MD_DIS_PAR__B 6 #define FEC_OC_IPR_MODE_MD_DIS_PAR__W 1 #define FEC_OC_IPR_MODE_MD_DIS_PAR__M 0 x40#define FEC_OC_IPR_MODE_MD_DIS_PAR__PRE 0 x0#define FEC_OC_IPR_MODE_MCLK_DIS_ERR__B 7 #define FEC_OC_IPR_MODE_MCLK_DIS_ERR__W 1 #define FEC_OC_IPR_MODE_MCLK_DIS_ERR__M 0 x80#define FEC_OC_IPR_MODE_MCLK_DIS_ERR__PRE 0 x0#define FEC_OC_IPR_MODE_MVAL_DIS_ERR__B 8 #define FEC_OC_IPR_MODE_MVAL_DIS_ERR__W 1 #define FEC_OC_IPR_MODE_MVAL_DIS_ERR__M 0 x100#define FEC_OC_IPR_MODE_MVAL_DIS_ERR__PRE 0 x0#define FEC_OC_IPR_MODE_MERR_DIS_ERR__B 9 #define FEC_OC_IPR_MODE_MERR_DIS_ERR__W 1 #define FEC_OC_IPR_MODE_MERR_DIS_ERR__M 0 x200#define FEC_OC_IPR_MODE_MERR_DIS_ERR__PRE 0 x0#define FEC_OC_IPR_MODE_MD_DIS_ERR__B 10 #define FEC_OC_IPR_MODE_MD_DIS_ERR__W 1 #define FEC_OC_IPR_MODE_MD_DIS_ERR__M 0 x400#define FEC_OC_IPR_MODE_MD_DIS_ERR__PRE 0 x0#define FEC_OC_IPR_MODE_MSTRT_DIS_ERR__B 11 #define FEC_OC_IPR_MODE_MSTRT_DIS_ERR__W 1 #define FEC_OC_IPR_MODE_MSTRT_DIS_ERR__M 0 x800#define FEC_OC_IPR_MODE_MSTRT_DIS_ERR__PRE 0 x0#define FEC_OC_IPR_INVERT__A 0 x2440049#define FEC_OC_IPR_INVERT__W 12 #define FEC_OC_IPR_INVERT__M 0 xFFF#define FEC_OC_IPR_INVERT__PRE 0 x0#define FEC_OC_IPR_INVERT_MD0__B 0 #define FEC_OC_IPR_INVERT_MD0__W 1 #define FEC_OC_IPR_INVERT_MD0__M 0 x1#define FEC_OC_IPR_INVERT_MD0__PRE 0 x0#define FEC_OC_IPR_INVERT_MD1__B 1 #define FEC_OC_IPR_INVERT_MD1__W 1 #define FEC_OC_IPR_INVERT_MD1__M 0 x2#define FEC_OC_IPR_INVERT_MD1__PRE 0 x0#define FEC_OC_IPR_INVERT_MD2__B 2 #define FEC_OC_IPR_INVERT_MD2__W 1 #define FEC_OC_IPR_INVERT_MD2__M 0 x4#define FEC_OC_IPR_INVERT_MD2__PRE 0 x0#define FEC_OC_IPR_INVERT_MD3__B 3 #define FEC_OC_IPR_INVERT_MD3__W 1 #define FEC_OC_IPR_INVERT_MD3__M 0 x8#define FEC_OC_IPR_INVERT_MD3__PRE 0 x0#define FEC_OC_IPR_INVERT_MD4__B 4 #define FEC_OC_IPR_INVERT_MD4__W 1 #define FEC_OC_IPR_INVERT_MD4__M 0 x10#define FEC_OC_IPR_INVERT_MD4__PRE 0 x0#define FEC_OC_IPR_INVERT_MD5__B 5 #define FEC_OC_IPR_INVERT_MD5__W 1 #define FEC_OC_IPR_INVERT_MD5__M 0 x20#define FEC_OC_IPR_INVERT_MD5__PRE 0 x0#define FEC_OC_IPR_INVERT_MD6__B 6 #define FEC_OC_IPR_INVERT_MD6__W 1 #define FEC_OC_IPR_INVERT_MD6__M 0 x40#define FEC_OC_IPR_INVERT_MD6__PRE 0 x0#define FEC_OC_IPR_INVERT_MD7__B 7 #define FEC_OC_IPR_INVERT_MD7__W 1 #define FEC_OC_IPR_INVERT_MD7__M 0 x80#define FEC_OC_IPR_INVERT_MD7__PRE 0 x0#define FEC_OC_IPR_INVERT_MERR__B 8 #define FEC_OC_IPR_INVERT_MERR__W 1 #define FEC_OC_IPR_INVERT_MERR__M 0 x100#define FEC_OC_IPR_INVERT_MERR__PRE 0 x0#define FEC_OC_IPR_INVERT_MSTRT__B 9 #define FEC_OC_IPR_INVERT_MSTRT__W 1 #define FEC_OC_IPR_INVERT_MSTRT__M 0 x200#define FEC_OC_IPR_INVERT_MSTRT__PRE 0 x0#define FEC_OC_IPR_INVERT_MVAL__B 10 #define FEC_OC_IPR_INVERT_MVAL__W 1 #define FEC_OC_IPR_INVERT_MVAL__M 0 x400#define FEC_OC_IPR_INVERT_MVAL__PRE 0 x0#define FEC_OC_IPR_INVERT_MCLK__B 11 #define FEC_OC_IPR_INVERT_MCLK__W 1 #define FEC_OC_IPR_INVERT_MCLK__M 0 x800#define FEC_OC_IPR_INVERT_MCLK__PRE 0 x0#define FEC_OC_OCR_MODE__A 0 x2440050#define FEC_OC_OCR_MODE__W 4 #define FEC_OC_OCR_MODE__M 0 xF#define FEC_OC_OCR_MODE__PRE 0 x0#define FEC_OC_OCR_MODE_MB_SELECT__B 0 #define FEC_OC_OCR_MODE_MB_SELECT__W 1 #define FEC_OC_OCR_MODE_MB_SELECT__M 0 x1#define FEC_OC_OCR_MODE_MB_SELECT__PRE 0 x0#define FEC_OC_OCR_MODE_GRAB_ENABLE__B 1 #define FEC_OC_OCR_MODE_GRAB_ENABLE__W 1 #define FEC_OC_OCR_MODE_GRAB_ENABLE__M 0 x2#define FEC_OC_OCR_MODE_GRAB_ENABLE__PRE 0 x0#define FEC_OC_OCR_MODE_GRAB_SELECT__B 2 #define FEC_OC_OCR_MODE_GRAB_SELECT__W 1 #define FEC_OC_OCR_MODE_GRAB_SELECT__M 0 x4#define FEC_OC_OCR_MODE_GRAB_SELECT__PRE 0 x0#define FEC_OC_OCR_MODE_GRAB_COUNTED__B 3 #define FEC_OC_OCR_MODE_GRAB_COUNTED__W 1 #define FEC_OC_OCR_MODE_GRAB_COUNTED__M 0 x8#define FEC_OC_OCR_MODE_GRAB_COUNTED__PRE 0 x0#define FEC_OC_OCR_RATE__A 0 x2440051#define FEC_OC_OCR_RATE__W 4 #define FEC_OC_OCR_RATE__M 0 xF#define FEC_OC_OCR_RATE__PRE 0 x0#define FEC_OC_OCR_RATE_RATE__B 0 #define FEC_OC_OCR_RATE_RATE__W 4 #define FEC_OC_OCR_RATE_RATE__M 0 xF#define FEC_OC_OCR_RATE_RATE__PRE 0 x0#define FEC_OC_OCR_INVERT__A 0 x2440052#define FEC_OC_OCR_INVERT__W 12 #define FEC_OC_OCR_INVERT__M 0 xFFF#define FEC_OC_OCR_INVERT__PRE 0 x800#define FEC_OC_OCR_INVERT_INVERT__B 0 #define FEC_OC_OCR_INVERT_INVERT__W 12 #define FEC_OC_OCR_INVERT_INVERT__M 0 xFFF#define FEC_OC_OCR_INVERT_INVERT__PRE 0 x800#define FEC_OC_OCR_GRAB_COUNT__A 0 x2440053#define FEC_OC_OCR_GRAB_COUNT__W 16 #define FEC_OC_OCR_GRAB_COUNT__M 0 xFFFF#define FEC_OC_OCR_GRAB_COUNT__PRE 0 x0#define FEC_OC_OCR_GRAB_COUNT_COUNT__B 0 #define FEC_OC_OCR_GRAB_COUNT_COUNT__W 16 #define FEC_OC_OCR_GRAB_COUNT_COUNT__M 0 xFFFF#define FEC_OC_OCR_GRAB_COUNT_COUNT__PRE 0 x0#define FEC_OC_OCR_GRAB_SYNC__A 0 x2440054#define FEC_OC_OCR_GRAB_SYNC__W 8 #define FEC_OC_OCR_GRAB_SYNC__M 0 xFF#define FEC_OC_OCR_GRAB_SYNC__PRE 0 x0#define FEC_OC_OCR_GRAB_SYNC_BYTE_SEL__B 0 #define FEC_OC_OCR_GRAB_SYNC_BYTE_SEL__W 3 #define FEC_OC_OCR_GRAB_SYNC_BYTE_SEL__M 0 x7#define FEC_OC_OCR_GRAB_SYNC_BYTE_SEL__PRE 0 x0#define FEC_OC_OCR_GRAB_SYNC_BIT_SEL__B 3 #define FEC_OC_OCR_GRAB_SYNC_BIT_SEL__W 4 #define FEC_OC_OCR_GRAB_SYNC_BIT_SEL__M 0 x78#define FEC_OC_OCR_GRAB_SYNC_BIT_SEL__PRE 0 x0#define FEC_OC_OCR_GRAB_SYNC_VALUE_SEL__B 7 #define FEC_OC_OCR_GRAB_SYNC_VALUE_SEL__W 1 #define FEC_OC_OCR_GRAB_SYNC_VALUE_SEL__M 0 x80#define FEC_OC_OCR_GRAB_SYNC_VALUE_SEL__PRE 0 x0#define FEC_OC_OCR_GRAB_RD0__A 0 x2440055#define FEC_OC_OCR_GRAB_RD0__W 10 #define FEC_OC_OCR_GRAB_RD0__M 0 x3FF#define FEC_OC_OCR_GRAB_RD0__PRE 0 x0#define FEC_OC_OCR_GRAB_RD0_DATA__B 0 #define FEC_OC_OCR_GRAB_RD0_DATA__W 10 #define FEC_OC_OCR_GRAB_RD0_DATA__M 0 x3FF#define FEC_OC_OCR_GRAB_RD0_DATA__PRE 0 x0#define FEC_OC_OCR_GRAB_RD1__A 0 x2440056#define FEC_OC_OCR_GRAB_RD1__W 10 #define FEC_OC_OCR_GRAB_RD1__M 0 x3FF#define FEC_OC_OCR_GRAB_RD1__PRE 0 x0#define FEC_OC_OCR_GRAB_RD1_DATA__B 0 #define FEC_OC_OCR_GRAB_RD1_DATA__W 10 #define FEC_OC_OCR_GRAB_RD1_DATA__M 0 x3FF#define FEC_OC_OCR_GRAB_RD1_DATA__PRE 0 x0#define FEC_OC_OCR_GRAB_RD2__A 0 x2440057#define FEC_OC_OCR_GRAB_RD2__W 10 #define FEC_OC_OCR_GRAB_RD2__M 0 x3FF#define FEC_OC_OCR_GRAB_RD2__PRE 0 x0#define FEC_OC_OCR_GRAB_RD2_DATA__B 0 #define FEC_OC_OCR_GRAB_RD2_DATA__W 10 #define FEC_OC_OCR_GRAB_RD2_DATA__M 0 x3FF#define FEC_OC_OCR_GRAB_RD2_DATA__PRE 0 x0#define FEC_OC_OCR_GRAB_RD3__A 0 x2440058#define FEC_OC_OCR_GRAB_RD3__W 10 #define FEC_OC_OCR_GRAB_RD3__M 0 x3FF#define FEC_OC_OCR_GRAB_RD3__PRE 0 x0#define FEC_OC_OCR_GRAB_RD3_DATA__B 0 #define FEC_OC_OCR_GRAB_RD3_DATA__W 10 #define FEC_OC_OCR_GRAB_RD3_DATA__M 0 x3FF#define FEC_OC_OCR_GRAB_RD3_DATA__PRE 0 x0#define FEC_OC_OCR_GRAB_RD4__A 0 x2440059#define FEC_OC_OCR_GRAB_RD4__W 10 #define FEC_OC_OCR_GRAB_RD4__M 0 x3FF#define FEC_OC_OCR_GRAB_RD4__PRE 0 x0#define FEC_OC_OCR_GRAB_RD4_DATA__B 0 #define FEC_OC_OCR_GRAB_RD4_DATA__W 10 #define FEC_OC_OCR_GRAB_RD4_DATA__M 0 x3FF#define FEC_OC_OCR_GRAB_RD4_DATA__PRE 0 x0#define FEC_OC_OCR_GRAB_RD5__A 0 x244005A#define FEC_OC_OCR_GRAB_RD5__W 10 #define FEC_OC_OCR_GRAB_RD5__M 0 x3FF#define FEC_OC_OCR_GRAB_RD5__PRE 0 x0#define FEC_OC_OCR_GRAB_RD5_DATA__B 0 #define FEC_OC_OCR_GRAB_RD5_DATA__W 10 #define FEC_OC_OCR_GRAB_RD5_DATA__M 0 x3FF#define FEC_OC_OCR_GRAB_RD5_DATA__PRE 0 x0#define FEC_DI_RAM__A 0 x2450000#define FEC_RS_RAM__A 0 x2460000#define FEC_OC_RAM__A 0 x2470000#define IQM_COMM_EXEC__A 0 x1800000#define IQM_COMM_EXEC__W 2 #define IQM_COMM_EXEC__M 0 x3#define IQM_COMM_EXEC__PRE 0 x0#define IQM_COMM_EXEC_STOP 0 x0#define IQM_COMM_EXEC_ACTIVE 0 x1#define IQM_COMM_EXEC_HOLD 0 x2#define IQM_COMM_MB__A 0 x1800002#define IQM_COMM_MB__W 16 #define IQM_COMM_MB__M 0 xFFFF#define IQM_COMM_MB__PRE 0 x0#define IQM_COMM_INT_REQ__A 0 x1800003#define IQM_COMM_INT_REQ__W 2 #define IQM_COMM_INT_REQ__M 0 x3#define IQM_COMM_INT_REQ__PRE 0 x0#define IQM_COMM_INT_REQ_AF_REQ__B 0 #define IQM_COMM_INT_REQ_AF_REQ__W 1 #define IQM_COMM_INT_REQ_AF_REQ__M 0 x1#define IQM_COMM_INT_REQ_AF_REQ__PRE 0 x0#define IQM_COMM_INT_REQ_CF_REQ__B 1 #define IQM_COMM_INT_REQ_CF_REQ__W 1 #define IQM_COMM_INT_REQ_CF_REQ__M 0 x2#define IQM_COMM_INT_REQ_CF_REQ__PRE 0 x0#define IQM_COMM_INT_STA__A 0 x1800005#define IQM_COMM_INT_STA__W 16 #define IQM_COMM_INT_STA__M 0 xFFFF#define IQM_COMM_INT_STA__PRE 0 x0#define IQM_COMM_INT_MSK__A 0 x1800006#define IQM_COMM_INT_MSK__W 16 #define IQM_COMM_INT_MSK__M 0 xFFFF#define IQM_COMM_INT_MSK__PRE 0 x0#define IQM_COMM_INT_STM__A 0 x1800007#define IQM_COMM_INT_STM__W 16 #define IQM_COMM_INT_STM__M 0 xFFFF#define IQM_COMM_INT_STM__PRE 0 x0#define IQM_FS_COMM_EXEC__A 0 x1820000#define IQM_FS_COMM_EXEC__W 2 #define IQM_FS_COMM_EXEC__M 0 x3#define IQM_FS_COMM_EXEC__PRE 0 x0#define IQM_FS_COMM_EXEC_STOP 0 x0#define IQM_FS_COMM_EXEC_ACTIVE 0 x1#define IQM_FS_COMM_EXEC_HOLD 0 x2#define IQM_FS_COMM_MB__A 0 x1820002#define IQM_FS_COMM_MB__W 2 #define IQM_FS_COMM_MB__M 0 x3#define IQM_FS_COMM_MB__PRE 0 x0#define IQM_FS_COMM_MB_CTL__B 0 #define IQM_FS_COMM_MB_CTL__W 1 #define IQM_FS_COMM_MB_CTL__M 0 x1#define IQM_FS_COMM_MB_CTL__PRE 0 x0#define IQM_FS_COMM_MB_CTL_CTL_OFF 0 x0#define IQM_FS_COMM_MB_CTL_CTL_ON 0 x1#define IQM_FS_COMM_MB_OBS__B 1 #define IQM_FS_COMM_MB_OBS__W 1 #define IQM_FS_COMM_MB_OBS__M 0 x2#define IQM_FS_COMM_MB_OBS__PRE 0 x0#define IQM_FS_COMM_MB_OBS_OBS_OFF 0 x0#define IQM_FS_COMM_MB_OBS_OBS_ON 0 x2#define IQM_FS_RATE_OFS_LO__A 0 x1820010#define IQM_FS_RATE_OFS_LO__W 16 #define IQM_FS_RATE_OFS_LO__M 0 xFFFF#define IQM_FS_RATE_OFS_LO__PRE 0 x0#define IQM_FS_RATE_OFS_HI__A 0 x1820011#define IQM_FS_RATE_OFS_HI__W 12 #define IQM_FS_RATE_OFS_HI__M 0 xFFF#define IQM_FS_RATE_OFS_HI__PRE 0 x0#define IQM_FS_RATE_LO__A 0 x1820012#define IQM_FS_RATE_LO__W 16 #define IQM_FS_RATE_LO__M 0 xFFFF#define IQM_FS_RATE_LO__PRE 0 x0#define IQM_FS_RATE_HI__A 0 x1820013#define IQM_FS_RATE_HI__W 12 #define IQM_FS_RATE_HI__M 0 xFFF#define IQM_FS_RATE_HI__PRE 0 x0#define IQM_FS_ADJ_SEL__A 0 x1820014#define IQM_FS_ADJ_SEL__W 2 #define IQM_FS_ADJ_SEL__M 0 x3#define IQM_FS_ADJ_SEL__PRE 0 x0#define IQM_FS_ADJ_SEL_OFF 0 x0#define IQM_FS_ADJ_SEL_QAM 0 x1#define IQM_FS_ADJ_SEL_VSB 0 x2#define IQM_FD_COMM_EXEC__A 0 x1830000#define IQM_FD_COMM_EXEC__W 2 #define IQM_FD_COMM_EXEC__M 0 x3#define IQM_FD_COMM_EXEC__PRE 0 x0#define IQM_FD_COMM_EXEC_STOP 0 x0#define IQM_FD_COMM_EXEC_ACTIVE 0 x1#define IQM_FD_COMM_EXEC_HOLD 0 x2#define IQM_FD_COMM_MB__A 0 x1830002#define IQM_FD_COMM_MB__W 2 #define IQM_FD_COMM_MB__M 0 x3#define IQM_FD_COMM_MB__PRE 0 x0#define IQM_FD_COMM_MB_CTL__B 0 #define IQM_FD_COMM_MB_CTL__W 1 #define IQM_FD_COMM_MB_CTL__M 0 x1#define IQM_FD_COMM_MB_CTL__PRE 0 x0#define IQM_FD_COMM_MB_CTL_CTL_OFF 0 x0#define IQM_FD_COMM_MB_CTL_CTL_ON 0 x1#define IQM_FD_COMM_MB_OBS__B 1 #define IQM_FD_COMM_MB_OBS__W 1 #define IQM_FD_COMM_MB_OBS__M 0 x2#define IQM_FD_COMM_MB_OBS__PRE 0 x0#define IQM_FD_COMM_MB_OBS_OBS_OFF 0 x0#define IQM_FD_COMM_MB_OBS_OBS_ON 0 x2#define IQM_RC_COMM_EXEC__A 0 x1840000#define IQM_RC_COMM_EXEC__W 2 #define IQM_RC_COMM_EXEC__M 0 x3#define IQM_RC_COMM_EXEC__PRE 0 x0#define IQM_RC_COMM_EXEC_STOP 0 x0#define IQM_RC_COMM_EXEC_ACTIVE 0 x1#define IQM_RC_COMM_EXEC_HOLD 0 x2#define IQM_RC_COMM_MB__A 0 x1840002#define IQM_RC_COMM_MB__W 2 #define IQM_RC_COMM_MB__M 0 x3#define IQM_RC_COMM_MB__PRE 0 x0#define IQM_RC_COMM_MB_CTL__B 0 #define IQM_RC_COMM_MB_CTL__W 1 #define IQM_RC_COMM_MB_CTL__M 0 x1#define IQM_RC_COMM_MB_CTL__PRE 0 x0#define IQM_RC_COMM_MB_CTL_CTL_OFF 0 x0#define IQM_RC_COMM_MB_CTL_CTL_ON 0 x1#define IQM_RC_COMM_MB_OBS__B 1 #define IQM_RC_COMM_MB_OBS__W 1 #define IQM_RC_COMM_MB_OBS__M 0 x2#define IQM_RC_COMM_MB_OBS__PRE 0 x0#define IQM_RC_COMM_MB_OBS_OBS_OFF 0 x0#define IQM_RC_COMM_MB_OBS_OBS_ON 0 x2#define IQM_RC_RATE_OFS_LO__A 0 x1840010#define IQM_RC_RATE_OFS_LO__W 16 #define IQM_RC_RATE_OFS_LO__M 0 xFFFF#define IQM_RC_RATE_OFS_LO__PRE 0 x0#define IQM_RC_RATE_OFS_HI__A 0 x1840011#define IQM_RC_RATE_OFS_HI__W 8 #define IQM_RC_RATE_OFS_HI__M 0 xFF#define IQM_RC_RATE_OFS_HI__PRE 0 x0#define IQM_RC_RATE_LO__A 0 x1840012#define IQM_RC_RATE_LO__W 16 #define IQM_RC_RATE_LO__M 0 xFFFF#define IQM_RC_RATE_LO__PRE 0 x0#define IQM_RC_RATE_HI__A 0 x1840013#define IQM_RC_RATE_HI__W 8 #define IQM_RC_RATE_HI__M 0 xFF#define IQM_RC_RATE_HI__PRE 0 x0#define IQM_RC_ADJ_SEL__A 0 x1840014#define IQM_RC_ADJ_SEL__W 2 #define IQM_RC_ADJ_SEL__M 0 x3#define IQM_RC_ADJ_SEL__PRE 0 x0#define IQM_RC_ADJ_SEL_OFF 0 x0#define IQM_RC_ADJ_SEL_QAM 0 x1#define IQM_RC_ADJ_SEL_VSB 0 x2#define IQM_RC_CROUT_ENA__A 0 x1840015#define IQM_RC_CROUT_ENA__W 1 #define IQM_RC_CROUT_ENA__M 0 x1#define IQM_RC_CROUT_ENA__PRE 0 x0#define IQM_RC_CROUT_ENA_ENA__B 0 #define IQM_RC_CROUT_ENA_ENA__W 1 #define IQM_RC_CROUT_ENA_ENA__M 0 x1#define IQM_RC_CROUT_ENA_ENA__PRE 0 x0#define IQM_RC_STRETCH__A 0 x1840016#define IQM_RC_STRETCH__W 5 #define IQM_RC_STRETCH__M 0 x1F#define IQM_RC_STRETCH__PRE 0 x0#define IQM_RC_STRETCH_QAM_B_64 0 x1E#define IQM_RC_STRETCH_QAM_B_256 0 x1C#define IQM_RC_STRETCH_ATV 0 xF#define IQM_RT_COMM_EXEC__A 0 x1850000#define IQM_RT_COMM_EXEC__W 2 #define IQM_RT_COMM_EXEC__M 0 x3#define IQM_RT_COMM_EXEC__PRE 0 x0#define IQM_RT_COMM_EXEC_STOP 0 x0#define IQM_RT_COMM_EXEC_ACTIVE 0 x1#define IQM_RT_COMM_EXEC_HOLD 0 x2#define IQM_RT_COMM_MB__A 0 x1850002#define IQM_RT_COMM_MB__W 2 #define IQM_RT_COMM_MB__M 0 x3#define IQM_RT_COMM_MB__PRE 0 x0#define IQM_RT_COMM_MB_CTL__B 0 #define IQM_RT_COMM_MB_CTL__W 1 #define IQM_RT_COMM_MB_CTL__M 0 x1#define IQM_RT_COMM_MB_CTL__PRE 0 x0#define IQM_RT_COMM_MB_CTL_CTL_OFF 0 x0#define IQM_RT_COMM_MB_CTL_CTL_ON 0 x1#define IQM_RT_COMM_MB_OBS__B 1 #define IQM_RT_COMM_MB_OBS__W 1 #define IQM_RT_COMM_MB_OBS__M 0 x2#define IQM_RT_COMM_MB_OBS__PRE 0 x0#define IQM_RT_COMM_MB_OBS_OBS_OFF 0 x0#define IQM_RT_COMM_MB_OBS_OBS_ON 0 x2#define IQM_RT_ACTIVE__A 0 x1850010#define IQM_RT_ACTIVE__W 2 #define IQM_RT_ACTIVE__M 0 x3#define IQM_RT_ACTIVE__PRE 0 x0#define IQM_RT_ACTIVE_ACTIVE_RT__B 0 #define IQM_RT_ACTIVE_ACTIVE_RT__W 1 #define IQM_RT_ACTIVE_ACTIVE_RT__M 0 x1#define IQM_RT_ACTIVE_ACTIVE_RT__PRE 0 x0#define IQM_RT_ACTIVE_ACTIVE_RT_ATV_FCR_OFF 0 x0#define IQM_RT_ACTIVE_ACTIVE_RT_ATV_FCR_ON 0 x1#define IQM_RT_ACTIVE_ACTIVE_CR__B 1 #define IQM_RT_ACTIVE_ACTIVE_CR__W 1 #define IQM_RT_ACTIVE_ACTIVE_CR__M 0 x2#define IQM_RT_ACTIVE_ACTIVE_CR__PRE 0 x0#define IQM_RT_ACTIVE_ACTIVE_CR_ATV_CR_OFF 0 x0#define IQM_RT_ACTIVE_ACTIVE_CR_ATV_CR_ON 0 x2#define IQM_RT_LO_INCR__A 0 x1850011#define IQM_RT_LO_INCR__W 12 #define IQM_RT_LO_INCR__M 0 xFFF#define IQM_RT_LO_INCR__PRE 0 x588#define IQM_RT_LO_INCR_FM 0 x0#define IQM_RT_LO_INCR_MN 0 x588#define IQM_RT_ROT_BP__A 0 x1850012#define IQM_RT_ROT_BP__W 2 #define IQM_RT_ROT_BP__M 0 x3#define IQM_RT_ROT_BP__PRE 0 x0#define IQM_RT_ROT_BP_ROT_OFF__B 0 #define IQM_RT_ROT_BP_ROT_OFF__W 1 #define IQM_RT_ROT_BP_ROT_OFF__M 0 x1#define IQM_RT_ROT_BP_ROT_OFF__PRE 0 x0#define IQM_RT_ROT_BP_ROT_OFF_ACTIVE 0 x0#define IQM_RT_ROT_BP_ROT_OFF_OFF 0 x1#define IQM_RT_ROT_BP_ROT_BPF__B 1 #define IQM_RT_ROT_BP_ROT_BPF__W 1 #define IQM_RT_ROT_BP_ROT_BPF__M 0 x2#define IQM_RT_ROT_BP_ROT_BPF__PRE 0 x0#define IQM_RT_LP_BP__A 0 x1850013#define IQM_RT_LP_BP__W 1 #define IQM_RT_LP_BP__M 0 x1#define IQM_RT_LP_BP__PRE 0 x0#define IQM_RT_DELAY__A 0 x1850014#define IQM_RT_DELAY__W 7 #define IQM_RT_DELAY__M 0 x7F#define IQM_RT_DELAY__PRE 0 x45#define IQM_CF_COMM_EXEC__A 0 x1860000#define IQM_CF_COMM_EXEC__W 2 #define IQM_CF_COMM_EXEC__M 0 x3#define IQM_CF_COMM_EXEC__PRE 0 x0#define IQM_CF_COMM_EXEC_STOP 0 x0#define IQM_CF_COMM_EXEC_ACTIVE 0 x1#define IQM_CF_COMM_EXEC_HOLD 0 x2#define IQM_CF_COMM_MB__A 0 x1860002#define IQM_CF_COMM_MB__W 2 #define IQM_CF_COMM_MB__M 0 x3#define IQM_CF_COMM_MB__PRE 0 x0#define IQM_CF_COMM_MB_CTL__B 0 #define IQM_CF_COMM_MB_CTL__W 1 #define IQM_CF_COMM_MB_CTL__M 0 x1#define IQM_CF_COMM_MB_CTL__PRE 0 x0#define IQM_CF_COMM_MB_CTL_CTL_OFF 0 x0#define IQM_CF_COMM_MB_CTL_CTL_ON 0 x1#define IQM_CF_COMM_MB_OBS__B 1 #define IQM_CF_COMM_MB_OBS__W 1 #define IQM_CF_COMM_MB_OBS__M 0 x2#define IQM_CF_COMM_MB_OBS__PRE 0 x0#define IQM_CF_COMM_MB_OBS_OBS_OFF 0 x0#define IQM_CF_COMM_MB_OBS_OBS_ON 0 x2#define IQM_CF_COMM_INT_REQ__A 0 x1860003#define IQM_CF_COMM_INT_REQ__W 1 #define IQM_CF_COMM_INT_REQ__M 0 x1#define IQM_CF_COMM_INT_REQ__PRE 0 x0#define IQM_CF_COMM_INT_STA__A 0 x1860005#define IQM_CF_COMM_INT_STA__W 1 #define IQM_CF_COMM_INT_STA__M 0 x1#define IQM_CF_COMM_INT_STA__PRE 0 x0#define IQM_CF_COMM_INT_STA_PM__B 0 #define IQM_CF_COMM_INT_STA_PM__W 1 #define IQM_CF_COMM_INT_STA_PM__M 0 x1#define IQM_CF_COMM_INT_STA_PM__PRE 0 x0#define IQM_CF_COMM_INT_MSK__A 0 x1860006#define IQM_CF_COMM_INT_MSK__W 1 #define IQM_CF_COMM_INT_MSK__M 0 x1#define IQM_CF_COMM_INT_MSK__PRE 0 x0#define IQM_CF_COMM_INT_MSK_PM__B 0 #define IQM_CF_COMM_INT_MSK_PM__W 1 #define IQM_CF_COMM_INT_MSK_PM__M 0 x1#define IQM_CF_COMM_INT_MSK_PM__PRE 0 x0#define IQM_CF_COMM_INT_STM__A 0 x1860007#define IQM_CF_COMM_INT_STM__W 1 #define IQM_CF_COMM_INT_STM__M 0 x1#define IQM_CF_COMM_INT_STM__PRE 0 x0#define IQM_CF_COMM_INT_STM_PM__B 0 #define IQM_CF_COMM_INT_STM_PM__W 1 #define IQM_CF_COMM_INT_STM_PM__M 0 x1#define IQM_CF_COMM_INT_STM_PM__PRE 0 x0#define IQM_CF_SYMMETRIC__A 0 x1860010#define IQM_CF_SYMMETRIC__W 2 #define IQM_CF_SYMMETRIC__M 0 x3#define IQM_CF_SYMMETRIC__PRE 0 x0#define IQM_CF_SYMMETRIC_RE__B 0 #define IQM_CF_SYMMETRIC_RE__W 1 #define IQM_CF_SYMMETRIC_RE__M 0 x1#define IQM_CF_SYMMETRIC_RE__PRE 0 x0#define IQM_CF_SYMMETRIC_IM__B 1 #define IQM_CF_SYMMETRIC_IM__W 1 #define IQM_CF_SYMMETRIC_IM__M 0 x2#define IQM_CF_SYMMETRIC_IM__PRE 0 x0#define IQM_CF_MIDTAP__A 0 x1860011#define IQM_CF_MIDTAP__W 2 #define IQM_CF_MIDTAP__M 0 x3#define IQM_CF_MIDTAP__PRE 0 x3#define IQM_CF_MIDTAP_RE__B 0 #define IQM_CF_MIDTAP_RE__W 1 #define IQM_CF_MIDTAP_RE__M 0 x1#define IQM_CF_MIDTAP_RE__PRE 0 x1#define IQM_CF_MIDTAP_IM__B 1 #define IQM_CF_MIDTAP_IM__W 1 #define IQM_CF_MIDTAP_IM__M 0 x2#define IQM_CF_MIDTAP_IM__PRE 0 x2#define IQM_CF_OUT_ENA__A 0 x1860012#define IQM_CF_OUT_ENA__W 3 #define IQM_CF_OUT_ENA__M 0 x7#define IQM_CF_OUT_ENA__PRE 0 x0#define IQM_CF_OUT_ENA_ATV__B 0 #define IQM_CF_OUT_ENA_ATV__W 1 #define IQM_CF_OUT_ENA_ATV__M 0 x1#define IQM_CF_OUT_ENA_ATV__PRE 0 x0#define IQM_CF_OUT_ENA_QAM__B 1 #define IQM_CF_OUT_ENA_QAM__W 1 #define IQM_CF_OUT_ENA_QAM__M 0 x2#define IQM_CF_OUT_ENA_QAM__PRE 0 x0#define IQM_CF_OUT_ENA_VSB__B 2 #define IQM_CF_OUT_ENA_VSB__W 1 #define IQM_CF_OUT_ENA_VSB__M 0 x4#define IQM_CF_OUT_ENA_VSB__PRE 0 x0#define IQM_CF_ADJ_SEL__A 0 x1860013#define IQM_CF_ADJ_SEL__W 2 #define IQM_CF_ADJ_SEL__M 0 x3#define IQM_CF_ADJ_SEL__PRE 0 x0#define IQM_CF_SCALE__A 0 x1860014#define IQM_CF_SCALE__W 14 #define IQM_CF_SCALE__M 0 x3FFF#define IQM_CF_SCALE__PRE 0 x400#define IQM_CF_SCALE_SH__A 0 x1860015#define IQM_CF_SCALE_SH__W 2 #define IQM_CF_SCALE_SH__M 0 x3#define IQM_CF_SCALE_SH__PRE 0 x0#define IQM_CF_AMP__A 0 x1860016#define IQM_CF_AMP__W 14 #define IQM_CF_AMP__M 0 x3FFF#define IQM_CF_AMP__PRE 0 x0#define IQM_CF_POW_MEAS_LEN__A 0 x1860017#define IQM_CF_POW_MEAS_LEN__W 3 #define IQM_CF_POW_MEAS_LEN__M 0 x7#define IQM_CF_POW_MEAS_LEN__PRE 0 x2#define IQM_CF_POW_MEAS_LEN_QAM_B_64 0 x1#define IQM_CF_POW_MEAS_LEN_QAM_B_256 0 x1#define IQM_CF_POW__A 0 x1860018#define IQM_CF_POW__W 16 #define IQM_CF_POW__M 0 xFFFF#define IQM_CF_POW__PRE 0 x2#define IQM_CF_TAP_RE0__A 0 x1860020#define IQM_CF_TAP_RE0__W 7 #define IQM_CF_TAP_RE0__M 0 x7F#define IQM_CF_TAP_RE0__PRE 0 x2#define IQM_CF_TAP_RE1__A 0 x1860021#define IQM_CF_TAP_RE1__W 7 #define IQM_CF_TAP_RE1__M 0 x7F#define IQM_CF_TAP_RE1__PRE 0 x2#define IQM_CF_TAP_RE2__A 0 x1860022#define IQM_CF_TAP_RE2__W 7 #define IQM_CF_TAP_RE2__M 0 x7F#define IQM_CF_TAP_RE2__PRE 0 x2#define IQM_CF_TAP_RE3__A 0 x1860023#define IQM_CF_TAP_RE3__W 7 #define IQM_CF_TAP_RE3__M 0 x7F#define IQM_CF_TAP_RE3__PRE 0 x2#define IQM_CF_TAP_RE4__A 0 x1860024#define IQM_CF_TAP_RE4__W 7 #define IQM_CF_TAP_RE4__M 0 x7F#define IQM_CF_TAP_RE4__PRE 0 x2#define IQM_CF_TAP_RE5__A 0 x1860025#define IQM_CF_TAP_RE5__W 7 #define IQM_CF_TAP_RE5__M 0 x7F#define IQM_CF_TAP_RE5__PRE 0 x2#define IQM_CF_TAP_RE6__A 0 x1860026#define IQM_CF_TAP_RE6__W 7 #define IQM_CF_TAP_RE6__M 0 x7F#define IQM_CF_TAP_RE6__PRE 0 x2#define IQM_CF_TAP_RE7__A 0 x1860027#define IQM_CF_TAP_RE7__W 9 #define IQM_CF_TAP_RE7__M 0 x1FF#define IQM_CF_TAP_RE7__PRE 0 x2#define IQM_CF_TAP_RE8__A 0 x1860028#define IQM_CF_TAP_RE8__W 9 #define IQM_CF_TAP_RE8__M 0 x1FF#define IQM_CF_TAP_RE8__PRE 0 x2#define IQM_CF_TAP_RE9__A 0 x1860029#define IQM_CF_TAP_RE9__W 9 #define IQM_CF_TAP_RE9__M 0 x1FF#define IQM_CF_TAP_RE9__PRE 0 x2#define IQM_CF_TAP_RE10__A 0 x186002A#define IQM_CF_TAP_RE10__W 9 #define IQM_CF_TAP_RE10__M 0 x1FF#define IQM_CF_TAP_RE10__PRE 0 x2#define IQM_CF_TAP_RE11__A 0 x186002B#define IQM_CF_TAP_RE11__W 9 #define IQM_CF_TAP_RE11__M 0 x1FF#define IQM_CF_TAP_RE11__PRE 0 x2#define IQM_CF_TAP_RE12__A 0 x186002C#define IQM_CF_TAP_RE12__W 9 #define IQM_CF_TAP_RE12__M 0 x1FF#define IQM_CF_TAP_RE12__PRE 0 x2#define IQM_CF_TAP_RE13__A 0 x186002D#define IQM_CF_TAP_RE13__W 9 #define IQM_CF_TAP_RE13__M 0 x1FF#define IQM_CF_TAP_RE13__PRE 0 x2#define IQM_CF_TAP_RE14__A 0 x186002E#define IQM_CF_TAP_RE14__W 9 #define IQM_CF_TAP_RE14__M 0 x1FF#define IQM_CF_TAP_RE14__PRE 0 x2#define IQM_CF_TAP_RE15__A 0 x186002F#define IQM_CF_TAP_RE15__W 9 #define IQM_CF_TAP_RE15__M 0 x1FF#define IQM_CF_TAP_RE15__PRE 0 x2#define IQM_CF_TAP_RE16__A 0 x1860030#define IQM_CF_TAP_RE16__W 9 #define IQM_CF_TAP_RE16__M 0 x1FF#define IQM_CF_TAP_RE16__PRE 0 x2#define IQM_CF_TAP_RE17__A 0 x1860031#define IQM_CF_TAP_RE17__W 9 #define IQM_CF_TAP_RE17__M 0 x1FF#define IQM_CF_TAP_RE17__PRE 0 x2#define IQM_CF_TAP_RE18__A 0 x1860032#define IQM_CF_TAP_RE18__W 9 #define IQM_CF_TAP_RE18__M 0 x1FF#define IQM_CF_TAP_RE18__PRE 0 x2#define IQM_CF_TAP_RE19__A 0 x1860033#define IQM_CF_TAP_RE19__W 9 #define IQM_CF_TAP_RE19__M 0 x1FF#define IQM_CF_TAP_RE19__PRE 0 x2#define IQM_CF_TAP_RE20__A 0 x1860034#define IQM_CF_TAP_RE20__W 9 #define IQM_CF_TAP_RE20__M 0 x1FF#define IQM_CF_TAP_RE20__PRE 0 x2#define IQM_CF_TAP_RE21__A 0 x1860035#define IQM_CF_TAP_RE21__W 11 #define IQM_CF_TAP_RE21__M 0 x7FF#define IQM_CF_TAP_RE21__PRE 0 x2#define IQM_CF_TAP_RE22__A 0 x1860036#define IQM_CF_TAP_RE22__W 11 #define IQM_CF_TAP_RE22__M 0 x7FF#define IQM_CF_TAP_RE22__PRE 0 x2#define IQM_CF_TAP_RE23__A 0 x1860037#define IQM_CF_TAP_RE23__W 11 #define IQM_CF_TAP_RE23__M 0 x7FF#define IQM_CF_TAP_RE23__PRE 0 x2#define IQM_CF_TAP_RE24__A 0 x1860038#define IQM_CF_TAP_RE24__W 11 #define IQM_CF_TAP_RE24__M 0 x7FF#define IQM_CF_TAP_RE24__PRE 0 x2#define IQM_CF_TAP_RE25__A 0 x1860039#define IQM_CF_TAP_RE25__W 11 #define IQM_CF_TAP_RE25__M 0 x7FF#define IQM_CF_TAP_RE25__PRE 0 x2#define IQM_CF_TAP_RE26__A 0 x186003A#define IQM_CF_TAP_RE26__W 11 #define IQM_CF_TAP_RE26__M 0 x7FF#define IQM_CF_TAP_RE26__PRE 0 x2#define IQM_CF_TAP_RE27__A 0 x186003B#define IQM_CF_TAP_RE27__W 11 #define IQM_CF_TAP_RE27__M 0 x7FF#define IQM_CF_TAP_RE27__PRE 0 x2#define IQM_CF_TAP_IM0__A 0 x1860040#define IQM_CF_TAP_IM0__W 7 #define IQM_CF_TAP_IM0__M 0 x7F#define IQM_CF_TAP_IM0__PRE 0 x2#define IQM_CF_TAP_IM1__A 0 x1860041#define IQM_CF_TAP_IM1__W 7 #define IQM_CF_TAP_IM1__M 0 x7F#define IQM_CF_TAP_IM1__PRE 0 x2#define IQM_CF_TAP_IM2__A 0 x1860042#define IQM_CF_TAP_IM2__W 7 #define IQM_CF_TAP_IM2__M 0 x7F#define IQM_CF_TAP_IM2__PRE 0 x2#define IQM_CF_TAP_IM3__A 0 x1860043#define IQM_CF_TAP_IM3__W 7 #define IQM_CF_TAP_IM3__M 0 x7F#define IQM_CF_TAP_IM3__PRE 0 x2#define IQM_CF_TAP_IM4__A 0 x1860044#define IQM_CF_TAP_IM4__W 7 #define IQM_CF_TAP_IM4__M 0 x7F#define IQM_CF_TAP_IM4__PRE 0 x2#define IQM_CF_TAP_IM5__A 0 x1860045#define IQM_CF_TAP_IM5__W 7 #define IQM_CF_TAP_IM5__M 0 x7F#define IQM_CF_TAP_IM5__PRE 0 x2#define IQM_CF_TAP_IM6__A 0 x1860046#define IQM_CF_TAP_IM6__W 7 #define IQM_CF_TAP_IM6__M 0 x7F#define IQM_CF_TAP_IM6__PRE 0 x2#define IQM_CF_TAP_IM7__A 0 x1860047#define IQM_CF_TAP_IM7__W 9 #define IQM_CF_TAP_IM7__M 0 x1FF#define IQM_CF_TAP_IM7__PRE 0 x2#define IQM_CF_TAP_IM8__A 0 x1860048#define IQM_CF_TAP_IM8__W 9 #define IQM_CF_TAP_IM8__M 0 x1FF#define IQM_CF_TAP_IM8__PRE 0 x2#define IQM_CF_TAP_IM9__A 0 x1860049#define IQM_CF_TAP_IM9__W 9 #define IQM_CF_TAP_IM9__M 0 x1FF#define IQM_CF_TAP_IM9__PRE 0 x2#define IQM_CF_TAP_IM10__A 0 x186004A#define IQM_CF_TAP_IM10__W 9 #define IQM_CF_TAP_IM10__M 0 x1FF#define IQM_CF_TAP_IM10__PRE 0 x2#define IQM_CF_TAP_IM11__A 0 x186004B#define IQM_CF_TAP_IM11__W 9 #define IQM_CF_TAP_IM11__M 0 x1FF#define IQM_CF_TAP_IM11__PRE 0 x2#define IQM_CF_TAP_IM12__A 0 x186004C#define IQM_CF_TAP_IM12__W 9 #define IQM_CF_TAP_IM12__M 0 x1FF#define IQM_CF_TAP_IM12__PRE 0 x2#define IQM_CF_TAP_IM13__A 0 x186004D#define IQM_CF_TAP_IM13__W 9 #define IQM_CF_TAP_IM13__M 0 x1FF#define IQM_CF_TAP_IM13__PRE 0 x2#define IQM_CF_TAP_IM14__A 0 x186004E#define IQM_CF_TAP_IM14__W 9 #define IQM_CF_TAP_IM14__M 0 x1FF#define IQM_CF_TAP_IM14__PRE 0 x2#define IQM_CF_TAP_IM15__A 0 x186004F#define IQM_CF_TAP_IM15__W 9 #define IQM_CF_TAP_IM15__M 0 x1FF#define IQM_CF_TAP_IM15__PRE 0 x2#define IQM_CF_TAP_IM16__A 0 x1860050#define IQM_CF_TAP_IM16__W 9 #define IQM_CF_TAP_IM16__M 0 x1FF#define IQM_CF_TAP_IM16__PRE 0 x2#define IQM_CF_TAP_IM17__A 0 x1860051#define IQM_CF_TAP_IM17__W 9 #define IQM_CF_TAP_IM17__M 0 x1FF#define IQM_CF_TAP_IM17__PRE 0 x2#define IQM_CF_TAP_IM18__A 0 x1860052#define IQM_CF_TAP_IM18__W 9 #define IQM_CF_TAP_IM18__M 0 x1FF#define IQM_CF_TAP_IM18__PRE 0 x2#define IQM_CF_TAP_IM19__A 0 x1860053#define IQM_CF_TAP_IM19__W 9 #define IQM_CF_TAP_IM19__M 0 x1FF#define IQM_CF_TAP_IM19__PRE 0 x2#define IQM_CF_TAP_IM20__A 0 x1860054#define IQM_CF_TAP_IM20__W 9 #define IQM_CF_TAP_IM20__M 0 x1FF#define IQM_CF_TAP_IM20__PRE 0 x2#define IQM_CF_TAP_IM21__A 0 x1860055#define IQM_CF_TAP_IM21__W 11 #define IQM_CF_TAP_IM21__M 0 x7FF#define IQM_CF_TAP_IM21__PRE 0 x2#define IQM_CF_TAP_IM22__A 0 x1860056#define IQM_CF_TAP_IM22__W 11 #define IQM_CF_TAP_IM22__M 0 x7FF#define IQM_CF_TAP_IM22__PRE 0 x2#define IQM_CF_TAP_IM23__A 0 x1860057#define IQM_CF_TAP_IM23__W 11 #define IQM_CF_TAP_IM23__M 0 x7FF#define IQM_CF_TAP_IM23__PRE 0 x2#define IQM_CF_TAP_IM24__A 0 x1860058#define IQM_CF_TAP_IM24__W 11 #define IQM_CF_TAP_IM24__M 0 x7FF#define IQM_CF_TAP_IM24__PRE 0 x2#define IQM_CF_TAP_IM25__A 0 x1860059#define IQM_CF_TAP_IM25__W 11 #define IQM_CF_TAP_IM25__M 0 x7FF#define IQM_CF_TAP_IM25__PRE 0 x2#define IQM_CF_TAP_IM26__A 0 x186005A#define IQM_CF_TAP_IM26__W 11 #define IQM_CF_TAP_IM26__M 0 x7FF#define IQM_CF_TAP_IM26__PRE 0 x2#define IQM_CF_TAP_IM27__A 0 x186005B#define IQM_CF_TAP_IM27__W 11 #define IQM_CF_TAP_IM27__M 0 x7FF#define IQM_CF_TAP_IM27__PRE 0 x2#define IQM_AF_COMM_EXEC__A 0 x1870000#define IQM_AF_COMM_EXEC__W 2 #define IQM_AF_COMM_EXEC__M 0 x3#define IQM_AF_COMM_EXEC__PRE 0 x0#define IQM_AF_COMM_EXEC_STOP 0 x0#define IQM_AF_COMM_EXEC_ACTIVE 0 x1#define IQM_AF_COMM_EXEC_HOLD 0 x2#define IQM_AF_COMM_MB__A 0 x1870002#define IQM_AF_COMM_MB__W 8 #define IQM_AF_COMM_MB__M 0 xFF#define IQM_AF_COMM_MB__PRE 0 x0#define IQM_AF_COMM_MB_CTL__B 0 #define IQM_AF_COMM_MB_CTL__W 1 #define IQM_AF_COMM_MB_CTL__M 0 x1#define IQM_AF_COMM_MB_CTL__PRE 0 x0#define IQM_AF_COMM_MB_CTL_CTL_OFF 0 x0#define IQM_AF_COMM_MB_CTL_CTL_ON 0 x1#define IQM_AF_COMM_MB_OBS__B 1 #define IQM_AF_COMM_MB_OBS__W 1 #define IQM_AF_COMM_MB_OBS__M 0 x2#define IQM_AF_COMM_MB_OBS__PRE 0 x0#define IQM_AF_COMM_MB_OBS_OBS_OFF 0 x0#define IQM_AF_COMM_MB_OBS_OBS_ON 0 x2#define IQM_AF_COMM_MB_MUX_CTRL__B 2 #define IQM_AF_COMM_MB_MUX_CTRL__W 3 #define IQM_AF_COMM_MB_MUX_CTRL__M 0 x1C#define IQM_AF_COMM_MB_MUX_CTRL__PRE 0 x0#define IQM_AF_COMM_MB_MUX_CTRL_AF_DATA_INPUT 0 x0#define IQM_AF_COMM_MB_MUX_CTRL_SENSE_INPUT 0 x4#define IQM_AF_COMM_MB_MUX_CTRL_AF_DATA_OUTPUT 0 x8#define IQM_AF_COMM_MB_MUX_CTRL_IF_AGC_OUTPUT 0 xC#define IQM_AF_COMM_MB_MUX_CTRL_RF_AGC_OUTPUT 0 x10#define IQM_AF_COMM_MB_MUX_OBS__B 5 #define IQM_AF_COMM_MB_MUX_OBS__W 3 #define IQM_AF_COMM_MB_MUX_OBS__M 0 xE0#define IQM_AF_COMM_MB_MUX_OBS__PRE 0 x0#define IQM_AF_COMM_MB_MUX_OBS_AF_DATA_INPUT 0 x0#define IQM_AF_COMM_MB_MUX_OBS_SENSE_INPUT 0 x20#define IQM_AF_COMM_MB_MUX_OBS_AF_DATA_OUTPUT 0 x40#define IQM_AF_COMM_MB_MUX_OBS_IF_AGC_OUTPUT 0 x60#define IQM_AF_COMM_MB_MUX_OBS_RF_AGC_OUTPUT 0 x80#define IQM_AF_COMM_INT_REQ__A 0 x1870003#define IQM_AF_COMM_INT_REQ__W 1 #define IQM_AF_COMM_INT_REQ__M 0 x1#define IQM_AF_COMM_INT_REQ__PRE 0 x0#define IQM_AF_COMM_INT_STA__A 0 x1870005#define IQM_AF_COMM_INT_STA__W 2 #define IQM_AF_COMM_INT_STA__M 0 x3#define IQM_AF_COMM_INT_STA__PRE 0 x0#define IQM_AF_COMM_INT_STA_CLP_INT_STA__B 0 #define IQM_AF_COMM_INT_STA_CLP_INT_STA__W 1 #define IQM_AF_COMM_INT_STA_CLP_INT_STA__M 0 x1#define IQM_AF_COMM_INT_STA_CLP_INT_STA__PRE 0 x0#define IQM_AF_COMM_INT_STA_SNS_INT_STA__B 1 #define IQM_AF_COMM_INT_STA_SNS_INT_STA__W 1 #define IQM_AF_COMM_INT_STA_SNS_INT_STA__M 0 x2#define IQM_AF_COMM_INT_STA_SNS_INT_STA__PRE 0 x0#define IQM_AF_COMM_INT_MSK__A 0 x1870006#define IQM_AF_COMM_INT_MSK__W 2 #define IQM_AF_COMM_INT_MSK__M 0 x3#define IQM_AF_COMM_INT_MSK__PRE 0 x0#define IQM_AF_COMM_INT_MSK_CLP_INT_MSK__B 0 #define IQM_AF_COMM_INT_MSK_CLP_INT_MSK__W 1 #define IQM_AF_COMM_INT_MSK_CLP_INT_MSK__M 0 x1#define IQM_AF_COMM_INT_MSK_CLP_INT_MSK__PRE 0 x0#define IQM_AF_COMM_INT_MSK_SNS_INT_MSK__B 1 #define IQM_AF_COMM_INT_MSK_SNS_INT_MSK__W 1 #define IQM_AF_COMM_INT_MSK_SNS_INT_MSK__M 0 x2#define IQM_AF_COMM_INT_MSK_SNS_INT_MSK__PRE 0 x0#define IQM_AF_COMM_INT_STM__A 0 x1870007#define IQM_AF_COMM_INT_STM__W 2 #define IQM_AF_COMM_INT_STM__M 0 x3#define IQM_AF_COMM_INT_STM__PRE 0 x0#define IQM_AF_COMM_INT_STM_CLP_INT_STA__B 0 #define IQM_AF_COMM_INT_STM_CLP_INT_STA__W 1 #define IQM_AF_COMM_INT_STM_CLP_INT_STA__M 0 x1#define IQM_AF_COMM_INT_STM_CLP_INT_STA__PRE 0 x0#define IQM_AF_COMM_INT_STM_SNS_INT_STA__B 1 #define IQM_AF_COMM_INT_STM_SNS_INT_STA__W 1 #define IQM_AF_COMM_INT_STM_SNS_INT_STA__M 0 x2#define IQM_AF_COMM_INT_STM_SNS_INT_STA__PRE 0 x0#define IQM_AF_FDB_SEL__A 0 x1870010#define IQM_AF_FDB_SEL__W 1 #define IQM_AF_FDB_SEL__M 0 x1#define IQM_AF_FDB_SEL__PRE 0 x0#define IQM_AF_INVEXT__A 0 x1870011#define IQM_AF_INVEXT__W 1 #define IQM_AF_INVEXT__M 0 x1#define IQM_AF_INVEXT__PRE 0 x0#define IQM_AF_CLKNEG__A 0 x1870012#define IQM_AF_CLKNEG__W 2 #define IQM_AF_CLKNEG__M 0 x3#define IQM_AF_CLKNEG__PRE 0 x0#define IQM_AF_CLKNEG_CLKNEGPEAK__B 0 #define IQM_AF_CLKNEG_CLKNEGPEAK__W 1 #define IQM_AF_CLKNEG_CLKNEGPEAK__M 0 x1#define IQM_AF_CLKNEG_CLKNEGPEAK__PRE 0 x0#define IQM_AF_CLKNEG_CLKNEGPEAK_CLK_ADC_PEAK_POS 0 x0#define IQM_AF_CLKNEG_CLKNEGPEAK_CLK_ADC_PEAK_NEG 0 x1#define IQM_AF_CLKNEG_CLKNEGDATA__B 1 #define IQM_AF_CLKNEG_CLKNEGDATA__W 1 #define IQM_AF_CLKNEG_CLKNEGDATA__M 0 x2#define IQM_AF_CLKNEG_CLKNEGDATA__PRE 0 x0#define IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS 0 x0#define IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_NEG 0 x2#define IQM_AF_MON_IN_MUX__A 0 x1870013#define IQM_AF_MON_IN_MUX__W 2 #define IQM_AF_MON_IN_MUX__M 0 x3#define IQM_AF_MON_IN_MUX__PRE 0 x0#define IQM_AF_MON_IN5__A 0 x1870014#define IQM_AF_MON_IN5__W 10 #define IQM_AF_MON_IN5__M 0 x3FF#define IQM_AF_MON_IN5__PRE 0 x0#define IQM_AF_MON_IN4__A 0 x1870015#define IQM_AF_MON_IN4__W 10 #define IQM_AF_MON_IN4__M 0 x3FF#define IQM_AF_MON_IN4__PRE 0 x0#define IQM_AF_MON_IN3__A 0 x1870016#define IQM_AF_MON_IN3__W 10 #define IQM_AF_MON_IN3__M 0 x3FF#define IQM_AF_MON_IN3__PRE 0 x0#define IQM_AF_MON_IN2__A 0 x1870017#define IQM_AF_MON_IN2__W 10 #define IQM_AF_MON_IN2__M 0 x3FF#define IQM_AF_MON_IN2__PRE 0 x0#define IQM_AF_MON_IN1__A 0 x1870018#define IQM_AF_MON_IN1__W 10 #define IQM_AF_MON_IN1__M 0 x3FF#define IQM_AF_MON_IN1__PRE 0 x0#define IQM_AF_MON_IN0__A 0 x1870019#define IQM_AF_MON_IN0__W 10 #define IQM_AF_MON_IN0__M 0 x3FF#define IQM_AF_MON_IN0__PRE 0 x0#define IQM_AF_MON_IN_VAL__A 0 x187001A#define IQM_AF_MON_IN_VAL__W 1 #define IQM_AF_MON_IN_VAL__M 0 x1#define IQM_AF_MON_IN_VAL__PRE 0 x0#define IQM_AF_START_LOCK__A 0 x187001B#define IQM_AF_START_LOCK__W 1 #define IQM_AF_START_LOCK__M 0 x1#define IQM_AF_START_LOCK__PRE 0 x0#define IQM_AF_PHASE0__A 0 x187001C#define IQM_AF_PHASE0__W 7 #define IQM_AF_PHASE0__M 0 x7F#define IQM_AF_PHASE0__PRE 0 x0#define IQM_AF_PHASE1__A 0 x187001D#define IQM_AF_PHASE1__W 7 #define IQM_AF_PHASE1__M 0 x7F#define IQM_AF_PHASE1__PRE 0 x0#define IQM_AF_PHASE2__A 0 x187001E#define IQM_AF_PHASE2__W 7 #define IQM_AF_PHASE2__M 0 x7F#define IQM_AF_PHASE2__PRE 0 x0#define IQM_AF_SCU_PHASE__A 0 x187001F#define IQM_AF_SCU_PHASE__W 2 #define IQM_AF_SCU_PHASE__M 0 x3#define IQM_AF_SCU_PHASE__PRE 0 x0#define IQM_AF_SYNC_SEL__A 0 x1870020#define IQM_AF_SYNC_SEL__W 2 #define IQM_AF_SYNC_SEL__M 0 x3#define IQM_AF_SYNC_SEL__PRE 0 x0#define IQM_AF_ADC_CONF__A 0 x1870021#define IQM_AF_ADC_CONF__W 4 #define IQM_AF_ADC_CONF__M 0 xF#define IQM_AF_ADC_CONF__PRE 0 x0#define IQM_AF_ADC_CONF_ADC_SIGN__B 0 #define IQM_AF_ADC_CONF_ADC_SIGN__W 1 #define IQM_AF_ADC_CONF_ADC_SIGN__M 0 x1#define IQM_AF_ADC_CONF_ADC_SIGN__PRE 0 x0#define IQM_AF_ADC_CONF_ADC_SIGN_ADC_SIGNED 0 x0#define IQM_AF_ADC_CONF_ADC_SIGN_ADC_UNSIGNED 0 x1#define IQM_AF_ADC_CONF_BITREVERSE_ADC__B 1 #define IQM_AF_ADC_CONF_BITREVERSE_ADC__W 1 #define IQM_AF_ADC_CONF_BITREVERSE_ADC__M 0 x2#define IQM_AF_ADC_CONF_BITREVERSE_ADC__PRE 0 x0#define IQM_AF_ADC_CONF_BITREVERSE_ADC_ADC_NORMAL 0 x0#define IQM_AF_ADC_CONF_BITREVERSE_ADC_ADC_BITREVERSED 0 x2#define IQM_AF_ADC_CONF_BITREVERSE_NSSI__B 2 #define IQM_AF_ADC_CONF_BITREVERSE_NSSI__W 1 #define IQM_AF_ADC_CONF_BITREVERSE_NSSI__M 0 x4#define IQM_AF_ADC_CONF_BITREVERSE_NSSI__PRE 0 x0#define IQM_AF_ADC_CONF_BITREVERSE_NSSI_IFAGC_DAC_NORMAL 0 x0#define IQM_AF_ADC_CONF_BITREVERSE_NSSI_IFAGC_DAC_BITREVERSED 0 x4#define IQM_AF_ADC_CONF_BITREVERSE_NSSR__B 3 #define IQM_AF_ADC_CONF_BITREVERSE_NSSR__W 1 #define IQM_AF_ADC_CONF_BITREVERSE_NSSR__M 0 x8#define IQM_AF_ADC_CONF_BITREVERSE_NSSR__PRE 0 x0#define IQM_AF_ADC_CONF_BITREVERSE_NSSR_RFAGC_DAC_NORMAL 0 x0#define IQM_AF_ADC_CONF_BITREVERSE_NSSR_RFAGC_DAC_BITREVERSED 0 x8#define IQM_AF_CLP_CLIP__A 0 x1870022#define IQM_AF_CLP_CLIP__W 16 #define IQM_AF_CLP_CLIP__M 0 xFFFF#define IQM_AF_CLP_CLIP__PRE 0 x0#define IQM_AF_CLP_LEN__A 0 x1870023#define IQM_AF_CLP_LEN__W 16 #define IQM_AF_CLP_LEN__M 0 xFFFF#define IQM_AF_CLP_LEN__PRE 0 x0#define IQM_AF_CLP_LEN_QAM_B_64 0 x400#define IQM_AF_CLP_LEN_QAM_B_256 0 x400#define IQM_AF_CLP_LEN_ATV 0 x0#define IQM_AF_CLP_TH__A 0 x1870024#define IQM_AF_CLP_TH__W 9 #define IQM_AF_CLP_TH__M 0 x1FF#define IQM_AF_CLP_TH__PRE 0 x0#define IQM_AF_CLP_TH_QAM_B_64 0 x80#define IQM_AF_CLP_TH_QAM_B_256 0 x80#define IQM_AF_CLP_TH_ATV 0 x1C0#define IQM_AF_DCF_BYPASS__A 0 x1870025#define IQM_AF_DCF_BYPASS__W 1 #define IQM_AF_DCF_BYPASS__M 0 x1#define IQM_AF_DCF_BYPASS__PRE 0 x0#define IQM_AF_DCF_BYPASS_ACTIVE 0 x0#define IQM_AF_DCF_BYPASS_BYPASS 0 x1#define IQM_AF_SNS_LEN__A 0 x1870026#define IQM_AF_SNS_LEN__W 16 #define IQM_AF_SNS_LEN__M 0 xFFFF#define IQM_AF_SNS_LEN__PRE 0 x0#define IQM_AF_SNS_LEN_QAM_B_64 0 x400#define IQM_AF_SNS_LEN_QAM_B_256 0 x400#define IQM_AF_SNS_LEN_ATV 0 x0#define IQM_AF_SNS_SENSE__A 0 x1870027#define IQM_AF_SNS_SENSE__W 16 #define IQM_AF_SNS_SENSE__M 0 xFFFF#define IQM_AF_SNS_SENSE__PRE 0 x0#define IQM_AF_AGC_IF__A 0 x1870028#define IQM_AF_AGC_IF__W 15 #define IQM_AF_AGC_IF__M 0 x7FFF#define IQM_AF_AGC_IF__PRE 0 x0#define IQM_AF_AGC_RF__A 0 x1870029#define IQM_AF_AGC_RF__W 15 #define IQM_AF_AGC_RF__M 0 x7FFF#define IQM_AF_AGC_RF__PRE 0 x0#define IQM_AF_PGA_GAIN__A 0 x187002A#define IQM_AF_PGA_GAIN__W 4 #define IQM_AF_PGA_GAIN__M 0 xF#define IQM_AF_PGA_GAIN__PRE 0 x0#define IQM_AF_PDREF__A 0 x187002B#define IQM_AF_PDREF__W 5 #define IQM_AF_PDREF__M 0 x1F#define IQM_AF_PDREF__PRE 0 x0#define IQM_AF_PDREF_QAM_B_64 0 xF#define IQM_AF_PDREF_QAM_B_256 0 xF#define IQM_AF_PDREF_ATV 0 xF#define IQM_AF_STDBY__A 0 x187002C#define IQM_AF_STDBY__W 6 #define IQM_AF_STDBY__M 0 x3F#define IQM_AF_STDBY__PRE 0 x0#define IQM_AF_STDBY_STDBY_BIAS__B 0 #define IQM_AF_STDBY_STDBY_BIAS__W 1 #define IQM_AF_STDBY_STDBY_BIAS__M 0 x1#define IQM_AF_STDBY_STDBY_BIAS__PRE 0 x0#define IQM_AF_STDBY_STDBY_BIAS_ACTIVE 0 x0#define IQM_AF_STDBY_STDBY_BIAS_STANDBY 0 x1#define IQM_AF_STDBY_STDBY_ADC__B 1 #define IQM_AF_STDBY_STDBY_ADC__W 1 #define IQM_AF_STDBY_STDBY_ADC__M 0 x2#define IQM_AF_STDBY_STDBY_ADC__PRE 0 x0#define IQM_AF_STDBY_STDBY_ADC_A1_ACTIVE 0 x0#define IQM_AF_STDBY_STDBY_ADC_A1_STANDBY 0 x2#define IQM_AF_STDBY_STDBY_ADC_A2_ACTIVE 0 x2#define IQM_AF_STDBY_STDBY_ADC_A2_STANDBY 0 x0#define IQM_AF_STDBY_STDBY_AMP__B 2 #define IQM_AF_STDBY_STDBY_AMP__W 1 #define IQM_AF_STDBY_STDBY_AMP__M 0 x4#define IQM_AF_STDBY_STDBY_AMP__PRE 0 x0#define IQM_AF_STDBY_STDBY_AMP_A1_ACTIVE 0 x0#define IQM_AF_STDBY_STDBY_AMP_A1_STANDBY 0 x4#define IQM_AF_STDBY_STDBY_AMP_A2_ACTIVE 0 x4#define IQM_AF_STDBY_STDBY_AMP_A2_STANDBY 0 x0#define IQM_AF_STDBY_STDBY_PD__B 3 #define IQM_AF_STDBY_STDBY_PD__W 1 #define IQM_AF_STDBY_STDBY_PD__M 0 x8#define IQM_AF_STDBY_STDBY_PD__PRE 0 x0#define IQM_AF_STDBY_STDBY_PD_A1_ACTIVE 0 x0#define IQM_AF_STDBY_STDBY_PD_A1_STANDBY 0 x8#define IQM_AF_STDBY_STDBY_PD_A2_ACTIVE 0 x8#define IQM_AF_STDBY_STDBY_PD_A2_STANDBY 0 x0#define IQM_AF_STDBY_STDBY_TAGC_IF__B 4 #define IQM_AF_STDBY_STDBY_TAGC_IF__W 1 #define IQM_AF_STDBY_STDBY_TAGC_IF__M 0 x10#define IQM_AF_STDBY_STDBY_TAGC_IF__PRE 0 x0#define IQM_AF_STDBY_STDBY_TAGC_IF_A1_ACTIVE 0 x0#define IQM_AF_STDBY_STDBY_TAGC_IF_A1_STANDBY 0 x10#define IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE 0 x10#define IQM_AF_STDBY_STDBY_TAGC_IF_A2_STANDBY 0 x0#define IQM_AF_STDBY_STDBY_TAGC_RF__B 5 #define IQM_AF_STDBY_STDBY_TAGC_RF__W 1 #define IQM_AF_STDBY_STDBY_TAGC_RF__M 0 x20#define IQM_AF_STDBY_STDBY_TAGC_RF__PRE 0 x0#define IQM_AF_STDBY_STDBY_TAGC_RF_A1_ACTIVE 0 x0#define IQM_AF_STDBY_STDBY_TAGC_RF_A1_STANDBY 0 x20#define IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE 0 x20#define IQM_AF_STDBY_STDBY_TAGC_RF_A2_STANDBY 0 x0#define IQM_AF_AMUX__A 0 x187002D#define IQM_AF_AMUX__W 2 #define IQM_AF_AMUX__M 0 x3#define IQM_AF_AMUX__PRE 0 x0#define IQM_AF_TST_AFEMAIN__A 0 x187002E#define IQM_AF_TST_AFEMAIN__W 8 #define IQM_AF_TST_AFEMAIN__M 0 xFF#define IQM_AF_TST_AFEMAIN__PRE 0 x0#define IQM_RT_RAM__A 0 x1880000#define IQM_RT_RAM_DLY__B 0 #define IQM_RT_RAM_DLY__W 13 #define IQM_RT_RAM_DLY__M 0 x1FFF#define IQM_RT_RAM_DLY__PRE 0 x0#define ORX_COMM_EXEC__A 0 x2000000#define ORX_COMM_EXEC__W 2 #define ORX_COMM_EXEC__M 0 x3#define ORX_COMM_EXEC__PRE 0 x0#define ORX_COMM_EXEC_STOP 0 x0#define ORX_COMM_EXEC_ACTIVE 0 x1#define ORX_COMM_EXEC_HOLD 0 x2#define ORX_COMM_STATE__A 0 x2000001#define ORX_COMM_STATE__W 16 #define ORX_COMM_STATE__M 0 xFFFF#define ORX_COMM_STATE__PRE 0 x0#define ORX_COMM_MB__A 0 x2000002#define ORX_COMM_MB__W 16 #define ORX_COMM_MB__M 0 xFFFF#define ORX_COMM_MB__PRE 0 x0#define ORX_COMM_INT_REQ__A 0 x2000003#define ORX_COMM_INT_REQ__W 16 #define ORX_COMM_INT_REQ__M 0 xFFFF#define ORX_COMM_INT_REQ__PRE 0 x0#define ORX_COMM_INT_REQ_EQU_REQ__B 0 #define ORX_COMM_INT_REQ_EQU_REQ__W 1 #define ORX_COMM_INT_REQ_EQU_REQ__M 0 x1#define ORX_COMM_INT_REQ_EQU_REQ__PRE 0 x0#define ORX_COMM_INT_REQ_DDC_REQ__B 1 #define ORX_COMM_INT_REQ_DDC_REQ__W 1 #define ORX_COMM_INT_REQ_DDC_REQ__M 0 x2#define ORX_COMM_INT_REQ_DDC_REQ__PRE 0 x0#define ORX_COMM_INT_REQ_FWP_REQ__B 2 #define ORX_COMM_INT_REQ_FWP_REQ__W 1 #define ORX_COMM_INT_REQ_FWP_REQ__M 0 x4#define ORX_COMM_INT_REQ_FWP_REQ__PRE 0 x0#define ORX_COMM_INT_REQ_CON_REQ__B 3 #define ORX_COMM_INT_REQ_CON_REQ__W 1 #define ORX_COMM_INT_REQ_CON_REQ__M 0 x8#define ORX_COMM_INT_REQ_CON_REQ__PRE 0 x0#define ORX_COMM_INT_REQ_NSU_REQ__B 4 #define ORX_COMM_INT_REQ_NSU_REQ__W 1 #define ORX_COMM_INT_REQ_NSU_REQ__M 0 x10#define ORX_COMM_INT_REQ_NSU_REQ__PRE 0 x0#define ORX_COMM_INT_STA__A 0 x2000005#define ORX_COMM_INT_STA__W 16 #define ORX_COMM_INT_STA__M 0 xFFFF#define ORX_COMM_INT_STA__PRE 0 x0#define ORX_COMM_INT_MSK__A 0 x2000006#define ORX_COMM_INT_MSK__W 16 #define ORX_COMM_INT_MSK__M 0 xFFFF#define ORX_COMM_INT_MSK__PRE 0 x0#define ORX_COMM_INT_STM__A 0 x2000007#define ORX_COMM_INT_STM__W 16 #define ORX_COMM_INT_STM__M 0 xFFFF#define ORX_COMM_INT_STM__PRE 0 x0#define ORX_TOP_COMM_EXEC__A 0 x2010000#define ORX_TOP_COMM_EXEC__W 2 #define ORX_TOP_COMM_EXEC__M 0 x3#define ORX_TOP_COMM_EXEC__PRE 0 x0#define ORX_TOP_COMM_EXEC_STOP 0 x0#define ORX_TOP_COMM_EXEC_ACTIVE 0 x1#define ORX_TOP_COMM_EXEC_HOLD 0 x2#define ORX_TOP_COMM_KEY__A 0 x201000F#define ORX_TOP_COMM_KEY__W 16 #define ORX_TOP_COMM_KEY__M 0 xFFFF#define ORX_TOP_COMM_KEY__PRE 0 x0#define ORX_TOP_COMM_KEY_KEY 0 xFABA#define ORX_TOP_MDE_W__A 0 x2010010#define ORX_TOP_MDE_W__W 2 #define ORX_TOP_MDE_W__M 0 x3#define ORX_TOP_MDE_W__PRE 0 x2#define ORX_TOP_MDE_W_RATE_1544KBPS 0 x0#define ORX_TOP_MDE_W_RATE_3088KBPS 0 x1#define ORX_TOP_MDE_W_RATE_2048KBPS_SQRT 0 x2#define ORX_TOP_MDE_W_RATE_2048KBPS_RO 0 x3#define ORX_TOP_AIF_CTRL_W__A 0 x2010011#define ORX_TOP_AIF_CTRL_W__W 3 #define ORX_TOP_AIF_CTRL_W__M 0 x7#define ORX_TOP_AIF_CTRL_W__PRE 0 x0#define ORX_TOP_AIF_CTRL_W_NEG_CLK_EDGE__B 0 #define ORX_TOP_AIF_CTRL_W_NEG_CLK_EDGE__W 1 #define ORX_TOP_AIF_CTRL_W_NEG_CLK_EDGE__M 0 x1#define ORX_TOP_AIF_CTRL_W_NEG_CLK_EDGE__PRE 0 x0#define ORX_TOP_AIF_CTRL_W_NEG_CLK_EDGE_ADC_SAMPL_ON_POS_CLK_EDGE 0 x0#define ORX_TOP_AIF_CTRL_W_NEG_CLK_EDGE_ADC_SAMPL_ON_NEG_CLK_EDGE 0 x1#define ORX_TOP_AIF_CTRL_W_BIT_REVERSE__B 1 #define ORX_TOP_AIF_CTRL_W_BIT_REVERSE__W 1 #define ORX_TOP_AIF_CTRL_W_BIT_REVERSE__M 0 x2#define ORX_TOP_AIF_CTRL_W_BIT_REVERSE__PRE 0 x0#define ORX_TOP_AIF_CTRL_W_BIT_REVERSE_REGULAR_BIT_ORDER_ADC 0 x0#define ORX_TOP_AIF_CTRL_W_BIT_REVERSE_REVERSAL_BIT_ORDER_ADC 0 x2#define ORX_TOP_AIF_CTRL_W_INV_MSB__B 2 #define ORX_TOP_AIF_CTRL_W_INV_MSB__W 1 #define ORX_TOP_AIF_CTRL_W_INV_MSB__M 0 x4#define ORX_TOP_AIF_CTRL_W_INV_MSB__PRE 0 x0#define ORX_TOP_AIF_CTRL_W_INV_MSB_NO_MSB_INVERSION_ADC 0 x0#define ORX_TOP_AIF_CTRL_W_INV_MSB_MSB_INVERSION_ADC 0 x4#define ORX_FWP_COMM_EXEC__A 0 x2020000#define ORX_FWP_COMM_EXEC__W 2 #define ORX_FWP_COMM_EXEC__M 0 x3#define ORX_FWP_COMM_EXEC__PRE 0 x0#define ORX_FWP_COMM_EXEC_STOP 0 x0#define ORX_FWP_COMM_EXEC_ACTIVE 0 x1#define ORX_FWP_COMM_EXEC_HOLD 0 x2#define ORX_FWP_COMM_MB__A 0 x2020002#define ORX_FWP_COMM_MB__W 8 #define ORX_FWP_COMM_MB__M 0 xFF#define ORX_FWP_COMM_MB__PRE 0 x0#define ORX_FWP_COMM_MB_CTL__B 0 #define ORX_FWP_COMM_MB_CTL__W 1 #define ORX_FWP_COMM_MB_CTL__M 0 x1#define ORX_FWP_COMM_MB_CTL__PRE 0 x0#define ORX_FWP_COMM_MB_CTL_OFF 0 x0#define ORX_FWP_COMM_MB_CTL_ON 0 x1#define ORX_FWP_COMM_MB_OBS__B 1 #define ORX_FWP_COMM_MB_OBS__W 1 #define ORX_FWP_COMM_MB_OBS__M 0 x2#define ORX_FWP_COMM_MB_OBS__PRE 0 x0#define ORX_FWP_COMM_MB_OBS_OFF 0 x0#define ORX_FWP_COMM_MB_OBS_ON 0 x2#define ORX_FWP_COMM_MB_CTL_MUX__B 2 #define ORX_FWP_COMM_MB_CTL_MUX__W 3 #define ORX_FWP_COMM_MB_CTL_MUX__M 0 x1C#define ORX_FWP_COMM_MB_CTL_MUX__PRE 0 x0#define ORX_FWP_COMM_MB_OBS_MUX__B 5 #define ORX_FWP_COMM_MB_OBS_MUX__W 3 #define ORX_FWP_COMM_MB_OBS_MUX__M 0 xE0#define ORX_FWP_COMM_MB_OBS_MUX__PRE 0 x0#define ORX_FWP_AAG_LEN_W__A 0 x2020010#define ORX_FWP_AAG_LEN_W__W 16 #define ORX_FWP_AAG_LEN_W__M 0 xFFFF#define ORX_FWP_AAG_LEN_W__PRE 0 x800#define ORX_FWP_AAG_THR_W__A 0 x2020011#define ORX_FWP_AAG_THR_W__W 8 #define ORX_FWP_AAG_THR_W__M 0 xFF#define ORX_FWP_AAG_THR_W__PRE 0 x50#define ORX_FWP_AAG_THR_CNT_R__A 0 x2020012#define ORX_FWP_AAG_THR_CNT_R__W 16 #define ORX_FWP_AAG_THR_CNT_R__M 0 xFFFF#define ORX_FWP_AAG_THR_CNT_R__PRE 0 x0#define ORX_FWP_AAG_SNS_CNT_R__A 0 x2020013#define ORX_FWP_AAG_SNS_CNT_R__W 16 #define ORX_FWP_AAG_SNS_CNT_R__M 0 xFFFF#define ORX_FWP_AAG_SNS_CNT_R__PRE 0 x0#define ORX_FWP_PFI_A_W__A 0 x2020014#define ORX_FWP_PFI_A_W__W 8 #define ORX_FWP_PFI_A_W__M 0 xFF#define ORX_FWP_PFI_A_W__PRE 0 xB0#define ORX_FWP_PFI_A_W_RATE_2048KBPS 0 xB0#define ORX_FWP_PFI_A_W_RATE_1544KBPS 0 xA4#define ORX_FWP_PFI_A_W_RATE_3088KBPS 0 xC0#define ORX_FWP_PFI_B_W__A 0 x2020015#define ORX_FWP_PFI_B_W__W 8 #define ORX_FWP_PFI_B_W__M 0 xFF#define ORX_FWP_PFI_B_W__PRE 0 x9E#define ORX_FWP_PFI_B_W_RATE_2048KBPS 0 x9E#define ORX_FWP_PFI_B_W_RATE_1544KBPS 0 x94#define ORX_FWP_PFI_B_W_RATE_3088KBPS 0 xB0#define ORX_FWP_PFI_C_W__A 0 x2020016#define ORX_FWP_PFI_C_W__W 8 #define ORX_FWP_PFI_C_W__M 0 xFF#define ORX_FWP_PFI_C_W__PRE 0 x5C#define ORX_FWP_PFI_C_W_RATE_2048KBPS 0 x5C#define ORX_FWP_PFI_C_W_RATE_1544KBPS 0 x64#define ORX_FWP_PFI_C_W_RATE_3088KBPS 0 x50#define ORX_FWP_KR1_AMP_R__A 0 x2020017#define ORX_FWP_KR1_AMP_R__W 9 #define ORX_FWP_KR1_AMP_R__M 0 x1FF#define ORX_FWP_KR1_AMP_R__PRE 0 x0#define ORX_FWP_KR1_LDT_W__A 0 x2020018#define ORX_FWP_KR1_LDT_W__W 3 #define ORX_FWP_KR1_LDT_W__M 0 x7#define ORX_FWP_KR1_LDT_W__PRE 0 x2#define ORX_FWP_SRC_DGN_W__A 0 x2020019#define ORX_FWP_SRC_DGN_W__W 16 #define ORX_FWP_SRC_DGN_W__M 0 xFFFF#define ORX_FWP_SRC_DGN_W__PRE 0 x1FF#define ORX_FWP_SRC_DGN_W_MANT__B 0 #define ORX_FWP_SRC_DGN_W_MANT__W 9 #define ORX_FWP_SRC_DGN_W_MANT__M 0 x1FF#define ORX_FWP_SRC_DGN_W_MANT__PRE 0 x1FF#define ORX_FWP_SRC_DGN_W_EXP__B 12 #define ORX_FWP_SRC_DGN_W_EXP__W 4 #define ORX_FWP_SRC_DGN_W_EXP__M 0 xF000#define ORX_FWP_SRC_DGN_W_EXP__PRE 0 x0#define ORX_FWP_NYQ_ADR_W__A 0 x202001A#define ORX_FWP_NYQ_ADR_W__W 5 #define ORX_FWP_NYQ_ADR_W__M 0 x1F#define ORX_FWP_NYQ_ADR_W__PRE 0 x1F#define ORX_FWP_NYQ_COF_RW__A 0 x202001B#define ORX_FWP_NYQ_COF_RW__W 10 #define ORX_FWP_NYQ_COF_RW__M 0 x3FF#define ORX_FWP_NYQ_COF_RW__PRE 0 x0#define ORX_FWP_IQM_FRQ_W__A 0 x202001C#define ORX_FWP_IQM_FRQ_W__W 16 #define ORX_FWP_IQM_FRQ_W__M 0 xFFFF#define ORX_FWP_IQM_FRQ_W__PRE 0 x4301#define ORX_EQU_COMM_EXEC__A 0 x2030000#define ORX_EQU_COMM_EXEC__W 2 #define ORX_EQU_COMM_EXEC__M 0 x3#define ORX_EQU_COMM_EXEC__PRE 0 x0#define ORX_EQU_COMM_EXEC_STOP 0 x0#define ORX_EQU_COMM_EXEC_ACTIVE 0 x1#define ORX_EQU_COMM_EXEC_HOLD 0 x2#define ORX_EQU_COMM_MB__A 0 x2030002#define ORX_EQU_COMM_MB__W 8 #define ORX_EQU_COMM_MB__M 0 xFF#define ORX_EQU_COMM_MB__PRE 0 x0#define ORX_EQU_COMM_MB_CTL__B 0 #define ORX_EQU_COMM_MB_CTL__W 1 #define ORX_EQU_COMM_MB_CTL__M 0 x1#define ORX_EQU_COMM_MB_CTL__PRE 0 x0#define ORX_EQU_COMM_MB_CTL_OFF 0 x0#define ORX_EQU_COMM_MB_CTL_ON 0 x1#define ORX_EQU_COMM_MB_OBS__B 1 #define ORX_EQU_COMM_MB_OBS__W 1 #define ORX_EQU_COMM_MB_OBS__M 0 x2#define ORX_EQU_COMM_MB_OBS__PRE 0 x0#define ORX_EQU_COMM_MB_OBS_OFF 0 x0#define ORX_EQU_COMM_MB_OBS_ON 0 x2#define ORX_EQU_COMM_MB_CTL_MUX__B 2 #define ORX_EQU_COMM_MB_CTL_MUX__W 3 #define ORX_EQU_COMM_MB_CTL_MUX__M 0 x1C#define ORX_EQU_COMM_MB_CTL_MUX__PRE 0 x0#define ORX_EQU_COMM_MB_OBS_MUX__B 5 #define ORX_EQU_COMM_MB_OBS_MUX__W 3 #define ORX_EQU_COMM_MB_OBS_MUX__M 0 xE0#define ORX_EQU_COMM_MB_OBS_MUX__PRE 0 x0#define ORX_EQU_COMM_INT_REQ__A 0 x2030003#define ORX_EQU_COMM_INT_REQ__W 1 #define ORX_EQU_COMM_INT_REQ__M 0 x1#define ORX_EQU_COMM_INT_REQ__PRE 0 x0#define ORX_EQU_COMM_INT_STA__A 0 x2030005#define ORX_EQU_COMM_INT_STA__W 2 #define ORX_EQU_COMM_INT_STA__M 0 x3#define ORX_EQU_COMM_INT_STA__PRE 0 x0#define ORX_EQU_COMM_INT_STA_FFF_READ__B 0 #define ORX_EQU_COMM_INT_STA_FFF_READ__W 1 #define ORX_EQU_COMM_INT_STA_FFF_READ__M 0 x1#define ORX_EQU_COMM_INT_STA_FFF_READ__PRE 0 x0#define ORX_EQU_COMM_INT_STA_FBF_READ__B 1 #define ORX_EQU_COMM_INT_STA_FBF_READ__W 1 #define ORX_EQU_COMM_INT_STA_FBF_READ__M 0 x2#define ORX_EQU_COMM_INT_STA_FBF_READ__PRE 0 x0#define ORX_EQU_COMM_INT_MSK__A 0 x2030006#define ORX_EQU_COMM_INT_MSK__W 2 #define ORX_EQU_COMM_INT_MSK__M 0 x3#define ORX_EQU_COMM_INT_MSK__PRE 0 x0#define ORX_EQU_COMM_INT_MSK_FFF_READ__B 0 #define ORX_EQU_COMM_INT_MSK_FFF_READ__W 1 #define ORX_EQU_COMM_INT_MSK_FFF_READ__M 0 x1#define ORX_EQU_COMM_INT_MSK_FFF_READ__PRE 0 x0#define ORX_EQU_COMM_INT_MSK_FBF_READ__B 1 #define ORX_EQU_COMM_INT_MSK_FBF_READ__W 1 #define ORX_EQU_COMM_INT_MSK_FBF_READ__M 0 x2#define ORX_EQU_COMM_INT_MSK_FBF_READ__PRE 0 x0#define ORX_EQU_COMM_INT_STM__A 0 x2030007#define ORX_EQU_COMM_INT_STM__W 2 #define ORX_EQU_COMM_INT_STM__M 0 x3#define ORX_EQU_COMM_INT_STM__PRE 0 x0#define ORX_EQU_COMM_INT_STM_FFF_READ__B 0 #define ORX_EQU_COMM_INT_STM_FFF_READ__W 1 #define ORX_EQU_COMM_INT_STM_FFF_READ__M 0 x1#define ORX_EQU_COMM_INT_STM_FFF_READ__PRE 0 x0#define ORX_EQU_COMM_INT_STM_FBF_READ__B 1 #define ORX_EQU_COMM_INT_STM_FBF_READ__W 1 #define ORX_EQU_COMM_INT_STM_FBF_READ__M 0 x2#define ORX_EQU_COMM_INT_STM_FBF_READ__PRE 0 x0#define ORX_EQU_FFF_SCL_W__A 0 x2030010#define ORX_EQU_FFF_SCL_W__W 1 #define ORX_EQU_FFF_SCL_W__M 0 x1#define ORX_EQU_FFF_SCL_W__PRE 0 x0#define ORX_EQU_FFF_SCL_W_SCALE_GAIN_1 0 x0#define ORX_EQU_FFF_SCL_W_SCALE_GAIN_2 0 x1#define ORX_EQU_FFF_UPD_W__A 0 x2030011#define ORX_EQU_FFF_UPD_W__W 1 #define ORX_EQU_FFF_UPD_W__M 0 x1#define ORX_EQU_FFF_UPD_W__PRE 0 x0#define ORX_EQU_FFF_UPD_W_NO_UPDATE 0 x0#define ORX_EQU_FFF_UPD_W_LMS_UPDATE 0 x1#define ORX_EQU_FFF_STP_W__A 0 x2030012#define ORX_EQU_FFF_STP_W__W 3 #define ORX_EQU_FFF_STP_W__M 0 x7#define ORX_EQU_FFF_STP_W__PRE 0 x2#define ORX_EQU_FFF_LEA_W__A 0 x2030013#define ORX_EQU_FFF_LEA_W__W 4 #define ORX_EQU_FFF_LEA_W__M 0 xF#define ORX_EQU_FFF_LEA_W__PRE 0 x4#define ORX_EQU_FFF_RWT_W__A 0 x2030014#define ORX_EQU_FFF_RWT_W__W 2 #define ORX_EQU_FFF_RWT_W__M 0 x3#define ORX_EQU_FFF_RWT_W__PRE 0 x0#define ORX_EQU_FFF_C0RE_RW__A 0 x2030015#define ORX_EQU_FFF_C0RE_RW__W 12 #define ORX_EQU_FFF_C0RE_RW__M 0 xFFF#define ORX_EQU_FFF_C0RE_RW__PRE 0 x0#define ORX_EQU_FFF_C0IM_RW__A 0 x2030016#define ORX_EQU_FFF_C0IM_RW__W 12 #define ORX_EQU_FFF_C0IM_RW__M 0 xFFF#define ORX_EQU_FFF_C0IM_RW__PRE 0 x0#define ORX_EQU_FFF_C1RE_RW__A 0 x2030017#define ORX_EQU_FFF_C1RE_RW__W 12 #define ORX_EQU_FFF_C1RE_RW__M 0 xFFF#define ORX_EQU_FFF_C1RE_RW__PRE 0 x0#define ORX_EQU_FFF_C1IM_RW__A 0 x2030018#define ORX_EQU_FFF_C1IM_RW__W 12 #define ORX_EQU_FFF_C1IM_RW__M 0 xFFF#define ORX_EQU_FFF_C1IM_RW__PRE 0 x0#define ORX_EQU_FFF_C2RE_RW__A 0 x2030019#define ORX_EQU_FFF_C2RE_RW__W 12 #define ORX_EQU_FFF_C2RE_RW__M 0 xFFF#define ORX_EQU_FFF_C2RE_RW__PRE 0 x0#define ORX_EQU_FFF_C2IM_RW__A 0 x203001A#define ORX_EQU_FFF_C2IM_RW__W 12 #define ORX_EQU_FFF_C2IM_RW__M 0 xFFF#define ORX_EQU_FFF_C2IM_RW__PRE 0 x0#define ORX_EQU_FFF_C3RE_RW__A 0 x203001B#define ORX_EQU_FFF_C3RE_RW__W 12 #define ORX_EQU_FFF_C3RE_RW__M 0 xFFF#define ORX_EQU_FFF_C3RE_RW__PRE 0 x0#define ORX_EQU_FFF_C3IM_RW__A 0 x203001C#define ORX_EQU_FFF_C3IM_RW__W 12 #define ORX_EQU_FFF_C3IM_RW__M 0 xFFF#define ORX_EQU_FFF_C3IM_RW__PRE 0 x0#define ORX_EQU_FFF_C4RE_RW__A 0 x203001D#define ORX_EQU_FFF_C4RE_RW__W 12 #define ORX_EQU_FFF_C4RE_RW__M 0 xFFF#define ORX_EQU_FFF_C4RE_RW__PRE 0 x400#define ORX_EQU_FFF_C4IM_RW__A 0 x203001E#define ORX_EQU_FFF_C4IM_RW__W 12 #define ORX_EQU_FFF_C4IM_RW__M 0 xFFF#define ORX_EQU_FFF_C4IM_RW__PRE 0 x0#define ORX_EQU_FFF_C5RE_RW__A 0 x203001F#define ORX_EQU_FFF_C5RE_RW__W 12 #define ORX_EQU_FFF_C5RE_RW__M 0 xFFF#define ORX_EQU_FFF_C5RE_RW__PRE 0 x0#define ORX_EQU_FFF_C5IM_RW__A 0 x2030020#define ORX_EQU_FFF_C5IM_RW__W 12 #define ORX_EQU_FFF_C5IM_RW__M 0 xFFF#define ORX_EQU_FFF_C5IM_RW__PRE 0 x0#define ORX_EQU_FFF_C6RE_RW__A 0 x2030021#define ORX_EQU_FFF_C6RE_RW__W 12 #define ORX_EQU_FFF_C6RE_RW__M 0 xFFF#define ORX_EQU_FFF_C6RE_RW__PRE 0 x0#define ORX_EQU_FFF_C6IM_RW__A 0 x2030022#define ORX_EQU_FFF_C6IM_RW__W 12 #define ORX_EQU_FFF_C6IM_RW__M 0 xFFF#define ORX_EQU_FFF_C6IM_RW__PRE 0 x0#define ORX_EQU_FFF_C7RE_RW__A 0 x2030023#define ORX_EQU_FFF_C7RE_RW__W 12 #define ORX_EQU_FFF_C7RE_RW__M 0 xFFF#define ORX_EQU_FFF_C7RE_RW__PRE 0 x0#define ORX_EQU_FFF_C7IM_RW__A 0 x2030024#define ORX_EQU_FFF_C7IM_RW__W 12 #define ORX_EQU_FFF_C7IM_RW__M 0 xFFF#define ORX_EQU_FFF_C7IM_RW__PRE 0 x0#define ORX_EQU_FFF_C8RE_RW__A 0 x2030025#define ORX_EQU_FFF_C8RE_RW__W 12 #define ORX_EQU_FFF_C8RE_RW__M 0 xFFF#define ORX_EQU_FFF_C8RE_RW__PRE 0 x0#define ORX_EQU_FFF_C8IM_RW__A 0 x2030026#define ORX_EQU_FFF_C8IM_RW__W 12 #define ORX_EQU_FFF_C8IM_RW__M 0 xFFF#define ORX_EQU_FFF_C8IM_RW__PRE 0 x0#define ORX_EQU_FFF_C9RE_RW__A 0 x2030027#define ORX_EQU_FFF_C9RE_RW__W 12 #define ORX_EQU_FFF_C9RE_RW__M 0 xFFF#define ORX_EQU_FFF_C9RE_RW__PRE 0 x0#define ORX_EQU_FFF_C9IM_RW__A 0 x2030028#define ORX_EQU_FFF_C9IM_RW__W 12 #define ORX_EQU_FFF_C9IM_RW__M 0 xFFF#define ORX_EQU_FFF_C9IM_RW__PRE 0 x0#define ORX_EQU_FFF_C10RE_RW__A 0 x2030029#define ORX_EQU_FFF_C10RE_RW__W 12 #define ORX_EQU_FFF_C10RE_RW__M 0 xFFF#define ORX_EQU_FFF_C10RE_RW__PRE 0 x0#define ORX_EQU_FFF_C10IM_RW__A 0 x203002A#define ORX_EQU_FFF_C10IM_RW__W 12 #define ORX_EQU_FFF_C10IM_RW__M 0 xFFF#define ORX_EQU_FFF_C10IM_RW__PRE 0 x0#define ORX_EQU_MXB_SEL_W__A 0 x203002B#define ORX_EQU_MXB_SEL_W__W 1 #define ORX_EQU_MXB_SEL_W__M 0 x1#define ORX_EQU_MXB_SEL_W__PRE 0 x0#define ORX_EQU_MXB_SEL_W_UNDECIDED_SYMBOLS 0 x0#define ORX_EQU_MXB_SEL_W_DECIDED_SYMBOLS 0 x1#define ORX_EQU_FBF_UPD_W__A 0 x203002C#define ORX_EQU_FBF_UPD_W__W 1 #define ORX_EQU_FBF_UPD_W__M 0 x1#define ORX_EQU_FBF_UPD_W__PRE 0 x0#define ORX_EQU_FBF_UPD_W_NO_UPDATE 0 x0#define ORX_EQU_FBF_UPD_W_LMS_UPDATE 0 x1#define ORX_EQU_FBF_STP_W__A 0 x203002D#define ORX_EQU_FBF_STP_W__W 3 #define ORX_EQU_FBF_STP_W__M 0 x7#define ORX_EQU_FBF_STP_W__PRE 0 x2#define ORX_EQU_FBF_LEA_W__A 0 x203002E#define ORX_EQU_FBF_LEA_W__W 4 #define ORX_EQU_FBF_LEA_W__M 0 xF#define ORX_EQU_FBF_LEA_W__PRE 0 x4#define ORX_EQU_FBF_RWT_W__A 0 x203002F#define ORX_EQU_FBF_RWT_W__W 2 #define ORX_EQU_FBF_RWT_W__M 0 x3#define ORX_EQU_FBF_RWT_W__PRE 0 x0#define ORX_EQU_FBF_C0RE_RW__A 0 x2030030#define ORX_EQU_FBF_C0RE_RW__W 12 #define ORX_EQU_FBF_C0RE_RW__M 0 xFFF#define ORX_EQU_FBF_C0RE_RW__PRE 0 x0#define ORX_EQU_FBF_C0IM_RW__A 0 x2030031#define ORX_EQU_FBF_C0IM_RW__W 12 #define ORX_EQU_FBF_C0IM_RW__M 0 xFFF#define ORX_EQU_FBF_C0IM_RW__PRE 0 x0#define ORX_EQU_FBF_C1RE_RW__A 0 x2030032#define ORX_EQU_FBF_C1RE_RW__W 12 #define ORX_EQU_FBF_C1RE_RW__M 0 xFFF#define ORX_EQU_FBF_C1RE_RW__PRE 0 x0#define ORX_EQU_FBF_C1IM_RW__A 0 x2030033#define ORX_EQU_FBF_C1IM_RW__W 12 #define ORX_EQU_FBF_C1IM_RW__M 0 xFFF#define ORX_EQU_FBF_C1IM_RW__PRE 0 x0#define ORX_EQU_FBF_C2RE_RW__A 0 x2030034#define ORX_EQU_FBF_C2RE_RW__W 12 #define ORX_EQU_FBF_C2RE_RW__M 0 xFFF#define ORX_EQU_FBF_C2RE_RW__PRE 0 x0#define ORX_EQU_FBF_C2IM_RW__A 0 x2030035#define ORX_EQU_FBF_C2IM_RW__W 12 #define ORX_EQU_FBF_C2IM_RW__M 0 xFFF#define ORX_EQU_FBF_C2IM_RW__PRE 0 x0#define ORX_EQU_FBF_C3RE_RW__A 0 x2030036#define ORX_EQU_FBF_C3RE_RW__W 12 #define ORX_EQU_FBF_C3RE_RW__M 0 xFFF#define ORX_EQU_FBF_C3RE_RW__PRE 0 x0#define ORX_EQU_FBF_C3IM_RW__A 0 x2030037#define ORX_EQU_FBF_C3IM_RW__W 12 #define ORX_EQU_FBF_C3IM_RW__M 0 xFFF#define ORX_EQU_FBF_C3IM_RW__PRE 0 x0#define ORX_EQU_FBF_C4RE_RW__A 0 x2030038#define ORX_EQU_FBF_C4RE_RW__W 12 #define ORX_EQU_FBF_C4RE_RW__M 0 xFFF#define ORX_EQU_FBF_C4RE_RW__PRE 0 x0#define ORX_EQU_FBF_C4IM_RW__A 0 x2030039#define ORX_EQU_FBF_C4IM_RW__W 12 #define ORX_EQU_FBF_C4IM_RW__M 0 xFFF#define ORX_EQU_FBF_C4IM_RW__PRE 0 x0#define ORX_EQU_FBF_C5RE_RW__A 0 x203003A#define ORX_EQU_FBF_C5RE_RW__W 12 #define ORX_EQU_FBF_C5RE_RW__M 0 xFFF#define ORX_EQU_FBF_C5RE_RW__PRE 0 x0#define ORX_EQU_FBF_C5IM_RW__A 0 x203003B#define ORX_EQU_FBF_C5IM_RW__W 12 #define ORX_EQU_FBF_C5IM_RW__M 0 xFFF#define ORX_EQU_FBF_C5IM_RW__PRE 0 x0#define ORX_EQU_ERR_SEL_W__A 0 x203003C#define ORX_EQU_ERR_SEL_W__W 1 #define ORX_EQU_ERR_SEL_W__M 0 x1#define ORX_EQU_ERR_SEL_W__PRE 0 x0#define ORX_EQU_ERR_SEL_W_CMA_ERROR 0 x0#define ORX_EQU_ERR_SEL_W_DDA_ERROR 0 x1#define ORX_EQU_ERR_TIS_W__A 0 x203003D#define ORX_EQU_ERR_TIS_W__W 1 #define ORX_EQU_ERR_TIS_W__M 0 x1#define ORX_EQU_ERR_TIS_W__PRE 0 x0#define ORX_EQU_ERR_TIS_W_CMA_SIGNALS 0 x0#define ORX_EQU_ERR_TIS_W_DDA_SIGNALS 0 x1#define ORX_EQU_ERR_EDI_R__A 0 x203003E#define ORX_EQU_ERR_EDI_R__W 5 #define ORX_EQU_ERR_EDI_R__M 0 x1F#define ORX_EQU_ERR_EDI_R__PRE 0 xF#define ORX_EQU_ERR_EDQ_R__A 0 x203003F#define ORX_EQU_ERR_EDQ_R__W 5 #define ORX_EQU_ERR_EDQ_R__M 0 x1F#define ORX_EQU_ERR_EDQ_R__PRE 0 xF#define ORX_EQU_ERR_ECI_R__A 0 x2030040#define ORX_EQU_ERR_ECI_R__W 5 #define ORX_EQU_ERR_ECI_R__M 0 x1F#define ORX_EQU_ERR_ECI_R__PRE 0 xF#define ORX_EQU_ERR_ECQ_R__A 0 x2030041#define ORX_EQU_ERR_ECQ_R__W 5 #define ORX_EQU_ERR_ECQ_R__M 0 x1F#define ORX_EQU_ERR_ECQ_R__PRE 0 xF#define ORX_EQU_MER_MER_R__A 0 x2030042#define ORX_EQU_MER_MER_R__W 6 #define ORX_EQU_MER_MER_R__M 0 x3F#define ORX_EQU_MER_MER_R__PRE 0 x3F#define ORX_EQU_MER_LDT_W__A 0 x2030043#define ORX_EQU_MER_LDT_W__W 3 #define ORX_EQU_MER_LDT_W__M 0 x7#define ORX_EQU_MER_LDT_W__PRE 0 x4#define ORX_EQU_SYN_LEN_W__A 0 x2030044#define ORX_EQU_SYN_LEN_W__W 16 #define ORX_EQU_SYN_LEN_W__M 0 xFFFF#define ORX_EQU_SYN_LEN_W__PRE 0 x0#define ORX_DDC_COMM_EXEC__A 0 x2040000#define ORX_DDC_COMM_EXEC__W 2 #define ORX_DDC_COMM_EXEC__M 0 x3#define ORX_DDC_COMM_EXEC__PRE 0 x0#define ORX_DDC_COMM_EXEC_STOP 0 x0#define ORX_DDC_COMM_EXEC_ACTIVE 0 x1#define ORX_DDC_COMM_EXEC_HOLD 0 x2#define ORX_DDC_COMM_MB__A 0 x2040002#define ORX_DDC_COMM_MB__W 6 #define ORX_DDC_COMM_MB__M 0 x3F#define ORX_DDC_COMM_MB__PRE 0 x0#define ORX_DDC_COMM_MB_CTL__B 0 #define ORX_DDC_COMM_MB_CTL__W 1 #define ORX_DDC_COMM_MB_CTL__M 0 x1#define ORX_DDC_COMM_MB_CTL__PRE 0 x0#define ORX_DDC_COMM_MB_CTL_OFF 0 x0#define ORX_DDC_COMM_MB_CTL_ON 0 x1#define ORX_DDC_COMM_MB_OBS__B 1 #define ORX_DDC_COMM_MB_OBS__W 1 #define ORX_DDC_COMM_MB_OBS__M 0 x2#define ORX_DDC_COMM_MB_OBS__PRE 0 x0#define ORX_DDC_COMM_MB_OBS_OFF 0 x0#define ORX_DDC_COMM_MB_OBS_ON 0 x2#define ORX_DDC_COMM_MB_CTL_MUX__B 2 #define ORX_DDC_COMM_MB_CTL_MUX__W 2 #define ORX_DDC_COMM_MB_CTL_MUX__M 0 xC#define ORX_DDC_COMM_MB_CTL_MUX__PRE 0 x0#define ORX_DDC_COMM_MB_OBS_MUX__B 4 #define ORX_DDC_COMM_MB_OBS_MUX__W 2 #define ORX_DDC_COMM_MB_OBS_MUX__M 0 x30#define ORX_DDC_COMM_MB_OBS_MUX__PRE 0 x0#define ORX_DDC_COMM_INT_REQ__A 0 x2040003#define ORX_DDC_COMM_INT_REQ__W 1 #define ORX_DDC_COMM_INT_REQ__M 0 x1#define ORX_DDC_COMM_INT_REQ__PRE 0 x0#define ORX_DDC_COMM_INT_STA__A 0 x2040005#define ORX_DDC_COMM_INT_STA__W 1 #define ORX_DDC_COMM_INT_STA__M 0 x1#define ORX_DDC_COMM_INT_STA__PRE 0 x0#define ORX_DDC_COMM_INT_MSK__A 0 x2040006#define ORX_DDC_COMM_INT_MSK__W 1 #define ORX_DDC_COMM_INT_MSK__M 0 x1#define ORX_DDC_COMM_INT_MSK__PRE 0 x0#define ORX_DDC_COMM_INT_STM__A 0 x2040007#define ORX_DDC_COMM_INT_STM__W 1 #define ORX_DDC_COMM_INT_STM__M 0 x1#define ORX_DDC_COMM_INT_STM__PRE 0 x0#define ORX_DDC_DEC_MAP_W__A 0 x2040010#define ORX_DDC_DEC_MAP_W__W 9 #define ORX_DDC_DEC_MAP_W__M 0 x1FF#define ORX_DDC_DEC_MAP_W__PRE 0 x178#define ORX_DDC_DEC_MAP_W_QUADR0__B 0 #define ORX_DDC_DEC_MAP_W_QUADR0__W 2 #define ORX_DDC_DEC_MAP_W_QUADR0__M 0 x3#define ORX_DDC_DEC_MAP_W_QUADR0__PRE 0 x0#define ORX_DDC_DEC_MAP_W_QUADR0_ROTATE_DEFAULT 0 x0#define ORX_DDC_DEC_MAP_W_QUADR0_ROTATE_ALTERNATE 0 x0#define ORX_DDC_DEC_MAP_W_QUADR1__B 2 #define ORX_DDC_DEC_MAP_W_QUADR1__W 2 #define ORX_DDC_DEC_MAP_W_QUADR1__M 0 xC#define ORX_DDC_DEC_MAP_W_QUADR1__PRE 0 x8#define ORX_DDC_DEC_MAP_W_QUADR1_ROTATE_DEFAULT 0 x8#define ORX_DDC_DEC_MAP_W_QUADR1_ROTATE_ALTERNATE 0 x4#define ORX_DDC_DEC_MAP_W_QUADR2__B 4 #define ORX_DDC_DEC_MAP_W_QUADR2__W 2 #define ORX_DDC_DEC_MAP_W_QUADR2__M 0 x30#define ORX_DDC_DEC_MAP_W_QUADR2__PRE 0 x30#define ORX_DDC_DEC_MAP_W_QUADR2_ROTATE_DEFAULT 0 x30#define ORX_DDC_DEC_MAP_W_QUADR2_ROTATE_ALTERNATE 0 x30#define ORX_DDC_DEC_MAP_W_QUADR3__B 6 #define ORX_DDC_DEC_MAP_W_QUADR3__W 2 #define ORX_DDC_DEC_MAP_W_QUADR3__M 0 xC0#define ORX_DDC_DEC_MAP_W_QUADR3__PRE 0 x40#define ORX_DDC_DEC_MAP_W_QUADR3_ROTATE_DEFAULT 0 x40#define ORX_DDC_DEC_MAP_W_QUADR3_ROTATE_ALTERNATE 0 x80#define ORX_DDC_DEC_MAP_W_DIFF_DECOD__B 8 #define ORX_DDC_DEC_MAP_W_DIFF_DECOD__W 1 #define ORX_DDC_DEC_MAP_W_DIFF_DECOD__M 0 x100#define ORX_DDC_DEC_MAP_W_DIFF_DECOD__PRE 0 x100#define ORX_DDC_DEC_MAP_W_DIFF_DECOD_COHERENT_DECODING 0 x0#define ORX_DDC_DEC_MAP_W_DIFF_DECOD_DIFF_DECODING 0 x100#define ORX_DDC_OFO_SET_W__A 0 x2040011#define ORX_DDC_OFO_SET_W__W 16 #define ORX_DDC_OFO_SET_W__M 0 xFFFF#define ORX_DDC_OFO_SET_W__PRE 0 x1402#define ORX_DDC_OFO_SET_W_PHASE__B 0 #define ORX_DDC_OFO_SET_W_PHASE__W 7 #define ORX_DDC_OFO_SET_W_PHASE__M 0 x7F#define ORX_DDC_OFO_SET_W_PHASE__PRE 0 x2#define ORX_DDC_OFO_SET_W_CRXHITIME__B 7 #define ORX_DDC_OFO_SET_W_CRXHITIME__W 7 #define ORX_DDC_OFO_SET_W_CRXHITIME__M 0 x3F80#define ORX_DDC_OFO_SET_W_CRXHITIME__PRE 0 x1400#define ORX_DDC_OFO_SET_W_CRXINV__B 14 #define ORX_DDC_OFO_SET_W_CRXINV__W 1 #define ORX_DDC_OFO_SET_W_CRXINV__M 0 x4000#define ORX_DDC_OFO_SET_W_CRXINV__PRE 0 x0#define ORX_DDC_OFO_SET_W_DISABLE__B 15 #define ORX_DDC_OFO_SET_W_DISABLE__W 1 #define ORX_DDC_OFO_SET_W_DISABLE__M 0 x8000#define ORX_DDC_OFO_SET_W_DISABLE__PRE 0 x0#define ORX_CON_COMM_EXEC__A 0 x2050000#define ORX_CON_COMM_EXEC__W 2 #define ORX_CON_COMM_EXEC__M 0 x3#define ORX_CON_COMM_EXEC__PRE 0 x0#define ORX_CON_COMM_EXEC_STOP 0 x0#define ORX_CON_COMM_EXEC_ACTIVE 0 x1#define ORX_CON_COMM_EXEC_HOLD 0 x2#define ORX_CON_LDT_W__A 0 x2050010#define ORX_CON_LDT_W__W 3 #define ORX_CON_LDT_W__M 0 x7#define ORX_CON_LDT_W__PRE 0 x3#define ORX_CON_LDT_W_CON_LDT_W__B 0 #define ORX_CON_LDT_W_CON_LDT_W__W 3 #define ORX_CON_LDT_W_CON_LDT_W__M 0 x7#define ORX_CON_LDT_W_CON_LDT_W__PRE 0 x3#define ORX_CON_RST_W__A 0 x2050011#define ORX_CON_RST_W__W 4 #define ORX_CON_RST_W__M 0 xF#define ORX_CON_RST_W__PRE 0 x0#define ORX_CON_RST_W_CPH__B 0 #define ORX_CON_RST_W_CPH__W 1 #define ORX_CON_RST_W_CPH__M 0 x1#define ORX_CON_RST_W_CPH__PRE 0 x0#define ORX_CON_RST_W_CTI__B 1 #define ORX_CON_RST_W_CTI__W 1 #define ORX_CON_RST_W_CTI__M 0 x2#define ORX_CON_RST_W_CTI__PRE 0 x0#define ORX_CON_RST_W_KRN__B 2 #define ORX_CON_RST_W_KRN__W 1 #define ORX_CON_RST_W_KRN__M 0 x4#define ORX_CON_RST_W_KRN__PRE 0 x0#define ORX_CON_RST_W_KRP__B 3 #define ORX_CON_RST_W_KRP__W 1 #define ORX_CON_RST_W_KRP__M 0 x8#define ORX_CON_RST_W_KRP__PRE 0 x0#define ORX_CON_CPH_PHI_R__A 0 x2050012#define ORX_CON_CPH_PHI_R__W 16 #define ORX_CON_CPH_PHI_R__M 0 xFFFF#define ORX_CON_CPH_PHI_R__PRE 0 x0#define ORX_CON_CPH_FRQ_R__A 0 x2050013#define ORX_CON_CPH_FRQ_R__W 16 #define ORX_CON_CPH_FRQ_R__M 0 xFFFF#define ORX_CON_CPH_FRQ_R__PRE 0 x0#define ORX_CON_CPH_AMP_R__A 0 x2050014#define ORX_CON_CPH_AMP_R__W 16 #define ORX_CON_CPH_AMP_R__M 0 xFFFF#define ORX_CON_CPH_AMP_R__PRE 0 x0#define ORX_CON_CPH_KDF_W__A 0 x2050015#define ORX_CON_CPH_KDF_W__W 4 #define ORX_CON_CPH_KDF_W__M 0 xF#define ORX_CON_CPH_KDF_W__PRE 0 x0#define ORX_CON_CPH_KPF_W__A 0 x2050016#define ORX_CON_CPH_KPF_W__W 4 #define ORX_CON_CPH_KPF_W__M 0 xF#define ORX_CON_CPH_KPF_W__PRE 0 x0#define ORX_CON_CPH_KIF_W__A 0 x2050017#define ORX_CON_CPH_KIF_W__W 4 #define ORX_CON_CPH_KIF_W__M 0 xF#define ORX_CON_CPH_KIF_W__PRE 0 x0#define ORX_CON_CPH_APT_W__A 0 x2050018#define ORX_CON_CPH_APT_W__W 16 #define ORX_CON_CPH_APT_W__M 0 xFFFF#define ORX_CON_CPH_APT_W__PRE 0 x804#define ORX_CON_CPH_APT_W_PTH__B 0 #define ORX_CON_CPH_APT_W_PTH__W 8 #define ORX_CON_CPH_APT_W_PTH__M 0 xFF#define ORX_CON_CPH_APT_W_PTH__PRE 0 x4#define ORX_CON_CPH_APT_W_ATH__B 8 #define ORX_CON_CPH_APT_W_ATH__W 8 #define ORX_CON_CPH_APT_W_ATH__M 0 xFF00#define ORX_CON_CPH_APT_W_ATH__PRE 0 x800#define ORX_CON_CPH_WLC_W__A 0 x2050019#define ORX_CON_CPH_WLC_W__W 8 #define ORX_CON_CPH_WLC_W__M 0 xFF#define ORX_CON_CPH_WLC_W__PRE 0 x81#define ORX_CON_CPH_WLC_W_LATC__B 0 #define ORX_CON_CPH_WLC_W_LATC__W 4 #define ORX_CON_CPH_WLC_W_LATC__M 0 xF#define ORX_CON_CPH_WLC_W_LATC__PRE 0 x1#define ORX_CON_CPH_WLC_W_WLIM__B 4 #define ORX_CON_CPH_WLC_W_WLIM__W 4 #define ORX_CON_CPH_WLC_W_WLIM__M 0 xF0#define ORX_CON_CPH_WLC_W_WLIM__PRE 0 x80#define ORX_CON_CPH_DLY_W__A 0 x205001A#define ORX_CON_CPH_DLY_W__W 3 #define ORX_CON_CPH_DLY_W__M 0 x7#define ORX_CON_CPH_DLY_W__PRE 0 x4#define ORX_CON_CPH_TCL_W__A 0 x205001B#define ORX_CON_CPH_TCL_W__W 3 #define ORX_CON_CPH_TCL_W__M 0 x7#define ORX_CON_CPH_TCL_W__PRE 0 x3#define ORX_CON_KRP_AMP_R__A 0 x205001C#define ORX_CON_KRP_AMP_R__W 9 #define ORX_CON_KRP_AMP_R__M 0 x1FF#define ORX_CON_KRP_AMP_R__PRE 0 x0#define ORX_CON_KRN_AMP_R__A 0 x205001D#define ORX_CON_KRN_AMP_R__W 9 #define ORX_CON_KRN_AMP_R__M 0 x1FF#define ORX_CON_KRN_AMP_R__PRE 0 x0#define ORX_CON_CTI_DTI_R__A 0 x205001E#define ORX_CON_CTI_DTI_R__W 16 #define ORX_CON_CTI_DTI_R__M 0 xFFFF#define ORX_CON_CTI_DTI_R__PRE 0 x0#define ORX_CON_CTI_KDT_W__A 0 x205001F#define ORX_CON_CTI_KDT_W__W 4 #define ORX_CON_CTI_KDT_W__M 0 xF#define ORX_CON_CTI_KDT_W__PRE 0 x4#define ORX_CON_CTI_KPT_W__A 0 x2050020#define ORX_CON_CTI_KPT_W__W 4 #define ORX_CON_CTI_KPT_W__M 0 xF#define ORX_CON_CTI_KPT_W__PRE 0 x3#define ORX_CON_CTI_KIT_W__A 0 x2050021#define ORX_CON_CTI_KIT_W__W 4 #define ORX_CON_CTI_KIT_W__M 0 xF#define ORX_CON_CTI_KIT_W__PRE 0 xB#define ORX_CON_CTI_TAT_W__A 0 x2050022#define ORX_CON_CTI_TAT_W__W 4 #define ORX_CON_CTI_TAT_W__M 0 xF#define ORX_CON_CTI_TAT_W__PRE 0 x3#define ORX_NSU_COMM_EXEC__A 0 x2060000#define ORX_NSU_COMM_EXEC__W 2 #define ORX_NSU_COMM_EXEC__M 0 x3#define ORX_NSU_COMM_EXEC__PRE 0 x0#define ORX_NSU_COMM_EXEC_STOP 0 x0#define ORX_NSU_COMM_EXEC_ACTIVE 0 x1#define ORX_NSU_COMM_EXEC_HOLD 0 x2#define ORX_NSU_AOX_STDBY_W__A 0 x2060010#define ORX_NSU_AOX_STDBY_W__W 8 #define ORX_NSU_AOX_STDBY_W__M 0 xFF#define ORX_NSU_AOX_STDBY_W__PRE 0 x0#define ORX_NSU_AOX_STDBY_W_STDBYADC__B 0 #define ORX_NSU_AOX_STDBY_W_STDBYADC__W 1 #define ORX_NSU_AOX_STDBY_W_STDBYADC__M 0 x1#define ORX_NSU_AOX_STDBY_W_STDBYADC__PRE 0 x0#define ORX_NSU_AOX_STDBY_W_STDBYADC_A1_ON 0 x0#define ORX_NSU_AOX_STDBY_W_STDBYADC_A1_OFF 0 x1#define ORX_NSU_AOX_STDBY_W_STDBYADC_A2_OFF 0 x0#define ORX_NSU_AOX_STDBY_W_STDBYADC_A2_ON 0 x1#define ORX_NSU_AOX_STDBY_W_STDBYAMP__B 1 #define ORX_NSU_AOX_STDBY_W_STDBYAMP__W 1 #define ORX_NSU_AOX_STDBY_W_STDBYAMP__M 0 x2#define ORX_NSU_AOX_STDBY_W_STDBYAMP__PRE 0 x0#define ORX_NSU_AOX_STDBY_W_STDBYAMP_A1_ON 0 x0#define ORX_NSU_AOX_STDBY_W_STDBYAMP_A1_OFF 0 x2#define ORX_NSU_AOX_STDBY_W_STDBYAMP_A2_OFF 0 x0#define ORX_NSU_AOX_STDBY_W_STDBYAMP_A2_ON 0 x2#define ORX_NSU_AOX_STDBY_W_STDBYBIAS__B 2 #define ORX_NSU_AOX_STDBY_W_STDBYBIAS__W 1 #define ORX_NSU_AOX_STDBY_W_STDBYBIAS__M 0 x4#define ORX_NSU_AOX_STDBY_W_STDBYBIAS__PRE 0 x0#define ORX_NSU_AOX_STDBY_W_STDBYBIAS_A1_ON 0 x0#define ORX_NSU_AOX_STDBY_W_STDBYBIAS_A1_OFF 0 x4#define ORX_NSU_AOX_STDBY_W_STDBYBIAS_A2_OFF 0 x0#define ORX_NSU_AOX_STDBY_W_STDBYBIAS_A2_ON 0 x4#define ORX_NSU_AOX_STDBY_W_STDBYPLL__B 3 #define ORX_NSU_AOX_STDBY_W_STDBYPLL__W 1 #define ORX_NSU_AOX_STDBY_W_STDBYPLL__M 0 x8#define ORX_NSU_AOX_STDBY_W_STDBYPLL__PRE 0 x0#define ORX_NSU_AOX_STDBY_W_STDBYPLL_A1_ON 0 x0#define ORX_NSU_AOX_STDBY_W_STDBYPLL_A1_OFF 0 x8#define ORX_NSU_AOX_STDBY_W_STDBYPLL_A2_OFF 0 x0#define ORX_NSU_AOX_STDBY_W_STDBYPLL_A2_ON 0 x8#define ORX_NSU_AOX_STDBY_W_STDBYPD__B 4 #define ORX_NSU_AOX_STDBY_W_STDBYPD__W 1 #define ORX_NSU_AOX_STDBY_W_STDBYPD__M 0 x10#define ORX_NSU_AOX_STDBY_W_STDBYPD__PRE 0 x0#define ORX_NSU_AOX_STDBY_W_STDBYPD_A1_ON 0 x0#define ORX_NSU_AOX_STDBY_W_STDBYPD_A1_OFF 0 x10#define ORX_NSU_AOX_STDBY_W_STDBYPD_A2_OFF 0 x0#define ORX_NSU_AOX_STDBY_W_STDBYPD_A2_ON 0 x10#define ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF__B 5 #define ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF__W 1 #define ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF__M 0 x20#define ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF__PRE 0 x0#define ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF_A1_ON 0 x0#define ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF_A1_OFF 0 x20#define ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF_A2_OFF 0 x0#define ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF_A2_ON 0 x20#define ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF__B 6 #define ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF__W 1 #define ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF__M 0 x40#define ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF__PRE 0 x0#define ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF_A1_ON 0 x0#define ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF_A1_OFF 0 x40#define ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF_A2_OFF 0 x0#define ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF_A2_ON 0 x40#define ORX_NSU_AOX_STDBY_W_STDBYFLT__B 7 #define ORX_NSU_AOX_STDBY_W_STDBYFLT__W 1 #define ORX_NSU_AOX_STDBY_W_STDBYFLT__M 0 x80#define ORX_NSU_AOX_STDBY_W_STDBYFLT__PRE 0 x0#define ORX_NSU_AOX_STDBY_W_STDBYFLT_A1_ON 0 x0#define ORX_NSU_AOX_STDBY_W_STDBYFLT_A1_OFF 0 x80#define ORX_NSU_AOX_STDBY_W_STDBYFLT_A2_OFF 0 x0#define ORX_NSU_AOX_STDBY_W_STDBYFLT_A2_ON 0 x80#define ORX_NSU_AOX_LOFRQ_W__A 0 x2060011#define ORX_NSU_AOX_LOFRQ_W__W 16 #define ORX_NSU_AOX_LOFRQ_W__M 0 xFFFF#define ORX_NSU_AOX_LOFRQ_W__PRE 0 x0#define ORX_NSU_AOX_LOMDE_W__A 0 x2060012#define ORX_NSU_AOX_LOMDE_W__W 16 #define ORX_NSU_AOX_LOMDE_W__M 0 xFFFF#define ORX_NSU_AOX_LOMDE_W__PRE 0 x0#define ORX_NSU_AOX_LOMDE_W_AOX_LOFRQ_EXT__B 0 #define ORX_NSU_AOX_LOMDE_W_AOX_LOFRQ_EXT__W 8 #define ORX_NSU_AOX_LOMDE_W_AOX_LOFRQ_EXT__M 0 xFF#define ORX_NSU_AOX_LOMDE_W_AOX_LOFRQ_EXT__PRE 0 x0#define ORX_NSU_AOX_LOMDE_W_RESET_VCO__B 13 #define ORX_NSU_AOX_LOMDE_W_RESET_VCO__W 1 #define ORX_NSU_AOX_LOMDE_W_RESET_VCO__M 0 x2000#define ORX_NSU_AOX_LOMDE_W_RESET_VCO__PRE 0 x0#define ORX_NSU_AOX_LOMDE_W_PLL_DIV__B 14 #define ORX_NSU_AOX_LOMDE_W_PLL_DIV__W 2 #define ORX_NSU_AOX_LOMDE_W_PLL_DIV__M 0 xC000#define ORX_NSU_AOX_LOMDE_W_PLL_DIV__PRE 0 x0#define ORX_NSU_AOX_LOPOW_W__A 0 x2060013#define ORX_NSU_AOX_LOPOW_W__W 2 #define ORX_NSU_AOX_LOPOW_W__M 0 x3#define ORX_NSU_AOX_LOPOW_W__PRE 0 x0#define ORX_NSU_AOX_LOPOW_W_POWER_MINUS0DB 0 x0#define ORX_NSU_AOX_LOPOW_W_POWER_MINUS5DB 0 x1#define ORX_NSU_AOX_LOPOW_W_POWER_MINUS10DB 0 x2#define ORX_NSU_AOX_LOPOW_W_POWER_MINUS15DB 0 x3#define ORX_NSU_AOX_STHR_W__A 0 x2060014#define ORX_NSU_AOX_STHR_W__W 5 #define ORX_NSU_AOX_STHR_W__M 0 x1F#define ORX_NSU_AOX_STHR_W__PRE 0 x0#define ORX_NSU_TUN_RFGAIN_W__A 0 x2060015#define ORX_NSU_TUN_RFGAIN_W__W 15 #define ORX_NSU_TUN_RFGAIN_W__M 0 x7FFF#define ORX_NSU_TUN_RFGAIN_W__PRE 0 x0#define ORX_NSU_TUN_IFGAIN_W__A 0 x2060016#define ORX_NSU_TUN_IFGAIN_W__W 15 #define ORX_NSU_TUN_IFGAIN_W__M 0 x7FFF#define ORX_NSU_TUN_IFGAIN_W__PRE 0 x0#define ORX_NSU_TUN_BPF_W__A 0 x2060017#define ORX_NSU_TUN_BPF_W__W 15 #define ORX_NSU_TUN_BPF_W__M 0 x7FFF#define ORX_NSU_TUN_BPF_W__PRE 0 x1F9#define ORX_NSU_NSS_BITSWAP_W__A 0 x2060018#define ORX_NSU_NSS_BITSWAP_W__W 3 #define ORX_NSU_NSS_BITSWAP_W__M 0 x7#define ORX_NSU_NSS_BITSWAP_W__PRE 0 x0#define ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS0_RF__B 0 #define ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS0_RF__W 1 #define ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS0_RF__M 0 x1#define ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS0_RF__PRE 0 x0#define ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS1_IF__B 1 #define ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS1_IF__W 1 #define ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS1_IF__M 0 x2#define ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS1_IF__PRE 0 x0#define ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS2_BP__B 2 #define ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS2_BP__W 1 #define ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS2_BP__M 0 x4#define ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS2_BP__PRE 0 x0#define ORX_TST_COMM_EXEC__A 0 x23F0000#define ORX_TST_COMM_EXEC__W 2 #define ORX_TST_COMM_EXEC__M 0 x3#define ORX_TST_COMM_EXEC__PRE 0 x0#define ORX_TST_COMM_EXEC_STOP 0 x0#define ORX_TST_COMM_EXEC_ACTIVE 0 x1#define ORX_TST_COMM_EXEC_HOLD 0 x2#define ORX_TST_AOX_TST_W__A 0 x23F0010#define ORX_TST_AOX_TST_W__W 8 #define ORX_TST_AOX_TST_W__M 0 xFF#define ORX_TST_AOX_TST_W__PRE 0 x0#define QAM_COMM_EXEC__A 0 x1400000#define QAM_COMM_EXEC__W 2 #define QAM_COMM_EXEC__M 0 x3#define QAM_COMM_EXEC__PRE 0 x0#define QAM_COMM_EXEC_STOP 0 x0#define QAM_COMM_EXEC_ACTIVE 0 x1#define QAM_COMM_EXEC_HOLD 0 x2#define QAM_COMM_MB__A 0 x1400002#define QAM_COMM_MB__W 16 #define QAM_COMM_MB__M 0 xFFFF#define QAM_COMM_MB__PRE 0 x0#define QAM_COMM_INT_REQ__A 0 x1400003#define QAM_COMM_INT_REQ__W 16 #define QAM_COMM_INT_REQ__M 0 xFFFF#define QAM_COMM_INT_REQ__PRE 0 x0#define QAM_COMM_INT_REQ_SL_REQ__B 0 #define QAM_COMM_INT_REQ_SL_REQ__W 1 #define QAM_COMM_INT_REQ_SL_REQ__M 0 x1#define QAM_COMM_INT_REQ_SL_REQ__PRE 0 x0#define QAM_COMM_INT_REQ_LC_REQ__B 1 #define QAM_COMM_INT_REQ_LC_REQ__W 1 #define QAM_COMM_INT_REQ_LC_REQ__M 0 x2#define QAM_COMM_INT_REQ_LC_REQ__PRE 0 x0#define QAM_COMM_INT_REQ_VD_REQ__B 2 #define QAM_COMM_INT_REQ_VD_REQ__W 1 #define QAM_COMM_INT_REQ_VD_REQ__M 0 x4#define QAM_COMM_INT_REQ_VD_REQ__PRE 0 x0#define QAM_COMM_INT_REQ_SY_REQ__B 3 #define QAM_COMM_INT_REQ_SY_REQ__W 1 #define QAM_COMM_INT_REQ_SY_REQ__M 0 x8#define QAM_COMM_INT_REQ_SY_REQ__PRE 0 x0#define QAM_COMM_INT_STA__A 0 x1400005#define QAM_COMM_INT_STA__W 16 #define QAM_COMM_INT_STA__M 0 xFFFF#define QAM_COMM_INT_STA__PRE 0 x0#define QAM_COMM_INT_MSK__A 0 x1400006#define QAM_COMM_INT_MSK__W 16 #define QAM_COMM_INT_MSK__M 0 xFFFF#define QAM_COMM_INT_MSK__PRE 0 x0#define QAM_COMM_INT_STM__A 0 x1400007#define QAM_COMM_INT_STM__W 16 #define QAM_COMM_INT_STM__M 0 xFFFF#define QAM_COMM_INT_STM__PRE 0 x0#define QAM_TOP_COMM_EXEC__A 0 x1410000#define QAM_TOP_COMM_EXEC__W 2 #define QAM_TOP_COMM_EXEC__M 0 x3#define QAM_TOP_COMM_EXEC__PRE 0 x0#define QAM_TOP_COMM_EXEC_STOP 0 x0#define QAM_TOP_COMM_EXEC_ACTIVE 0 x1#define QAM_TOP_COMM_EXEC_HOLD 0 x2#define QAM_TOP_ANNEX__A 0 x1410010#define QAM_TOP_ANNEX__W 2 #define QAM_TOP_ANNEX__M 0 x3#define QAM_TOP_ANNEX__PRE 0 x1#define QAM_TOP_ANNEX_A 0 x0#define QAM_TOP_ANNEX_B 0 x1#define QAM_TOP_ANNEX_C 0 x2#define QAM_TOP_ANNEX_D 0 x3#define QAM_TOP_CONSTELLATION__A 0 x1410011#define QAM_TOP_CONSTELLATION__W 3 #define QAM_TOP_CONSTELLATION__M 0 x7#define QAM_TOP_CONSTELLATION__PRE 0 x5#define QAM_TOP_CONSTELLATION_NONE 0 x0#define QAM_TOP_CONSTELLATION_QPSK 0 x1#define QAM_TOP_CONSTELLATION_QAM8 0 x2#define QAM_TOP_CONSTELLATION_QAM16 0 x3#define QAM_TOP_CONSTELLATION_QAM32 0 x4#define QAM_TOP_CONSTELLATION_QAM64 0 x5#define QAM_TOP_CONSTELLATION_QAM128 0 x6#define QAM_TOP_CONSTELLATION_QAM256 0 x7#define QAM_FQ_COMM_EXEC__A 0 x1420000#define QAM_FQ_COMM_EXEC__W 2 #define QAM_FQ_COMM_EXEC__M 0 x3#define QAM_FQ_COMM_EXEC__PRE 0 x0#define QAM_FQ_COMM_EXEC_STOP 0 x0#define QAM_FQ_COMM_EXEC_ACTIVE 0 x1#define QAM_FQ_COMM_EXEC_HOLD 0 x2#define QAM_FQ_MODE__A 0 x1420010#define QAM_FQ_MODE__W 3 #define QAM_FQ_MODE__M 0 x7#define QAM_FQ_MODE__PRE 0 x0#define QAM_FQ_MODE_TAPRESET__B 0 #define QAM_FQ_MODE_TAPRESET__W 1 #define QAM_FQ_MODE_TAPRESET__M 0 x1#define QAM_FQ_MODE_TAPRESET__PRE 0 x0#define QAM_FQ_MODE_TAPRESET_RST 0 x1#define QAM_FQ_MODE_TAPLMS__B 1 #define QAM_FQ_MODE_TAPLMS__W 1 #define QAM_FQ_MODE_TAPLMS__M 0 x2#define QAM_FQ_MODE_TAPLMS__PRE 0 x0#define QAM_FQ_MODE_TAPLMS_UPD 0 x2#define QAM_FQ_MODE_TAPDRAIN__B 2 #define QAM_FQ_MODE_TAPDRAIN__W 1 #define QAM_FQ_MODE_TAPDRAIN__M 0 x4#define QAM_FQ_MODE_TAPDRAIN__PRE 0 x0#define QAM_FQ_MODE_TAPDRAIN_DRAIN 0 x4#define QAM_FQ_MU_FACTOR__A 0 x1420011#define QAM_FQ_MU_FACTOR__W 3 #define QAM_FQ_MU_FACTOR__M 0 x7#define QAM_FQ_MU_FACTOR__PRE 0 x0#define QAM_FQ_LA_FACTOR__A 0 x1420012#define QAM_FQ_LA_FACTOR__W 4 #define QAM_FQ_LA_FACTOR__M 0 xF#define QAM_FQ_LA_FACTOR__PRE 0 xC#define QAM_FQ_CENTTAP_IDX__A 0 x1420016#define QAM_FQ_CENTTAP_IDX__W 5 #define QAM_FQ_CENTTAP_IDX__M 0 x1F#define QAM_FQ_CENTTAP_IDX__PRE 0 x13#define QAM_FQ_CENTTAP_IDX_IDX__B 0 #define QAM_FQ_CENTTAP_IDX_IDX__W 5 #define QAM_FQ_CENTTAP_IDX_IDX__M 0 x1F#define QAM_FQ_CENTTAP_IDX_IDX__PRE 0 x13#define QAM_FQ_CENTTAP_VALUE__A 0 x1420017#define QAM_FQ_CENTTAP_VALUE__W 12 #define QAM_FQ_CENTTAP_VALUE__M 0 xFFF#define QAM_FQ_CENTTAP_VALUE__PRE 0 x600#define QAM_FQ_CENTTAP_VALUE_TAP__B 0 #define QAM_FQ_CENTTAP_VALUE_TAP__W 12 #define QAM_FQ_CENTTAP_VALUE_TAP__M 0 xFFF#define QAM_FQ_CENTTAP_VALUE_TAP__PRE 0 x600#define QAM_FQ_TAP_RE_EL0__A 0 x1420020#define QAM_FQ_TAP_RE_EL0__W 12 #define QAM_FQ_TAP_RE_EL0__M 0 xFFF#define QAM_FQ_TAP_RE_EL0__PRE 0 x2#define QAM_FQ_TAP_RE_EL0_TAP__B 0 #define QAM_FQ_TAP_RE_EL0_TAP__W 12 #define QAM_FQ_TAP_RE_EL0_TAP__M 0 xFFF#define QAM_FQ_TAP_RE_EL0_TAP__PRE 0 x2#define QAM_FQ_TAP_IM_EL0__A 0 x1420021#define QAM_FQ_TAP_IM_EL0__W 12 #define QAM_FQ_TAP_IM_EL0__M 0 xFFF#define QAM_FQ_TAP_IM_EL0__PRE 0 x2#define QAM_FQ_TAP_IM_EL0_TAP__B 0 #define QAM_FQ_TAP_IM_EL0_TAP__W 12 #define QAM_FQ_TAP_IM_EL0_TAP__M 0 xFFF#define QAM_FQ_TAP_IM_EL0_TAP__PRE 0 x2#define QAM_FQ_TAP_RE_EL1__A 0 x1420022#define QAM_FQ_TAP_RE_EL1__W 12 #define QAM_FQ_TAP_RE_EL1__M 0 xFFF#define QAM_FQ_TAP_RE_EL1__PRE 0 x2#define QAM_FQ_TAP_RE_EL1_TAP__B 0 #define QAM_FQ_TAP_RE_EL1_TAP__W 12 #define QAM_FQ_TAP_RE_EL1_TAP__M 0 xFFF#define QAM_FQ_TAP_RE_EL1_TAP__PRE 0 x2#define QAM_FQ_TAP_IM_EL1__A 0 x1420023#define QAM_FQ_TAP_IM_EL1__W 12 #define QAM_FQ_TAP_IM_EL1__M 0 xFFF#define QAM_FQ_TAP_IM_EL1__PRE 0 x2#define QAM_FQ_TAP_IM_EL1_TAP__B 0 #define QAM_FQ_TAP_IM_EL1_TAP__W 12 #define QAM_FQ_TAP_IM_EL1_TAP__M 0 xFFF#define QAM_FQ_TAP_IM_EL1_TAP__PRE 0 x2#define QAM_FQ_TAP_RE_EL2__A 0 x1420024#define QAM_FQ_TAP_RE_EL2__W 12 #define QAM_FQ_TAP_RE_EL2__M 0 xFFF#define QAM_FQ_TAP_RE_EL2__PRE 0 x2#define QAM_FQ_TAP_RE_EL2_TAP__B 0 #define QAM_FQ_TAP_RE_EL2_TAP__W 12 #define QAM_FQ_TAP_RE_EL2_TAP__M 0 xFFF#define QAM_FQ_TAP_RE_EL2_TAP__PRE 0 x2#define QAM_FQ_TAP_IM_EL2__A 0 x1420025#define QAM_FQ_TAP_IM_EL2__W 12 #define QAM_FQ_TAP_IM_EL2__M 0 xFFF#define QAM_FQ_TAP_IM_EL2__PRE 0 x2#define QAM_FQ_TAP_IM_EL2_TAP__B 0 #define QAM_FQ_TAP_IM_EL2_TAP__W 12 #define QAM_FQ_TAP_IM_EL2_TAP__M 0 xFFF#define QAM_FQ_TAP_IM_EL2_TAP__PRE 0 x2#define QAM_FQ_TAP_RE_EL3__A 0 x1420026#define QAM_FQ_TAP_RE_EL3__W 12 #define QAM_FQ_TAP_RE_EL3__M 0 xFFF#define QAM_FQ_TAP_RE_EL3__PRE 0 x2#define QAM_FQ_TAP_RE_EL3_TAP__B 0 #define QAM_FQ_TAP_RE_EL3_TAP__W 12 #define QAM_FQ_TAP_RE_EL3_TAP__M 0 xFFF#define QAM_FQ_TAP_RE_EL3_TAP__PRE 0 x2#define QAM_FQ_TAP_IM_EL3__A 0 x1420027#define QAM_FQ_TAP_IM_EL3__W 12 #define QAM_FQ_TAP_IM_EL3__M 0 xFFF#define QAM_FQ_TAP_IM_EL3__PRE 0 x2#define QAM_FQ_TAP_IM_EL3_TAP__B 0 #define QAM_FQ_TAP_IM_EL3_TAP__W 12 #define QAM_FQ_TAP_IM_EL3_TAP__M 0 xFFF#define QAM_FQ_TAP_IM_EL3_TAP__PRE 0 x2#define QAM_FQ_TAP_RE_EL4__A 0 x1420028#define QAM_FQ_TAP_RE_EL4__W 12 #define QAM_FQ_TAP_RE_EL4__M 0 xFFF#define QAM_FQ_TAP_RE_EL4__PRE 0 x2#define QAM_FQ_TAP_RE_EL4_TAP__B 0 #define QAM_FQ_TAP_RE_EL4_TAP__W 12 #define QAM_FQ_TAP_RE_EL4_TAP__M 0 xFFF#define QAM_FQ_TAP_RE_EL4_TAP__PRE 0 x2#define QAM_FQ_TAP_IM_EL4__A 0 x1420029#define QAM_FQ_TAP_IM_EL4__W 12 #define QAM_FQ_TAP_IM_EL4__M 0 xFFF#define QAM_FQ_TAP_IM_EL4__PRE 0 x2#define QAM_FQ_TAP_IM_EL4_TAP__B 0 #define QAM_FQ_TAP_IM_EL4_TAP__W 12 #define QAM_FQ_TAP_IM_EL4_TAP__M 0 xFFF#define QAM_FQ_TAP_IM_EL4_TAP__PRE 0 x2#define QAM_FQ_TAP_RE_EL5__A 0 x142002A#define QAM_FQ_TAP_RE_EL5__W 12 #define QAM_FQ_TAP_RE_EL5__M 0 xFFF#define QAM_FQ_TAP_RE_EL5__PRE 0 x2#define QAM_FQ_TAP_RE_EL5_TAP__B 0 #define QAM_FQ_TAP_RE_EL5_TAP__W 12 #define QAM_FQ_TAP_RE_EL5_TAP__M 0 xFFF#define QAM_FQ_TAP_RE_EL5_TAP__PRE 0 x2#define QAM_FQ_TAP_IM_EL5__A 0 x142002B#define QAM_FQ_TAP_IM_EL5__W 12 #define QAM_FQ_TAP_IM_EL5__M 0 xFFF#define QAM_FQ_TAP_IM_EL5__PRE 0 x2#define QAM_FQ_TAP_IM_EL5_TAP__B 0 #define QAM_FQ_TAP_IM_EL5_TAP__W 12 #define QAM_FQ_TAP_IM_EL5_TAP__M 0 xFFF#define QAM_FQ_TAP_IM_EL5_TAP__PRE 0 x2#define QAM_FQ_TAP_RE_EL6__A 0 x142002C#define QAM_FQ_TAP_RE_EL6__W 12 #define QAM_FQ_TAP_RE_EL6__M 0 xFFF#define QAM_FQ_TAP_RE_EL6__PRE 0 x2#define QAM_FQ_TAP_RE_EL6_TAP__B 0 #define QAM_FQ_TAP_RE_EL6_TAP__W 12 #define QAM_FQ_TAP_RE_EL6_TAP__M 0 xFFF#define QAM_FQ_TAP_RE_EL6_TAP__PRE 0 x2#define QAM_FQ_TAP_IM_EL6__A 0 x142002D#define QAM_FQ_TAP_IM_EL6__W 12 #define QAM_FQ_TAP_IM_EL6__M 0 xFFF#define QAM_FQ_TAP_IM_EL6__PRE 0 x2#define QAM_FQ_TAP_IM_EL6_TAP__B 0 #define QAM_FQ_TAP_IM_EL6_TAP__W 12 #define QAM_FQ_TAP_IM_EL6_TAP__M 0 xFFF#define QAM_FQ_TAP_IM_EL6_TAP__PRE 0 x2#define QAM_FQ_TAP_RE_EL7__A 0 x142002E#define QAM_FQ_TAP_RE_EL7__W 12 #define QAM_FQ_TAP_RE_EL7__M 0 xFFF#define QAM_FQ_TAP_RE_EL7__PRE 0 x2#define QAM_FQ_TAP_RE_EL7_TAP__B 0 #define QAM_FQ_TAP_RE_EL7_TAP__W 12 #define QAM_FQ_TAP_RE_EL7_TAP__M 0 xFFF#define QAM_FQ_TAP_RE_EL7_TAP__PRE 0 x2#define QAM_FQ_TAP_IM_EL7__A 0 x142002F#define QAM_FQ_TAP_IM_EL7__W 12 #define QAM_FQ_TAP_IM_EL7__M 0 xFFF#define QAM_FQ_TAP_IM_EL7__PRE 0 x2#define QAM_FQ_TAP_IM_EL7_TAP__B 0 #define QAM_FQ_TAP_IM_EL7_TAP__W 12 #define QAM_FQ_TAP_IM_EL7_TAP__M 0 xFFF#define QAM_FQ_TAP_IM_EL7_TAP__PRE 0 x2#define QAM_FQ_TAP_RE_EL8__A 0 x1420030#define QAM_FQ_TAP_RE_EL8__W 12 #define QAM_FQ_TAP_RE_EL8__M 0 xFFF#define QAM_FQ_TAP_RE_EL8__PRE 0 x2#define QAM_FQ_TAP_RE_EL8_TAP__B 0 #define QAM_FQ_TAP_RE_EL8_TAP__W 12 #define QAM_FQ_TAP_RE_EL8_TAP__M 0 xFFF#define QAM_FQ_TAP_RE_EL8_TAP__PRE 0 x2#define QAM_FQ_TAP_IM_EL8__A 0 x1420031#define QAM_FQ_TAP_IM_EL8__W 12 #define QAM_FQ_TAP_IM_EL8__M 0 xFFF#define QAM_FQ_TAP_IM_EL8__PRE 0 x2#define QAM_FQ_TAP_IM_EL8_TAP__B 0 #define QAM_FQ_TAP_IM_EL8_TAP__W 12 #define QAM_FQ_TAP_IM_EL8_TAP__M 0 xFFF#define QAM_FQ_TAP_IM_EL8_TAP__PRE 0 x2#define QAM_FQ_TAP_RE_EL9__A 0 x1420032#define QAM_FQ_TAP_RE_EL9__W 12 #define QAM_FQ_TAP_RE_EL9__M 0 xFFF#define QAM_FQ_TAP_RE_EL9__PRE 0 x2#define QAM_FQ_TAP_RE_EL9_TAP__B 0 #define QAM_FQ_TAP_RE_EL9_TAP__W 12 #define QAM_FQ_TAP_RE_EL9_TAP__M 0 xFFF#define QAM_FQ_TAP_RE_EL9_TAP__PRE 0 x2#define QAM_FQ_TAP_IM_EL9__A 0 x1420033#define QAM_FQ_TAP_IM_EL9__W 12 #define QAM_FQ_TAP_IM_EL9__M 0 xFFF#define QAM_FQ_TAP_IM_EL9__PRE 0 x2#define QAM_FQ_TAP_IM_EL9_TAP__B 0 #define QAM_FQ_TAP_IM_EL9_TAP__W 12 #define QAM_FQ_TAP_IM_EL9_TAP__M 0 xFFF#define QAM_FQ_TAP_IM_EL9_TAP__PRE 0 x2#define QAM_FQ_TAP_RE_EL10__A 0 x1420034#define QAM_FQ_TAP_RE_EL10__W 12 #define QAM_FQ_TAP_RE_EL10__M 0 xFFF#define QAM_FQ_TAP_RE_EL10__PRE 0 x2#define QAM_FQ_TAP_RE_EL10_TAP__B 0 #define QAM_FQ_TAP_RE_EL10_TAP__W 12 #define QAM_FQ_TAP_RE_EL10_TAP__M 0 xFFF#define QAM_FQ_TAP_RE_EL10_TAP__PRE 0 x2#define QAM_FQ_TAP_IM_EL10__A 0 x1420035#define QAM_FQ_TAP_IM_EL10__W 12 #define QAM_FQ_TAP_IM_EL10__M 0 xFFF#define QAM_FQ_TAP_IM_EL10__PRE 0 x2#define QAM_FQ_TAP_IM_EL10_TAP__B 0 #define QAM_FQ_TAP_IM_EL10_TAP__W 12 #define QAM_FQ_TAP_IM_EL10_TAP__M 0 xFFF#define QAM_FQ_TAP_IM_EL10_TAP__PRE 0 x2#define QAM_FQ_TAP_RE_EL11__A 0 x1420036#define QAM_FQ_TAP_RE_EL11__W 12 #define QAM_FQ_TAP_RE_EL11__M 0 xFFF#define QAM_FQ_TAP_RE_EL11__PRE 0 x2#define QAM_FQ_TAP_RE_EL11_TAP__B 0 #define QAM_FQ_TAP_RE_EL11_TAP__W 12 #define QAM_FQ_TAP_RE_EL11_TAP__M 0 xFFF#define QAM_FQ_TAP_RE_EL11_TAP__PRE 0 x2#define QAM_FQ_TAP_IM_EL11__A 0 x1420037#define QAM_FQ_TAP_IM_EL11__W 12 #define QAM_FQ_TAP_IM_EL11__M 0 xFFF#define QAM_FQ_TAP_IM_EL11__PRE 0 x2#define QAM_FQ_TAP_IM_EL11_TAP__B 0 #define QAM_FQ_TAP_IM_EL11_TAP__W 12 #define QAM_FQ_TAP_IM_EL11_TAP__M 0 xFFF#define QAM_FQ_TAP_IM_EL11_TAP__PRE 0 x2#define QAM_FQ_TAP_RE_EL12__A 0 x1420038#define QAM_FQ_TAP_RE_EL12__W 12 #define QAM_FQ_TAP_RE_EL12__M 0 xFFF#define QAM_FQ_TAP_RE_EL12__PRE 0 x2#define QAM_FQ_TAP_RE_EL12_TAP__B 0 #define QAM_FQ_TAP_RE_EL12_TAP__W 12 #define QAM_FQ_TAP_RE_EL12_TAP__M 0 xFFF#define QAM_FQ_TAP_RE_EL12_TAP__PRE 0 x2#define QAM_FQ_TAP_IM_EL12__A 0 x1420039#define QAM_FQ_TAP_IM_EL12__W 12 #define QAM_FQ_TAP_IM_EL12__M 0 xFFF#define QAM_FQ_TAP_IM_EL12__PRE 0 x2#define QAM_FQ_TAP_IM_EL12_TAP__B 0 #define QAM_FQ_TAP_IM_EL12_TAP__W 12 #define QAM_FQ_TAP_IM_EL12_TAP__M 0 xFFF#define QAM_FQ_TAP_IM_EL12_TAP__PRE 0 x2#define QAM_FQ_TAP_RE_EL13__A 0 x142003A#define QAM_FQ_TAP_RE_EL13__W 12 #define QAM_FQ_TAP_RE_EL13__M 0 xFFF#define QAM_FQ_TAP_RE_EL13__PRE 0 x2#define QAM_FQ_TAP_RE_EL13_TAP__B 0 #define QAM_FQ_TAP_RE_EL13_TAP__W 12 #define QAM_FQ_TAP_RE_EL13_TAP__M 0 xFFF#define QAM_FQ_TAP_RE_EL13_TAP__PRE 0 x2#define QAM_FQ_TAP_IM_EL13__A 0 x142003B#define QAM_FQ_TAP_IM_EL13__W 12 #define QAM_FQ_TAP_IM_EL13__M 0 xFFF#define QAM_FQ_TAP_IM_EL13__PRE 0 x2#define QAM_FQ_TAP_IM_EL13_TAP__B 0 #define QAM_FQ_TAP_IM_EL13_TAP__W 12 #define QAM_FQ_TAP_IM_EL13_TAP__M 0 xFFF#define QAM_FQ_TAP_IM_EL13_TAP__PRE 0 x2#define QAM_FQ_TAP_RE_EL14__A 0 x142003C#define QAM_FQ_TAP_RE_EL14__W 12 #define QAM_FQ_TAP_RE_EL14__M 0 xFFF#define QAM_FQ_TAP_RE_EL14__PRE 0 x2#define QAM_FQ_TAP_RE_EL14_TAP__B 0 #define QAM_FQ_TAP_RE_EL14_TAP__W 12 #define QAM_FQ_TAP_RE_EL14_TAP__M 0 xFFF#define QAM_FQ_TAP_RE_EL14_TAP__PRE 0 x2#define QAM_FQ_TAP_IM_EL14__A 0 x142003D#define QAM_FQ_TAP_IM_EL14__W 12 #define QAM_FQ_TAP_IM_EL14__M 0 xFFF#define QAM_FQ_TAP_IM_EL14__PRE 0 x2#define QAM_FQ_TAP_IM_EL14_TAP__B 0 #define QAM_FQ_TAP_IM_EL14_TAP__W 12 #define QAM_FQ_TAP_IM_EL14_TAP__M 0 xFFF#define QAM_FQ_TAP_IM_EL14_TAP__PRE 0 x2#define QAM_FQ_TAP_RE_EL15__A 0 x142003E#define QAM_FQ_TAP_RE_EL15__W 12 #define QAM_FQ_TAP_RE_EL15__M 0 xFFF#define QAM_FQ_TAP_RE_EL15__PRE 0 x2#define QAM_FQ_TAP_RE_EL15_TAP__B 0 #define QAM_FQ_TAP_RE_EL15_TAP__W 12 #define QAM_FQ_TAP_RE_EL15_TAP__M 0 xFFF#define QAM_FQ_TAP_RE_EL15_TAP__PRE 0 x2#define QAM_FQ_TAP_IM_EL15__A 0 x142003F#define QAM_FQ_TAP_IM_EL15__W 12 #define QAM_FQ_TAP_IM_EL15__M 0 xFFF#define QAM_FQ_TAP_IM_EL15__PRE 0 x2#define QAM_FQ_TAP_IM_EL15_TAP__B 0 #define QAM_FQ_TAP_IM_EL15_TAP__W 12 #define QAM_FQ_TAP_IM_EL15_TAP__M 0 xFFF#define QAM_FQ_TAP_IM_EL15_TAP__PRE 0 x2#define QAM_FQ_TAP_RE_EL16__A 0 x1420040#define QAM_FQ_TAP_RE_EL16__W 12 #define QAM_FQ_TAP_RE_EL16__M 0 xFFF#define QAM_FQ_TAP_RE_EL16__PRE 0 x2#define QAM_FQ_TAP_RE_EL16_TAP__B 0 #define QAM_FQ_TAP_RE_EL16_TAP__W 12 #define QAM_FQ_TAP_RE_EL16_TAP__M 0 xFFF#define QAM_FQ_TAP_RE_EL16_TAP__PRE 0 x2#define QAM_FQ_TAP_IM_EL16__A 0 x1420041#define QAM_FQ_TAP_IM_EL16__W 12 #define QAM_FQ_TAP_IM_EL16__M 0 xFFF#define QAM_FQ_TAP_IM_EL16__PRE 0 x2#define QAM_FQ_TAP_IM_EL16_TAP__B 0 #define QAM_FQ_TAP_IM_EL16_TAP__W 12 #define QAM_FQ_TAP_IM_EL16_TAP__M 0 xFFF#define QAM_FQ_TAP_IM_EL16_TAP__PRE 0 x2#define QAM_FQ_TAP_RE_EL17__A 0 x1420042#define QAM_FQ_TAP_RE_EL17__W 12 #define QAM_FQ_TAP_RE_EL17__M 0 xFFF#define QAM_FQ_TAP_RE_EL17__PRE 0 x2#define QAM_FQ_TAP_RE_EL17_TAP__B 0 #define QAM_FQ_TAP_RE_EL17_TAP__W 12 #define QAM_FQ_TAP_RE_EL17_TAP__M 0 xFFF#define QAM_FQ_TAP_RE_EL17_TAP__PRE 0 x2#define QAM_FQ_TAP_IM_EL17__A 0 x1420043#define QAM_FQ_TAP_IM_EL17__W 12 #define QAM_FQ_TAP_IM_EL17__M 0 xFFF#define QAM_FQ_TAP_IM_EL17__PRE 0 x2#define QAM_FQ_TAP_IM_EL17_TAP__B 0 #define QAM_FQ_TAP_IM_EL17_TAP__W 12 #define QAM_FQ_TAP_IM_EL17_TAP__M 0 xFFF#define QAM_FQ_TAP_IM_EL17_TAP__PRE 0 x2#define QAM_FQ_TAP_RE_EL18__A 0 x1420044#define QAM_FQ_TAP_RE_EL18__W 12 #define QAM_FQ_TAP_RE_EL18__M 0 xFFF#define QAM_FQ_TAP_RE_EL18__PRE 0 x2#define QAM_FQ_TAP_RE_EL18_TAP__B 0 #define QAM_FQ_TAP_RE_EL18_TAP__W 12 #define QAM_FQ_TAP_RE_EL18_TAP__M 0 xFFF#define QAM_FQ_TAP_RE_EL18_TAP__PRE 0 x2#define QAM_FQ_TAP_IM_EL18__A 0 x1420045#define QAM_FQ_TAP_IM_EL18__W 12 #define QAM_FQ_TAP_IM_EL18__M 0 xFFF#define QAM_FQ_TAP_IM_EL18__PRE 0 x2#define QAM_FQ_TAP_IM_EL18_TAP__B 0 #define QAM_FQ_TAP_IM_EL18_TAP__W 12 #define QAM_FQ_TAP_IM_EL18_TAP__M 0 xFFF#define QAM_FQ_TAP_IM_EL18_TAP__PRE 0 x2#define QAM_FQ_TAP_RE_EL19__A 0 x1420046#define QAM_FQ_TAP_RE_EL19__W 12 #define QAM_FQ_TAP_RE_EL19__M 0 xFFF#define QAM_FQ_TAP_RE_EL19__PRE 0 x600#define QAM_FQ_TAP_RE_EL19_TAP__B 0 #define QAM_FQ_TAP_RE_EL19_TAP__W 12 #define QAM_FQ_TAP_RE_EL19_TAP__M 0 xFFF#define QAM_FQ_TAP_RE_EL19_TAP__PRE 0 x600#define QAM_FQ_TAP_IM_EL19__A 0 x1420047#define QAM_FQ_TAP_IM_EL19__W 12 #define QAM_FQ_TAP_IM_EL19__M 0 xFFF#define QAM_FQ_TAP_IM_EL19__PRE 0 x2#define QAM_FQ_TAP_IM_EL19_TAP__B 0 #define QAM_FQ_TAP_IM_EL19_TAP__W 12 #define QAM_FQ_TAP_IM_EL19_TAP__M 0 xFFF#define QAM_FQ_TAP_IM_EL19_TAP__PRE 0 x2#define QAM_FQ_TAP_RE_EL20__A 0 x1420048#define QAM_FQ_TAP_RE_EL20__W 12 #define QAM_FQ_TAP_RE_EL20__M 0 xFFF#define QAM_FQ_TAP_RE_EL20__PRE 0 x2#define QAM_FQ_TAP_RE_EL20_TAP__B 0 #define QAM_FQ_TAP_RE_EL20_TAP__W 12 #define QAM_FQ_TAP_RE_EL20_TAP__M 0 xFFF#define QAM_FQ_TAP_RE_EL20_TAP__PRE 0 x2#define QAM_FQ_TAP_IM_EL20__A 0 x1420049#define QAM_FQ_TAP_IM_EL20__W 12 #define QAM_FQ_TAP_IM_EL20__M 0 xFFF#define QAM_FQ_TAP_IM_EL20__PRE 0 x2#define QAM_FQ_TAP_IM_EL20_TAP__B 0 #define QAM_FQ_TAP_IM_EL20_TAP__W 12 #define QAM_FQ_TAP_IM_EL20_TAP__M 0 xFFF#define QAM_FQ_TAP_IM_EL20_TAP__PRE 0 x2#define QAM_FQ_TAP_RE_EL21__A 0 x142004A#define QAM_FQ_TAP_RE_EL21__W 12 #define QAM_FQ_TAP_RE_EL21__M 0 xFFF#define QAM_FQ_TAP_RE_EL21__PRE 0 x2#define QAM_FQ_TAP_RE_EL21_TAP__B 0 #define QAM_FQ_TAP_RE_EL21_TAP__W 12 #define QAM_FQ_TAP_RE_EL21_TAP__M 0 xFFF#define QAM_FQ_TAP_RE_EL21_TAP__PRE 0 x2#define QAM_FQ_TAP_IM_EL21__A 0 x142004B#define QAM_FQ_TAP_IM_EL21__W 12 #define QAM_FQ_TAP_IM_EL21__M 0 xFFF#define QAM_FQ_TAP_IM_EL21__PRE 0 x2#define QAM_FQ_TAP_IM_EL21_TAP__B 0 #define QAM_FQ_TAP_IM_EL21_TAP__W 12 #define QAM_FQ_TAP_IM_EL21_TAP__M 0 xFFF#define QAM_FQ_TAP_IM_EL21_TAP__PRE 0 x2#define QAM_FQ_TAP_RE_EL22__A 0 x142004C#define QAM_FQ_TAP_RE_EL22__W 12 #define QAM_FQ_TAP_RE_EL22__M 0 xFFF#define QAM_FQ_TAP_RE_EL22__PRE 0 x2#define QAM_FQ_TAP_RE_EL22_TAP__B 0 #define QAM_FQ_TAP_RE_EL22_TAP__W 12 #define QAM_FQ_TAP_RE_EL22_TAP__M 0 xFFF#define QAM_FQ_TAP_RE_EL22_TAP__PRE 0 x2#define QAM_FQ_TAP_IM_EL22__A 0 x142004D#define QAM_FQ_TAP_IM_EL22__W 12 #define QAM_FQ_TAP_IM_EL22__M 0 xFFF#define QAM_FQ_TAP_IM_EL22__PRE 0 x2#define QAM_FQ_TAP_IM_EL22_TAP__B 0 #define QAM_FQ_TAP_IM_EL22_TAP__W 12 #define QAM_FQ_TAP_IM_EL22_TAP__M 0 xFFF#define QAM_FQ_TAP_IM_EL22_TAP__PRE 0 x2#define QAM_FQ_TAP_RE_EL23__A 0 x142004E#define QAM_FQ_TAP_RE_EL23__W 12 #define QAM_FQ_TAP_RE_EL23__M 0 xFFF#define QAM_FQ_TAP_RE_EL23__PRE 0 x2#define QAM_FQ_TAP_RE_EL23_TAP__B 0 #define QAM_FQ_TAP_RE_EL23_TAP__W 12 #define QAM_FQ_TAP_RE_EL23_TAP__M 0 xFFF#define QAM_FQ_TAP_RE_EL23_TAP__PRE 0 x2#define QAM_FQ_TAP_IM_EL23__A 0 x142004F#define QAM_FQ_TAP_IM_EL23__W 12 #define QAM_FQ_TAP_IM_EL23__M 0 xFFF#define QAM_FQ_TAP_IM_EL23__PRE 0 x2#define QAM_FQ_TAP_IM_EL23_TAP__B 0 #define QAM_FQ_TAP_IM_EL23_TAP__W 12 #define QAM_FQ_TAP_IM_EL23_TAP__M 0 xFFF#define QAM_FQ_TAP_IM_EL23_TAP__PRE 0 x2#define QAM_SL_COMM_EXEC__A 0 x1430000#define QAM_SL_COMM_EXEC__W 2 #define QAM_SL_COMM_EXEC__M 0 x3#define QAM_SL_COMM_EXEC__PRE 0 x0#define QAM_SL_COMM_EXEC_STOP 0 x0#define QAM_SL_COMM_EXEC_ACTIVE 0 x1#define QAM_SL_COMM_EXEC_HOLD 0 x2#define QAM_SL_COMM_MB__A 0 x1430002#define QAM_SL_COMM_MB__W 4 #define QAM_SL_COMM_MB__M 0 xF#define QAM_SL_COMM_MB__PRE 0 x0#define QAM_SL_COMM_MB_CTL__B 0 #define QAM_SL_COMM_MB_CTL__W 1 #define QAM_SL_COMM_MB_CTL__M 0 x1#define QAM_SL_COMM_MB_CTL__PRE 0 x0#define QAM_SL_COMM_MB_CTL_OFF 0 x0#define QAM_SL_COMM_MB_CTL_ON 0 x1#define QAM_SL_COMM_MB_OBS__B 1 #define QAM_SL_COMM_MB_OBS__W 1 #define QAM_SL_COMM_MB_OBS__M 0 x2#define QAM_SL_COMM_MB_OBS__PRE 0 x0#define QAM_SL_COMM_MB_OBS_OFF 0 x0#define QAM_SL_COMM_MB_OBS_ON 0 x2#define QAM_SL_COMM_MB_MUX_OBS__B 2 #define QAM_SL_COMM_MB_MUX_OBS__W 2 #define QAM_SL_COMM_MB_MUX_OBS__M 0 xC#define QAM_SL_COMM_MB_MUX_OBS__PRE 0 x0#define QAM_SL_COMM_MB_MUX_OBS_CONST_CORR 0 x0#define QAM_SL_COMM_MB_MUX_OBS_CONST2LC_O 0 x4#define QAM_SL_COMM_MB_MUX_OBS_CONST2DQ_O 0 x8#define QAM_SL_COMM_MB_MUX_OBS_VDEC_O 0 xC#define QAM_SL_COMM_INT_REQ__A 0 x1430003#define QAM_SL_COMM_INT_REQ__W 1 #define QAM_SL_COMM_INT_REQ__M 0 x1#define QAM_SL_COMM_INT_REQ__PRE 0 x0#define QAM_SL_COMM_INT_STA__A 0 x1430005#define QAM_SL_COMM_INT_STA__W 2 #define QAM_SL_COMM_INT_STA__M 0 x3#define QAM_SL_COMM_INT_STA__PRE 0 x0#define QAM_SL_COMM_INT_STA_MED_ERR_INT__B 0 #define QAM_SL_COMM_INT_STA_MED_ERR_INT__W 1 #define QAM_SL_COMM_INT_STA_MED_ERR_INT__M 0 x1#define QAM_SL_COMM_INT_STA_MED_ERR_INT__PRE 0 x0#define QAM_SL_COMM_INT_STA_MER_INT__B 1 #define QAM_SL_COMM_INT_STA_MER_INT__W 1 #define QAM_SL_COMM_INT_STA_MER_INT__M 0 x2#define QAM_SL_COMM_INT_STA_MER_INT__PRE 0 x0#define QAM_SL_COMM_INT_MSK__A 0 x1430006#define QAM_SL_COMM_INT_MSK__W 2 #define QAM_SL_COMM_INT_MSK__M 0 x3#define QAM_SL_COMM_INT_MSK__PRE 0 x0#define QAM_SL_COMM_INT_MSK_MED_ERR_MSK__B 0 #define QAM_SL_COMM_INT_MSK_MED_ERR_MSK__W 1 #define QAM_SL_COMM_INT_MSK_MED_ERR_MSK__M 0 x1#define QAM_SL_COMM_INT_MSK_MED_ERR_MSK__PRE 0 x0#define QAM_SL_COMM_INT_MSK_MER_MSK__B 1 #define QAM_SL_COMM_INT_MSK_MER_MSK__W 1 #define QAM_SL_COMM_INT_MSK_MER_MSK__M 0 x2#define QAM_SL_COMM_INT_MSK_MER_MSK__PRE 0 x0#define QAM_SL_COMM_INT_STM__A 0 x1430007#define QAM_SL_COMM_INT_STM__W 2 #define QAM_SL_COMM_INT_STM__M 0 x3#define QAM_SL_COMM_INT_STM__PRE 0 x0#define QAM_SL_COMM_INT_STM_MED_ERR_STM__B 0 #define QAM_SL_COMM_INT_STM_MED_ERR_STM__W 1 #define QAM_SL_COMM_INT_STM_MED_ERR_STM__M 0 x1#define QAM_SL_COMM_INT_STM_MED_ERR_STM__PRE 0 x0#define QAM_SL_COMM_INT_STM_MER_STM__B 1 #define QAM_SL_COMM_INT_STM_MER_STM__W 1 #define QAM_SL_COMM_INT_STM_MER_STM__M 0 x2#define QAM_SL_COMM_INT_STM_MER_STM__PRE 0 x0#define QAM_SL_MODE__A 0 x1430010#define QAM_SL_MODE__W 11 #define QAM_SL_MODE__M 0 x7FF#define QAM_SL_MODE__PRE 0 x0#define QAM_SL_MODE_SLICER4LC__B 0 #define QAM_SL_MODE_SLICER4LC__W 2 #define QAM_SL_MODE_SLICER4LC__M 0 x3#define QAM_SL_MODE_SLICER4LC__PRE 0 x0#define QAM_SL_MODE_SLICER4LC_RECT 0 x0#define QAM_SL_MODE_SLICER4LC_ONET 0 x1#define QAM_SL_MODE_SLICER4LC_RAD 0 x2#define QAM_SL_MODE_SLICER4DQ__B 2 #define QAM_SL_MODE_SLICER4DQ__W 2 #define QAM_SL_MODE_SLICER4DQ__M 0 xC#define QAM_SL_MODE_SLICER4DQ__PRE 0 x0#define QAM_SL_MODE_SLICER4DQ_RECT 0 x0#define QAM_SL_MODE_SLICER4DQ_ONET 0 x4#define QAM_SL_MODE_SLICER4DQ_RAD 0 x8#define QAM_SL_MODE_SLICER4VD__B 4 #define QAM_SL_MODE_SLICER4VD__W 2 #define QAM_SL_MODE_SLICER4VD__M 0 x30#define QAM_SL_MODE_SLICER4VD__PRE 0 x0#define QAM_SL_MODE_SLICER4VD_RECT 0 x0#define QAM_SL_MODE_SLICER4VD_ONET 0 x10#define QAM_SL_MODE_SLICER4VD_RAD 0 x20#define QAM_SL_MODE_ROT_DIS__B 6 #define QAM_SL_MODE_ROT_DIS__W 1 #define QAM_SL_MODE_ROT_DIS__M 0 x40#define QAM_SL_MODE_ROT_DIS__PRE 0 x0#define QAM_SL_MODE_DQROT_DIS__B 7 #define QAM_SL_MODE_DQROT_DIS__W 1 #define QAM_SL_MODE_DQROT_DIS__M 0 x80#define QAM_SL_MODE_DQROT_DIS__PRE 0 x0#define QAM_SL_MODE_DFE_DIS__B 8 #define QAM_SL_MODE_DFE_DIS__W 1 #define QAM_SL_MODE_DFE_DIS__M 0 x100#define QAM_SL_MODE_DFE_DIS__PRE 0 x0#define QAM_SL_MODE_RADIUS_MIX__B 9 #define QAM_SL_MODE_RADIUS_MIX__W 1 #define QAM_SL_MODE_RADIUS_MIX__M 0 x200#define QAM_SL_MODE_RADIUS_MIX__PRE 0 x0#define QAM_SL_MODE_TILT_COMP__B 10 #define QAM_SL_MODE_TILT_COMP__W 1 #define QAM_SL_MODE_TILT_COMP__M 0 x400#define QAM_SL_MODE_TILT_COMP__PRE 0 x0#define QAM_SL_K_FACTOR__A 0 x1430011#define QAM_SL_K_FACTOR__W 4 #define QAM_SL_K_FACTOR__M 0 xF#define QAM_SL_K_FACTOR__PRE 0 x0#define QAM_SL_MEDIAN__A 0 x1430012#define QAM_SL_MEDIAN__W 14 #define QAM_SL_MEDIAN__M 0 x3FFF#define QAM_SL_MEDIAN__PRE 0 x0#define QAM_SL_MEDIAN_LENGTH__B 0 #define QAM_SL_MEDIAN_LENGTH__W 2 #define QAM_SL_MEDIAN_LENGTH__M 0 x3#define QAM_SL_MEDIAN_LENGTH__PRE 0 x0#define QAM_SL_MEDIAN_CORRECT__B 2 #define QAM_SL_MEDIAN_CORRECT__W 4 #define QAM_SL_MEDIAN_CORRECT__M 0 x3C#define QAM_SL_MEDIAN_CORRECT__PRE 0 x0#define QAM_SL_MEDIAN_TOLERANCE__B 6 #define QAM_SL_MEDIAN_TOLERANCE__W 7 #define QAM_SL_MEDIAN_TOLERANCE__M 0 x1FC0#define QAM_SL_MEDIAN_TOLERANCE__PRE 0 x0#define QAM_SL_MEDIAN_FAST__B 13 #define QAM_SL_MEDIAN_FAST__W 1 #define QAM_SL_MEDIAN_FAST__M 0 x2000#define QAM_SL_MEDIAN_FAST__PRE 0 x0#define QAM_SL_ALPHA__A 0 x1430013#define QAM_SL_ALPHA__W 3 #define QAM_SL_ALPHA__M 0 x7#define QAM_SL_ALPHA__PRE 0 x0#define QAM_SL_PHASELIMIT__A 0 x1430014#define QAM_SL_PHASELIMIT__W 9 #define QAM_SL_PHASELIMIT__M 0 x1FF#define QAM_SL_PHASELIMIT__PRE 0 x0#define QAM_SL_MTA_LENGTH__A 0 x1430015#define QAM_SL_MTA_LENGTH__W 2 #define QAM_SL_MTA_LENGTH__M 0 x3#define QAM_SL_MTA_LENGTH__PRE 0 x1#define QAM_SL_MTA_LENGTH_LENGTH__B 0 #define QAM_SL_MTA_LENGTH_LENGTH__W 2 #define QAM_SL_MTA_LENGTH_LENGTH__M 0 x3#define QAM_SL_MTA_LENGTH_LENGTH__PRE 0 x1#define QAM_SL_MEDIAN_ERROR__A 0 x1430016#define QAM_SL_MEDIAN_ERROR__W 10 #define QAM_SL_MEDIAN_ERROR__M 0 x3FF#define QAM_SL_MEDIAN_ERROR__PRE 0 x0#define QAM_SL_MEDIAN_ERROR_MEDIAN_ERR__B 0 #define QAM_SL_MEDIAN_ERROR_MEDIAN_ERR__W 10 #define QAM_SL_MEDIAN_ERROR_MEDIAN_ERR__M 0 x3FF#define QAM_SL_MEDIAN_ERROR_MEDIAN_ERR__PRE 0 x0#define QAM_SL_ERR_POWER__A 0 x1430017#define QAM_SL_ERR_POWER__W 16 #define QAM_SL_ERR_POWER__M 0 xFFFF#define QAM_SL_ERR_POWER__PRE 0 x0#define QAM_DQ_COMM_EXEC__A 0 x1440000#define QAM_DQ_COMM_EXEC__W 2 #define QAM_DQ_COMM_EXEC__M 0 x3#define QAM_DQ_COMM_EXEC__PRE 0 x0#define QAM_DQ_COMM_EXEC_STOP 0 x0#define QAM_DQ_COMM_EXEC_ACTIVE 0 x1#define QAM_DQ_COMM_EXEC_HOLD 0 x2#define QAM_DQ_MODE__A 0 x1440010#define QAM_DQ_MODE__W 5 #define QAM_DQ_MODE__M 0 x1F#define QAM_DQ_MODE__PRE 0 x0#define QAM_DQ_MODE_TAPRESET__B 0 #define QAM_DQ_MODE_TAPRESET__W 1 #define QAM_DQ_MODE_TAPRESET__M 0 x1#define QAM_DQ_MODE_TAPRESET__PRE 0 x0#define QAM_DQ_MODE_TAPRESET_RST 0 x1#define QAM_DQ_MODE_TAPLMS__B 1 #define QAM_DQ_MODE_TAPLMS__W 1 #define QAM_DQ_MODE_TAPLMS__M 0 x2#define QAM_DQ_MODE_TAPLMS__PRE 0 x0#define QAM_DQ_MODE_TAPLMS_UPD 0 x2#define QAM_DQ_MODE_TAPDRAIN__B 2 #define QAM_DQ_MODE_TAPDRAIN__W 1 #define QAM_DQ_MODE_TAPDRAIN__M 0 x4#define QAM_DQ_MODE_TAPDRAIN__PRE 0 x0#define QAM_DQ_MODE_TAPDRAIN_DRAIN 0 x4#define QAM_DQ_MODE_FB__B 3 #define QAM_DQ_MODE_FB__W 2 #define QAM_DQ_MODE_FB__M 0 x18#define QAM_DQ_MODE_FB__PRE 0 x0#define QAM_DQ_MODE_FB_CMA 0 x0#define QAM_DQ_MODE_FB_RADIUS 0 x8#define QAM_DQ_MODE_FB_DFB 0 x10#define QAM_DQ_MODE_FB_TRELLIS 0 x18#define QAM_DQ_MU_FACTOR__A 0 x1440011#define QAM_DQ_MU_FACTOR__W 3 #define QAM_DQ_MU_FACTOR__M 0 x7#define QAM_DQ_MU_FACTOR__PRE 0 x0#define QAM_DQ_LA_FACTOR__A 0 x1440012#define QAM_DQ_LA_FACTOR__W 4 #define QAM_DQ_LA_FACTOR__M 0 xF#define QAM_DQ_LA_FACTOR__PRE 0 xC#define QAM_DQ_CMA_RATIO__A 0 x1440013#define QAM_DQ_CMA_RATIO__W 14 #define QAM_DQ_CMA_RATIO__M 0 x3FFF#define QAM_DQ_CMA_RATIO__PRE 0 x3CF9#define QAM_DQ_CMA_RATIO_QPSK 0 x2000#define QAM_DQ_CMA_RATIO_QAM16 0 x34CD#define QAM_DQ_CMA_RATIO_QAM64 0 x3A00#define QAM_DQ_CMA_RATIO_QAM256 0 x3B4D#define QAM_DQ_CMA_RATIO_QAM1024 0 x3BA0#define QAM_DQ_QUAL_RADSEL__A 0 x1440014#define QAM_DQ_QUAL_RADSEL__W 3 #define QAM_DQ_QUAL_RADSEL__M 0 x7#define QAM_DQ_QUAL_RADSEL__PRE 0 x0#define QAM_DQ_QUAL_RADSEL_BIT__B 0 #define QAM_DQ_QUAL_RADSEL_BIT__W 3 #define QAM_DQ_QUAL_RADSEL_BIT__M 0 x7#define QAM_DQ_QUAL_RADSEL_BIT__PRE 0 x0#define QAM_DQ_QUAL_RADSEL_BIT_PURE_RADIUS 0 x0#define QAM_DQ_QUAL_RADSEL_BIT_PURE_CMA 0 x6#define QAM_DQ_QUAL_ENA__A 0 x1440015#define QAM_DQ_QUAL_ENA__W 1 #define QAM_DQ_QUAL_ENA__M 0 x1#define QAM_DQ_QUAL_ENA__PRE 0 x0#define QAM_DQ_QUAL_ENA_ENA__B 0 #define QAM_DQ_QUAL_ENA_ENA__W 1 #define QAM_DQ_QUAL_ENA_ENA__M 0 x1#define QAM_DQ_QUAL_ENA_ENA__PRE 0 x0#define QAM_DQ_QUAL_ENA_ENA_QUAL_WEIGHTING 0 x1#define QAM_DQ_QUAL_FUN0__A 0 x1440018#define QAM_DQ_QUAL_FUN0__W 6 #define QAM_DQ_QUAL_FUN0__M 0 x3F#define QAM_DQ_QUAL_FUN0__PRE 0 x4#define QAM_DQ_QUAL_FUN0_BIT__B 0 #define QAM_DQ_QUAL_FUN0_BIT__W 6 #define QAM_DQ_QUAL_FUN0_BIT__M 0 x3F#define QAM_DQ_QUAL_FUN0_BIT__PRE 0 x4#define QAM_DQ_QUAL_FUN1__A 0 x1440019#define QAM_DQ_QUAL_FUN1__W 6 #define QAM_DQ_QUAL_FUN1__M 0 x3F#define QAM_DQ_QUAL_FUN1__PRE 0 x4#define QAM_DQ_QUAL_FUN1_BIT__B 0 #define QAM_DQ_QUAL_FUN1_BIT__W 6 #define QAM_DQ_QUAL_FUN1_BIT__M 0 x3F#define QAM_DQ_QUAL_FUN1_BIT__PRE 0 x4#define QAM_DQ_QUAL_FUN2__A 0 x144001A#define QAM_DQ_QUAL_FUN2__W 6 #define QAM_DQ_QUAL_FUN2__M 0 x3F#define QAM_DQ_QUAL_FUN2__PRE 0 x4#define QAM_DQ_QUAL_FUN2_BIT__B 0 #define QAM_DQ_QUAL_FUN2_BIT__W 6 #define QAM_DQ_QUAL_FUN2_BIT__M 0 x3F#define QAM_DQ_QUAL_FUN2_BIT__PRE 0 x4#define QAM_DQ_QUAL_FUN3__A 0 x144001B#define QAM_DQ_QUAL_FUN3__W 6 #define QAM_DQ_QUAL_FUN3__M 0 x3F#define QAM_DQ_QUAL_FUN3__PRE 0 x4#define QAM_DQ_QUAL_FUN3_BIT__B 0 #define QAM_DQ_QUAL_FUN3_BIT__W 6 #define QAM_DQ_QUAL_FUN3_BIT__M 0 x3F#define QAM_DQ_QUAL_FUN3_BIT__PRE 0 x4#define QAM_DQ_QUAL_FUN4__A 0 x144001C#define QAM_DQ_QUAL_FUN4__W 6 #define QAM_DQ_QUAL_FUN4__M 0 x3F#define QAM_DQ_QUAL_FUN4__PRE 0 x6#define QAM_DQ_QUAL_FUN4_BIT__B 0 #define QAM_DQ_QUAL_FUN4_BIT__W 6 #define QAM_DQ_QUAL_FUN4_BIT__M 0 x3F#define QAM_DQ_QUAL_FUN4_BIT__PRE 0 x6#define QAM_DQ_QUAL_FUN5__A 0 x144001D#define QAM_DQ_QUAL_FUN5__W 6 #define QAM_DQ_QUAL_FUN5__M 0 x3F#define QAM_DQ_QUAL_FUN5__PRE 0 x6#define QAM_DQ_QUAL_FUN5_BIT__B 0 #define QAM_DQ_QUAL_FUN5_BIT__W 6 #define QAM_DQ_QUAL_FUN5_BIT__M 0 x3F#define QAM_DQ_QUAL_FUN5_BIT__PRE 0 x6#define QAM_DQ_RAW_LIM__A 0 x144001E#define QAM_DQ_RAW_LIM__W 5 #define QAM_DQ_RAW_LIM__M 0 x1F#define QAM_DQ_RAW_LIM__PRE 0 x1F#define QAM_DQ_RAW_LIM_BIT__B 0 #define QAM_DQ_RAW_LIM_BIT__W 5 #define QAM_DQ_RAW_LIM_BIT__M 0 x1F#define QAM_DQ_RAW_LIM_BIT__PRE 0 x1F#define QAM_DQ_TAP_RE_EL0__A 0 x1440020#define QAM_DQ_TAP_RE_EL0__W 12 #define QAM_DQ_TAP_RE_EL0__M 0 xFFF#define QAM_DQ_TAP_RE_EL0__PRE 0 x2#define QAM_DQ_TAP_RE_EL0_TAP__B 0 #define QAM_DQ_TAP_RE_EL0_TAP__W 12 #define QAM_DQ_TAP_RE_EL0_TAP__M 0 xFFF#define QAM_DQ_TAP_RE_EL0_TAP__PRE 0 x2#define QAM_DQ_TAP_IM_EL0__A 0 x1440021#define QAM_DQ_TAP_IM_EL0__W 12 #define QAM_DQ_TAP_IM_EL0__M 0 xFFF#define QAM_DQ_TAP_IM_EL0__PRE 0 x2#define QAM_DQ_TAP_IM_EL0_TAP__B 0 #define QAM_DQ_TAP_IM_EL0_TAP__W 12 #define QAM_DQ_TAP_IM_EL0_TAP__M 0 xFFF#define QAM_DQ_TAP_IM_EL0_TAP__PRE 0 x2#define QAM_DQ_TAP_RE_EL1__A 0 x1440022#define QAM_DQ_TAP_RE_EL1__W 12 #define QAM_DQ_TAP_RE_EL1__M 0 xFFF#define QAM_DQ_TAP_RE_EL1__PRE 0 x2#define QAM_DQ_TAP_RE_EL1_TAP__B 0 #define QAM_DQ_TAP_RE_EL1_TAP__W 12 #define QAM_DQ_TAP_RE_EL1_TAP__M 0 xFFF#define QAM_DQ_TAP_RE_EL1_TAP__PRE 0 x2#define QAM_DQ_TAP_IM_EL1__A 0 x1440023#define QAM_DQ_TAP_IM_EL1__W 12 #define QAM_DQ_TAP_IM_EL1__M 0 xFFF#define QAM_DQ_TAP_IM_EL1__PRE 0 x2#define QAM_DQ_TAP_IM_EL1_TAP__B 0 #define QAM_DQ_TAP_IM_EL1_TAP__W 12 #define QAM_DQ_TAP_IM_EL1_TAP__M 0 xFFF#define QAM_DQ_TAP_IM_EL1_TAP__PRE 0 x2#define QAM_DQ_TAP_RE_EL2__A 0 x1440024#define QAM_DQ_TAP_RE_EL2__W 12 #define QAM_DQ_TAP_RE_EL2__M 0 xFFF#define QAM_DQ_TAP_RE_EL2__PRE 0 x2#define QAM_DQ_TAP_RE_EL2_TAP__B 0 #define QAM_DQ_TAP_RE_EL2_TAP__W 12 #define QAM_DQ_TAP_RE_EL2_TAP__M 0 xFFF#define QAM_DQ_TAP_RE_EL2_TAP__PRE 0 x2#define QAM_DQ_TAP_IM_EL2__A 0 x1440025#define QAM_DQ_TAP_IM_EL2__W 12 #define QAM_DQ_TAP_IM_EL2__M 0 xFFF#define QAM_DQ_TAP_IM_EL2__PRE 0 x2#define QAM_DQ_TAP_IM_EL2_TAP__B 0 #define QAM_DQ_TAP_IM_EL2_TAP__W 12 #define QAM_DQ_TAP_IM_EL2_TAP__M 0 xFFF#define QAM_DQ_TAP_IM_EL2_TAP__PRE 0 x2#define QAM_DQ_TAP_RE_EL3__A 0 x1440026#define QAM_DQ_TAP_RE_EL3__W 12 #define QAM_DQ_TAP_RE_EL3__M 0 xFFF#define QAM_DQ_TAP_RE_EL3__PRE 0 x2#define QAM_DQ_TAP_RE_EL3_TAP__B 0 #define QAM_DQ_TAP_RE_EL3_TAP__W 12 #define QAM_DQ_TAP_RE_EL3_TAP__M 0 xFFF#define QAM_DQ_TAP_RE_EL3_TAP__PRE 0 x2#define QAM_DQ_TAP_IM_EL3__A 0 x1440027#define QAM_DQ_TAP_IM_EL3__W 12 #define QAM_DQ_TAP_IM_EL3__M 0 xFFF#define QAM_DQ_TAP_IM_EL3__PRE 0 x2#define QAM_DQ_TAP_IM_EL3_TAP__B 0 #define QAM_DQ_TAP_IM_EL3_TAP__W 12 #define QAM_DQ_TAP_IM_EL3_TAP__M 0 xFFF#define QAM_DQ_TAP_IM_EL3_TAP__PRE 0 x2#define QAM_DQ_TAP_RE_EL4__A 0 x1440028#define QAM_DQ_TAP_RE_EL4__W 12 #define QAM_DQ_TAP_RE_EL4__M 0 xFFF#define QAM_DQ_TAP_RE_EL4__PRE 0 x2#define QAM_DQ_TAP_RE_EL4_TAP__B 0 #define QAM_DQ_TAP_RE_EL4_TAP__W 12 #define QAM_DQ_TAP_RE_EL4_TAP__M 0 xFFF#define QAM_DQ_TAP_RE_EL4_TAP__PRE 0 x2#define QAM_DQ_TAP_IM_EL4__A 0 x1440029#define QAM_DQ_TAP_IM_EL4__W 12 #define QAM_DQ_TAP_IM_EL4__M 0 xFFF#define QAM_DQ_TAP_IM_EL4__PRE 0 x2#define QAM_DQ_TAP_IM_EL4_TAP__B 0 #define QAM_DQ_TAP_IM_EL4_TAP__W 12 #define QAM_DQ_TAP_IM_EL4_TAP__M 0 xFFF#define QAM_DQ_TAP_IM_EL4_TAP__PRE 0 x2#define QAM_DQ_TAP_RE_EL5__A 0 x144002A#define QAM_DQ_TAP_RE_EL5__W 12 #define QAM_DQ_TAP_RE_EL5__M 0 xFFF#define QAM_DQ_TAP_RE_EL5__PRE 0 x2#define QAM_DQ_TAP_RE_EL5_TAP__B 0 #define QAM_DQ_TAP_RE_EL5_TAP__W 12 #define QAM_DQ_TAP_RE_EL5_TAP__M 0 xFFF#define QAM_DQ_TAP_RE_EL5_TAP__PRE 0 x2#define QAM_DQ_TAP_IM_EL5__A 0 x144002B#define QAM_DQ_TAP_IM_EL5__W 12 #define QAM_DQ_TAP_IM_EL5__M 0 xFFF#define QAM_DQ_TAP_IM_EL5__PRE 0 x2#define QAM_DQ_TAP_IM_EL5_TAP__B 0 #define QAM_DQ_TAP_IM_EL5_TAP__W 12 #define QAM_DQ_TAP_IM_EL5_TAP__M 0 xFFF#define QAM_DQ_TAP_IM_EL5_TAP__PRE 0 x2#define QAM_DQ_TAP_RE_EL6__A 0 x144002C#define QAM_DQ_TAP_RE_EL6__W 12 #define QAM_DQ_TAP_RE_EL6__M 0 xFFF#define QAM_DQ_TAP_RE_EL6__PRE 0 x2#define QAM_DQ_TAP_RE_EL6_TAP__B 0 #define QAM_DQ_TAP_RE_EL6_TAP__W 12 #define QAM_DQ_TAP_RE_EL6_TAP__M 0 xFFF#define QAM_DQ_TAP_RE_EL6_TAP__PRE 0 x2#define QAM_DQ_TAP_IM_EL6__A 0 x144002D#define QAM_DQ_TAP_IM_EL6__W 12 #define QAM_DQ_TAP_IM_EL6__M 0 xFFF#define QAM_DQ_TAP_IM_EL6__PRE 0 x2#define QAM_DQ_TAP_IM_EL6_TAP__B 0 #define QAM_DQ_TAP_IM_EL6_TAP__W 12 #define QAM_DQ_TAP_IM_EL6_TAP__M 0 xFFF#define QAM_DQ_TAP_IM_EL6_TAP__PRE 0 x2#define QAM_DQ_TAP_RE_EL7__A 0 x144002E#define QAM_DQ_TAP_RE_EL7__W 12 #define QAM_DQ_TAP_RE_EL7__M 0 xFFF#define QAM_DQ_TAP_RE_EL7__PRE 0 x2#define QAM_DQ_TAP_RE_EL7_TAP__B 0 #define QAM_DQ_TAP_RE_EL7_TAP__W 12 #define QAM_DQ_TAP_RE_EL7_TAP__M 0 xFFF#define QAM_DQ_TAP_RE_EL7_TAP__PRE 0 x2#define QAM_DQ_TAP_IM_EL7__A 0 x144002F#define QAM_DQ_TAP_IM_EL7__W 12 #define QAM_DQ_TAP_IM_EL7__M 0 xFFF#define QAM_DQ_TAP_IM_EL7__PRE 0 x2#define QAM_DQ_TAP_IM_EL7_TAP__B 0 #define QAM_DQ_TAP_IM_EL7_TAP__W 12 #define QAM_DQ_TAP_IM_EL7_TAP__M 0 xFFF#define QAM_DQ_TAP_IM_EL7_TAP__PRE 0 x2#define QAM_DQ_TAP_RE_EL8__A 0 x1440030#define QAM_DQ_TAP_RE_EL8__W 12 #define QAM_DQ_TAP_RE_EL8__M 0 xFFF#define QAM_DQ_TAP_RE_EL8__PRE 0 x2#define QAM_DQ_TAP_RE_EL8_TAP__B 0 #define QAM_DQ_TAP_RE_EL8_TAP__W 12 #define QAM_DQ_TAP_RE_EL8_TAP__M 0 xFFF#define QAM_DQ_TAP_RE_EL8_TAP__PRE 0 x2#define QAM_DQ_TAP_IM_EL8__A 0 x1440031#define QAM_DQ_TAP_IM_EL8__W 12 #define QAM_DQ_TAP_IM_EL8__M 0 xFFF#define QAM_DQ_TAP_IM_EL8__PRE 0 x2#define QAM_DQ_TAP_IM_EL8_TAP__B 0 #define QAM_DQ_TAP_IM_EL8_TAP__W 12 #define QAM_DQ_TAP_IM_EL8_TAP__M 0 xFFF#define QAM_DQ_TAP_IM_EL8_TAP__PRE 0 x2#define QAM_DQ_TAP_RE_EL9__A 0 x1440032#define QAM_DQ_TAP_RE_EL9__W 12 #define QAM_DQ_TAP_RE_EL9__M 0 xFFF#define QAM_DQ_TAP_RE_EL9__PRE 0 x2#define QAM_DQ_TAP_RE_EL9_TAP__B 0 #define QAM_DQ_TAP_RE_EL9_TAP__W 12 #define QAM_DQ_TAP_RE_EL9_TAP__M 0 xFFF#define QAM_DQ_TAP_RE_EL9_TAP__PRE 0 x2#define QAM_DQ_TAP_IM_EL9__A 0 x1440033#define QAM_DQ_TAP_IM_EL9__W 12 #define QAM_DQ_TAP_IM_EL9__M 0 xFFF#define QAM_DQ_TAP_IM_EL9__PRE 0 x2#define QAM_DQ_TAP_IM_EL9_TAP__B 0 #define QAM_DQ_TAP_IM_EL9_TAP__W 12 #define QAM_DQ_TAP_IM_EL9_TAP__M 0 xFFF#define QAM_DQ_TAP_IM_EL9_TAP__PRE 0 x2#define QAM_DQ_TAP_RE_EL10__A 0 x1440034#define QAM_DQ_TAP_RE_EL10__W 12 #define QAM_DQ_TAP_RE_EL10__M 0 xFFF#define QAM_DQ_TAP_RE_EL10__PRE 0 x2#define QAM_DQ_TAP_RE_EL10_TAP__B 0 #define QAM_DQ_TAP_RE_EL10_TAP__W 12 #define QAM_DQ_TAP_RE_EL10_TAP__M 0 xFFF#define QAM_DQ_TAP_RE_EL10_TAP__PRE 0 x2#define QAM_DQ_TAP_IM_EL10__A 0 x1440035#define QAM_DQ_TAP_IM_EL10__W 12 #define QAM_DQ_TAP_IM_EL10__M 0 xFFF#define QAM_DQ_TAP_IM_EL10__PRE 0 x2#define QAM_DQ_TAP_IM_EL10_TAP__B 0 #define QAM_DQ_TAP_IM_EL10_TAP__W 12 #define QAM_DQ_TAP_IM_EL10_TAP__M 0 xFFF#define QAM_DQ_TAP_IM_EL10_TAP__PRE 0 x2#define QAM_DQ_TAP_RE_EL11__A 0 x1440036#define QAM_DQ_TAP_RE_EL11__W 12 #define QAM_DQ_TAP_RE_EL11__M 0 xFFF#define QAM_DQ_TAP_RE_EL11__PRE 0 x2#define QAM_DQ_TAP_RE_EL11_TAP__B 0 #define QAM_DQ_TAP_RE_EL11_TAP__W 12 #define QAM_DQ_TAP_RE_EL11_TAP__M 0 xFFF#define QAM_DQ_TAP_RE_EL11_TAP__PRE 0 x2#define QAM_DQ_TAP_IM_EL11__A 0 x1440037#define QAM_DQ_TAP_IM_EL11__W 12 #define QAM_DQ_TAP_IM_EL11__M 0 xFFF#define QAM_DQ_TAP_IM_EL11__PRE 0 x2#define QAM_DQ_TAP_IM_EL11_TAP__B 0 #define QAM_DQ_TAP_IM_EL11_TAP__W 12 #define QAM_DQ_TAP_IM_EL11_TAP__M 0 xFFF#define QAM_DQ_TAP_IM_EL11_TAP__PRE 0 x2#define QAM_DQ_TAP_RE_EL12__A 0 x1440038#define QAM_DQ_TAP_RE_EL12__W 12 #define QAM_DQ_TAP_RE_EL12__M 0 xFFF#define QAM_DQ_TAP_RE_EL12__PRE 0 x2#define QAM_DQ_TAP_RE_EL12_TAP__B 0 #define QAM_DQ_TAP_RE_EL12_TAP__W 12 #define QAM_DQ_TAP_RE_EL12_TAP__M 0 xFFF#define QAM_DQ_TAP_RE_EL12_TAP__PRE 0 x2#define QAM_DQ_TAP_IM_EL12__A 0 x1440039#define QAM_DQ_TAP_IM_EL12__W 12 #define QAM_DQ_TAP_IM_EL12__M 0 xFFF#define QAM_DQ_TAP_IM_EL12__PRE 0 x2#define QAM_DQ_TAP_IM_EL12_TAP__B 0 #define QAM_DQ_TAP_IM_EL12_TAP__W 12 #define QAM_DQ_TAP_IM_EL12_TAP__M 0 xFFF#define QAM_DQ_TAP_IM_EL12_TAP__PRE 0 x2#define QAM_DQ_TAP_RE_EL13__A 0 x144003A#define QAM_DQ_TAP_RE_EL13__W 12 #define QAM_DQ_TAP_RE_EL13__M 0 xFFF#define QAM_DQ_TAP_RE_EL13__PRE 0 x2#define QAM_DQ_TAP_RE_EL13_TAP__B 0 #define QAM_DQ_TAP_RE_EL13_TAP__W 12 #define QAM_DQ_TAP_RE_EL13_TAP__M 0 xFFF#define QAM_DQ_TAP_RE_EL13_TAP__PRE 0 x2#define QAM_DQ_TAP_IM_EL13__A 0 x144003B#define QAM_DQ_TAP_IM_EL13__W 12 #define QAM_DQ_TAP_IM_EL13__M 0 xFFF#define QAM_DQ_TAP_IM_EL13__PRE 0 x2#define QAM_DQ_TAP_IM_EL13_TAP__B 0 #define QAM_DQ_TAP_IM_EL13_TAP__W 12 #define QAM_DQ_TAP_IM_EL13_TAP__M 0 xFFF#define QAM_DQ_TAP_IM_EL13_TAP__PRE 0 x2#define QAM_DQ_TAP_RE_EL14__A 0 x144003C#define QAM_DQ_TAP_RE_EL14__W 12 #define QAM_DQ_TAP_RE_EL14__M 0 xFFF#define QAM_DQ_TAP_RE_EL14__PRE 0 x2#define QAM_DQ_TAP_RE_EL14_TAP__B 0 #define QAM_DQ_TAP_RE_EL14_TAP__W 12 #define QAM_DQ_TAP_RE_EL14_TAP__M 0 xFFF#define QAM_DQ_TAP_RE_EL14_TAP__PRE 0 x2#define QAM_DQ_TAP_IM_EL14__A 0 x144003D#define QAM_DQ_TAP_IM_EL14__W 12 #define QAM_DQ_TAP_IM_EL14__M 0 xFFF#define QAM_DQ_TAP_IM_EL14__PRE 0 x2#define QAM_DQ_TAP_IM_EL14_TAP__B 0 #define QAM_DQ_TAP_IM_EL14_TAP__W 12 #define QAM_DQ_TAP_IM_EL14_TAP__M 0 xFFF#define QAM_DQ_TAP_IM_EL14_TAP__PRE 0 x2#define QAM_DQ_TAP_RE_EL15__A 0 x144003E#define QAM_DQ_TAP_RE_EL15__W 12 #define QAM_DQ_TAP_RE_EL15__M 0 xFFF#define QAM_DQ_TAP_RE_EL15__PRE 0 x2#define QAM_DQ_TAP_RE_EL15_TAP__B 0 #define QAM_DQ_TAP_RE_EL15_TAP__W 12 #define QAM_DQ_TAP_RE_EL15_TAP__M 0 xFFF#define QAM_DQ_TAP_RE_EL15_TAP__PRE 0 x2#define QAM_DQ_TAP_IM_EL15__A 0 x144003F#define QAM_DQ_TAP_IM_EL15__W 12 #define QAM_DQ_TAP_IM_EL15__M 0 xFFF#define QAM_DQ_TAP_IM_EL15__PRE 0 x2#define QAM_DQ_TAP_IM_EL15_TAP__B 0 #define QAM_DQ_TAP_IM_EL15_TAP__W 12 #define QAM_DQ_TAP_IM_EL15_TAP__M 0 xFFF#define QAM_DQ_TAP_IM_EL15_TAP__PRE 0 x2#define QAM_DQ_TAP_RE_EL16__A 0 x1440040#define QAM_DQ_TAP_RE_EL16__W 12 #define QAM_DQ_TAP_RE_EL16__M 0 xFFF#define QAM_DQ_TAP_RE_EL16__PRE 0 x2#define QAM_DQ_TAP_RE_EL16_TAP__B 0 #define QAM_DQ_TAP_RE_EL16_TAP__W 12 #define QAM_DQ_TAP_RE_EL16_TAP__M 0 xFFF#define QAM_DQ_TAP_RE_EL16_TAP__PRE 0 x2#define QAM_DQ_TAP_IM_EL16__A 0 x1440041#define QAM_DQ_TAP_IM_EL16__W 12 #define QAM_DQ_TAP_IM_EL16__M 0 xFFF#define QAM_DQ_TAP_IM_EL16__PRE 0 x2#define QAM_DQ_TAP_IM_EL16_TAP__B 0 #define QAM_DQ_TAP_IM_EL16_TAP__W 12 #define QAM_DQ_TAP_IM_EL16_TAP__M 0 xFFF#define QAM_DQ_TAP_IM_EL16_TAP__PRE 0 x2#define QAM_DQ_TAP_RE_EL17__A 0 x1440042#define QAM_DQ_TAP_RE_EL17__W 12 #define QAM_DQ_TAP_RE_EL17__M 0 xFFF#define QAM_DQ_TAP_RE_EL17__PRE 0 x2#define QAM_DQ_TAP_RE_EL17_TAP__B 0 #define QAM_DQ_TAP_RE_EL17_TAP__W 12 #define QAM_DQ_TAP_RE_EL17_TAP__M 0 xFFF#define QAM_DQ_TAP_RE_EL17_TAP__PRE 0 x2#define QAM_DQ_TAP_IM_EL17__A 0 x1440043#define QAM_DQ_TAP_IM_EL17__W 12 #define QAM_DQ_TAP_IM_EL17__M 0 xFFF#define QAM_DQ_TAP_IM_EL17__PRE 0 x2#define QAM_DQ_TAP_IM_EL17_TAP__B 0 #define QAM_DQ_TAP_IM_EL17_TAP__W 12 #define QAM_DQ_TAP_IM_EL17_TAP__M 0 xFFF#define QAM_DQ_TAP_IM_EL17_TAP__PRE 0 x2#define QAM_DQ_TAP_RE_EL18__A 0 x1440044#define QAM_DQ_TAP_RE_EL18__W 12 #define QAM_DQ_TAP_RE_EL18__M 0 xFFF#define QAM_DQ_TAP_RE_EL18__PRE 0 x2#define QAM_DQ_TAP_RE_EL18_TAP__B 0 #define QAM_DQ_TAP_RE_EL18_TAP__W 12 #define QAM_DQ_TAP_RE_EL18_TAP__M 0 xFFF#define QAM_DQ_TAP_RE_EL18_TAP__PRE 0 x2#define QAM_DQ_TAP_IM_EL18__A 0 x1440045#define QAM_DQ_TAP_IM_EL18__W 12 #define QAM_DQ_TAP_IM_EL18__M 0 xFFF#define QAM_DQ_TAP_IM_EL18__PRE 0 x2#define QAM_DQ_TAP_IM_EL18_TAP__B 0 #define QAM_DQ_TAP_IM_EL18_TAP__W 12 #define QAM_DQ_TAP_IM_EL18_TAP__M 0 xFFF#define QAM_DQ_TAP_IM_EL18_TAP__PRE 0 x2#define QAM_DQ_TAP_RE_EL19__A 0 x1440046#define QAM_DQ_TAP_RE_EL19__W 12 #define QAM_DQ_TAP_RE_EL19__M 0 xFFF#define QAM_DQ_TAP_RE_EL19__PRE 0 x2#define QAM_DQ_TAP_RE_EL19_TAP__B 0 #define QAM_DQ_TAP_RE_EL19_TAP__W 12 #define QAM_DQ_TAP_RE_EL19_TAP__M 0 xFFF#define QAM_DQ_TAP_RE_EL19_TAP__PRE 0 x2#define QAM_DQ_TAP_IM_EL19__A 0 x1440047#define QAM_DQ_TAP_IM_EL19__W 12 #define QAM_DQ_TAP_IM_EL19__M 0 xFFF#define QAM_DQ_TAP_IM_EL19__PRE 0 x2#define QAM_DQ_TAP_IM_EL19_TAP__B 0 #define QAM_DQ_TAP_IM_EL19_TAP__W 12 #define QAM_DQ_TAP_IM_EL19_TAP__M 0 xFFF#define QAM_DQ_TAP_IM_EL19_TAP__PRE 0 x2#define QAM_DQ_TAP_RE_EL20__A 0 x1440048#define QAM_DQ_TAP_RE_EL20__W 12 #define QAM_DQ_TAP_RE_EL20__M 0 xFFF#define QAM_DQ_TAP_RE_EL20__PRE 0 x2#define QAM_DQ_TAP_RE_EL20_TAP__B 0 #define QAM_DQ_TAP_RE_EL20_TAP__W 12 #define QAM_DQ_TAP_RE_EL20_TAP__M 0 xFFF#define QAM_DQ_TAP_RE_EL20_TAP__PRE 0 x2#define QAM_DQ_TAP_IM_EL20__A 0 x1440049#define QAM_DQ_TAP_IM_EL20__W 12 #define QAM_DQ_TAP_IM_EL20__M 0 xFFF#define QAM_DQ_TAP_IM_EL20__PRE 0 x2#define QAM_DQ_TAP_IM_EL20_TAP__B 0 #define QAM_DQ_TAP_IM_EL20_TAP__W 12 #define QAM_DQ_TAP_IM_EL20_TAP__M 0 xFFF#define QAM_DQ_TAP_IM_EL20_TAP__PRE 0 x2#define QAM_DQ_TAP_RE_EL21__A 0 x144004A#define QAM_DQ_TAP_RE_EL21__W 12 #define QAM_DQ_TAP_RE_EL21__M 0 xFFF#define QAM_DQ_TAP_RE_EL21__PRE 0 x2#define QAM_DQ_TAP_RE_EL21_TAP__B 0 #define QAM_DQ_TAP_RE_EL21_TAP__W 12 #define QAM_DQ_TAP_RE_EL21_TAP__M 0 xFFF#define QAM_DQ_TAP_RE_EL21_TAP__PRE 0 x2#define QAM_DQ_TAP_IM_EL21__A 0 x144004B#define QAM_DQ_TAP_IM_EL21__W 12 #define QAM_DQ_TAP_IM_EL21__M 0 xFFF#define QAM_DQ_TAP_IM_EL21__PRE 0 x2#define QAM_DQ_TAP_IM_EL21_TAP__B 0 #define QAM_DQ_TAP_IM_EL21_TAP__W 12 #define QAM_DQ_TAP_IM_EL21_TAP__M 0 xFFF#define QAM_DQ_TAP_IM_EL21_TAP__PRE 0 x2#define QAM_DQ_TAP_RE_EL22__A 0 x144004C#define QAM_DQ_TAP_RE_EL22__W 12 #define QAM_DQ_TAP_RE_EL22__M 0 xFFF#define QAM_DQ_TAP_RE_EL22__PRE 0 x2#define QAM_DQ_TAP_RE_EL22_TAP__B 0 #define QAM_DQ_TAP_RE_EL22_TAP__W 12 #define QAM_DQ_TAP_RE_EL22_TAP__M 0 xFFF#define QAM_DQ_TAP_RE_EL22_TAP__PRE 0 x2#define QAM_DQ_TAP_IM_EL22__A 0 x144004D#define QAM_DQ_TAP_IM_EL22__W 12 #define QAM_DQ_TAP_IM_EL22__M 0 xFFF#define QAM_DQ_TAP_IM_EL22__PRE 0 x2#define QAM_DQ_TAP_IM_EL22_TAP__B 0 #define QAM_DQ_TAP_IM_EL22_TAP__W 12 #define QAM_DQ_TAP_IM_EL22_TAP__M 0 xFFF#define QAM_DQ_TAP_IM_EL22_TAP__PRE 0 x2#define QAM_DQ_TAP_RE_EL23__A 0 x144004E#define QAM_DQ_TAP_RE_EL23__W 12 #define QAM_DQ_TAP_RE_EL23__M 0 xFFF#define QAM_DQ_TAP_RE_EL23__PRE 0 x2#define QAM_DQ_TAP_RE_EL23_TAP__B 0 #define QAM_DQ_TAP_RE_EL23_TAP__W 12 #define QAM_DQ_TAP_RE_EL23_TAP__M 0 xFFF#define QAM_DQ_TAP_RE_EL23_TAP__PRE 0 x2#define QAM_DQ_TAP_IM_EL23__A 0 x144004F#define QAM_DQ_TAP_IM_EL23__W 12 #define QAM_DQ_TAP_IM_EL23__M 0 xFFF#define QAM_DQ_TAP_IM_EL23__PRE 0 x2#define QAM_DQ_TAP_IM_EL23_TAP__B 0 #define QAM_DQ_TAP_IM_EL23_TAP__W 12 #define QAM_DQ_TAP_IM_EL23_TAP__M 0 xFFF#define QAM_DQ_TAP_IM_EL23_TAP__PRE 0 x2#define QAM_DQ_TAP_RE_EL24__A 0 x1440050#define QAM_DQ_TAP_RE_EL24__W 12 #define QAM_DQ_TAP_RE_EL24__M 0 xFFF#define QAM_DQ_TAP_RE_EL24__PRE 0 x2#define QAM_DQ_TAP_RE_EL24_TAP__B 0 #define QAM_DQ_TAP_RE_EL24_TAP__W 12 #define QAM_DQ_TAP_RE_EL24_TAP__M 0 xFFF#define QAM_DQ_TAP_RE_EL24_TAP__PRE 0 x2#define QAM_DQ_TAP_IM_EL24__A 0 x1440051#define QAM_DQ_TAP_IM_EL24__W 12 #define QAM_DQ_TAP_IM_EL24__M 0 xFFF#define QAM_DQ_TAP_IM_EL24__PRE 0 x2#define QAM_DQ_TAP_IM_EL24_TAP__B 0 #define QAM_DQ_TAP_IM_EL24_TAP__W 12 #define QAM_DQ_TAP_IM_EL24_TAP__M 0 xFFF#define QAM_DQ_TAP_IM_EL24_TAP__PRE 0 x2#define QAM_DQ_TAP_RE_EL25__A 0 x1440052#define QAM_DQ_TAP_RE_EL25__W 12 #define QAM_DQ_TAP_RE_EL25__M 0 xFFF#define QAM_DQ_TAP_RE_EL25__PRE 0 x2#define QAM_DQ_TAP_RE_EL25_TAP__B 0 #define QAM_DQ_TAP_RE_EL25_TAP__W 12 #define QAM_DQ_TAP_RE_EL25_TAP__M 0 xFFF#define QAM_DQ_TAP_RE_EL25_TAP__PRE 0 x2#define QAM_DQ_TAP_IM_EL25__A 0 x1440053#define QAM_DQ_TAP_IM_EL25__W 12 #define QAM_DQ_TAP_IM_EL25__M 0 xFFF#define QAM_DQ_TAP_IM_EL25__PRE 0 x2#define QAM_DQ_TAP_IM_EL25_TAP__B 0 #define QAM_DQ_TAP_IM_EL25_TAP__W 12 #define QAM_DQ_TAP_IM_EL25_TAP__M 0 xFFF#define QAM_DQ_TAP_IM_EL25_TAP__PRE 0 x2#define QAM_DQ_TAP_RE_EL26__A 0 x1440054#define QAM_DQ_TAP_RE_EL26__W 12 #define QAM_DQ_TAP_RE_EL26__M 0 xFFF#define QAM_DQ_TAP_RE_EL26__PRE 0 x2#define QAM_DQ_TAP_RE_EL26_TAP__B 0 #define QAM_DQ_TAP_RE_EL26_TAP__W 12 #define QAM_DQ_TAP_RE_EL26_TAP__M 0 xFFF#define QAM_DQ_TAP_RE_EL26_TAP__PRE 0 x2#define QAM_DQ_TAP_IM_EL26__A 0 x1440055#define QAM_DQ_TAP_IM_EL26__W 12 #define QAM_DQ_TAP_IM_EL26__M 0 xFFF#define QAM_DQ_TAP_IM_EL26__PRE 0 x2#define QAM_DQ_TAP_IM_EL26_TAP__B 0 #define QAM_DQ_TAP_IM_EL26_TAP__W 12 #define QAM_DQ_TAP_IM_EL26_TAP__M 0 xFFF#define QAM_DQ_TAP_IM_EL26_TAP__PRE 0 x2#define QAM_DQ_TAP_RE_EL27__A 0 x1440056#define QAM_DQ_TAP_RE_EL27__W 12 #define QAM_DQ_TAP_RE_EL27__M 0 xFFF#define QAM_DQ_TAP_RE_EL27__PRE 0 x2#define QAM_DQ_TAP_RE_EL27_TAP__B 0 #define QAM_DQ_TAP_RE_EL27_TAP__W 12 #define QAM_DQ_TAP_RE_EL27_TAP__M 0 xFFF#define QAM_DQ_TAP_RE_EL27_TAP__PRE 0 x2#define QAM_DQ_TAP_IM_EL27__A 0 x1440057#define QAM_DQ_TAP_IM_EL27__W 12 #define QAM_DQ_TAP_IM_EL27__M 0 xFFF#define QAM_DQ_TAP_IM_EL27__PRE 0 x2#define QAM_DQ_TAP_IM_EL27_TAP__B 0 #define QAM_DQ_TAP_IM_EL27_TAP__W 12 #define QAM_DQ_TAP_IM_EL27_TAP__M 0 xFFF#define QAM_DQ_TAP_IM_EL27_TAP__PRE 0 x2#define QAM_LC_COMM_EXEC__A 0 x1450000#define QAM_LC_COMM_EXEC__W 2 #define QAM_LC_COMM_EXEC__M 0 x3#define QAM_LC_COMM_EXEC__PRE 0 x0#define QAM_LC_COMM_EXEC_STOP 0 x0#define QAM_LC_COMM_EXEC_ACTIVE 0 x1#define QAM_LC_COMM_EXEC_HOLD 0 x2#define QAM_LC_COMM_MB__A 0 x1450002#define QAM_LC_COMM_MB__W 2 #define QAM_LC_COMM_MB__M 0 x3#define QAM_LC_COMM_MB__PRE 0 x0#define QAM_LC_COMM_MB_CTL__B 0 #define QAM_LC_COMM_MB_CTL__W 1 #define QAM_LC_COMM_MB_CTL__M 0 x1#define QAM_LC_COMM_MB_CTL__PRE 0 x0#define QAM_LC_COMM_MB_CTL_OFF 0 x0#define QAM_LC_COMM_MB_CTL_ON 0 x1#define QAM_LC_COMM_MB_OBS__B 1 #define QAM_LC_COMM_MB_OBS__W 1 #define QAM_LC_COMM_MB_OBS__M 0 x2#define QAM_LC_COMM_MB_OBS__PRE 0 x0#define QAM_LC_COMM_MB_OBS_OFF 0 x0#define QAM_LC_COMM_MB_OBS_ON 0 x2#define QAM_LC_COMM_INT_REQ__A 0 x1450003#define QAM_LC_COMM_INT_REQ__W 1 #define QAM_LC_COMM_INT_REQ__M 0 x1#define QAM_LC_COMM_INT_REQ__PRE 0 x0#define QAM_LC_COMM_INT_STA__A 0 x1450005#define QAM_LC_COMM_INT_STA__W 3 #define QAM_LC_COMM_INT_STA__M 0 x7#define QAM_LC_COMM_INT_STA__PRE 0 x0#define QAM_LC_COMM_INT_STA_READY__B 0 #define QAM_LC_COMM_INT_STA_READY__W 1 #define QAM_LC_COMM_INT_STA_READY__M 0 x1#define QAM_LC_COMM_INT_STA_READY__PRE 0 x0#define QAM_LC_COMM_INT_STA_OVERFLOW__B 1 #define QAM_LC_COMM_INT_STA_OVERFLOW__W 1 #define QAM_LC_COMM_INT_STA_OVERFLOW__M 0 x2#define QAM_LC_COMM_INT_STA_OVERFLOW__PRE 0 x0#define QAM_LC_COMM_INT_STA_FREQ_WRAP__B 2 #define QAM_LC_COMM_INT_STA_FREQ_WRAP__W 1 #define QAM_LC_COMM_INT_STA_FREQ_WRAP__M 0 x4#define QAM_LC_COMM_INT_STA_FREQ_WRAP__PRE 0 x0#define QAM_LC_COMM_INT_MSK__A 0 x1450006#define QAM_LC_COMM_INT_MSK__W 3 #define QAM_LC_COMM_INT_MSK__M 0 x7#define QAM_LC_COMM_INT_MSK__PRE 0 x0#define QAM_LC_COMM_INT_MSK_READY__B 0 #define QAM_LC_COMM_INT_MSK_READY__W 1 #define QAM_LC_COMM_INT_MSK_READY__M 0 x1#define QAM_LC_COMM_INT_MSK_READY__PRE 0 x0#define QAM_LC_COMM_INT_MSK_OVERFLOW__B 1 #define QAM_LC_COMM_INT_MSK_OVERFLOW__W 1 #define QAM_LC_COMM_INT_MSK_OVERFLOW__M 0 x2#define QAM_LC_COMM_INT_MSK_OVERFLOW__PRE 0 x0#define QAM_LC_COMM_INT_MSK_FREQ_WRAP__B 2 #define QAM_LC_COMM_INT_MSK_FREQ_WRAP__W 1 #define QAM_LC_COMM_INT_MSK_FREQ_WRAP__M 0 x4#define QAM_LC_COMM_INT_MSK_FREQ_WRAP__PRE 0 x0#define QAM_LC_COMM_INT_STM__A 0 x1450007#define QAM_LC_COMM_INT_STM__W 3 #define QAM_LC_COMM_INT_STM__M 0 x7#define QAM_LC_COMM_INT_STM__PRE 0 x0#define QAM_LC_COMM_INT_STM_READY__B 0 #define QAM_LC_COMM_INT_STM_READY__W 1 #define QAM_LC_COMM_INT_STM_READY__M 0 x1#define QAM_LC_COMM_INT_STM_READY__PRE 0 x0#define QAM_LC_COMM_INT_STM_OVERFLOW__B 1 #define QAM_LC_COMM_INT_STM_OVERFLOW__W 1 #define QAM_LC_COMM_INT_STM_OVERFLOW__M 0 x2#define QAM_LC_COMM_INT_STM_OVERFLOW__PRE 0 x0#define QAM_LC_COMM_INT_STM_FREQ_WRAP__B 2 #define QAM_LC_COMM_INT_STM_FREQ_WRAP__W 1 #define QAM_LC_COMM_INT_STM_FREQ_WRAP__M 0 x4#define QAM_LC_COMM_INT_STM_FREQ_WRAP__PRE 0 x0#define QAM_LC_MODE__A 0 x1450010#define QAM_LC_MODE__W 3 #define QAM_LC_MODE__M 0 x7#define QAM_LC_MODE__PRE 0 x7#define QAM_LC_MODE_ENABLE_A__B 0 #define QAM_LC_MODE_ENABLE_A__W 1 #define QAM_LC_MODE_ENABLE_A__M 0 x1#define QAM_LC_MODE_ENABLE_A__PRE 0 x1#define QAM_LC_MODE_ENABLE_F__B 1 #define QAM_LC_MODE_ENABLE_F__W 1 #define QAM_LC_MODE_ENABLE_F__M 0 x2#define QAM_LC_MODE_ENABLE_F__PRE 0 x2#define QAM_LC_MODE_ENABLE_R__B 2 #define QAM_LC_MODE_ENABLE_R__W 1 #define QAM_LC_MODE_ENABLE_R__M 0 x4#define QAM_LC_MODE_ENABLE_R__PRE 0 x4#define QAM_LC_CA__A 0 x1450011#define QAM_LC_CA__W 6 #define QAM_LC_CA__M 0 x3F#define QAM_LC_CA__PRE 0 x28#define QAM_LC_CA_COEF__B 0 #define QAM_LC_CA_COEF__W 6 #define QAM_LC_CA_COEF__M 0 x3F#define QAM_LC_CA_COEF__PRE 0 x28#define QAM_LC_CF__A 0 x1450012#define QAM_LC_CF__W 8 #define QAM_LC_CF__M 0 xFF#define QAM_LC_CF__PRE 0 x8C#define QAM_LC_CF_COEF__B 0 #define QAM_LC_CF_COEF__W 8 #define QAM_LC_CF_COEF__M 0 xFF#define QAM_LC_CF_COEF__PRE 0 x8C#define QAM_LC_CF1__A 0 x1450013#define QAM_LC_CF1__W 8 #define QAM_LC_CF1__M 0 xFF#define QAM_LC_CF1__PRE 0 x1E#define QAM_LC_CF1_COEF__B 0 #define QAM_LC_CF1_COEF__W 8 #define QAM_LC_CF1_COEF__M 0 xFF#define QAM_LC_CF1_COEF__PRE 0 x1E#define QAM_LC_CP__A 0 x1450014#define QAM_LC_CP__W 8 #define QAM_LC_CP__M 0 xFF#define QAM_LC_CP__PRE 0 x78#define QAM_LC_CP_COEF__B 0 #define QAM_LC_CP_COEF__W 8 #define QAM_LC_CP_COEF__M 0 xFF#define QAM_LC_CP_COEF__PRE 0 x78#define QAM_LC_CI__A 0 x1450015#define QAM_LC_CI__W 8 #define QAM_LC_CI__M 0 xFF#define QAM_LC_CI__PRE 0 x46#define QAM_LC_CI_COEF__B 0 #define QAM_LC_CI_COEF__W 8 #define QAM_LC_CI_COEF__M 0 xFF#define QAM_LC_CI_COEF__PRE 0 x46#define QAM_LC_EP__A 0 x1450016#define QAM_LC_EP__W 6 #define QAM_LC_EP__M 0 x3F#define QAM_LC_EP__PRE 0 x0#define QAM_LC_EP_COEF__B 0 #define QAM_LC_EP_COEF__W 6 #define QAM_LC_EP_COEF__M 0 x3F#define QAM_LC_EP_COEF__PRE 0 x0#define QAM_LC_EI__A 0 x1450017#define QAM_LC_EI__W 6 #define QAM_LC_EI__M 0 x3F#define QAM_LC_EI__PRE 0 x0#define QAM_LC_EI_COEF__B 0 #define QAM_LC_EI_COEF__W 6 #define QAM_LC_EI_COEF__M 0 x3F#define QAM_LC_EI_COEF__PRE 0 x0#define QAM_LC_QUAL_TAB0__A 0 x1450018#define QAM_LC_QUAL_TAB0__W 5 #define QAM_LC_QUAL_TAB0__M 0 x1F#define QAM_LC_QUAL_TAB0__PRE 0 x1#define QAM_LC_QUAL_TAB0_VALUE__B 0 #define QAM_LC_QUAL_TAB0_VALUE__W 5 #define QAM_LC_QUAL_TAB0_VALUE__M 0 x1F#define QAM_LC_QUAL_TAB0_VALUE__PRE 0 x1#define QAM_LC_QUAL_TAB1__A 0 x1450019#define QAM_LC_QUAL_TAB1__W 5 #define QAM_LC_QUAL_TAB1__M 0 x1F#define QAM_LC_QUAL_TAB1__PRE 0 x1#define QAM_LC_QUAL_TAB1_VALUE__B 0 #define QAM_LC_QUAL_TAB1_VALUE__W 5 #define QAM_LC_QUAL_TAB1_VALUE__M 0 x1F#define QAM_LC_QUAL_TAB1_VALUE__PRE 0 x1#define QAM_LC_QUAL_TAB2__A 0 x145001A#define QAM_LC_QUAL_TAB2__W 5 #define QAM_LC_QUAL_TAB2__M 0 x1F#define QAM_LC_QUAL_TAB2__PRE 0 x1#define QAM_LC_QUAL_TAB2_VALUE__B 0 #define QAM_LC_QUAL_TAB2_VALUE__W 5 #define QAM_LC_QUAL_TAB2_VALUE__M 0 x1F#define QAM_LC_QUAL_TAB2_VALUE__PRE 0 x1#define QAM_LC_QUAL_TAB3__A 0 x145001B#define QAM_LC_QUAL_TAB3__W 5 #define QAM_LC_QUAL_TAB3__M 0 x1F#define QAM_LC_QUAL_TAB3__PRE 0 x1#define QAM_LC_QUAL_TAB3_VALUE__B 0 #define QAM_LC_QUAL_TAB3_VALUE__W 5 #define QAM_LC_QUAL_TAB3_VALUE__M 0 x1F#define QAM_LC_QUAL_TAB3_VALUE__PRE 0 x1#define QAM_LC_QUAL_TAB4__A 0 x145001C#define QAM_LC_QUAL_TAB4__W 5 #define QAM_LC_QUAL_TAB4__M 0 x1F#define QAM_LC_QUAL_TAB4__PRE 0 x1#define QAM_LC_QUAL_TAB4_VALUE__B 0 #define QAM_LC_QUAL_TAB4_VALUE__W 5 #define QAM_LC_QUAL_TAB4_VALUE__M 0 x1F#define QAM_LC_QUAL_TAB4_VALUE__PRE 0 x1#define QAM_LC_QUAL_TAB5__A 0 x145001D#define QAM_LC_QUAL_TAB5__W 5 #define QAM_LC_QUAL_TAB5__M 0 x1F#define QAM_LC_QUAL_TAB5__PRE 0 x1#define QAM_LC_QUAL_TAB5_VALUE__B 0 #define QAM_LC_QUAL_TAB5_VALUE__W 5 #define QAM_LC_QUAL_TAB5_VALUE__M 0 x1F#define QAM_LC_QUAL_TAB5_VALUE__PRE 0 x1#define QAM_LC_QUAL_TAB6__A 0 x145001E#define QAM_LC_QUAL_TAB6__W 5 #define QAM_LC_QUAL_TAB6__M 0 x1F#define QAM_LC_QUAL_TAB6__PRE 0 x1#define QAM_LC_QUAL_TAB6_VALUE__B 0 #define QAM_LC_QUAL_TAB6_VALUE__W 5 #define QAM_LC_QUAL_TAB6_VALUE__M 0 x1F#define QAM_LC_QUAL_TAB6_VALUE__PRE 0 x1#define QAM_LC_QUAL_TAB8__A 0 x145001F#define QAM_LC_QUAL_TAB8__W 5 #define QAM_LC_QUAL_TAB8__M 0 x1F#define QAM_LC_QUAL_TAB8__PRE 0 x1#define QAM_LC_QUAL_TAB8_VALUE__B 0 #define QAM_LC_QUAL_TAB8_VALUE__W 5 #define QAM_LC_QUAL_TAB8_VALUE__M 0 x1F#define QAM_LC_QUAL_TAB8_VALUE__PRE 0 x1#define QAM_LC_QUAL_TAB9__A 0 x1450020#define QAM_LC_QUAL_TAB9__W 5 #define QAM_LC_QUAL_TAB9__M 0 x1F#define QAM_LC_QUAL_TAB9__PRE 0 x1#define QAM_LC_QUAL_TAB9_VALUE__B 0 #define QAM_LC_QUAL_TAB9_VALUE__W 5 #define QAM_LC_QUAL_TAB9_VALUE__M 0 x1F#define QAM_LC_QUAL_TAB9_VALUE__PRE 0 x1#define QAM_LC_QUAL_TAB10__A 0 x1450021#define QAM_LC_QUAL_TAB10__W 5 #define QAM_LC_QUAL_TAB10__M 0 x1F#define QAM_LC_QUAL_TAB10__PRE 0 x1#define QAM_LC_QUAL_TAB10_VALUE__B 0 #define QAM_LC_QUAL_TAB10_VALUE__W 5 #define QAM_LC_QUAL_TAB10_VALUE__M 0 x1F#define QAM_LC_QUAL_TAB10_VALUE__PRE 0 x1#define QAM_LC_QUAL_TAB12__A 0 x1450022#define QAM_LC_QUAL_TAB12__W 5 #define QAM_LC_QUAL_TAB12__M 0 x1F#define QAM_LC_QUAL_TAB12__PRE 0 x1#define QAM_LC_QUAL_TAB12_VALUE__B 0 #define QAM_LC_QUAL_TAB12_VALUE__W 5 #define QAM_LC_QUAL_TAB12_VALUE__M 0 x1F#define QAM_LC_QUAL_TAB12_VALUE__PRE 0 x1#define QAM_LC_QUAL_TAB15__A 0 x1450023#define QAM_LC_QUAL_TAB15__W 5 #define QAM_LC_QUAL_TAB15__M 0 x1F#define QAM_LC_QUAL_TAB15__PRE 0 x1#define QAM_LC_QUAL_TAB15_VALUE__B 0 #define QAM_LC_QUAL_TAB15_VALUE__W 5 #define QAM_LC_QUAL_TAB15_VALUE__M 0 x1F#define QAM_LC_QUAL_TAB15_VALUE__PRE 0 x1#define QAM_LC_QUAL_TAB16__A 0 x1450024#define QAM_LC_QUAL_TAB16__W 5 #define QAM_LC_QUAL_TAB16__M 0 x1F#define QAM_LC_QUAL_TAB16__PRE 0 x1#define QAM_LC_QUAL_TAB16_VALUE__B 0 #define QAM_LC_QUAL_TAB16_VALUE__W 5 #define QAM_LC_QUAL_TAB16_VALUE__M 0 x1F#define QAM_LC_QUAL_TAB16_VALUE__PRE 0 x1#define QAM_LC_QUAL_TAB20__A 0 x1450025#define QAM_LC_QUAL_TAB20__W 5 #define QAM_LC_QUAL_TAB20__M 0 x1F#define QAM_LC_QUAL_TAB20__PRE 0 x1#define QAM_LC_QUAL_TAB20_VALUE__B 0 #define QAM_LC_QUAL_TAB20_VALUE__W 5 #define QAM_LC_QUAL_TAB20_VALUE__M 0 x1F#define QAM_LC_QUAL_TAB20_VALUE__PRE 0 x1#define QAM_LC_QUAL_TAB25__A 0 x1450026#define QAM_LC_QUAL_TAB25__W 5 #define QAM_LC_QUAL_TAB25__M 0 x1F#define QAM_LC_QUAL_TAB25__PRE 0 x1#define QAM_LC_QUAL_TAB25_VALUE__B 0 #define QAM_LC_QUAL_TAB25_VALUE__W 5 #define QAM_LC_QUAL_TAB25_VALUE__M 0 x1F#define QAM_LC_QUAL_TAB25_VALUE__PRE 0 x1#define QAM_LC_EQ_TIMING__A 0 x1450027#define QAM_LC_EQ_TIMING__W 10 #define QAM_LC_EQ_TIMING__M 0 x3FF#define QAM_LC_EQ_TIMING__PRE 0 x0#define QAM_LC_EQ_TIMING_OFFS__B 0 #define QAM_LC_EQ_TIMING_OFFS__W 10 #define QAM_LC_EQ_TIMING_OFFS__M 0 x3FF#define QAM_LC_EQ_TIMING_OFFS__PRE 0 x0#define QAM_LC_LPF_FACTORP__A 0 x1450028#define QAM_LC_LPF_FACTORP__W 3 #define QAM_LC_LPF_FACTORP__M 0 x7#define QAM_LC_LPF_FACTORP__PRE 0 x3#define QAM_LC_LPF_FACTORP_FACTOR__B 0 #define QAM_LC_LPF_FACTORP_FACTOR__W 3 #define QAM_LC_LPF_FACTORP_FACTOR__M 0 x7#define QAM_LC_LPF_FACTORP_FACTOR__PRE 0 x3#define QAM_LC_LPF_FACTORI__A 0 x1450029#define QAM_LC_LPF_FACTORI__W 3 #define QAM_LC_LPF_FACTORI__M 0 x7#define QAM_LC_LPF_FACTORI__PRE 0 x3#define QAM_LC_LPF_FACTORI_FACTOR__B 0 #define QAM_LC_LPF_FACTORI_FACTOR__W 3 #define QAM_LC_LPF_FACTORI_FACTOR__M 0 x7#define QAM_LC_LPF_FACTORI_FACTOR__PRE 0 x3#define QAM_LC_RATE_LIMIT__A 0 x145002A#define QAM_LC_RATE_LIMIT__W 2 #define QAM_LC_RATE_LIMIT__M 0 x3#define QAM_LC_RATE_LIMIT__PRE 0 x3#define QAM_LC_RATE_LIMIT_LIMIT__B 0 #define QAM_LC_RATE_LIMIT_LIMIT__W 2 #define QAM_LC_RATE_LIMIT_LIMIT__M 0 x3#define QAM_LC_RATE_LIMIT_LIMIT__PRE 0 x3#define QAM_LC_SYMBOL_FREQ__A 0 x145002B#define QAM_LC_SYMBOL_FREQ__W 10 #define QAM_LC_SYMBOL_FREQ__M 0 x3FF#define QAM_LC_SYMBOL_FREQ__PRE 0 x199#define QAM_LC_SYMBOL_FREQ_FREQ__B 0 #define QAM_LC_SYMBOL_FREQ_FREQ__W 10 #define QAM_LC_SYMBOL_FREQ_FREQ__M 0 x3FF#define QAM_LC_SYMBOL_FREQ_FREQ__PRE 0 x199#define QAM_LC_SYMBOL_FREQ_FREQ_QAM_B_64 0 x197#define QAM_LC_SYMBOL_FREQ_FREQ_QAM_B_256 0 x1B2#define QAM_LC_MTA_LENGTH__A 0 x145002C#define QAM_LC_MTA_LENGTH__W 2 #define QAM_LC_MTA_LENGTH__M 0 x3#define QAM_LC_MTA_LENGTH__PRE 0 x2#define QAM_LC_MTA_LENGTH_LENGTH__B 0 #define QAM_LC_MTA_LENGTH_LENGTH__W 2 #define QAM_LC_MTA_LENGTH_LENGTH__M 0 x3#define QAM_LC_MTA_LENGTH_LENGTH__PRE 0 x2#define QAM_LC_AMP_ACCU__A 0 x145002D#define QAM_LC_AMP_ACCU__W 14 #define QAM_LC_AMP_ACCU__M 0 x3FFF#define QAM_LC_AMP_ACCU__PRE 0 x600#define QAM_LC_AMP_ACCU_ACCU__B 0 #define QAM_LC_AMP_ACCU_ACCU__W 14 #define QAM_LC_AMP_ACCU_ACCU__M 0 x3FFF#define QAM_LC_AMP_ACCU_ACCU__PRE 0 x600#define QAM_LC_FREQ_ACCU__A 0 x145002E#define QAM_LC_FREQ_ACCU__W 10 #define QAM_LC_FREQ_ACCU__M 0 x3FF#define QAM_LC_FREQ_ACCU__PRE 0 x0#define QAM_LC_FREQ_ACCU_ACCU__B 0 #define QAM_LC_FREQ_ACCU_ACCU__W 10 #define QAM_LC_FREQ_ACCU_ACCU__M 0 x3FF#define QAM_LC_FREQ_ACCU_ACCU__PRE 0 x0#define QAM_LC_RATE_ACCU__A 0 x145002F#define QAM_LC_RATE_ACCU__W 10 #define QAM_LC_RATE_ACCU__M 0 x3FF#define QAM_LC_RATE_ACCU__PRE 0 x0#define QAM_LC_RATE_ACCU_ACCU__B 0 #define QAM_LC_RATE_ACCU_ACCU__W 10 #define QAM_LC_RATE_ACCU_ACCU__M 0 x3FF#define QAM_LC_RATE_ACCU_ACCU__PRE 0 x0#define QAM_LC_AMPLITUDE__A 0 x1450030#define QAM_LC_AMPLITUDE__W 10 #define QAM_LC_AMPLITUDE__M 0 x3FF#define QAM_LC_AMPLITUDE__PRE 0 x0#define QAM_LC_AMPLITUDE_SIZE__B 0 #define QAM_LC_AMPLITUDE_SIZE__W 10 #define QAM_LC_AMPLITUDE_SIZE__M 0 x3FF#define QAM_LC_AMPLITUDE_SIZE__PRE 0 x0#define QAM_LC_RAD_ERROR__A 0 x1450031#define QAM_LC_RAD_ERROR__W 10 #define QAM_LC_RAD_ERROR__M 0 x3FF#define QAM_LC_RAD_ERROR__PRE 0 x0#define QAM_LC_RAD_ERROR_SIZE__B 0 #define QAM_LC_RAD_ERROR_SIZE__W 10 #define QAM_LC_RAD_ERROR_SIZE__M 0 x3FF#define QAM_LC_RAD_ERROR_SIZE__PRE 0 x0#define QAM_LC_FREQ_OFFS__A 0 x1450032#define QAM_LC_FREQ_OFFS__W 10 #define QAM_LC_FREQ_OFFS__M 0 x3FF#define QAM_LC_FREQ_OFFS__PRE 0 x0#define QAM_LC_FREQ_OFFS_OFFS__B 0 #define QAM_LC_FREQ_OFFS_OFFS__W 10 #define QAM_LC_FREQ_OFFS_OFFS__M 0 x3FF#define QAM_LC_FREQ_OFFS_OFFS__PRE 0 x0#define QAM_LC_PHASE_ERROR__A 0 x1450033#define QAM_LC_PHASE_ERROR__W 10 #define QAM_LC_PHASE_ERROR__M 0 x3FF#define QAM_LC_PHASE_ERROR__PRE 0 x0#define QAM_LC_PHASE_ERROR_SIZE__B 0 #define QAM_LC_PHASE_ERROR_SIZE__W 10 #define QAM_LC_PHASE_ERROR_SIZE__M 0 x3FF#define QAM_LC_PHASE_ERROR_SIZE__PRE 0 x0#define QAM_VD_COMM_EXEC__A 0 x1460000#define QAM_VD_COMM_EXEC__W 2 #define QAM_VD_COMM_EXEC__M 0 x3#define QAM_VD_COMM_EXEC__PRE 0 x0#define QAM_VD_COMM_EXEC_STOP 0 x0#define QAM_VD_COMM_EXEC_ACTIVE 0 x1#define QAM_VD_COMM_EXEC_HOLD 0 x2#define QAM_VD_COMM_MB__A 0 x1460002#define QAM_VD_COMM_MB__W 2 #define QAM_VD_COMM_MB__M 0 x3#define QAM_VD_COMM_MB__PRE 0 x0#define QAM_VD_COMM_MB_CTL__B 0 #define QAM_VD_COMM_MB_CTL__W 1 #define QAM_VD_COMM_MB_CTL__M 0 x1#define QAM_VD_COMM_MB_CTL__PRE 0 x0#define QAM_VD_COMM_MB_CTL_OFF 0 x0#define QAM_VD_COMM_MB_CTL_ON 0 x1#define QAM_VD_COMM_MB_OBS__B 1 #define QAM_VD_COMM_MB_OBS__W 1 #define QAM_VD_COMM_MB_OBS__M 0 x2#define QAM_VD_COMM_MB_OBS__PRE 0 x0#define QAM_VD_COMM_MB_OBS_OFF 0 x0#define QAM_VD_COMM_MB_OBS_ON 0 x2#define QAM_VD_COMM_INT_REQ__A 0 x1460003#define QAM_VD_COMM_INT_REQ__W 1 #define QAM_VD_COMM_INT_REQ__M 0 x1#define QAM_VD_COMM_INT_REQ__PRE 0 x0#define QAM_VD_COMM_INT_STA__A 0 x1460005#define QAM_VD_COMM_INT_STA__W 2 #define QAM_VD_COMM_INT_STA__M 0 x3#define QAM_VD_COMM_INT_STA__PRE 0 x0#define QAM_VD_COMM_INT_STA_LOCK_INT__B 0 #define QAM_VD_COMM_INT_STA_LOCK_INT__W 1 #define QAM_VD_COMM_INT_STA_LOCK_INT__M 0 x1#define QAM_VD_COMM_INT_STA_LOCK_INT__PRE 0 x0#define QAM_VD_COMM_INT_STA_PERIOD_INT__B 1 #define QAM_VD_COMM_INT_STA_PERIOD_INT__W 1 #define QAM_VD_COMM_INT_STA_PERIOD_INT__M 0 x2#define QAM_VD_COMM_INT_STA_PERIOD_INT__PRE 0 x0#define QAM_VD_COMM_INT_MSK__A 0 x1460006#define QAM_VD_COMM_INT_MSK__W 2 #define QAM_VD_COMM_INT_MSK__M 0 x3#define QAM_VD_COMM_INT_MSK__PRE 0 x0#define QAM_VD_COMM_INT_MSK_LOCK_INT__B 0 #define QAM_VD_COMM_INT_MSK_LOCK_INT__W 1 #define QAM_VD_COMM_INT_MSK_LOCK_INT__M 0 x1#define QAM_VD_COMM_INT_MSK_LOCK_INT__PRE 0 x0#define QAM_VD_COMM_INT_MSK_PERIOD_INT__B 1 #define QAM_VD_COMM_INT_MSK_PERIOD_INT__W 1 #define QAM_VD_COMM_INT_MSK_PERIOD_INT__M 0 x2#define QAM_VD_COMM_INT_MSK_PERIOD_INT__PRE 0 x0#define QAM_VD_COMM_INT_STM__A 0 x1460007#define QAM_VD_COMM_INT_STM__W 2 #define QAM_VD_COMM_INT_STM__M 0 x3#define QAM_VD_COMM_INT_STM__PRE 0 x0#define QAM_VD_COMM_INT_STM_LOCK_INT__B 0 #define QAM_VD_COMM_INT_STM_LOCK_INT__W 1 #define QAM_VD_COMM_INT_STM_LOCK_INT__M 0 x1#define QAM_VD_COMM_INT_STM_LOCK_INT__PRE 0 x0#define QAM_VD_COMM_INT_STM_PERIOD_INT__B 1 #define QAM_VD_COMM_INT_STM_PERIOD_INT__W 1 #define QAM_VD_COMM_INT_STM_PERIOD_INT__M 0 x2#define QAM_VD_COMM_INT_STM_PERIOD_INT__PRE 0 x0#define QAM_VD_STATUS__A 0 x1460010#define QAM_VD_STATUS__W 1 #define QAM_VD_STATUS__M 0 x1#define QAM_VD_STATUS__PRE 0 x0#define QAM_VD_STATUS_LOCK__B 0 #define QAM_VD_STATUS_LOCK__W 1 #define QAM_VD_STATUS_LOCK__M 0 x1#define QAM_VD_STATUS_LOCK__PRE 0 x0#define QAM_VD_UNLOCK_CONTROL__A 0 x1460011#define QAM_VD_UNLOCK_CONTROL__W 1 #define QAM_VD_UNLOCK_CONTROL__M 0 x1#define QAM_VD_UNLOCK_CONTROL__PRE 0 x0#define QAM_VD_UNLOCK_CONTROL_UNLOCK_CTRL__B 0 #define QAM_VD_UNLOCK_CONTROL_UNLOCK_CTRL__W 1 #define QAM_VD_UNLOCK_CONTROL_UNLOCK_CTRL__M 0 x1#define QAM_VD_UNLOCK_CONTROL_UNLOCK_CTRL__PRE 0 x0#define QAM_VD_MIN_VOTING_ROUNDS__A 0 x1460012#define QAM_VD_MIN_VOTING_ROUNDS__W 6 #define QAM_VD_MIN_VOTING_ROUNDS__M 0 x3F#define QAM_VD_MIN_VOTING_ROUNDS__PRE 0 x10#define QAM_VD_MIN_VOTING_ROUNDS_ROUNDS__B 0 #define QAM_VD_MIN_VOTING_ROUNDS_ROUNDS__W 6 #define QAM_VD_MIN_VOTING_ROUNDS_ROUNDS__M 0 x3F#define QAM_VD_MIN_VOTING_ROUNDS_ROUNDS__PRE 0 x10#define QAM_VD_MAX_VOTING_ROUNDS__A 0 x1460013#define QAM_VD_MAX_VOTING_ROUNDS__W 6 #define QAM_VD_MAX_VOTING_ROUNDS__M 0 x3F#define QAM_VD_MAX_VOTING_ROUNDS__PRE 0 x10#define QAM_VD_MAX_VOTING_ROUNDS_ROUNDS__B 0 #define QAM_VD_MAX_VOTING_ROUNDS_ROUNDS__W 6 #define QAM_VD_MAX_VOTING_ROUNDS_ROUNDS__M 0 x3F#define QAM_VD_MAX_VOTING_ROUNDS_ROUNDS__PRE 0 x10#define QAM_VD_TRACEBACK_DEPTH__A 0 x1460014#define QAM_VD_TRACEBACK_DEPTH__W 5 #define QAM_VD_TRACEBACK_DEPTH__M 0 x1F#define QAM_VD_TRACEBACK_DEPTH__PRE 0 x10#define QAM_VD_TRACEBACK_DEPTH_LENGTH__B 0 #define QAM_VD_TRACEBACK_DEPTH_LENGTH__W 5 #define QAM_VD_TRACEBACK_DEPTH_LENGTH__M 0 x1F#define QAM_VD_TRACEBACK_DEPTH_LENGTH__PRE 0 x10#define QAM_VD_UNLOCK__A 0 x1460015#define QAM_VD_UNLOCK__W 1 #define QAM_VD_UNLOCK__M 0 x1#define QAM_VD_UNLOCK__PRE 0 x0#define QAM_VD_MEASUREMENT_PERIOD__A 0 x1460016#define QAM_VD_MEASUREMENT_PERIOD__W 16 #define QAM_VD_MEASUREMENT_PERIOD__M 0 xFFFF#define QAM_VD_MEASUREMENT_PERIOD__PRE 0 x8236#define QAM_VD_MEASUREMENT_PERIOD_PERIOD__B 0 #define QAM_VD_MEASUREMENT_PERIOD_PERIOD__W 16 #define QAM_VD_MEASUREMENT_PERIOD_PERIOD__M 0 xFFFF#define QAM_VD_MEASUREMENT_PERIOD_PERIOD__PRE 0 x8236#define QAM_VD_MEASUREMENT_PRESCALE__A 0 x1460017#define QAM_VD_MEASUREMENT_PRESCALE__W 16 #define QAM_VD_MEASUREMENT_PRESCALE__M 0 xFFFF#define QAM_VD_MEASUREMENT_PRESCALE__PRE 0 x4#define QAM_VD_MEASUREMENT_PRESCALE_PRESCALE__B 0 #define QAM_VD_MEASUREMENT_PRESCALE_PRESCALE__W 16 #define QAM_VD_MEASUREMENT_PRESCALE_PRESCALE__M 0 xFFFF#define QAM_VD_MEASUREMENT_PRESCALE_PRESCALE__PRE 0 x4#define QAM_VD_DELTA_PATH_METRIC__A 0 x1460018#define QAM_VD_DELTA_PATH_METRIC__W 16 #define QAM_VD_DELTA_PATH_METRIC__M 0 xFFFF#define QAM_VD_DELTA_PATH_METRIC__PRE 0 xFFFF#define QAM_VD_DELTA_PATH_METRIC_FIXED_MANT__B 0 #define QAM_VD_DELTA_PATH_METRIC_FIXED_MANT__W 12 #define QAM_VD_DELTA_PATH_METRIC_FIXED_MANT__M 0 xFFF#define QAM_VD_DELTA_PATH_METRIC_FIXED_MANT__PRE 0 xFFF#define QAM_VD_DELTA_PATH_METRIC_EXP__B 12 #define QAM_VD_DELTA_PATH_METRIC_EXP__W 4 #define QAM_VD_DELTA_PATH_METRIC_EXP__M 0 xF000#define QAM_VD_DELTA_PATH_METRIC_EXP__PRE 0 xF000#define QAM_VD_NR_QSYM_ERRORS__A 0 x1460019#define QAM_VD_NR_QSYM_ERRORS__W 16 #define QAM_VD_NR_QSYM_ERRORS__M 0 xFFFF#define QAM_VD_NR_QSYM_ERRORS__PRE 0 xFFFF#define QAM_VD_NR_QSYM_ERRORS_FIXED_MANT__B 0 #define QAM_VD_NR_QSYM_ERRORS_FIXED_MANT__W 12 #define QAM_VD_NR_QSYM_ERRORS_FIXED_MANT__M 0 xFFF#define QAM_VD_NR_QSYM_ERRORS_FIXED_MANT__PRE 0 xFFF#define QAM_VD_NR_QSYM_ERRORS_EXP__B 12 #define QAM_VD_NR_QSYM_ERRORS_EXP__W 4 #define QAM_VD_NR_QSYM_ERRORS_EXP__M 0 xF000#define QAM_VD_NR_QSYM_ERRORS_EXP__PRE 0 xF000#define QAM_VD_NR_SYMBOL_ERRORS__A 0 x146001A#define QAM_VD_NR_SYMBOL_ERRORS__W 16 #define QAM_VD_NR_SYMBOL_ERRORS__M 0 xFFFF#define QAM_VD_NR_SYMBOL_ERRORS__PRE 0 xFFFF#define QAM_VD_NR_SYMBOL_ERRORS_FIXED_MANT__B 0 #define QAM_VD_NR_SYMBOL_ERRORS_FIXED_MANT__W 12 #define QAM_VD_NR_SYMBOL_ERRORS_FIXED_MANT__M 0 xFFF#define QAM_VD_NR_SYMBOL_ERRORS_FIXED_MANT__PRE 0 xFFF#define QAM_VD_NR_SYMBOL_ERRORS_EXP__B 12 #define QAM_VD_NR_SYMBOL_ERRORS_EXP__W 4 #define QAM_VD_NR_SYMBOL_ERRORS_EXP__M 0 xF000#define QAM_VD_NR_SYMBOL_ERRORS_EXP__PRE 0 xF000#define QAM_VD_RELOCK_COUNT__A 0 x146001B#define QAM_VD_RELOCK_COUNT__W 16 #define QAM_VD_RELOCK_COUNT__M 0 xFFFF#define QAM_VD_RELOCK_COUNT__PRE 0 x0#define QAM_VD_RELOCK_COUNT_COUNT__B 0 #define QAM_VD_RELOCK_COUNT_COUNT__W 8 #define QAM_VD_RELOCK_COUNT_COUNT__M 0 xFF#define QAM_VD_RELOCK_COUNT_COUNT__PRE 0 x0#define QAM_SY_COMM_EXEC__A 0 x1470000#define QAM_SY_COMM_EXEC__W 2 #define QAM_SY_COMM_EXEC__M 0 x3#define QAM_SY_COMM_EXEC__PRE 0 x0#define QAM_SY_COMM_EXEC_STOP 0 x0#define QAM_SY_COMM_EXEC_ACTIVE 0 x1#define QAM_SY_COMM_EXEC_HOLD 0 x2#define QAM_SY_COMM_MB__A 0 x1470002#define QAM_SY_COMM_MB__W 2 #define QAM_SY_COMM_MB__M 0 x3#define QAM_SY_COMM_MB__PRE 0 x0#define QAM_SY_COMM_MB_CTL__B 0 #define QAM_SY_COMM_MB_CTL__W 1 #define QAM_SY_COMM_MB_CTL__M 0 x1#define QAM_SY_COMM_MB_CTL__PRE 0 x0#define QAM_SY_COMM_MB_CTL_OFF 0 x0#define QAM_SY_COMM_MB_CTL_ON 0 x1#define QAM_SY_COMM_MB_OBS__B 1 #define QAM_SY_COMM_MB_OBS__W 1 #define QAM_SY_COMM_MB_OBS__M 0 x2#define QAM_SY_COMM_MB_OBS__PRE 0 x0#define QAM_SY_COMM_MB_OBS_OFF 0 x0#define QAM_SY_COMM_MB_OBS_ON 0 x2#define QAM_SY_COMM_INT_REQ__A 0 x1470003#define QAM_SY_COMM_INT_REQ__W 1 #define QAM_SY_COMM_INT_REQ__M 0 x1#define QAM_SY_COMM_INT_REQ__PRE 0 x0#define QAM_SY_COMM_INT_STA__A 0 x1470005#define QAM_SY_COMM_INT_STA__W 4 #define QAM_SY_COMM_INT_STA__M 0 xF#define QAM_SY_COMM_INT_STA__PRE 0 x0#define QAM_SY_COMM_INT_STA_LOCK_INT__B 0 #define QAM_SY_COMM_INT_STA_LOCK_INT__W 1 #define QAM_SY_COMM_INT_STA_LOCK_INT__M 0 x1#define QAM_SY_COMM_INT_STA_LOCK_INT__PRE 0 x0#define QAM_SY_COMM_INT_STA_UNLOCK_INT__B 1 #define QAM_SY_COMM_INT_STA_UNLOCK_INT__W 1 #define QAM_SY_COMM_INT_STA_UNLOCK_INT__M 0 x2#define QAM_SY_COMM_INT_STA_UNLOCK_INT__PRE 0 x0#define QAM_SY_COMM_INT_STA_TIMEOUT_INT__B 2 #define QAM_SY_COMM_INT_STA_TIMEOUT_INT__W 1 #define QAM_SY_COMM_INT_STA_TIMEOUT_INT__M 0 x4#define QAM_SY_COMM_INT_STA_TIMEOUT_INT__PRE 0 x0#define QAM_SY_COMM_INT_STA_CTL_WORD_INT__B 3 #define QAM_SY_COMM_INT_STA_CTL_WORD_INT__W 1 #define QAM_SY_COMM_INT_STA_CTL_WORD_INT__M 0 x8#define QAM_SY_COMM_INT_STA_CTL_WORD_INT__PRE 0 x0#define QAM_SY_COMM_INT_MSK__A 0 x1470006#define QAM_SY_COMM_INT_MSK__W 4 #define QAM_SY_COMM_INT_MSK__M 0 xF#define QAM_SY_COMM_INT_MSK__PRE 0 x0#define QAM_SY_COMM_INT_MSK_LOCK_MSK__B 0 #define QAM_SY_COMM_INT_MSK_LOCK_MSK__W 1 #define QAM_SY_COMM_INT_MSK_LOCK_MSK__M 0 x1#define QAM_SY_COMM_INT_MSK_LOCK_MSK__PRE 0 x0#define QAM_SY_COMM_INT_MSK_UNLOCK_MSK__B 1 #define QAM_SY_COMM_INT_MSK_UNLOCK_MSK__W 1 #define QAM_SY_COMM_INT_MSK_UNLOCK_MSK__M 0 x2#define QAM_SY_COMM_INT_MSK_UNLOCK_MSK__PRE 0 x0#define QAM_SY_COMM_INT_MSK_TIMEOUT_MSK__B 2 #define QAM_SY_COMM_INT_MSK_TIMEOUT_MSK__W 1 #define QAM_SY_COMM_INT_MSK_TIMEOUT_MSK__M 0 x4#define QAM_SY_COMM_INT_MSK_TIMEOUT_MSK__PRE 0 x0#define QAM_SY_COMM_INT_MSK_CTL_WORD_MSK__B 3 #define QAM_SY_COMM_INT_MSK_CTL_WORD_MSK__W 1 #define QAM_SY_COMM_INT_MSK_CTL_WORD_MSK__M 0 x8#define QAM_SY_COMM_INT_MSK_CTL_WORD_MSK__PRE 0 x0#define QAM_SY_COMM_INT_STM__A 0 x1470007#define QAM_SY_COMM_INT_STM__W 4 #define QAM_SY_COMM_INT_STM__M 0 xF#define QAM_SY_COMM_INT_STM__PRE 0 x0#define QAM_SY_COMM_INT_STM_LOCK_MSK__B 0 #define QAM_SY_COMM_INT_STM_LOCK_MSK__W 1 #define QAM_SY_COMM_INT_STM_LOCK_MSK__M 0 x1#define QAM_SY_COMM_INT_STM_LOCK_MSK__PRE 0 x0#define QAM_SY_COMM_INT_STM_UNLOCK_MSK__B 1 #define QAM_SY_COMM_INT_STM_UNLOCK_MSK__W 1 #define QAM_SY_COMM_INT_STM_UNLOCK_MSK__M 0 x2#define QAM_SY_COMM_INT_STM_UNLOCK_MSK__PRE 0 x0#define QAM_SY_COMM_INT_STM_TIMEOUT_MSK__B 2 #define QAM_SY_COMM_INT_STM_TIMEOUT_MSK__W 1 #define QAM_SY_COMM_INT_STM_TIMEOUT_MSK__M 0 x4#define QAM_SY_COMM_INT_STM_TIMEOUT_MSK__PRE 0 x0#define QAM_SY_COMM_INT_STM_CTL_WORD_MSK__B 3 #define QAM_SY_COMM_INT_STM_CTL_WORD_MSK__W 1 #define QAM_SY_COMM_INT_STM_CTL_WORD_MSK__M 0 x8#define QAM_SY_COMM_INT_STM_CTL_WORD_MSK__PRE 0 x0#define QAM_SY_STATUS__A 0 x1470010#define QAM_SY_STATUS__W 2 #define QAM_SY_STATUS__M 0 x3#define QAM_SY_STATUS__PRE 0 x0#define QAM_SY_STATUS_SYNC_STATE__B 0 #define QAM_SY_STATUS_SYNC_STATE__W 2 #define QAM_SY_STATUS_SYNC_STATE__M 0 x3#define QAM_SY_STATUS_SYNC_STATE__PRE 0 x0#define QAM_SY_TIMEOUT__A 0 x1470011#define QAM_SY_TIMEOUT__W 16 #define QAM_SY_TIMEOUT__M 0 xFFFF#define QAM_SY_TIMEOUT__PRE 0 x3A98#define QAM_SY_SYNC_LWM__A 0 x1470012#define QAM_SY_SYNC_LWM__W 4 #define QAM_SY_SYNC_LWM__M 0 xF#define QAM_SY_SYNC_LWM__PRE 0 x2#define QAM_SY_SYNC_AWM__A 0 x1470013#define QAM_SY_SYNC_AWM__W 4 #define QAM_SY_SYNC_AWM__M 0 xF#define QAM_SY_SYNC_AWM__PRE 0 x3#define QAM_SY_SYNC_HWM__A 0 x1470014#define QAM_SY_SYNC_HWM__W 4 #define QAM_SY_SYNC_HWM__M 0 xF#define QAM_SY_SYNC_HWM__PRE 0 x5#define QAM_SY_UNLOCK__A 0 x1470015#define QAM_SY_UNLOCK__W 1 #define QAM_SY_UNLOCK__M 0 x1#define QAM_SY_UNLOCK__PRE 0 x0#define QAM_SY_CONTROL_WORD__A 0 x1470016#define QAM_SY_CONTROL_WORD__W 4 #define QAM_SY_CONTROL_WORD__M 0 xF#define QAM_SY_CONTROL_WORD__PRE 0 x0#define QAM_SY_CONTROL_WORD_CTRL_WORD__B 0 #define QAM_SY_CONTROL_WORD_CTRL_WORD__W 4 #define QAM_SY_CONTROL_WORD_CTRL_WORD__M 0 xF#define QAM_SY_CONTROL_WORD_CTRL_WORD__PRE 0 x0#define QAM_VD_ISS_RAM__A 0 x1480000#define QAM_VD_QSS_RAM__A 0 x1490000#define QAM_VD_SYM_RAM__A 0 x14A0000#define SCU_COMM_EXEC__A 0 x800000#define SCU_COMM_EXEC__W 2 #define SCU_COMM_EXEC__M 0 x3#define SCU_COMM_EXEC__PRE 0 x0#define SCU_COMM_EXEC_STOP 0 x0#define SCU_COMM_EXEC_ACTIVE 0 x1#define SCU_COMM_EXEC_HOLD 0 x2#define SCU_COMM_STATE__A 0 x800001#define SCU_COMM_STATE__W 16 #define SCU_COMM_STATE__M 0 xFFFF#define SCU_COMM_STATE__PRE 0 x0#define SCU_COMM_STATE_COMM_STATE__B 0 #define SCU_COMM_STATE_COMM_STATE__W 16 #define SCU_COMM_STATE_COMM_STATE__M 0 xFFFF#define SCU_COMM_STATE_COMM_STATE__PRE 0 x0#define SCU_TOP_COMM_EXEC__A 0 x810000#define SCU_TOP_COMM_EXEC__W 2 #define SCU_TOP_COMM_EXEC__M 0 x3#define SCU_TOP_COMM_EXEC__PRE 0 x0#define SCU_TOP_COMM_EXEC_STOP 0 x0#define SCU_TOP_COMM_EXEC_ACTIVE 0 x1#define SCU_TOP_COMM_EXEC_HOLD 0 x2#define SCU_TOP_COMM_STATE__A 0 x810001#define SCU_TOP_COMM_STATE__W 16 #define SCU_TOP_COMM_STATE__M 0 xFFFF#define SCU_TOP_COMM_STATE__PRE 0 x0#define SCU_TOP_MWAIT_CTR__A 0 x810010#define SCU_TOP_MWAIT_CTR__W 2 #define SCU_TOP_MWAIT_CTR__M 0 x3#define SCU_TOP_MWAIT_CTR__PRE 0 x0#define SCU_TOP_MWAIT_CTR_MWAIT_SEL__B 0 #define SCU_TOP_MWAIT_CTR_MWAIT_SEL__W 1 #define SCU_TOP_MWAIT_CTR_MWAIT_SEL__M 0 x1#define SCU_TOP_MWAIT_CTR_MWAIT_SEL__PRE 0 x0#define SCU_TOP_MWAIT_CTR_MWAIT_SEL_TR_MW_OFF 0 x0#define SCU_TOP_MWAIT_CTR_MWAIT_SEL_TR_MW_ON 0 x1#define SCU_TOP_MWAIT_CTR_READY_DIS__B 1 #define SCU_TOP_MWAIT_CTR_READY_DIS__W 1 #define SCU_TOP_MWAIT_CTR_READY_DIS__M 0 x2#define SCU_TOP_MWAIT_CTR_READY_DIS__PRE 0 x0#define SCU_TOP_MWAIT_CTR_READY_DIS_NMI_ON 0 x0#define SCU_TOP_MWAIT_CTR_READY_DIS_NMI_OFF 0 x2#define SCU_LOW_RAM__A 0 x820000#define SCU_LOW_RAM_LOW__B 0 #define SCU_LOW_RAM_LOW__W 16 #define SCU_LOW_RAM_LOW__M 0 xFFFF#define SCU_LOW_RAM_LOW__PRE 0 x0#define SCU_HIGH_RAM__A 0 x830000#define SCU_HIGH_RAM_HIGH__B 0 #define SCU_HIGH_RAM_HIGH__W 16 #define SCU_HIGH_RAM_HIGH__M 0 xFFFF#define SCU_HIGH_RAM_HIGH__PRE 0 x0#define SCU_RAM_AGC_RF_MAX__A 0 x831E96#define SCU_RAM_AGC_RF_MAX__W 15 #define SCU_RAM_AGC_RF_MAX__M 0 x7FFF#define SCU_RAM_AGC_RF_MAX__PRE 0 x0#define SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A 0 x831E97#define SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__W 16 #define SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__M 0 xFFFF#define SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__PRE 0 x0#define SCU_RAM_AGC_KI_CYCCNT__A 0 x831E98#define SCU_RAM_AGC_KI_CYCCNT__W 16 #define SCU_RAM_AGC_KI_CYCCNT__M 0 xFFFF#define SCU_RAM_AGC_KI_CYCCNT__PRE 0 x0#define SCU_RAM_AGC_KI_CYCLEN__A 0 x831E99#define SCU_RAM_AGC_KI_CYCLEN__W 16 #define SCU_RAM_AGC_KI_CYCLEN__M 0 xFFFF#define SCU_RAM_AGC_KI_CYCLEN__PRE 0 x0#define SCU_RAM_AGC_SNS_CYCLEN__A 0 x831E9A#define SCU_RAM_AGC_SNS_CYCLEN__W 16 #define SCU_RAM_AGC_SNS_CYCLEN__M 0 xFFFF#define SCU_RAM_AGC_SNS_CYCLEN__PRE 0 x0#define SCU_RAM_AGC_RF_SNS_DEV_MAX__A 0 x831E9B#define SCU_RAM_AGC_RF_SNS_DEV_MAX__W 16 #define SCU_RAM_AGC_RF_SNS_DEV_MAX__M 0 xFFFF#define SCU_RAM_AGC_RF_SNS_DEV_MAX__PRE 0 x0#define SCU_RAM_AGC_RF_SNS_DEV_MIN__A 0 x831E9C#define SCU_RAM_AGC_RF_SNS_DEV_MIN__W 16 #define SCU_RAM_AGC_RF_SNS_DEV_MIN__M 0 xFFFF#define SCU_RAM_AGC_RF_SNS_DEV_MIN__PRE 0 x0#define SCU_RAM_AGC_KI__A 0 x831E9D#define SCU_RAM_AGC_KI__W 15 #define SCU_RAM_AGC_KI__M 0 x7FFF#define SCU_RAM_AGC_KI__PRE 0 x0#define SCU_RAM_AGC_KI_DGAIN__B 0 #define SCU_RAM_AGC_KI_DGAIN__W 4 #define SCU_RAM_AGC_KI_DGAIN__M 0 xF#define SCU_RAM_AGC_KI_DGAIN__PRE 0 x0#define SCU_RAM_AGC_KI_RF__B 4 #define SCU_RAM_AGC_KI_RF__W 4 #define SCU_RAM_AGC_KI_RF__M 0 xF0#define SCU_RAM_AGC_KI_RF__PRE 0 x0#define SCU_RAM_AGC_KI_IF__B 8 #define SCU_RAM_AGC_KI_IF__W 4 #define SCU_RAM_AGC_KI_IF__M 0 xF00#define SCU_RAM_AGC_KI_IF__PRE 0 x0#define SCU_RAM_AGC_KI_IF_AGC_DISABLE__B 12 #define SCU_RAM_AGC_KI_IF_AGC_DISABLE__W 1 #define SCU_RAM_AGC_KI_IF_AGC_DISABLE__M 0 x1000#define SCU_RAM_AGC_KI_IF_AGC_DISABLE__PRE 0 x0#define SCU_RAM_AGC_KI_INV_IF_POL__B 13 #define SCU_RAM_AGC_KI_INV_IF_POL__W 1 #define SCU_RAM_AGC_KI_INV_IF_POL__M 0 x2000#define SCU_RAM_AGC_KI_INV_IF_POL__PRE 0 x0#define SCU_RAM_AGC_KI_INV_RF_POL__B 14 #define SCU_RAM_AGC_KI_INV_RF_POL__W 1 #define SCU_RAM_AGC_KI_INV_RF_POL__M 0 x4000#define SCU_RAM_AGC_KI_INV_RF_POL__PRE 0 x0#define SCU_RAM_AGC_KI_RED__A 0 x831E9E#define SCU_RAM_AGC_KI_RED__W 6 #define SCU_RAM_AGC_KI_RED__M 0 x3F#define SCU_RAM_AGC_KI_RED__PRE 0 x0#define SCU_RAM_AGC_KI_RED_INNER_RED__B 0 #define SCU_RAM_AGC_KI_RED_INNER_RED__W 2 #define SCU_RAM_AGC_KI_RED_INNER_RED__M 0 x3#define SCU_RAM_AGC_KI_RED_INNER_RED__PRE 0 x0#define SCU_RAM_AGC_KI_RED_RAGC_RED__B 2 #define SCU_RAM_AGC_KI_RED_RAGC_RED__W 2 #define SCU_RAM_AGC_KI_RED_RAGC_RED__M 0 xC#define SCU_RAM_AGC_KI_RED_RAGC_RED__PRE 0 x0#define SCU_RAM_AGC_KI_RED_IAGC_RED__B 4 #define SCU_RAM_AGC_KI_RED_IAGC_RED__W 2 #define SCU_RAM_AGC_KI_RED_IAGC_RED__M 0 x30#define SCU_RAM_AGC_KI_RED_IAGC_RED__PRE 0 x0#define SCU_RAM_AGC_KI_INNERGAIN_MIN__A 0 x831E9F#define SCU_RAM_AGC_KI_INNERGAIN_MIN__W 16 #define SCU_RAM_AGC_KI_INNERGAIN_MIN__M 0 xFFFF#define SCU_RAM_AGC_KI_INNERGAIN_MIN__PRE 0 x0#define SCU_RAM_AGC_KI_MINGAIN__A 0 x831EA0#define SCU_RAM_AGC_KI_MINGAIN__W 16 #define SCU_RAM_AGC_KI_MINGAIN__M 0 xFFFF#define SCU_RAM_AGC_KI_MINGAIN__PRE 0 x0#define SCU_RAM_AGC_KI_MAXGAIN__A 0 x831EA1#define SCU_RAM_AGC_KI_MAXGAIN__W 16 #define SCU_RAM_AGC_KI_MAXGAIN__M 0 xFFFF#define SCU_RAM_AGC_KI_MAXGAIN__PRE 0 x0#define SCU_RAM_AGC_KI_MAXMINGAIN_TH__A 0 x831EA2#define SCU_RAM_AGC_KI_MAXMINGAIN_TH__W 16 #define SCU_RAM_AGC_KI_MAXMINGAIN_TH__M 0 xFFFF#define SCU_RAM_AGC_KI_MAXMINGAIN_TH__PRE 0 x0#define SCU_RAM_AGC_KI_MIN__A 0 x831EA3#define SCU_RAM_AGC_KI_MIN__W 12 #define SCU_RAM_AGC_KI_MIN__M 0 xFFF#define SCU_RAM_AGC_KI_MIN__PRE 0 x0#define SCU_RAM_AGC_KI_MIN_DGAIN__B 0 #define SCU_RAM_AGC_KI_MIN_DGAIN__W 4 #define SCU_RAM_AGC_KI_MIN_DGAIN__M 0 xF#define SCU_RAM_AGC_KI_MIN_DGAIN__PRE 0 x0#define SCU_RAM_AGC_KI_MIN_RF__B 4 #define SCU_RAM_AGC_KI_MIN_RF__W 4 #define SCU_RAM_AGC_KI_MIN_RF__M 0 xF0#define SCU_RAM_AGC_KI_MIN_RF__PRE 0 x0#define SCU_RAM_AGC_KI_MIN_IF__B 8 #define SCU_RAM_AGC_KI_MIN_IF__W 4 #define SCU_RAM_AGC_KI_MIN_IF__M 0 xF00#define SCU_RAM_AGC_KI_MIN_IF__PRE 0 x0#define SCU_RAM_AGC_KI_MAX__A 0 x831EA4#define SCU_RAM_AGC_KI_MAX__W 12 #define SCU_RAM_AGC_KI_MAX__M 0 xFFF#define SCU_RAM_AGC_KI_MAX__PRE 0 x0#define SCU_RAM_AGC_KI_MAX_DGAIN__B 0 #define SCU_RAM_AGC_KI_MAX_DGAIN__W 4 #define SCU_RAM_AGC_KI_MAX_DGAIN__M 0 xF#define SCU_RAM_AGC_KI_MAX_DGAIN__PRE 0 x0#define SCU_RAM_AGC_KI_MAX_RF__B 4 #define SCU_RAM_AGC_KI_MAX_RF__W 4 #define SCU_RAM_AGC_KI_MAX_RF__M 0 xF0#define SCU_RAM_AGC_KI_MAX_RF__PRE 0 x0#define SCU_RAM_AGC_KI_MAX_IF__B 8 #define SCU_RAM_AGC_KI_MAX_IF__W 4 #define SCU_RAM_AGC_KI_MAX_IF__M 0 xF00#define SCU_RAM_AGC_KI_MAX_IF__PRE 0 x0#define SCU_RAM_AGC_CLP_SUM__A 0 x831EA5#define SCU_RAM_AGC_CLP_SUM__W 16 #define SCU_RAM_AGC_CLP_SUM__M 0 xFFFF#define SCU_RAM_AGC_CLP_SUM__PRE 0 x0#define SCU_RAM_AGC_CLP_SUM_MIN__A 0 x831EA6#define SCU_RAM_AGC_CLP_SUM_MIN__W 16 #define SCU_RAM_AGC_CLP_SUM_MIN__M 0 xFFFF#define SCU_RAM_AGC_CLP_SUM_MIN__PRE 0 x0#define SCU_RAM_AGC_CLP_SUM_MAX__A 0 x831EA7#define SCU_RAM_AGC_CLP_SUM_MAX__W 16 #define SCU_RAM_AGC_CLP_SUM_MAX__M 0 xFFFF#define SCU_RAM_AGC_CLP_SUM_MAX__PRE 0 x0#define SCU_RAM_AGC_CLP_CYCLEN__A 0 x831EA8#define SCU_RAM_AGC_CLP_CYCLEN__W 16 #define SCU_RAM_AGC_CLP_CYCLEN__M 0 xFFFF#define SCU_RAM_AGC_CLP_CYCLEN__PRE 0 x0#define SCU_RAM_AGC_CLP_CYCCNT__A 0 x831EA9#define SCU_RAM_AGC_CLP_CYCCNT__W 16 #define SCU_RAM_AGC_CLP_CYCCNT__M 0 xFFFF#define SCU_RAM_AGC_CLP_CYCCNT__PRE 0 x0#define SCU_RAM_AGC_CLP_DIR_TO__A 0 x831EAA#define SCU_RAM_AGC_CLP_DIR_TO__W 8 #define SCU_RAM_AGC_CLP_DIR_TO__M 0 xFF#define SCU_RAM_AGC_CLP_DIR_TO__PRE 0 x0#define SCU_RAM_AGC_CLP_DIR_WD__A 0 x831EAB#define SCU_RAM_AGC_CLP_DIR_WD__W 8 #define SCU_RAM_AGC_CLP_DIR_WD__M 0 xFF#define SCU_RAM_AGC_CLP_DIR_WD__PRE 0 x0#define SCU_RAM_AGC_CLP_DIR_STP__A 0 x831EAC#define SCU_RAM_AGC_CLP_DIR_STP__W 16 #define SCU_RAM_AGC_CLP_DIR_STP__M 0 xFFFF#define SCU_RAM_AGC_CLP_DIR_STP__PRE 0 x0#define SCU_RAM_AGC_SNS_SUM__A 0 x831EAD#define SCU_RAM_AGC_SNS_SUM__W 16 #define SCU_RAM_AGC_SNS_SUM__M 0 xFFFF#define SCU_RAM_AGC_SNS_SUM__PRE 0 x0#define SCU_RAM_AGC_SNS_SUM_MIN__A 0 x831EAE#define SCU_RAM_AGC_SNS_SUM_MIN__W 16 #define SCU_RAM_AGC_SNS_SUM_MIN__M 0 xFFFF#define SCU_RAM_AGC_SNS_SUM_MIN__PRE 0 x0#define SCU_RAM_AGC_SNS_SUM_MAX__A 0 x831EAF#define SCU_RAM_AGC_SNS_SUM_MAX__W 16 #define SCU_RAM_AGC_SNS_SUM_MAX__M 0 xFFFF#define SCU_RAM_AGC_SNS_SUM_MAX__PRE 0 x0#define SCU_RAM_AGC_SNS_CYCCNT__A 0 x831EB0#define SCU_RAM_AGC_SNS_CYCCNT__W 16 #define SCU_RAM_AGC_SNS_CYCCNT__M 0 xFFFF#define SCU_RAM_AGC_SNS_CYCCNT__PRE 0 x0#define SCU_RAM_AGC_SNS_DIR_TO__A 0 x831EB1#define SCU_RAM_AGC_SNS_DIR_TO__W 8 #define SCU_RAM_AGC_SNS_DIR_TO__M 0 xFF#define SCU_RAM_AGC_SNS_DIR_TO__PRE 0 x0#define SCU_RAM_AGC_SNS_DIR_WD__A 0 x831EB2#define SCU_RAM_AGC_SNS_DIR_WD__W 8 #define SCU_RAM_AGC_SNS_DIR_WD__M 0 xFF#define SCU_RAM_AGC_SNS_DIR_WD__PRE 0 x0#define SCU_RAM_AGC_SNS_DIR_STP__A 0 x831EB3#define SCU_RAM_AGC_SNS_DIR_STP__W 16 #define SCU_RAM_AGC_SNS_DIR_STP__M 0 xFFFF#define SCU_RAM_AGC_SNS_DIR_STP__PRE 0 x0#define SCU_RAM_AGC_INGAIN__A 0 x831EB4#define SCU_RAM_AGC_INGAIN__W 16 #define SCU_RAM_AGC_INGAIN__M 0 xFFFF#define SCU_RAM_AGC_INGAIN__PRE 0 x0#define SCU_RAM_AGC_INGAIN_TGT__A 0 x831EB5#define SCU_RAM_AGC_INGAIN_TGT__W 15 #define SCU_RAM_AGC_INGAIN_TGT__M 0 x7FFF#define SCU_RAM_AGC_INGAIN_TGT__PRE 0 x0#define SCU_RAM_AGC_INGAIN_TGT_MIN__A 0 x831EB6#define SCU_RAM_AGC_INGAIN_TGT_MIN__W 15 #define SCU_RAM_AGC_INGAIN_TGT_MIN__M 0 x7FFF#define SCU_RAM_AGC_INGAIN_TGT_MIN__PRE 0 x0#define SCU_RAM_AGC_INGAIN_TGT_MAX__A 0 x831EB7#define SCU_RAM_AGC_INGAIN_TGT_MAX__W 15 #define SCU_RAM_AGC_INGAIN_TGT_MAX__M 0 x7FFF#define SCU_RAM_AGC_INGAIN_TGT_MAX__PRE 0 x0#define SCU_RAM_AGC_IF_IACCU_HI__A 0 x831EB8#define SCU_RAM_AGC_IF_IACCU_HI__W 16 #define SCU_RAM_AGC_IF_IACCU_HI__M 0 xFFFF#define SCU_RAM_AGC_IF_IACCU_HI__PRE 0 x0#define SCU_RAM_AGC_IF_IACCU_LO__A 0 x831EB9#define SCU_RAM_AGC_IF_IACCU_LO__W 8 #define SCU_RAM_AGC_IF_IACCU_LO__M 0 xFF#define SCU_RAM_AGC_IF_IACCU_LO__PRE 0 x0#define SCU_RAM_AGC_IF_IACCU_HI_TGT__A 0 x831EBA#define SCU_RAM_AGC_IF_IACCU_HI_TGT__W 15 #define SCU_RAM_AGC_IF_IACCU_HI_TGT__M 0 x7FFF#define SCU_RAM_AGC_IF_IACCU_HI_TGT__PRE 0 x0#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A 0 x831EBB#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__W 15 #define SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__M 0 x7FFF#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__PRE 0 x0#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A 0 x831EBC#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__W 15 #define SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__M 0 x7FFF#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__PRE 0 x0#define SCU_RAM_AGC_RF_IACCU_HI__A 0 x831EBD#define SCU_RAM_AGC_RF_IACCU_HI__W 16 #define SCU_RAM_AGC_RF_IACCU_HI__M 0 xFFFF#define SCU_RAM_AGC_RF_IACCU_HI__PRE 0 x0#define SCU_RAM_AGC_RF_IACCU_LO__A 0 x831EBE#define SCU_RAM_AGC_RF_IACCU_LO__W 8 #define SCU_RAM_AGC_RF_IACCU_LO__M 0 xFF#define SCU_RAM_AGC_RF_IACCU_LO__PRE 0 x0#define SCU_RAM_AGC_RF_IACCU_HI_CO__A 0 x831EBF#define SCU_RAM_AGC_RF_IACCU_HI_CO__W 16 #define SCU_RAM_AGC_RF_IACCU_HI_CO__M 0 xFFFF#define SCU_RAM_AGC_RF_IACCU_HI_CO__PRE 0 x0#define SCU_RAM_SP__A 0 x831EC0#define SCU_RAM_SP__W 16 #define SCU_RAM_SP__M 0 xFFFF#define SCU_RAM_SP__PRE 0 x0#define SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A 0 x831EC1#define SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__W 16 #define SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__M 0 xFFFF#define SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__PRE 0 x0#define SCU_RAM_AGC_KI_MIN_IFGAIN__A 0 x831EC2#define SCU_RAM_AGC_KI_MIN_IFGAIN__W 16 #define SCU_RAM_AGC_KI_MIN_IFGAIN__M 0 xFFFF#define SCU_RAM_AGC_KI_MIN_IFGAIN__PRE 0 x0#define SCU_RAM_AGC_KI_MAX_IFGAIN__A 0 x831EC3#define SCU_RAM_AGC_KI_MAX_IFGAIN__W 16 #define SCU_RAM_AGC_KI_MAX_IFGAIN__M 0 xFFFF#define SCU_RAM_AGC_KI_MAX_IFGAIN__PRE 0 x0#define SCU_RAM_FEC_MEAS_COUNT__A 0 x831EC4#define SCU_RAM_FEC_MEAS_COUNT__W 16 #define SCU_RAM_FEC_MEAS_COUNT__M 0 xFFFF#define SCU_RAM_FEC_MEAS_COUNT__PRE 0 x0#define SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__A 0 x831EC5#define SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__W 16 #define SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__M 0 xFFFF#define SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__PRE 0 x0#define SCU_RAM_FEC_ACCUM_CW_CORRECTED_HI__A 0 x831EC6#define SCU_RAM_FEC_ACCUM_CW_CORRECTED_HI__W 16 #define SCU_RAM_FEC_ACCUM_CW_CORRECTED_HI__M 0 xFFFF#define SCU_RAM_FEC_ACCUM_CW_CORRECTED_HI__PRE 0 x0#define SCU_RAM_GPIO__A 0 x831EC7#define SCU_RAM_GPIO__W 1 #define SCU_RAM_GPIO__M 0 x1#define SCU_RAM_GPIO__PRE 0 x0#define SCU_RAM_GPIO_HW_LOCK_IND__B 0 #define SCU_RAM_GPIO_HW_LOCK_IND__W 1 #define SCU_RAM_GPIO_HW_LOCK_IND__M 0 x1#define SCU_RAM_GPIO_HW_LOCK_IND__PRE 0 x0#define SCU_RAM_GPIO_HW_LOCK_IND_DISABLE 0 x0#define SCU_RAM_GPIO_HW_LOCK_IND_ENABLE 0 x1#define SCU_RAM_AGC_CLP_CTRL_MODE__A 0 x831EC8#define SCU_RAM_AGC_CLP_CTRL_MODE__W 8 #define SCU_RAM_AGC_CLP_CTRL_MODE__M 0 xFF#define SCU_RAM_AGC_CLP_CTRL_MODE__PRE 0 x0#define SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW__B 0 #define SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW__W 1 #define SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW__M 0 x1#define SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW__PRE 0 x0#define SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW_false 0 x0#define SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW_true 0 x1#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP__B 1 #define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP__W 1 #define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP__M 0 x2#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP__PRE 0 x0#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP_FCC_ENABLE 0 x0#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP_FCC_DISABLE 0 x2#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC__B 2 #define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC__W 1 #define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC__M 0 x4#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC__PRE 0 x0#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC_DEC_DISABLE 0 x0#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC_DEC_ENABLE 0 x4#define SCU_RAM_AGC_KI_MIN_RFGAIN__A 0 x831EC9#define SCU_RAM_AGC_KI_MIN_RFGAIN__W 16 #define SCU_RAM_AGC_KI_MIN_RFGAIN__M 0 xFFFF#define SCU_RAM_AGC_KI_MIN_RFGAIN__PRE 0 x0#define SCU_RAM_AGC_KI_MAX_RFGAIN__A 0 x831ECA#define SCU_RAM_AGC_KI_MAX_RFGAIN__W 16 #define SCU_RAM_AGC_KI_MAX_RFGAIN__M 0 xFFFF#define SCU_RAM_AGC_KI_MAX_RFGAIN__PRE 0 x0#define SCU_RAM_FEC_ACCUM_PKT_FAILURES__A 0 x831ECB#define SCU_RAM_FEC_ACCUM_PKT_FAILURES__W 16 #define SCU_RAM_FEC_ACCUM_PKT_FAILURES__M 0 xFFFF#define SCU_RAM_FEC_ACCUM_PKT_FAILURES__PRE 0 x0#define SCU_RAM_INHIBIT_1__A 0 x831ECC#define SCU_RAM_INHIBIT_1__W 16 #define SCU_RAM_INHIBIT_1__M 0 xFFFF#define SCU_RAM_INHIBIT_1__PRE 0 x0#define SCU_RAM_HTOL_BUF_0__A 0 x831ECD#define SCU_RAM_HTOL_BUF_0__W 16 #define SCU_RAM_HTOL_BUF_0__M 0 xFFFF#define SCU_RAM_HTOL_BUF_0__PRE 0 x0#define SCU_RAM_HTOL_BUF_1__A 0 x831ECE#define SCU_RAM_HTOL_BUF_1__W 16 #define SCU_RAM_HTOL_BUF_1__M 0 xFFFF#define SCU_RAM_HTOL_BUF_1__PRE 0 x0#define SCU_RAM_INHIBIT_2__A 0 x831ECF#define SCU_RAM_INHIBIT_2__W 16 #define SCU_RAM_INHIBIT_2__M 0 xFFFF#define SCU_RAM_INHIBIT_2__PRE 0 x0#define SCU_RAM_TR_SHORT_BUF_0__A 0 x831ED0#define SCU_RAM_TR_SHORT_BUF_0__W 16 #define SCU_RAM_TR_SHORT_BUF_0__M 0 xFFFF#define SCU_RAM_TR_SHORT_BUF_0__PRE 0 x0#define SCU_RAM_TR_SHORT_BUF_1__A 0 x831ED1#define SCU_RAM_TR_SHORT_BUF_1__W 16 #define SCU_RAM_TR_SHORT_BUF_1__M 0 xFFFF#define SCU_RAM_TR_SHORT_BUF_1__PRE 0 x0#define SCU_RAM_TR_LONG_BUF_0__A 0 x831ED2#define SCU_RAM_TR_LONG_BUF_0__W 16 #define SCU_RAM_TR_LONG_BUF_0__M 0 xFFFF#define SCU_RAM_TR_LONG_BUF_0__PRE 0 x0#define SCU_RAM_TR_LONG_BUF_1__A 0 x831ED3#define SCU_RAM_TR_LONG_BUF_1__W 16 #define SCU_RAM_TR_LONG_BUF_1__M 0 xFFFF#define SCU_RAM_TR_LONG_BUF_1__PRE 0 x0#define SCU_RAM_TR_LONG_BUF_2__A 0 x831ED4#define SCU_RAM_TR_LONG_BUF_2__W 16 #define SCU_RAM_TR_LONG_BUF_2__M 0 xFFFF#define SCU_RAM_TR_LONG_BUF_2__PRE 0 x0#define SCU_RAM_TR_LONG_BUF_3__A 0 x831ED5#define SCU_RAM_TR_LONG_BUF_3__W 16 #define SCU_RAM_TR_LONG_BUF_3__M 0 xFFFF#define SCU_RAM_TR_LONG_BUF_3__PRE 0 x0#define SCU_RAM_TR_LONG_BUF_4__A 0 x831ED6#define SCU_RAM_TR_LONG_BUF_4__W 16 #define SCU_RAM_TR_LONG_BUF_4__M 0 xFFFF#define SCU_RAM_TR_LONG_BUF_4__PRE 0 x0#define SCU_RAM_TR_LONG_BUF_5__A 0 x831ED7#define SCU_RAM_TR_LONG_BUF_5__W 16 #define SCU_RAM_TR_LONG_BUF_5__M 0 xFFFF#define SCU_RAM_TR_LONG_BUF_5__PRE 0 x0#define SCU_RAM_TR_LONG_BUF_6__A 0 x831ED8#define SCU_RAM_TR_LONG_BUF_6__W 16 #define SCU_RAM_TR_LONG_BUF_6__M 0 xFFFF#define SCU_RAM_TR_LONG_BUF_6__PRE 0 x0#define SCU_RAM_TR_LONG_BUF_7__A 0 x831ED9#define SCU_RAM_TR_LONG_BUF_7__W 16 #define SCU_RAM_TR_LONG_BUF_7__M 0 xFFFF#define SCU_RAM_TR_LONG_BUF_7__PRE 0 x0#define SCU_RAM_TR_LONG_BUF_8__A 0 x831EDA#define SCU_RAM_TR_LONG_BUF_8__W 16 #define SCU_RAM_TR_LONG_BUF_8__M 0 xFFFF#define SCU_RAM_TR_LONG_BUF_8__PRE 0 x0#define SCU_RAM_TR_LONG_BUF_9__A 0 x831EDB#define SCU_RAM_TR_LONG_BUF_9__W 16 #define SCU_RAM_TR_LONG_BUF_9__M 0 xFFFF#define SCU_RAM_TR_LONG_BUF_9__PRE 0 x0#define SCU_RAM_TR_LONG_BUF_10__A 0 x831EDC#define SCU_RAM_TR_LONG_BUF_10__W 16 #define SCU_RAM_TR_LONG_BUF_10__M 0 xFFFF#define SCU_RAM_TR_LONG_BUF_10__PRE 0 x0#define SCU_RAM_TR_LONG_BUF_11__A 0 x831EDD#define SCU_RAM_TR_LONG_BUF_11__W 16 #define SCU_RAM_TR_LONG_BUF_11__M 0 xFFFF#define SCU_RAM_TR_LONG_BUF_11__PRE 0 x0#define SCU_RAM_TR_LONG_BUF_12__A 0 x831EDE#define SCU_RAM_TR_LONG_BUF_12__W 16 #define SCU_RAM_TR_LONG_BUF_12__M 0 xFFFF#define SCU_RAM_TR_LONG_BUF_12__PRE 0 x0#define SCU_RAM_TR_LONG_BUF_13__A 0 x831EDF#define SCU_RAM_TR_LONG_BUF_13__W 16 #define SCU_RAM_TR_LONG_BUF_13__M 0 xFFFF#define SCU_RAM_TR_LONG_BUF_13__PRE 0 x0#define SCU_RAM_TR_LONG_BUF_14__A 0 x831EE0#define SCU_RAM_TR_LONG_BUF_14__W 16 #define SCU_RAM_TR_LONG_BUF_14__M 0 xFFFF#define SCU_RAM_TR_LONG_BUF_14__PRE 0 x0#define SCU_RAM_TR_LONG_BUF_15__A 0 x831EE1#define SCU_RAM_TR_LONG_BUF_15__W 16 #define SCU_RAM_TR_LONG_BUF_15__M 0 xFFFF#define SCU_RAM_TR_LONG_BUF_15__PRE 0 x0#define SCU_RAM_TR_LONG_BUF_16__A 0 x831EE2#define SCU_RAM_TR_LONG_BUF_16__W 16 #define SCU_RAM_TR_LONG_BUF_16__M 0 xFFFF#define SCU_RAM_TR_LONG_BUF_16__PRE 0 x0#define SCU_RAM_TR_LONG_BUF_17__A 0 x831EE3#define SCU_RAM_TR_LONG_BUF_17__W 16 #define SCU_RAM_TR_LONG_BUF_17__M 0 xFFFF#define SCU_RAM_TR_LONG_BUF_17__PRE 0 x0#define SCU_RAM_TR_LONG_BUF_18__A 0 x831EE4#define SCU_RAM_TR_LONG_BUF_18__W 16 #define SCU_RAM_TR_LONG_BUF_18__M 0 xFFFF#define SCU_RAM_TR_LONG_BUF_18__PRE 0 x0#define SCU_RAM_TR_LONG_BUF_19__A 0 x831EE5#define SCU_RAM_TR_LONG_BUF_19__W 16 #define SCU_RAM_TR_LONG_BUF_19__M 0 xFFFF#define SCU_RAM_TR_LONG_BUF_19__PRE 0 x0#define SCU_RAM_TR_LONG_BUF_20__A 0 x831EE6#define SCU_RAM_TR_LONG_BUF_20__W 16 #define SCU_RAM_TR_LONG_BUF_20__M 0 xFFFF#define SCU_RAM_TR_LONG_BUF_20__PRE 0 x0#define SCU_RAM_TR_LONG_BUF_21__A 0 x831EE7#define SCU_RAM_TR_LONG_BUF_21__W 16 #define SCU_RAM_TR_LONG_BUF_21__M 0 xFFFF#define SCU_RAM_TR_LONG_BUF_21__PRE 0 x0#define SCU_RAM_TR_LONG_BUF_22__A 0 x831EE8#define SCU_RAM_TR_LONG_BUF_22__W 16 #define SCU_RAM_TR_LONG_BUF_22__M 0 xFFFF#define SCU_RAM_TR_LONG_BUF_22__PRE 0 x0#define SCU_RAM_TR_LONG_BUF_23__A 0 x831EE9#define SCU_RAM_TR_LONG_BUF_23__W 16 #define SCU_RAM_TR_LONG_BUF_23__M 0 xFFFF#define SCU_RAM_TR_LONG_BUF_23__PRE 0 x0#define SCU_RAM_TR_LONG_BUF_24__A 0 x831EEA#define SCU_RAM_TR_LONG_BUF_24__W 16 #define SCU_RAM_TR_LONG_BUF_24__M 0 xFFFF#define SCU_RAM_TR_LONG_BUF_24__PRE 0 x0#define SCU_RAM_TR_LONG_BUF_25__A 0 x831EEB#define SCU_RAM_TR_LONG_BUF_25__W 16 #define SCU_RAM_TR_LONG_BUF_25__M 0 xFFFF#define SCU_RAM_TR_LONG_BUF_25__PRE 0 x0#define SCU_RAM_TR_LONG_BUF_26__A 0 x831EEC#define SCU_RAM_TR_LONG_BUF_26__W 16 #define SCU_RAM_TR_LONG_BUF_26__M 0 xFFFF#define SCU_RAM_TR_LONG_BUF_26__PRE 0 x0#define SCU_RAM_TR_LONG_BUF_27__A 0 x831EED#define SCU_RAM_TR_LONG_BUF_27__W 16 #define SCU_RAM_TR_LONG_BUF_27__M 0 xFFFF#define SCU_RAM_TR_LONG_BUF_27__PRE 0 x0#define SCU_RAM_TR_LONG_BUF_28__A 0 x831EEE#define SCU_RAM_TR_LONG_BUF_28__W 16 #define SCU_RAM_TR_LONG_BUF_28__M 0 xFFFF#define SCU_RAM_TR_LONG_BUF_28__PRE 0 x0#define SCU_RAM_TR_LONG_BUF_29__A 0 x831EEF#define SCU_RAM_TR_LONG_BUF_29__W 16 #define SCU_RAM_TR_LONG_BUF_29__M 0 xFFFF#define SCU_RAM_TR_LONG_BUF_29__PRE 0 x0#define SCU_RAM_TR_LONG_BUF_30__A 0 x831EF0#define SCU_RAM_TR_LONG_BUF_30__W 16 #define SCU_RAM_TR_LONG_BUF_30__M 0 xFFFF#define SCU_RAM_TR_LONG_BUF_30__PRE 0 x0#define SCU_RAM_TR_LONG_BUF_31__A 0 x831EF1#define SCU_RAM_TR_LONG_BUF_31__W 16 #define SCU_RAM_TR_LONG_BUF_31__M 0 xFFFF#define SCU_RAM_TR_LONG_BUF_31__PRE 0 x0#define SCU_RAM_ATV_AMS_MAX__A 0 x831EF2#define SCU_RAM_ATV_AMS_MAX__W 11 #define SCU_RAM_ATV_AMS_MAX__M 0 x7FF#define SCU_RAM_ATV_AMS_MAX__PRE 0 x0#define SCU_RAM_ATV_AMS_MAX_AMS_MAX__B 0 #define SCU_RAM_ATV_AMS_MAX_AMS_MAX__W 11 #define SCU_RAM_ATV_AMS_MAX_AMS_MAX__M 0 x7FF#define SCU_RAM_ATV_AMS_MAX_AMS_MAX__PRE 0 x0#define SCU_RAM_ATV_AMS_MIN__A 0 x831EF3#define SCU_RAM_ATV_AMS_MIN__W 11 #define SCU_RAM_ATV_AMS_MIN__M 0 x7FF#define SCU_RAM_ATV_AMS_MIN__PRE 0 x0#define SCU_RAM_ATV_AMS_MIN_AMS_MIN__B 0 #define SCU_RAM_ATV_AMS_MIN_AMS_MIN__W 11 #define SCU_RAM_ATV_AMS_MIN_AMS_MIN__M 0 x7FF#define SCU_RAM_ATV_AMS_MIN_AMS_MIN__PRE 0 x0#define SCU_RAM_ATV_FIELD_CNT__A 0 x831EF4#define SCU_RAM_ATV_FIELD_CNT__W 9 #define SCU_RAM_ATV_FIELD_CNT__M 0 x1FF#define SCU_RAM_ATV_FIELD_CNT__PRE 0 x0#define SCU_RAM_ATV_FIELD_CNT_FIELD_CNT__B 0 #define SCU_RAM_ATV_FIELD_CNT_FIELD_CNT__W 9 #define SCU_RAM_ATV_FIELD_CNT_FIELD_CNT__M 0 x1FF#define SCU_RAM_ATV_FIELD_CNT_FIELD_CNT__PRE 0 x0#define SCU_RAM_ATV_AAGC_FAST__A 0 x831EF5#define SCU_RAM_ATV_AAGC_FAST__W 1 #define SCU_RAM_ATV_AAGC_FAST__M 0 x1#define SCU_RAM_ATV_AAGC_FAST__PRE 0 x0#define SCU_RAM_ATV_AAGC_FAST_AAGC_FAST__B 0 #define SCU_RAM_ATV_AAGC_FAST_AAGC_FAST__W 1 #define SCU_RAM_ATV_AAGC_FAST_AAGC_FAST__M 0 x1#define SCU_RAM_ATV_AAGC_FAST_AAGC_FAST__PRE 0 x0#define SCU_RAM_ATV_AAGC_FAST_AAGC_FAST_OFF 0 x0#define SCU_RAM_ATV_AAGC_FAST_AAGC_FAST_ON 0 x1#define SCU_RAM_ATV_AAGC_LP2__A 0 x831EF6#define SCU_RAM_ATV_AAGC_LP2__W 16 #define SCU_RAM_ATV_AAGC_LP2__M 0 xFFFF#define SCU_RAM_ATV_AAGC_LP2__PRE 0 x0#define SCU_RAM_ATV_AAGC_LP2_AAGC_LP2__B 0 #define SCU_RAM_ATV_AAGC_LP2_AAGC_LP2__W 16 #define SCU_RAM_ATV_AAGC_LP2_AAGC_LP2__M 0 xFFFF#define SCU_RAM_ATV_AAGC_LP2_AAGC_LP2__PRE 0 x0#define SCU_RAM_ATV_BP_LVL__A 0 x831EF7#define SCU_RAM_ATV_BP_LVL__W 11 #define SCU_RAM_ATV_BP_LVL__M 0 x7FF#define SCU_RAM_ATV_BP_LVL__PRE 0 x0#define SCU_RAM_ATV_BP_LVL_BP_LVL__B 0 #define SCU_RAM_ATV_BP_LVL_BP_LVL__W 11 #define SCU_RAM_ATV_BP_LVL_BP_LVL__M 0 x7FF#define SCU_RAM_ATV_BP_LVL_BP_LVL__PRE 0 x0#define SCU_RAM_ATV_BP_RELY__A 0 x831EF8#define SCU_RAM_ATV_BP_RELY__W 8 #define SCU_RAM_ATV_BP_RELY__M 0 xFF#define SCU_RAM_ATV_BP_RELY__PRE 0 x0#define SCU_RAM_ATV_BP_RELY_BP_RELY__B 0 #define SCU_RAM_ATV_BP_RELY_BP_RELY__W 8 #define SCU_RAM_ATV_BP_RELY_BP_RELY__M 0 xFF#define SCU_RAM_ATV_BP_RELY_BP_RELY__PRE 0 x0#define SCU_RAM_ATV_BP_MTA__A 0 x831EF9#define SCU_RAM_ATV_BP_MTA__W 14 #define SCU_RAM_ATV_BP_MTA__M 0 x3FFF#define SCU_RAM_ATV_BP_MTA__PRE 0 x0#define SCU_RAM_ATV_BP_MTA_BP_MTA__B 0 #define SCU_RAM_ATV_BP_MTA_BP_MTA__W 14 #define SCU_RAM_ATV_BP_MTA_BP_MTA__M 0 x3FFF#define SCU_RAM_ATV_BP_MTA_BP_MTA__PRE 0 x0#define SCU_RAM_ATV_BP_REF__A 0 x831EFA#define SCU_RAM_ATV_BP_REF__W 11 #define SCU_RAM_ATV_BP_REF__M 0 x7FF#define SCU_RAM_ATV_BP_REF__PRE 0 x0#define SCU_RAM_ATV_BP_REF_BP_REF__B 0 #define SCU_RAM_ATV_BP_REF_BP_REF__W 11 #define SCU_RAM_ATV_BP_REF_BP_REF__M 0 x7FF#define SCU_RAM_ATV_BP_REF_BP_REF__PRE 0 x0#define SCU_RAM_ATV_BP_REF_MIN__A 0 x831EFB#define SCU_RAM_ATV_BP_REF_MIN__W 11 #define SCU_RAM_ATV_BP_REF_MIN__M 0 x7FF#define SCU_RAM_ATV_BP_REF_MIN__PRE 0 x0#define SCU_RAM_ATV_BP_REF_MIN_BP_REF_MIN__B 0 #define SCU_RAM_ATV_BP_REF_MIN_BP_REF_MIN__W 11 #define SCU_RAM_ATV_BP_REF_MIN_BP_REF_MIN__M 0 x7FF#define SCU_RAM_ATV_BP_REF_MIN_BP_REF_MIN__PRE 0 x0#define SCU_RAM_ATV_BP_REF_MAX__A 0 x831EFC#define SCU_RAM_ATV_BP_REF_MAX__W 11 #define SCU_RAM_ATV_BP_REF_MAX__M 0 x7FF#define SCU_RAM_ATV_BP_REF_MAX__PRE 0 x0#define SCU_RAM_ATV_BP_REF_MAX_BP_REF_MAX__B 0 #define SCU_RAM_ATV_BP_REF_MAX_BP_REF_MAX__W 11 #define SCU_RAM_ATV_BP_REF_MAX_BP_REF_MAX__M 0 x7FF#define SCU_RAM_ATV_BP_REF_MAX_BP_REF_MAX__PRE 0 x0#define SCU_RAM_ATV_BP_CNT__A 0 x831EFD#define SCU_RAM_ATV_BP_CNT__W 8 #define SCU_RAM_ATV_BP_CNT__M 0 xFF#define SCU_RAM_ATV_BP_CNT__PRE 0 x0#define SCU_RAM_ATV_BP_CNT_BP_CNT__B 0 #define SCU_RAM_ATV_BP_CNT_BP_CNT__W 8 #define SCU_RAM_ATV_BP_CNT_BP_CNT__M 0 xFF#define SCU_RAM_ATV_BP_CNT_BP_CNT__PRE 0 x0#define SCU_RAM_ATV_BP_XD_CNT__A 0 x831EFE#define SCU_RAM_ATV_BP_XD_CNT__W 12 #define SCU_RAM_ATV_BP_XD_CNT__M 0 xFFF#define SCU_RAM_ATV_BP_XD_CNT__PRE 0 x0#define SCU_RAM_ATV_BP_XD_CNT_BP_XD_CNT__B 0 #define SCU_RAM_ATV_BP_XD_CNT_BP_XD_CNT__W 12 #define SCU_RAM_ATV_BP_XD_CNT_BP_XD_CNT__M 0 xFFF#define SCU_RAM_ATV_BP_XD_CNT_BP_XD_CNT__PRE 0 x0#define SCU_RAM_ATV_PAGC_KI_MIN__A 0 x831EFF#define SCU_RAM_ATV_PAGC_KI_MIN__W 12 #define SCU_RAM_ATV_PAGC_KI_MIN__M 0 xFFF#define SCU_RAM_ATV_PAGC_KI_MIN__PRE 0 x0#define SCU_RAM_ATV_PAGC_KI_MIN_PAGC_KI_MIN__B 0 #define SCU_RAM_ATV_PAGC_KI_MIN_PAGC_KI_MIN__W 12 #define SCU_RAM_ATV_PAGC_KI_MIN_PAGC_KI_MIN__M 0 xFFF#define SCU_RAM_ATV_PAGC_KI_MIN_PAGC_KI_MIN__PRE 0 x0#define SCU_RAM_ATV_BPC_KI_MIN__A 0 x831F00#define SCU_RAM_ATV_BPC_KI_MIN__W 12 #define SCU_RAM_ATV_BPC_KI_MIN__M 0 xFFF#define SCU_RAM_ATV_BPC_KI_MIN__PRE 0 x0#define SCU_RAM_ATV_BPC_KI_MIN_BPC_KI_MIN__B 0 #define SCU_RAM_ATV_BPC_KI_MIN_BPC_KI_MIN__W 12 #define SCU_RAM_ATV_BPC_KI_MIN_BPC_KI_MIN__M 0 xFFF#define SCU_RAM_ATV_BPC_KI_MIN_BPC_KI_MIN__PRE 0 x0#define SCU_RAM_ORX_RF_RX_FREQUENCY_VALUE__A 0 x831F01#define SCU_RAM_ORX_RF_RX_FREQUENCY_VALUE__W 16 #define SCU_RAM_ORX_RF_RX_FREQUENCY_VALUE__M 0 xFFFF#define SCU_RAM_ORX_RF_RX_FREQUENCY_VALUE__PRE 0 x0#define SCU_RAM_ORX_RF_RX_DATA_RATE__A 0 x831F02#define SCU_RAM_ORX_RF_RX_DATA_RATE__W 8 #define SCU_RAM_ORX_RF_RX_DATA_RATE__M 0 xFF#define SCU_RAM_ORX_RF_RX_DATA_RATE__PRE 0 x0#define SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_REGSPEC 0 x0#define SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_INVSPEC 0 x1#define SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_REGSPEC_ALT 0 x40#define SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_INVSPEC_ALT 0 x41#define SCU_RAM_ORX_RF_RX_DATA_RATE_1544KBPS_REGSPEC 0 x80#define SCU_RAM_ORX_RF_RX_DATA_RATE_1544KBPS_INVSPEC 0 x81#define SCU_RAM_ORX_RF_RX_DATA_RATE_3088KBPS_REGSPEC 0 xC0#define SCU_RAM_ORX_RF_RX_DATA_RATE_3088KBPS_INVSPEC 0 xC1#define SCU_RAM_ORX_SCU_STATE__A 0 x831F03#define SCU_RAM_ORX_SCU_STATE__W 8 #define SCU_RAM_ORX_SCU_STATE__M 0 xFF#define SCU_RAM_ORX_SCU_STATE__PRE 0 x0#define SCU_RAM_ORX_SCU_STATE_RESET 0 x0#define SCU_RAM_ORX_SCU_STATE_AGN_HUNT 0 x1#define SCU_RAM_ORX_SCU_STATE_DGN_HUNT 0 x2#define SCU_RAM_ORX_SCU_STATE_AGC_HUNT 0 x3#define SCU_RAM_ORX_SCU_STATE_FRQ_HUNT 0 x4#define SCU_RAM_ORX_SCU_STATE_PHA_HUNT 0 x8#define SCU_RAM_ORX_SCU_STATE_TIM_HUNT 0 x10#define SCU_RAM_ORX_SCU_STATE_EQU_HUNT 0 x20#define SCU_RAM_ORX_SCU_STATE_EQT_HUNT 0 x30#define SCU_RAM_ORX_SCU_STATE_SYNC 0 x40#define SCU_RAM_ORX_SCU_LOCK__A 0 x831F04#define SCU_RAM_ORX_SCU_LOCK__W 16 #define SCU_RAM_ORX_SCU_LOCK__M 0 xFFFF#define SCU_RAM_ORX_SCU_LOCK__PRE 0 x0#define SCU_RAM_ORX_TARGET_MODE__A 0 x831F05#define SCU_RAM_ORX_TARGET_MODE__W 2 #define SCU_RAM_ORX_TARGET_MODE__M 0 x3#define SCU_RAM_ORX_TARGET_MODE__PRE 0 x0#define SCU_RAM_ORX_TARGET_MODE_1544KBPS 0 x0#define SCU_RAM_ORX_TARGET_MODE_3088KBPS 0 x1#define SCU_RAM_ORX_TARGET_MODE_2048KBPS_SQRT 0 x2
Messung V0.5 in Prozent C=98 H=94 G=95
¤ Dauer der Verarbeitung: 0.748 Sekunden
(vorverarbeitet am 2026-06-08)
¤ *© Formatika GbR, Deutschland
