Impressum irq-gic-v3-its.c
Sprache: C
// SPDX-License-Identifier: GPL-2.0-only /* * Copyright ( C ) 2013 - 2017 ARM Limited , All Rights Reserved . * Author : Marc Zyngier < marc . zyngier @ arm . com > #include <linux/acpi.h>#include <linux/acpi_iort.h>#include <linux/bitfield.h>#include <linux/bitmap.h>#include <linux/cpu.h>#include <linux/crash_dump.h>#include <linux/delay.h>#include <linux/efi.h>#include <linux/genalloc.h>#include <linux/interrupt.h>#include <linux/iommu.h>#include <linux/iopoll.h>#include <linux/irqdomain.h>#include <linux/list.h>#include <linux/log2.h>#include <linux/mem_encrypt.h>#include <linux/memblock.h>#include <linux/mm.h>#include <linux/msi.h>#include <linux/of.h>#include <linux/of_address.h>#include <linux/of_irq.h>#include <linux/of_pci.h>#include <linux/of_platform.h>#include <linux/percpu.h>#include <linux/set_memory.h>#include <linux/slab.h>#include <linux/syscore_ops.h>#include <linux/irqchip.h>#include <linux/irqchip/arm-gic-v3.h>#include <linux/irqchip/arm-gic-v4.h>#include <asm /cputype.h>#include <asm /exception.h>#include "irq-gic-common.h" #include "irq-gic-its-msi-parent.h" #include <linux/irqchip/irq-msi-lib.h>#define ITS_FLAGS_CMDQ_NEEDS_FLUSHING (1 ULL << 0 )#define ITS_FLAGS_WORKAROUND_CAVIUM_22375 (1 ULL << 1 )#define ITS_FLAGS_WORKAROUND_CAVIUM_23144 (1 ULL << 2 )#define ITS_FLAGS_FORCE_NON_SHAREABLE (1 ULL << 3 )#define ITS_FLAGS_WORKAROUND_HISILICON_162100801 (1 ULL << 4 )#define RD_LOCAL_LPI_ENABLED BIT(0 )#define RD_LOCAL_PENDTABLE_PREALLOCATED BIT(1 )#define RD_LOCAL_MEMRESERVE_DONE BIT(2 )static u32 lpi_id_bits;/* * We allocate memory for PROPBASE to cover 2 ^ lpi_id_bits LPIs to * deal with ( one configuration byte per interrupt ) . PENDBASE has to * be 64 kB aligned ( one bit per LPI , plus 8192 bits for SPI / PPI / SGI ) . #define LPI_NRBITS lpi_id_bits#define LPI_PROPBASE_SZ ALIGN(BIT(LPI_NRBITS), SZ_64K)#define LPI_PENDBASE_SZ ALIGN(BIT(LPI_NRBITS) / 8 , SZ_64K)static u8 __ro_after_init lpi_prop_prio;static struct its_node *find_4_1_its(void );/* * Collection structure - just an ID , and a redistributor address to * ping . We use one per CPU as a bag of interrupts assigned to this * CPU . struct its_collection {/* * The ITS_BASER structure - contains memory information , cached * value of BASER register configuration and ITS page size . struct its_baser {void *base;struct its_device;/* * The ITS structure - contains most of the infrastructure , with the * top - level MSI domain , the command queue , the collections , and the * list of devices writing to it . * * dev_alloc_lock has to be taken for device allocations , while the * spinlock must be taken to parse data structures such as the device * list . struct its_node {struct mutex dev_alloc_lock;struct list_head entry;void __iomem *base;void __iomem *sgir_base;struct its_cmd_block *cmd_base;struct its_cmd_block *cmd_write;struct its_baser tables[GITS_BASER_NR_REGS];struct its_collection *collections;struct fwnode_handle *fwnode_handle;struct its_device *its_dev);struct list_head its_device_list;unsigned long list_nr;int numa_node;unsigned int msi_domain_flags;/* for Socionext Synquacer */ int vlpi_redist_offset;static DEFINE_PER_CPU(struct its_node *, local_4_1_its);#define is_v4(its) (!!((its)->typer & GITS_TYPER_VLPIS))#define is_v4_1(its) (!!((its)->typer & GITS_TYPER_VMAPP))#define device_ids(its) (FIELD_GET(GITS_TYPER_DEVBITS, (its)->typer) + 1 )#define ITS_ITT_ALIGN SZ_256/* The maximum number of VPEID bits supported by VLPI commands */ #define ITS_MAX_VPEID_BITS \int nvpeid = 16 ; \if (gic_rdists->has_rvpeid && \1 + (gic_rdists->gicd_typer2 & \#define ITS_MAX_VPEID (1 << (ITS_MAX_VPEID_BITS))/* Convert page order to size in bytes */ #define PAGE_ORDER_TO_SIZE(o) (PAGE_SIZE << (o))struct event_lpi_map {unsigned long *lpi_map;int nr_lpis;struct its_vm *vm;struct its_vlpi_map *vlpi_maps;int nr_vlpis;/* * The ITS view of a device - belongs to an ITS , owns an interrupt * translation table , and a list of interrupts . If it some of its * LPIs are injected into a guest ( GICv4 ) , the event_map . vm field * indicates which one . struct its_device {struct list_head entry;struct its_node *its;struct event_lpi_map event_map;void *itt;bool shared;static struct {struct its_device *dev;struct its_vpe **vpes;int next_victim;struct cpu_lpi_count {static DEFINE_PER_CPU(struct cpu_lpi_count, cpu_lpi_count);static LIST_HEAD(its_nodes);static DEFINE_RAW_SPINLOCK(its_lock);static struct rdists *gic_rdists;static struct irq_domain *its_parent;static unsigned long its_list_map;static u16 vmovp_seq_num;static DEFINE_RAW_SPINLOCK(vmovp_lock);static DEFINE_IDA(its_vpeid_ida);#define gic_data_rdist() (raw_cpu_ptr(gic_rdists->rdist))#define gic_data_rdist_cpu(cpu) (per_cpu_ptr(gic_rdists->rdist, cpu))#define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base)#define gic_data_rdist_vlpi_base() (gic_data_rdist_rd_base() + SZ_128K)static gfp_t gfp_flags_quirk;static struct page *its_alloc_pages_node(int node, gfp_t gfp,unsigned int order)struct page *page;int ret = 0 ;if (!page)return NULL;unsigned long )page_address(page),1 << order);/* * If set_memory_decrypted ( ) fails then we don ' t know what state the * page is in , so we can ' t free it . Instead we leak it . * set_memory_decrypted ( ) will already have WARNed . if (ret)return NULL;return page;static struct page *its_alloc_pages(gfp_t gfp, unsigned int order)return its_alloc_pages_node(NUMA_NO_NODE, gfp, order);static void its_free_pages(void *addr, unsigned int order)/* * If the memory cannot be encrypted again then we must leak the pages . * set_memory_encrypted ( ) will already have WARNed . if (set_memory_encrypted((unsigned long )addr, 1 << order))return ;unsigned long )addr, order);static struct gen_pool *itt_pool;static void *itt_alloc_pool(int node, int size)unsigned long addr;struct page *page;if (size >= PAGE_SIZE) {return page ? page_address(page) : NULL;do {if (addr)break ;0 );if (!page)break ;unsigned long )page_address(page), PAGE_SIZE, node);while (!addr);return (void *)addr;static void itt_free_pool(void *addr, int size)if (!addr)return ;if (size >= PAGE_SIZE) {return ;unsigned long )addr, size);/* * Skip ITSs that have no vLPIs mapped , unless we ' re on GICv4 . 1 , as we * always have vSGIs mapped . static bool require_its_list_vmovp(struct its_vm *vm, struct its_node *its)return (gic_rdists->has_rvpeid || vm->vlpi_count[its->list_nr]);static bool rdists_support_shareable(void )return !(gic_rdists->flags & RDIST_FLAGS_FORCE_NON_SHAREABLE);static u16 get_its_list(struct its_vm *vm)struct its_node *its;unsigned long its_list = 0 ;if (!is_v4(its))continue ;if (require_its_list_vmovp(vm, its))return (u16)its_list;static inline u32 its_get_event_id(struct irq_data *d)struct its_device *its_dev = irq_data_get_irq_chip_data(d);return d->hwirq - its_dev->event_map.lpi_base;static struct its_collection *dev_event_to_col(struct its_device *its_dev,struct its_node *its = its_dev->its;return its->collections + its_dev->event_map.col_map[event];static struct its_vlpi_map *dev_event_to_vlpi_map(struct its_device *its_dev,if (WARN_ON_ONCE(event >= its_dev->event_map.nr_lpis))return NULL;return &its_dev->event_map.vlpi_maps[event];static struct its_vlpi_map *get_vlpi_map(struct irq_data *d)if (irqd_is_forwarded_to_vcpu(d)) {struct its_device *its_dev = irq_data_get_irq_chip_data(d);return dev_event_to_vlpi_map(its_dev, event);return NULL;static int vpe_to_cpuid_lock(struct its_vpe *vpe, unsigned long *flags)return vpe->col_idx;static void vpe_to_cpuid_unlock(struct its_vpe *vpe, unsigned long flags)static struct irq_chip its_vpe_irq_chip;static int irq_to_cpuid_lock(struct irq_data *d, unsigned long *flags)struct its_vpe *vpe = NULL;int cpu;if (d->chip == &its_vpe_irq_chip) {else {struct its_vlpi_map *map = get_vlpi_map(d);if (map)if (vpe) {else {/* Physical LPIs are already locked via the irq_desc lock */ struct its_device *its_dev = irq_data_get_irq_chip_data(d);/* Keep GCC quiet... */ 0 ;return cpu;static void irq_to_cpuid_unlock(struct irq_data *d, unsigned long flags)struct its_vpe *vpe = NULL;if (d->chip == &its_vpe_irq_chip) {else {struct its_vlpi_map *map = get_vlpi_map(d);if (map)if (vpe)static struct its_collection *valid_col(struct its_collection *col)if (WARN_ON_ONCE(col->target_address & GENMASK_ULL(15 , 0 )))return NULL;return col;static struct its_vpe *valid_vpe(struct its_node *its, struct its_vpe *vpe)if (valid_col(its->collections + vpe->col_idx))return vpe;return NULL;/* * ITS command descriptors - parameters to be encoded in a command * block . struct its_cmd_desc {union {struct {struct its_device *dev;struct {struct its_device *dev;struct {struct its_device *dev;struct {struct its_device *dev;int valid;struct {struct its_collection *col;int valid;struct {struct its_device *dev;struct {struct its_device *dev;struct its_collection *col;struct {struct its_device *dev;struct {struct its_collection *col;struct {struct its_vpe *vpe;struct {struct its_vpe *vpe;struct its_collection *col;bool valid;struct {struct its_vpe *vpe;struct its_device *dev;bool db_enabled;struct {struct its_vpe *vpe;struct its_device *dev;bool db_enabled;struct {struct its_vpe *vpe;struct its_collection *col;struct {struct its_vpe *vpe;struct {struct its_vpe *vpe;bool enable;bool group;bool clear;/* * The ITS command block , which is what the ITS actually parses . struct its_cmd_block {union {4 ];4 ];#define ITS_CMD_QUEUE_SZ SZ_64K#define ITS_CMD_QUEUE_NR_ENTRIES (ITS_CMD_QUEUE_SZ / sizeof (struct its_cmd_block))typedef struct its_collection *(*its_cmd_builder_t)(struct its_node *,struct its_cmd_block *,struct its_cmd_desc *);typedef struct its_vpe *(*its_cmd_vbuilder_t)(struct its_node *,struct its_cmd_block *,struct its_cmd_desc *);static void its_mask_encode(u64 *raw_cmd, u64 val, int h, int l)static void its_encode_cmd(struct its_cmd_block *cmd, u8 cmd_nr)0 ], cmd_nr, 7 , 0 );static void its_encode_devid(struct its_cmd_block *cmd, u32 devid)0 ], devid, 63 , 32 );static void its_encode_event_id(struct its_cmd_block *cmd, u32 id)1 ], id, 31 , 0 );static void its_encode_phys_id(struct its_cmd_block *cmd, u32 phys_id)1 ], phys_id, 63 , 32 );static void its_encode_size(struct its_cmd_block *cmd, u8 size)1 ], size, 4 , 0 );static void its_encode_itt(struct its_cmd_block *cmd, u64 itt_addr)2 ], itt_addr >> 8 , 51 , 8 );static void its_encode_valid(struct its_cmd_block *cmd, int valid)2 ], !!valid, 63 , 63 );static void its_encode_target(struct its_cmd_block *cmd, u64 target_addr)2 ], target_addr >> 16 , 51 , 16 );static void its_encode_collection(struct its_cmd_block *cmd, u16 col)2 ], col, 15 , 0 );static void its_encode_vpeid(struct its_cmd_block *cmd, u16 vpeid)1 ], vpeid, 47 , 32 );static void its_encode_virt_id(struct its_cmd_block *cmd, u32 virt_id)2 ], virt_id, 31 , 0 );static void its_encode_db_phys_id(struct its_cmd_block *cmd, u32 db_phys_id)2 ], db_phys_id, 63 , 32 );static void its_encode_db_valid(struct its_cmd_block *cmd, bool db_valid)2 ], db_valid, 0 , 0 );static void its_encode_seq_num(struct its_cmd_block *cmd, u16 seq_num)0 ], seq_num, 47 , 32 );static void its_encode_its_list(struct its_cmd_block *cmd, u16 its_list)1 ], its_list, 15 , 0 );static void its_encode_vpt_addr(struct its_cmd_block *cmd, u64 vpt_pa)3 ], vpt_pa >> 16 , 51 , 16 );static void its_encode_vpt_size(struct its_cmd_block *cmd, u8 vpt_size)3 ], vpt_size, 4 , 0 );static void its_encode_vconf_addr(struct its_cmd_block *cmd, u64 vconf_pa)0 ], vconf_pa >> 16 , 51 , 16 );static void its_encode_alloc(struct its_cmd_block *cmd, bool alloc)0 ], alloc, 8 , 8 );static void its_encode_ptz(struct its_cmd_block *cmd, bool ptz)0 ], ptz, 9 , 9 );static void its_encode_vmapp_default_db(struct its_cmd_block *cmd,1 ], vpe_db_lpi, 31 , 0 );static void its_encode_vmovp_default_db(struct its_cmd_block *cmd,3 ], vpe_db_lpi, 31 , 0 );static void its_encode_db(struct its_cmd_block *cmd, bool db)2 ], db, 63 , 63 );static void its_encode_sgi_intid(struct its_cmd_block *cmd, u8 sgi)0 ], sgi, 35 , 32 );static void its_encode_sgi_priority(struct its_cmd_block *cmd, u8 prio)0 ], prio >> 4 , 23 , 20 );static void its_encode_sgi_group(struct its_cmd_block *cmd, bool grp)0 ], grp, 10 , 10 );static void its_encode_sgi_clear(struct its_cmd_block *cmd, bool clr)0 ], clr, 9 , 9 );static void its_encode_sgi_enable(struct its_cmd_block *cmd, bool en)0 ], en, 8 , 8 );static inline void its_fixup_cmd(struct its_cmd_block *cmd)/* Let's fixup BE commands */ 0 ] = cpu_to_le64(cmd->raw_cmd[0 ]);1 ] = cpu_to_le64(cmd->raw_cmd[1 ]);2 ] = cpu_to_le64(cmd->raw_cmd[2 ]);3 ] = cpu_to_le64(cmd->raw_cmd[3 ]);static struct its_collection *its_build_mapd_cmd(struct its_node *its,struct its_cmd_block *cmd,struct its_cmd_desc *desc)unsigned long itt_addr;1 );return NULL;static struct its_collection *its_build_mapc_cmd(struct its_node *its,struct its_cmd_block *cmd,struct its_cmd_desc *desc)return desc->its_mapc_cmd.col;static struct its_collection *its_build_mapti_cmd(struct its_node *its,struct its_cmd_block *cmd,struct its_cmd_desc *desc)struct its_collection *col;return valid_col(col);static struct its_collection *its_build_movi_cmd(struct its_node *its,struct its_cmd_block *cmd,struct its_cmd_desc *desc)struct its_collection *col;return valid_col(col);static struct its_collection *its_build_discard_cmd(struct its_node *its,struct its_cmd_block *cmd,struct its_cmd_desc *desc)struct its_collection *col;return valid_col(col);static struct its_collection *its_build_inv_cmd(struct its_node *its,struct its_cmd_block *cmd,struct its_cmd_desc *desc)struct its_collection *col;return valid_col(col);static struct its_collection *its_build_int_cmd(struct its_node *its,struct its_cmd_block *cmd,struct its_cmd_desc *desc)struct its_collection *col;return valid_col(col);static struct its_collection *its_build_clear_cmd(struct its_node *its,struct its_cmd_block *cmd,struct its_cmd_desc *desc)struct its_collection *col;return valid_col(col);static struct its_collection *its_build_invall_cmd(struct its_node *its,struct its_cmd_block *cmd,struct its_cmd_desc *desc)return desc->its_invall_cmd.col;static struct its_vpe *its_build_vinvall_cmd(struct its_node *its,struct its_cmd_block *cmd,struct its_cmd_desc *desc)return valid_vpe(its, desc->its_vinvall_cmd.vpe);static struct its_vpe *its_build_vmapp_cmd(struct its_node *its,struct its_cmd_block *cmd,struct its_cmd_desc *desc)struct its_vpe *vpe = valid_vpe(its, desc->its_vmapp_cmd.vpe);unsigned long vpt_addr, vconf_addr;bool alloc;if (!desc->its_vmapp_cmd.valid) {if (is_v4_1(its)) {/* * Unmapping a VPE is self - synchronizing on GICv4 . 1 , * no need to issue a VSYNC . goto out;1 );if (!is_v4_1(its))goto out;/* * GICv4 . 1 provides a way to get the VLPI state , which needs the vPE * to be unmapped first , and in this case , we may remap the vPE * back while the VPT is not empty . So we can ' t assume that the * VPT is empty on map . This is why we never advertise PTZ . false );return vpe;static struct its_vpe *its_build_vmapti_cmd(struct its_node *its,struct its_cmd_block *cmd,struct its_cmd_desc *desc)if (!is_v4_1(its) && desc->its_vmapti_cmd.db_enabled)else 1023 ;return valid_vpe(its, desc->its_vmapti_cmd.vpe);static struct its_vpe *its_build_vmovi_cmd(struct its_node *its,struct its_cmd_block *cmd,struct its_cmd_desc *desc)if (!is_v4_1(its) && desc->its_vmovi_cmd.db_enabled)else 1023 ;true );return valid_vpe(its, desc->its_vmovi_cmd.vpe);static struct its_vpe *its_build_vmovp_cmd(struct its_node *its,struct its_cmd_block *cmd,struct its_cmd_desc *desc)if (is_v4_1(its)) {true );return valid_vpe(its, desc->its_vmovp_cmd.vpe);static struct its_vpe *its_build_vinv_cmd(struct its_node *its,struct its_cmd_block *cmd,struct its_cmd_desc *desc)struct its_vlpi_map *map;return valid_vpe(its, map->vpe);static struct its_vpe *its_build_vint_cmd(struct its_node *its,struct its_cmd_block *cmd,struct its_cmd_desc *desc)struct its_vlpi_map *map;return valid_vpe(its, map->vpe);static struct its_vpe *its_build_vclear_cmd(struct its_node *its,struct its_cmd_block *cmd,struct its_cmd_desc *desc)struct its_vlpi_map *map;return valid_vpe(its, map->vpe);static struct its_vpe *its_build_invdb_cmd(struct its_node *its,struct its_cmd_block *cmd,struct its_cmd_desc *desc)if (WARN_ON(!is_v4_1(its)))return NULL;return valid_vpe(its, desc->its_invdb_cmd.vpe);static struct its_vpe *its_build_vsgi_cmd(struct its_node *its,struct its_cmd_block *cmd,struct its_cmd_desc *desc)if (WARN_ON(!is_v4_1(its)))return NULL;return valid_vpe(its, desc->its_vsgi_cmd.vpe);static u64 its_cmd_ptr_to_offset(struct its_node *its,struct its_cmd_block *ptr)return (ptr - its->cmd_base) * sizeof (*ptr);static int its_queue_full(struct its_node *its)int widx;int ridx;sizeof (struct its_cmd_block);/* This is incredibly unlikely to happen, unless the ITS locks up. */ if (((widx + 1 ) % ITS_CMD_QUEUE_NR_ENTRIES) == ridx)return 1 ;return 0 ;static struct its_cmd_block *its_allocate_entry(struct its_node *its)struct its_cmd_block *cmd;1000000 ; /* 1s! */ while (its_queue_full(its)) {if (!count) {"ITS queue not draining\n" );return NULL;1 );/* Handle queue wrapping */ if (its->cmd_write == (its->cmd_base + ITS_CMD_QUEUE_NR_ENTRIES))/* Clear command */ 0 ] = 0 ;1 ] = 0 ;2 ] = 0 ;3 ] = 0 ;return cmd;static struct its_cmd_block *its_post_commands(struct its_node *its)return its->cmd_write;static void its_flush_cmd(struct its_node *its, struct its_cmd_block *cmd)/* * Make sure the commands written to memory are observable by * the ITS . if (its->flags & ITS_FLAGS_CMDQ_NEEDS_FLUSHING)sizeof (*cmd));else static int its_wait_for_range_completion(struct its_node *its,struct its_cmd_block *to)1000000 ; /* 1s! */ /* Linearize to_idx if the command set has wrapped around */ if (to_idx < prev_idx)while (1 ) {/* * Compute the read pointer progress , taking the * potential wrap - around into account . if (rd_idx < prev_idx)if (linear_idx >= to_idx)break ;if (!count) {"ITS queue timeout (%llu %llu)\n" ,return -1 ;1 );return 0 ;/* Warning, macro hell follows */ #define BUILD_SINGLE_CMD_FUNC(name, buildtype, synctype, buildfn) \void name(struct its_node *its, \struct its_cmd_desc *desc) \struct its_cmd_block *cmd, *sync_cmd, *next_cmd; \unsigned long flags; \if (!cmd) { /* We're soooooo screewed... */ \ return ; \if (sync_obj) { \if (!sync_cmd) \goto post; \if (its_wait_for_range_completion(its, rd_idx, next_cmd)) \"ITS cmd %ps failed\n" , builder); \static void its_build_sync_cmd(struct its_node *its,struct its_cmd_block *sync_cmd,struct its_collection *sync_col)static BUILD_SINGLE_CMD_FUNC(its_send_single_command, its_cmd_builder_t,struct its_collection, its_build_sync_cmd)static void its_build_vsync_cmd(struct its_node *its,struct its_cmd_block *sync_cmd,struct its_vpe *sync_vpe)static BUILD_SINGLE_CMD_FUNC(its_send_single_vcommand, its_cmd_vbuilder_t,struct its_vpe, its_build_vsync_cmd)static void its_send_int(struct its_device *dev, u32 event_id)struct its_cmd_desc desc;static void its_send_clear(struct its_device *dev, u32 event_id)struct its_cmd_desc desc;static void its_send_inv(struct its_device *dev, u32 event_id)struct its_cmd_desc desc;static void its_send_mapd(struct its_device *dev, int valid)struct its_cmd_desc desc;static void its_send_mapc(struct its_node *its, struct its_collection *col,int valid)struct its_cmd_desc desc;static void its_send_mapti(struct its_device *dev, u32 irq_id, u32 id)struct its_cmd_desc desc;static void its_send_movi(struct its_device *dev,struct its_collection *col, u32 id)struct its_cmd_desc desc;static void its_send_discard(struct its_device *dev, u32 id)struct its_cmd_desc desc;static void its_send_invall(struct its_node *its, struct its_collection *col)struct its_cmd_desc desc;static void its_send_vmapti(struct its_device *dev, u32 id)struct its_vlpi_map *map = dev_event_to_vlpi_map(dev, id);struct its_cmd_desc desc;static void its_send_vmovi(struct its_device *dev, u32 id)struct its_vlpi_map *map = dev_event_to_vlpi_map(dev, id);struct its_cmd_desc desc;static void its_send_vmapp(struct its_node *its,struct its_vpe *vpe, bool valid)struct its_cmd_desc desc;static void its_send_vmovp(struct its_vpe *vpe)struct its_cmd_desc desc = {};struct its_node *its;int col_id = vpe->col_idx;if (!its_list_map) {struct its_node, entry);return ;/* * Yet another marvel of the architecture . If using the * its_list " feature " , we need to make sure that all ITSs * receive all VMOVP commands in the same order . The only way * to guarantee this is to make vmovp a serialization point . * * Wall < - - Head . /* Emit VMOVPs */ if (!is_v4(its))continue ;if (!require_its_list_vmovp(vpe->its_vm, its))continue ;static void its_send_vinvall(struct its_node *its, struct its_vpe *vpe)struct its_cmd_desc desc;static void its_send_vinv(struct its_device *dev, u32 event_id)struct its_cmd_desc desc;/* * There is no real VINV command . This is just a normal INV , * with a VSYNC instead of a SYNC . static void its_send_vint(struct its_device *dev, u32 event_id)struct its_cmd_desc desc;/* * There is no real VINT command . This is just a normal INT , * with a VSYNC instead of a SYNC . static void its_send_vclear(struct its_device *dev, u32 event_id)struct its_cmd_desc desc;/* * There is no real VCLEAR command . This is just a normal CLEAR , * with a VSYNC instead of a SYNC . static void its_send_invdb(struct its_node *its, struct its_vpe *vpe)struct its_cmd_desc desc;/* * irqchip functions - assumes MSI , mostly . static void lpi_write_config(struct irq_data *d, u8 clr, u8 set)struct its_vlpi_map *map = get_vlpi_map(d);void *va;if (map) {/* Remember the updated property */ else {8192 ;/* * Make the above write visible to the redistributors . * And yes , we ' re flushing exactly : One . Single . Byte . * Humpf . . . if (gic_rdists->flags & RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING)sizeof (*cfg));else static void wait_for_syncr(void __iomem *rdbase)while (readl_relaxed(rdbase + GICR_SYNCR) & 1 )static void __direct_lpi_inv(struct irq_data *d, u64 val)void __iomem *rdbase;unsigned long flags;int cpu;/* Target the redistributor this LPI is currently routed to */ static void direct_lpi_inv(struct irq_data *d)struct its_vlpi_map *map = get_vlpi_map(d);if (map) {struct its_device *its_dev = irq_data_get_irq_chip_data(d);else {static void lpi_update_config(struct irq_data *d, u8 clr, u8 set)struct its_device *its_dev = irq_data_get_irq_chip_data(d);if (gic_rdists->has_direct_lpi &&else if (!irqd_is_forwarded_to_vcpu(d))else static void its_vlpi_set_doorbell(struct irq_data *d, bool enable)struct its_device *its_dev = irq_data_get_irq_chip_data(d);struct its_vlpi_map *map;/* * GICv4 . 1 does away with the per - LPI nonsense , nothing to do * here . if (is_v4_1(its_dev->its))return ;if (map->db_enabled == enable)return ;/* * More fun with the architecture : * * Ideally , we ' d issue a VMAPTI to set the doorbell to its LPI * value or to 1023 , depending on the enable bit . But that * would be issuing a mapping for an / existing / DevID + EventID * pair , which is UNPREDICTABLE . Instead , let ' s issue a VMOVI * to the / same / vPE , using this opportunity to adjust the * doorbell . Mouahahahaha . We loves it , Precious . static void its_mask_irq(struct irq_data *d)if (irqd_is_forwarded_to_vcpu(d))false );0 );static void its_unmask_irq(struct irq_data *d)if (irqd_is_forwarded_to_vcpu(d))true );0 , LPI_PROP_ENABLED);static __maybe_unused u32 its_read_lpi_count(struct irq_data *d, int cpu)if (irqd_affinity_is_managed(d))return atomic_read(&per_cpu_ptr(&cpu_lpi_count, cpu)->managed);return atomic_read(&per_cpu_ptr(&cpu_lpi_count, cpu)->unmanaged);static void its_inc_lpi_count(struct irq_data *d, int cpu)if (irqd_affinity_is_managed(d))else static void its_dec_lpi_count(struct irq_data *d, int cpu)if (irqd_affinity_is_managed(d))else static unsigned int cpumask_pick_least_loaded(struct irq_data *d,const struct cpumask *cpu_mask)unsigned int cpu = nr_cpu_ids, tmp;int count = S32_MAX;int this_count = its_read_lpi_count(d, tmp);if (this_count < count) {return cpu;/* * As suggested by Thomas Gleixner in : * https : //lore.kernel.org/r/87h80q2aoc.fsf@nanos.tec.linutronix.de static int its_select_cpu(struct irq_data *d,const struct cpumask *aff_mask)struct its_device *its_dev = irq_data_get_irq_chip_data(d);static DEFINE_RAW_SPINLOCK(tmpmask_lock);static struct cpumask __tmpmask;struct cpumask *tmpmask;unsigned long flags;int cpu, node;if (!irqd_affinity_is_managed(d)) {/* First try the NUMA node */ if (node != NUMA_NO_NODE) {/* * Try the intersection of the affinity mask and the * node mask ( and the online mask , just to be safe ) . /* * Ideally , we would check if the mask is empty , and * try again on the full node here . * * But it turns out that the way ACPI describes the * affinity for ITSs only deals about memory , and * not target CPUs , so it cannot describe a single * ITS placed next to two NUMA nodes . * * Instead , just fallback on the online mask . This * diverges from Thomas ' suggestion above . if (cpu < nr_cpu_ids)goto out;/* If we can't cross sockets, give up */ if ((its_dev->its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144))goto out;/* If the above failed, expand the search */ /* Try the intersection of the affinity and online masks */ /* If that doesn't fly, the online mask is the last resort */ if (cpumask_empty(tmpmask))else {/* If we cannot cross sockets, limit the search to that node */ if ((its_dev->its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) &&"IRQ%d -> %*pbl CPU%d\n" , d->irq, cpumask_pr_args(aff_mask), cpu);return cpu;static int its_set_affinity(struct irq_data *d, const struct cpumask *mask_val,bool force)struct its_device *its_dev = irq_data_get_irq_chip_data(d);struct its_collection *target_col;int cpu, prev_cpu;/* A forwarded interrupt should use irq_set_vcpu_affinity */ if (irqd_is_forwarded_to_vcpu(d))return -EINVAL;if (!force)else if (cpu < 0 || cpu >= nr_cpu_ids)goto err;/* don't set the affinity when the target cpu is same as current one */ if (cpu != prev_cpu) {return IRQ_SET_MASK_OK_DONE;return -EINVAL;static u64 its_irq_get_msi_base(struct its_device *its_dev)struct its_node *its = its_dev->its;return its->phys_base + GITS_TRANSLATER;static void its_irq_compose_msi_msg(struct irq_data *d, struct msi_msg *msg)struct its_device *its_dev = irq_data_get_irq_chip_data(d);static int its_irq_set_irqchip_state(struct irq_data *d,enum irqchip_irq_state which,bool state)struct its_device *its_dev = irq_data_get_irq_chip_data(d);if (which != IRQCHIP_STATE_PENDING)return -EINVAL;if (irqd_is_forwarded_to_vcpu(d)) {if (state)else else {if (state)else return 0 ;static int its_irq_retrigger(struct irq_data *d)return !its_irq_set_irqchip_state(d, IRQCHIP_STATE_PENDING, true );/* * Two favourable cases : * * ( a ) Either we have a GICv4 . 1 , and all vPEs have to be mapped at all times * for vSGI delivery * * ( b ) Or the ITSs do not use a list map , meaning that VMOVP is cheap enough * and we ' re better off mapping all VPEs always * * If neither ( a ) nor ( b ) is true , then we map vPEs on demand . * static bool gic_requires_eager_mapping(void )if (!its_list_map || gic_rdists->has_rvpeid)return true ;return false ;static void its_map_vm(struct its_node *its, struct its_vm *vm)if (gic_requires_eager_mapping())return ;/* * If the VM wasn ' t mapped yet , iterate over the vpes and get * them mapped now . if (vm->vlpi_count[its->list_nr] == 1 ) {int i;for (i = 0 ; i < vm->nr_vpes; i++) {struct its_vpe *vpe = vm->vpes[i];true );static void its_unmap_vm(struct its_node *its, struct its_vm *vm)/* Not using the ITS list? Everything is always mapped. */ if (gic_requires_eager_mapping())return ;if (!--vm->vlpi_count[its->list_nr]) {int i;for (i = 0 ; i < vm->nr_vpes; i++) {false );static int its_vlpi_map(struct irq_data *d, struct its_cmd_info *info)struct its_device *its_dev = irq_data_get_irq_chip_data(d);if (!info->map)return -EINVAL;if (!its_dev->event_map.vm) {struct its_vlpi_map *maps;sizeof (*maps),if (!maps)return -ENOMEM;else if (its_dev->event_map.vm != info->map->vm) {return -EINVAL;/* Get our private copy of the mapping information */ if (irqd_is_forwarded_to_vcpu(d)) {/* Already mapped, move it around */ else {/* Ensure all the VPEs are mapped on this ITS */ /* * Flag the interrupt as forwarded so that we can * start poking the virtual property table . /* Write out the property to the prop table */ 0 xff, info->map->properties);/* Drop the physical mapping */ /* and install the virtual one */ /* Increment the number of VLPIs */ return 0 ;static int its_vlpi_get(struct irq_data *d, struct its_cmd_info *info)struct its_device *its_dev = irq_data_get_irq_chip_data(d);struct its_vlpi_map *map;if (!its_dev->event_map.vm || !map)return -EINVAL;/* Copy our mapping information to the incoming request */ return 0 ;static int its_vlpi_unmap(struct irq_data *d)struct its_device *its_dev = irq_data_get_irq_chip_data(d);if (!its_dev->event_map.vm || !irqd_is_forwarded_to_vcpu(d))return -EINVAL;/* Drop the virtual mapping */ /* and restore the physical one */ 0 xff, (lpi_prop_prio |/* Potentially unmap the VM from this ITS */ /* * Drop the refcount and make the device available again if * this was the last VLPI . if (!--its_dev->event_map.nr_vlpis) {return 0 ;static int its_vlpi_prop_update(struct irq_data *d, struct its_cmd_info *info)struct its_device *its_dev = irq_data_get_irq_chip_data(d);if (!its_dev->event_map.vm || !irqd_is_forwarded_to_vcpu(d))return -EINVAL;if (info->cmd_type == PROP_UPDATE_AND_INV_VLPI)0 xff, info->config);else 0 xff, info->config);return 0 ;static int its_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)struct its_device *its_dev = irq_data_get_irq_chip_data(d);struct its_cmd_info *info = vcpu_info;/* Need a v4 ITS */ if (!is_v4(its_dev->its))return -EINVAL;/* Unmap request? */ if (!info)return its_vlpi_unmap(d);switch (info->cmd_type) {case MAP_VLPI:return its_vlpi_map(d, info);case GET_VLPI:return its_vlpi_get(d, info);case PROP_UPDATE_VLPI:case PROP_UPDATE_AND_INV_VLPI:return its_vlpi_prop_update(d, info);default :return -EINVAL;static struct irq_chip its_irq_chip = {"ITS" ,/* * How we allocate LPIs : * * lpi_range_list contains ranges of LPIs that are to available to * allocate from . To allocate LPIs , just pick the first range that * fits the required allocation , and reduce it by the required * amount . Once empty , remove the range from the list . * * To free a range of LPIs , add a free range to the list , sort it and * merge the result if the new range happens to be adjacent to an * already free block . * * The consequence of the above is that allocation is cost is low , but * freeing is expensive . We assumes that freeing rarely occurs . #define ITS_MAX_LPI_NRBITS 16 /* 64K LPIs */ static DEFINE_MUTEX(lpi_range_lock);static LIST_HEAD(lpi_range_list);struct lpi_range {struct list_head entry;static struct lpi_range *mk_lpi_range(u32 base, u32 span)struct lpi_range *range;sizeof (*range), GFP_KERNEL);if (range) {return range;static int alloc_lpi_range(u32 nr_lpis, u32 *base)struct lpi_range *range, *tmp;int err = -ENOSPC;if (range->span >= nr_lpis) {if (range->span == 0 ) {0 ;break ;"ITS: alloc %u:%u\n" , *base, nr_lpis);return err;static void merge_lpi_ranges(struct lpi_range *a, struct lpi_range *b)if (&a->entry == &lpi_range_list || &b->entry == &lpi_range_list)return ;if (a->base_id + a->span != b->base_id)return ;static int free_lpi_range(u32 base, u32 nr_lpis)struct lpi_range *new , *old;new = mk_lpi_range(base, nr_lpis);if (!new )return -ENOMEM;if (old->base_id < base)break ;/* * old is the last element with - > base_id smaller than base , * so new goes right after it . If there are no elements with * - > base_id smaller than base , & old - > entry ends up pointing * at the head of the list , and inserting new it the start of * the list is the right thing to do in that case as well . new ->entry, &old->entry);/* * Now check if we can merge with the preceding and / or * following ranges . new );new , list_next_entry(new , entry));return 0 ;static int __init its_lpi_init(u32 id_bits)1 UL << id_bits) - 8192 ;int err;1 UL << GICD_TYPER_NUM_LPIS(gic_rdists->gicd_typer);if (numlpis > 2 && !WARN_ON(numlpis > lpis)) {"ITS: Using hypervisor restricted LPI range [%u]\n" ,/* * Initializing the allocator is just the same as freeing the * full range of LPIs . 8192 , lpis);"ITS: Allocator initialized for %u LPIs\n" , lpis);return err;static unsigned long *its_lpi_alloc(int nr_irqs, u32 *base, int *nr_ids)unsigned long *bitmap = NULL;int err = 0 ;do {if (!err)break ;2 ;while (nr_irqs > 0 );if (!nr_irqs)if (err)goto out;if (!bitmap)goto out;if (!bitmap)0 ;return bitmap;static void its_lpi_free(unsigned long *bitmap, u32 base, u32 nr_ids)static void gic_reset_prop_table(void *va)/* Regular IRQ priority, Group-1, disabled */ /* Make sure the GIC will observe the written configuration */ static struct page *its_allocate_prop_table(gfp_t gfp_flags)struct page *prop_page;if (!prop_page)return NULL;return prop_page;static void its_free_prop_table(struct page *prop_page)static bool gic_check_reserved_range(phys_addr_t addr, unsigned long size)/* * We don ' t bother checking for a kdump kernel as by * construction , the LPI tables are out of this kernel ' s * memory map . if (is_kdump_kernel())return true ;1 ;if (addr >= start && addr_end <= end)return true ;/* Not found, not a good sign... */ "GICv3: Expected reserved range [%pa:%pa], not found\n" ,return false ;static int gic_reserve_range(phys_addr_t addr, unsigned long size)if (efi_enabled(EFI_CONFIG_TABLES))return efi_mem_reserve_persistent(addr, size);return 0 ;static int __init its_setup_lpi_prop_table(void )if (gic_rdists->flags & RDIST_FLAGS_RD_TABLES_PREALLOCATED) {1 ;51 , 12 );else {struct page *page;if (!page) {"Failed to allocate PROPBASE\n" );return -ENOMEM;"GICv3: using LPI property table @%pa\n" ,return its_lpi_init(lpi_id_bits);static const char *its_base_type_string[] = {"Devices" ,"Virtual CPUs" ,"Reserved (3)" ,"Interrupt Collections" ,"Reserved (5)" ,"Reserved (6)" ,"Reserved (7)" ,static u64 its_read_baser(struct its_node *its, struct its_baser *baser)return gits_read_baser(its->base + GITS_BASER + (idx << 3 ));static void its_write_baser(struct its_node *its, struct its_baser *baser,3 ));static int its_setup_baser(struct its_node *its, struct its_baser *baser,bool indirect)struct page *page;void *base;if (alloc_pages > GITS_BASER_PAGES_MAX) {"ITS@%pa: %s too large, reduce ITS pages %u->%u\n" ,if (!page)return -ENOMEM;void *)page_address(page);/* Check if the physical address of the memory is above 48bits */ if (IS_ENABLED(CONFIG_ARM64_64K_PAGES) && (baser_phys >> 48 )) {/* 52bit PA is supported only when PageSize=64K */ if (psz != SZ_64K) {"ITS: no 52bit PA support when psz=%d\n" , psz);return -ENXIO;/* Convert 52bit PA to 48bit field */ 1 ) << GITS_BASER_ENTRY_SIZE_SHIFT) |1 ) << GITS_BASER_PAGES_SHIFT) |0 x0;switch (psz) {case SZ_4K:break ;case SZ_16K:break ;case SZ_64K:break ;if (!shr)if ((val ^ tmp) & GITS_BASER_SHAREABILITY_MASK) {/* * Shareability didn ' t stick . Just use * whatever the read reported , which is likely * to be the only thing this redistributor * supports . If that ' s zero , make it * non - cacheable as well . if (!shr)goto retry_baser;if (val != tmp) {"ITS@%pa: %s doesn't stick: %llx %llx\n" ,return -ENXIO;"ITS@%pa: allocated %d %s @%lx (%s, esz %d, psz %dK, shr %d)\n" ,int )(PAGE_ORDER_TO_SIZE(order) / (int )tmp),unsigned long )virt_to_phys(base),"indirect" : "flat" , (int )esz,int )shr >> GITS_BASER_SHAREABILITY_SHIFT);return 0 ;static bool its_parse_indirect_baser(struct its_node *its,struct its_baser *baser,bool indirect = false ;/* No need to enable Indirection if memory requirement < (psz*2)bytes */ if ((esz << ids) > (psz * 2 )) {/* * Find out whether hw supports a single or two - level table by * table by reading bit at offset ' 62 ' after writing ' 1 ' to it . if (indirect) {/* * The size of the lvl2 table is equal to ITS page size * which is ' psz ' . For computing lvl1 table size , * subtract ID bits that sparse lvl2 table from ' ids ' * which is reported by ITS hardware times lvl1 table * entry size . int )esz);/* * Allocate as many entries as required to fit the * range of device IDs that the ITS can grok . . . The ID * space being incredibly sparse , this results in a * massive waste of memory if two - level device table * feature is not supported by hardware . if (new_order > MAX_PAGE_ORDER) {int )esz);"ITS@%pa: %s Table too large, reduce ids %llu->%u\n" ,return indirect;static u32 compute_common_aff(u64 val)return aff & ~(GENMASK(31 , 0 ) >> (clpiaff * 8 ));static u32 compute_its_aff(struct its_node *its)/* * Reencode the ITS SVPET and MPIDR as a GICR_TYPER , and compute * the resulting affinity . We then use that to see if this match * our own affinity . return compute_common_aff(val);static struct its_node *find_sibling_its(struct its_node *cur_its)struct its_node *its;if (!FIELD_GET(GITS_TYPER_SVPET, cur_its->typer))return NULL;if (!is_v4_1(its) || its == cur_its)continue ;if (!FIELD_GET(GITS_TYPER_SVPET, its->typer))continue ;if (aff != compute_its_aff(its))continue ;/* GICv4.1 guarantees that the vPE table is GITS_BASER2 */ 2 ].val;if (!(baser & GITS_BASER_VALID))continue ;return its;return NULL;static void its_free_tables(struct its_node *its)int i;for (i = 0 ; i < GITS_BASER_NR_REGS; i++) {if (its->tables[i].base) {static int its_probe_baser_psz(struct its_node *its, struct its_baser *baser)while (psz) {switch (psz) {case SZ_64K:break ;case SZ_16K:break ;case SZ_4K:default :break ;if (FIELD_GET(GITS_BASER_PAGE_SIZE_MASK, baser->val) == gpsz)break ;switch (psz) {case SZ_64K:break ;case SZ_16K:break ;case SZ_4K:default :return -1 ;return 0 ;static int its_alloc_tables(struct its_node *its)int err, i;if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_22375)/* erratum 24313: ignore memory access type */ if (its->flags & ITS_FLAGS_FORCE_NON_SHAREABLE) {0 ;for (i = 0 ; i < GITS_BASER_NR_REGS; i++) {struct its_baser *baser = its->tables + i;bool indirect = false ;if (type == GITS_BASER_TYPE_NONE)continue ;if (its_probe_baser_psz(its, baser)) {return -ENXIO;switch (type) {case GITS_BASER_TYPE_DEVICE:break ;case GITS_BASER_TYPE_VCPU:if (is_v4_1(its)) {struct its_node *sibling;2 );if ((sibling = find_sibling_its(its))) {2 ];continue ;break ;if (err < 0 ) {return err;/* Update settings which will be used for next BASERn */ return 0 ;static u64 inherit_vpe_l1_table_from_its(void )struct its_node *its;if (!is_v4_1(its))continue ;if (!FIELD_GET(GITS_TYPER_SVPET, its->typer))continue ;if (aff != compute_its_aff(its))continue ;/* GICv4.1 guarantees that the vPE table is GITS_BASER2 */ 2 ].val;if (!(baser & GITS_BASER_VALID))continue ;/* We have a winner! */ 2 ].base;if (baser & GITS_BASER_INDIRECT)switch (FIELD_GET(GITS_BASER_PAGE_SIZE_MASK, baser)) {case GIC_PAGE_SIZE_64K:break ;default :47 , 12 );break ;12 );if (rdists_support_shareable()) {1 );return val;return 0 ;static u64 inherit_vpe_l1_table_from_rd(cpumask_t **mask)int cpu;void __iomem *base = gic_data_rdist_cpu(cpu)->rd_base;if (!base || cpu == smp_processor_id())continue ;if (aff != compute_common_aff(val))continue ;/* * At this point , we have a victim . This particular CPU * has already booted , and has an affinity that matches * ours wrt CommonLPIAff . Let ' s use its own VPROPBASER . * Make sure we don ' t write the Z bit in that case . return val;return 0 ;static bool allocate_vpe_l2_table(int cpu, u32 id)void __iomem *base = gic_data_rdist_cpu(cpu)->rd_base;unsigned int psz, esz, idx, npg, gpsz;struct page *page;if (!gic_rdists->has_rvpeid)return true ;/* Skip non-present CPUs */ if (!base)return true ;1 ;1 ;switch (gpsz) {default :1 );case GIC_PAGE_SIZE_4K:break ;case GIC_PAGE_SIZE_16K:break ;case GIC_PAGE_SIZE_64K:break ;/* Don't allow vpe_id that exceeds single, flat table limit */ if (!(val & GICR_VPROPBASER_4_1_INDIRECT))return (id < (npg * psz / (esz * SZ_8)));/* Compute 1st level table index & check if that exceeds table limit */ if (idx >= (npg * psz / GITS_LVL1_ENTRY_SIZE))return false ;/* Allocate memory for 2nd level table */ if (!table[idx]) {if (!page)return false ;/* Flush Lvl2 table to PoC if hw doesn't support coherency */ if (!(val & GICR_VPROPBASER_SHAREABILITY_MASK))/* Flush Lvl1 entry to PoC if hw doesn't support coherency */ if (!(val & GICR_VPROPBASER_SHAREABILITY_MASK))/* Ensure updated table contents are visible to RD hardware */ return true ;static int allocate_vpe_l1_table(void )void __iomem *vlpi_base = gic_data_rdist_vlpi_base();unsigned int psz = SZ_64K;unsigned int np, epp, esz;struct page *page;if (!gic_rdists->has_rvpeid)return 0 ;/* * if VPENDBASER . Valid is set , disable any previously programmed * VPE by setting PendingLast while clearing Valid . This has the * effect of making sure no doorbell will be generated and we can * then safely clear VPROPBASER . Valid . if (gicr_read_vpendbaser(vlpi_base + GICR_VPENDBASER) & GICR_VPENDBASER_Valid)/* * If we can inherit the configuration from another RD , let ' s do * so . Otherwise , we have to go through the allocation process . We * assume that all RDs have the exact same requirements , as * nothing will work otherwise . if (val & GICR_VPROPBASER_4_1_VALID)goto out;sizeof (cpumask_t), GFP_ATOMIC);if (!gic_data_rdist()->vpe_table_mask)return -ENOMEM;if (val & GICR_VPROPBASER_4_1_VALID)goto out;/* First probe the page size */ switch (gpsz) {default :case GIC_PAGE_SIZE_4K:break ;case GIC_PAGE_SIZE_16K:break ;case GIC_PAGE_SIZE_64K:break ;/* * Start populating the register from scratch , including RO fields * ( which we want to print in debug cases . . . ) 0 ;/* How many entries per GIC page? */ /* * If we need more than just a single L1 page , flag the table * as indirect and compute the number of required L1 pages . if (epp < ITS_MAX_VPEID) {int nl2;/* Number of L2 pages required to cover the VPEID space */ /* Number of L1 pages to point to the L2 pages */ else {1 ;1 );/* Right, that's the number of CPU pages we need for L1 */ "np = %d, npg = %lld, psz = %d, epp = %d, esz = %d\n" ,if (!page)return -ENOMEM;12 );if (rdists_support_shareable()) {"CPU%d: VPROPBASER = %llx %*pbl\n" ,return 0 ;static int its_alloc_collections(struct its_node *its)int i;sizeof (*its->collections),if (!its->collections)return -ENOMEM;for (i = 0 ; i < nr_cpu_ids; i++)0 ULL;return 0 ;static struct page *its_allocate_pending_table(gfp_t gfp_flags)struct page *pend_page;if (!pend_page)return NULL;/* Make sure the GIC will observe the zero-ed page */ return pend_page;static void its_free_pending_table(struct page *pt)/* * Booting with kdump and LPIs enabled is generally fine . Any other * case is wrong in the absence of firmware / EFI support . static bool enabled_lpis_allowed(void )/* Check whether the property table is in a reserved region */ 51 , 12 );return gic_check_reserved_range(addr, LPI_PROPBASE_SZ);static int __init allocate_lpi_tables(void )int err, cpu;/* * If LPIs are enabled while we run this from the boot CPU , * flag the RD tables as pre - allocated if the stars do align . if ((val & GICR_CTLR_ENABLE_LPIS) && enabled_lpis_allowed()) {"GICv3: Using preallocated redistributor tables\n" );if (err)return err;/* * We allocate all the pending tables anyway , as we may have a * mix of RDs that have had LPIs enabled , and some that * don ' t . We ' ll free the unused ones as each CPU comes online . struct page *pend_page;if (!pend_page) {"Failed to allocate PENDBASE for CPU%d\n" , cpu);return -ENOMEM;return 0 ;static u64 read_vpend_dirty_clear(void __iomem *vlpi_base)1000000 ; /* 1s! */ bool clean;do {if (!clean) {1 );while (!clean && count);if (unlikely(!clean))"ITS virtual pending table not cleaning\n" );return val;static u64 its_clear_vpend_valid(void __iomem *vlpi_base, u64 clr, u64 set)/* Make sure we wait until the RD is done with the initial scan */ if (unlikely(val & GICR_VPENDBASER_Dirty))return val;static void its_cpu_init_lpis(void )void __iomem *rbase = gic_data_rdist_rd_base();struct page *pend_page;if (gic_data_rdist()->flags & RD_LOCAL_LPI_ENABLED)return ;if ((gic_rdists->flags & RDIST_FLAGS_RD_TABLES_PREALLOCATED) &&/* * Check that we get the same property table on all * RDs . If we don ' t , this is hopeless . 51 , 12 );if (WARN_ON(gic_rdists->prop_table_pa != paddr))51 , 16 );goto out;/* set PROPBASE */ 1 ) & GICR_PROPBASER_IDBITS_MASK));if (!rdists_support_shareable())if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) {if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) {/* * The HW reports non - shareable , we must * remove the cacheability attributes as * well . "GIC: using cache flushing for LPI property table\n" );/* set PENDBASE */ if (!rdists_support_shareable())if (!(tmp & GICR_PENDBASER_SHAREABILITY_MASK)) {/* * The HW reports non - shareable , we must remove the * cacheability attributes as well . /* Enable LPIs */ if (gic_rdists->has_vlpis && !gic_rdists->has_rvpeid) {void __iomem *vlpi_base = gic_data_rdist_vlpi_base();/* * It ' s possible for CPU to receive VLPIs before it is * scheduled as a vPE , especially for the first CPU , and the * VLPI with INTID larger than 2 ^ ( IDbits + 1 ) will be considered * as out of range and dropped by GIC . * So we initialize IDbits to known value to avoid VLPI drop . 1 ) & GICR_VPROPBASER_IDBITS_MASK;"GICv4: CPU%d: Init IDbits to 0x%llx for GICR_VPROPBASER\n" ,/* * Also clear Valid bit of GICR_VPENDBASER , in case some * ancient programming gets left in and has possibility of * corrupting memory . 0 , 0 );if (allocate_vpe_l1_table()) {/* * If the allocation has failed , we ' re in massive trouble . * Disable direct injection , and pray that no VM was * already running . . . false ;false ;/* Make sure the GIC has seen the above */ "GICv3: CPU%d: using %s LPI pending table @%pa\n" ,"reserved" : "allocated" ,static void its_cpu_init_collection(struct its_node *its)int cpu = smp_processor_id();/* avoid cross node collections and its mapping */ if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) {struct device_node *cpu_node;if (its->numa_node != NUMA_NO_NODE &&return ;/* * We now have to bind each collection to its target * redistributor . if (gic_read_typer(its->base + GITS_TYPER) & GITS_TYPER_PTA) {/* * This ITS wants the physical address of the * redistributor . else {/* This ITS wants a linear CPU number. */ 16 ;/* Perform collection mapping */ 1 );static void its_cpu_init_collections(void )struct its_node *its;static struct its_device *its_find_device(struct its_node *its, u32 dev_id)struct its_device *its_dev = NULL, *tmp;unsigned long flags;if (tmp->device_id == dev_id) {break ;return its_dev;static struct its_baser *its_get_baser(struct its_node *its, u32 type)int i;for (i = 0 ; i < GITS_BASER_NR_REGS; i++) {if (GITS_BASER_TYPE(its->tables[i].val) == type)return &its->tables[i];return NULL;static bool its_alloc_table_entry(struct its_node *its,struct its_baser *baser, u32 id)struct page *page;/* Don't allow device id that exceeds single, flat table limit */ if (!(baser->val & GITS_BASER_INDIRECT))return (id < (PAGE_ORDER_TO_SIZE(baser->order) / esz));/* Compute 1st level table index & check if that exceeds table limit */ if (idx >= (PAGE_ORDER_TO_SIZE(baser->order) / GITS_LVL1_ENTRY_SIZE))return false ;/* Allocate memory for 2nd level table */ if (!table[idx]) {if (!page)return false ;/* Flush Lvl2 table to PoC if hw doesn't support coherency */ if (!(baser->val & GITS_BASER_SHAREABILITY_MASK))/* Flush Lvl1 entry to PoC if hw doesn't support coherency */ if (!(baser->val & GITS_BASER_SHAREABILITY_MASK))/* Ensure updated table contents are visible to ITS hardware */ return true ;static bool its_alloc_device_table(struct its_node *its, u32 dev_id)struct its_baser *baser;/* Don't allow device id that exceeds ITS hardware limit */ if (!baser)return (ilog2(dev_id) < device_ids(its));return its_alloc_table_entry(its, baser, dev_id);static bool its_alloc_vpe_table(u32 vpe_id)struct its_node *its;int cpu;/* * Make sure the L2 tables are allocated on * all * v4 ITSs . We * could try and only do it on ITSs corresponding to devices * that have interrupts targeted at this VPE , but the * complexity becomes crazy ( and you have tons of memory * anyway , right ? ) . struct its_baser *baser;if (!is_v4(its))continue ;if (!baser)return false ;if (!its_alloc_table_entry(its, baser, vpe_id))return false ;/* Non v4.1? No need to iterate RDs and go back early. */ if (!gic_rdists->has_rvpeid)return true ;/* * Make sure the L2 tables are allocated for all copies of * the L1 table on * all * v4 . 1 RDs . if (!allocate_vpe_l2_table(cpu, vpe_id))return false ;return true ;static struct its_device *its_create_device(struct its_node *its, u32 dev_id,int nvecs, bool alloc_lpis)struct its_device *dev;unsigned long *lpi_map = NULL;unsigned long flags;void *itt;int lpi_base;int nr_lpis;int nr_ites;int sz;if (!its_alloc_device_table(its, dev_id))return NULL;if (WARN_ON(!is_power_of_2(nvecs)))/* * Even if the device wants a single LPI , the ITT must be * sized as a power of two ( and you need at least one bit . . . ) . 2 , nvecs);1 );sizeof (*dev), GFP_KERNEL);if (alloc_lpis) {if (lpi_map)sizeof (*col_map),else {sizeof (*col_map), GFP_KERNEL);0 ;0 ;if (!dev || !itt || !col_map || (!lpi_map && alloc_lpis)) {return NULL;/* Map device to its ITT */ 1 );return dev;static void its_free_device(struct its_device *its_dev)unsigned long flags;static int its_alloc_device_irq(struct its_device *dev, int nvecs, irq_hw_number_t *hwirq)int idx;/* Find a free LPI region in lpi_map and allocate them. */ if (idx < 0 )return -ENOSPC;return 0 ;static int its_msi_prepare(struct irq_domain *domain, struct device *dev,int nvec, msi_alloc_info_t *info)struct its_node *its;struct its_device *its_dev;struct msi_domain_info *msi_info;int err = 0 ;/* * We ignore " dev " entirely , and rely on the dev_id that has * been passed via the scratchpad . This limits this domain ' s * usefulness to upper layers that definitely know that they * are built on top of the ITS . 0 ].ul;if (!gic_rdists->has_direct_lpi &&/* Bad luck. Get yourself a better implementation */ 1 , "DevId %x clashes with GICv4 VPE proxy device\n" ,return -EINVAL;if (its_dev) {/* * We already have seen this ID , probably through * another alias ( PCI bridge of some sort ) . No need to * create the device . true ;"Reusing ITT for devID %x\n" , dev_id);goto out;true );if (!its_dev) {goto out;if (info->flags & MSI_ALLOC_FLAGS_PROXY_DEVICE)true ;"ITT %d entries, %d bits\n" , nvec, ilog2(nvec));0 ].ptr = its_dev;return err;static void its_msi_teardown(struct irq_domain *domain, msi_alloc_info_t *info)struct its_device *its_dev = info->scratchpad[0 ].ptr;/* If the device is shared, keep everything around */ if (its_dev->shared)return ;/* LPIs should have been already unmapped at this stage */ if (WARN_ON_ONCE(!bitmap_empty(its_dev->event_map.lpi_map,return ;/* Unmap device/itt, and get rid of the tracking */ 0 );static struct msi_domain_ops its_msi_domain_ops = {static int its_irq_gic_domain_alloc(struct irq_domain *domain,unsigned int virq,struct irq_fwspec fwspec;if (irq_domain_get_of_node(domain->parent)) {3 ;0 ] = GIC_IRQ_TYPE_LPI;1 ] = hwirq;2 ] = IRQ_TYPE_EDGE_RISING;else if (is_fwnode_irqchip(domain->parent->fwnode)) {2 ;0 ] = hwirq;1 ] = IRQ_TYPE_EDGE_RISING;else {return -EINVAL;return irq_domain_alloc_irqs_parent(domain, virq, 1 , &fwspec);static int its_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,unsigned int nr_irqs, void *args)struct its_device *its_dev = info->scratchpad[0 ].ptr;struct its_node *its = its_dev->its;struct irq_data *irqd;int err;int i;if (err)return err;if (err)return err;for (i = 0 ; i < nr_irqs; i++) {if (err)return err;"ID:%d pID:%d vID:%d\n" ,int )(hwirq + i - its_dev->event_map.lpi_base),int )(hwirq + i), virq + i);return 0 ;static int its_irq_domain_activate(struct irq_domain *domain,struct irq_data *d, bool reserve)struct its_device *its_dev = irq_data_get_irq_chip_data(d);int cpu;if (cpu < 0 || cpu >= nr_cpu_ids)return -EINVAL;/* Map the GIC IRQ and event to the device */ return 0 ;static void its_irq_domain_deactivate(struct irq_domain *domain,struct irq_data *d)struct its_device *its_dev = irq_data_get_irq_chip_data(d);/* Stop the delivery of interrupts */ static void its_irq_domain_free(struct irq_domain *domain, unsigned int virq,unsigned int nr_irqs)struct irq_data *d = irq_domain_get_irq_data(domain, virq);struct its_device *its_dev = irq_data_get_irq_chip_data(d);int i;for (i = 0 ; i < nr_irqs; i++) {struct irq_data *data = irq_domain_get_irq_data(domain,/* Nuke the entry in the domain */ static const struct irq_domain_ops its_domain_ops = {/* * This is insane . * * If a GICv4 . 0 doesn ' t implement Direct LPIs ( which is extremely * likely ) , the only way to perform an invalidate is to use a fake * device to issue an INV command , implying that the LPI has first * been mapped to some event on that device . Since this is not exactly * cheap , we try to keep that mapping around as long as possible , and * only issue an UNMAP if we ' re short on available slots . * * Broken by design ( tm ) . * * GICv4 . 1 , on the other hand , mandates that we ' re able to invalidate * by writing to a MMIO register . It doesn ' t implement the whole of * DirectLPI , but that ' s good enough . And most of the time , we don ' t * even have to invalidate anything , as the redistributor can be told * whether to generate a doorbell or not ( we thus leave it enabled , * always ) . static void its_vpe_db_proxy_unmap_locked(struct its_vpe *vpe)/* GICv4.1 doesn't use a proxy, so nothing to do here */ if (gic_rdists->has_rvpeid)return ;/* Already unmapped? */ if (vpe->vpe_proxy_event == -1 )return ;/* * We don ' t track empty slots at all , so let ' s move the * next_victim pointer if we can quickly reuse that slot * instead of nuking an existing entry . Not clear that this is * always a win though , and this might just generate a ripple * effect . . . Let ' s just hope VPEs don ' t migrate too often . if (vpe_proxy.vpes[vpe_proxy.next_victim])1 ;static void its_vpe_db_proxy_unmap(struct its_vpe *vpe)/* GICv4.1 doesn't use a proxy, so nothing to do here */ if (gic_rdists->has_rvpeid)return ;if (!gic_rdists->has_direct_lpi) {unsigned long flags;static void its_vpe_db_proxy_map_locked(struct its_vpe *vpe)/* GICv4.1 doesn't use a proxy, so nothing to do here */ if (gic_rdists->has_rvpeid)return ;/* Already mapped? */ if (vpe->vpe_proxy_event != -1 )return ;/* This slot was already allocated. Kick the other VPE out. */ if (vpe_proxy.vpes[vpe_proxy.next_victim])/* Map the new VPE instead */ 1 ) % vpe_proxy.dev->nr_ites;static void its_vpe_db_proxy_move(struct its_vpe *vpe, int from, int to)unsigned long flags;struct its_collection *target_col;/* GICv4.1 doesn't use a proxy, so nothing to do here */ if (gic_rdists->has_rvpeid)return ;if (gic_rdists->has_direct_lpi) {void __iomem *rdbase;return ;static void its_vpe_4_1_invall_locked(int cpu, struct its_vpe *vpe)void __iomem *rdbase;static int its_vpe_set_affinity(struct irq_data *d,const struct cpumask *mask_val,bool force)struct its_vpe *vpe = irq_data_get_irq_chip_data(d);unsigned int from, cpu = nr_cpu_ids;struct cpumask *table_mask;struct its_node *its;unsigned long flags;/* * Check if we ' re racing against a VPE being destroyed , for * which we don ' t want to allow a VMOVP . if (!atomic_read(&vpe->vmapp_count)) {if (gic_requires_eager_mapping())return -EINVAL;/* * If we lazily map the VPEs , this isn ' t an error and * we can exit cleanly . return IRQ_SET_MASK_OK_DONE;/* * Changing affinity is mega expensive , so let ' s be as lazy as * we can and only do it if we really have to . Also , if mapped * into the proxy device , we need to move the doorbell * interrupt to its new location . * * Another thing is that changing the affinity of a vPE affects * * other interrupts * such as all the vLPIs that are routed to * this vPE . This means that the irq_desc lock is not enough to * protect us , and that we must ensure nobody samples vpe - > col_idx * during the update , hence the lock below which must also be * taken on any vLPI handling path that evaluates vpe - > col_idx . * * Finally , we must protect ourselves against concurrent updates of * the mapping state on this VM should the ITS list be in use ( see * the shortcut in its_send_vmovp ( ) otherewise ) . if (its_list_map)/* * If we are offered another CPU in the same GICv4 . 1 ITS * affinity , pick this one . Otherwise , any CPU will do . if (table_mask)if (cpu < nr_cpu_ids) {if (cpumask_test_cpu(from, mask_val) &&else {if (from == cpu)goto out;if (its && its->flags & ITS_FLAGS_WORKAROUND_HISILICON_162100801)if (its_list_map)return IRQ_SET_MASK_OK_DONE;static void its_wait_vpt_parse_complete(void )void __iomem *vlpi_base = gic_data_rdist_vlpi_base();if (!gic_rdists->has_vpend_valid_dirty)return ;1 , 500 ));static void its_vpe_schedule(struct its_vpe *vpe)void __iomem *vlpi_base = gic_data_rdist_vlpi_base();/* Schedule the VPE */ 51 , 12 );1 ) & GICR_VPROPBASER_IDBITS_MASK;if (rdists_support_shareable()) {51 , 16 );if (rdists_support_shareable()) {/* * There is no good way of finding out if the pending table is * empty as we can race against the doorbell interrupt very * easily . So in the end , vpe - > pending_last is only an * indication that the vcpu has something pending , not one * that the pending table is empty . A good implementation * would be able to read its coarse map pretty quickly anyway , * making this a tolerable issue . 0 ;static void its_vpe_deschedule(struct its_vpe *vpe)void __iomem *vlpi_base = gic_data_rdist_vlpi_base();0 , 0 );static void its_vpe_invall(struct its_vpe *vpe)struct its_node *its;if (!is_v4(its))continue ;if (its_list_map && !vpe->its_vm->vlpi_count[its->list_nr])continue ;/* * Sending a VINVALL to a single ITS is enough , as all * we need is to reach the redistributors . return ;static int its_vpe_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)struct its_vpe *vpe = irq_data_get_irq_chip_data(d);struct its_cmd_info *info = vcpu_info;switch (info->cmd_type) {case SCHEDULE_VPE:return 0 ;case DESCHEDULE_VPE:return 0 ;case COMMIT_VPE:return 0 ;case INVALL_VPE:return 0 ;default :return -EINVAL;static void its_vpe_send_cmd(struct its_vpe *vpe,void (*cmd)(struct its_device *, u32))unsigned long flags;static void its_vpe_send_inv(struct irq_data *d)struct its_vpe *vpe = irq_data_get_irq_chip_data(d);if (gic_rdists->has_direct_lpi)else static void its_vpe_mask_irq(struct irq_data *d)/* * We need to unmask the LPI , which is described by the parent * irq_data . Instead of calling into the parent ( which won ' t * exactly do the right thing , let ' s simply use the * parent_data pointer . Yes , I ' m naughty . 0 );static void its_vpe_unmask_irq(struct irq_data *d)/* Same hack as above... */ 0 , LPI_PROP_ENABLED);static int its_vpe_set_irqchip_state(struct irq_data *d,enum irqchip_irq_state which,bool state)struct its_vpe *vpe = irq_data_get_irq_chip_data(d);if (which != IRQCHIP_STATE_PENDING)return -EINVAL;if (gic_rdists->has_direct_lpi) {void __iomem *rdbase;if (state) {else {else {if (state)else return 0 ;static int its_vpe_retrigger(struct irq_data *d)return !its_vpe_set_irqchip_state(d, IRQCHIP_STATE_PENDING, true );static struct irq_chip its_vpe_irq_chip = {"GICv4-vpe" ,static struct its_node *find_4_1_its(void )struct its_node *its = *this_cpu_ptr(&local_4_1_its);if (!its) {if (is_v4_1(its))return its;/* Oops? */ return its;static void its_vpe_4_1_send_inv(struct irq_data *d)struct its_vpe *vpe = irq_data_get_irq_chip_data(d);struct its_node *its;/* * GICv4 . 1 wants doorbells to be invalidated using the * INVDB command in order to be broadcast to all RDs . Send * it to the first valid ITS , and let the HW do its magic . if (its)static void its_vpe_4_1_mask_irq(struct irq_data *d)0 );static void its_vpe_4_1_unmask_irq(struct irq_data *d)0 , LPI_PROP_ENABLED);static void its_vpe_4_1_schedule(struct its_vpe *vpe,struct its_cmd_info *info)void __iomem *vlpi_base = gic_data_rdist_vlpi_base();0 ;/* Schedule the VPE */ 0 ;0 ;static void its_vpe_4_1_deschedule(struct its_vpe *vpe,struct its_cmd_info *info)void __iomem *vlpi_base = gic_data_rdist_vlpi_base();if (info->req_db) {unsigned long flags;/* * vPE is going to block : make the vPE non - resident with * PendingLast clear and DB set . The GIC guarantees that if * we read - back PendingLast clear , then a doorbell will be * delivered when an interrupt comes . * * Note the locking to deal with the concurrent update of * pending_last from the doorbell interrupt handler that can * run concurrently . else {/* * We ' re not blocking , so just make the vPE non - resident * with PendingLast set , indicating that we ' ll be back . 0 ,true ;static void its_vpe_4_1_invall(struct its_vpe *vpe)unsigned long flags;int cpu;/* Target the redistributor this vPE is currently known on */ static int its_vpe_4_1_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)struct its_vpe *vpe = irq_data_get_irq_chip_data(d);struct its_cmd_info *info = vcpu_info;switch (info->cmd_type) {case SCHEDULE_VPE:return 0 ;case DESCHEDULE_VPE:return 0 ;case COMMIT_VPE:return 0 ;case INVALL_VPE:return 0 ;default :return -EINVAL;static struct irq_chip its_vpe_4_1_irq_chip = {"GICv4.1-vpe" ,static void its_configure_sgi(struct irq_data *d, bool clear)struct its_vpe *vpe = irq_data_get_irq_chip_data(d);struct its_cmd_desc desc;/* * GICv4 . 1 allows us to send VSGI commands to any ITS as long as the * destination VPE is mapped there . Since we map them eagerly at * activation time , we ' re pretty sure the first GICv4 . 1 ITS will do . static void its_sgi_mask_irq(struct irq_data *d)struct its_vpe *vpe = irq_data_get_irq_chip_data(d);false ;false );static void its_sgi_unmask_irq(struct irq_data *d)struct its_vpe *vpe = irq_data_get_irq_chip_data(d);true ;false );static int its_sgi_set_affinity(struct irq_data *d,const struct cpumask *mask_val,bool force)/* * There is no notion of affinity for virtual SGIs , at least * not on the host ( since they can only be targeting a vPE ) . * Tell the kernel we ' ve done whatever it asked for . return IRQ_SET_MASK_OK;static int its_sgi_set_irqchip_state(struct irq_data *d,enum irqchip_irq_state which,bool state)if (which != IRQCHIP_STATE_PENDING)return -EINVAL;if (state) {struct its_vpe *vpe = irq_data_get_irq_chip_data(d);struct its_node *its = find_4_1_its();else {true );return 0 ;static int its_sgi_get_irqchip_state(struct irq_data *d,enum irqchip_irq_state which, bool *val)struct its_vpe *vpe = irq_data_get_irq_chip_data(d);void __iomem *base;unsigned long flags;1000000 ; /* 1s! */ int cpu;if (which != IRQCHIP_STATE_PENDING)return -EINVAL;/* * Locking galore ! We can race against two different events : * * - Concurrent vPE affinity change : we must make sure it cannot * happen , or we ' ll talk to the wrong redistributor . This is * identical to what happens with vLPIs . * * - Concurrent VSGIPENDR access : As it involves accessing two * MMIO registers , this must be made atomic one way or another . do {if (!(status & GICR_VSGIPENDR_BUSY))goto out;if (!count) {"Unable to get SGI status\n" );goto out;1 );while (count);if (!count)return -ENXIO;1 << d->hwirq));return 0 ;static int its_sgi_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)struct its_vpe *vpe = irq_data_get_irq_chip_data(d);struct its_cmd_info *info = vcpu_info;switch (info->cmd_type) {case PROP_UPDATE_VSGI:false );return 0 ;default :return -EINVAL;static struct irq_chip its_sgi_irq_chip = {"GICv4.1-sgi" ,static int its_sgi_irq_domain_alloc(struct irq_domain *domain,unsigned int virq, unsigned int nr_irqs,void *args)struct its_vpe *vpe = args;int i;/* Yes, we do want 16 SGIs */ 16 );for (i = 0 ; i < 16 ; i++) {0 ;false ;false ;return 0 ;static void its_sgi_irq_domain_free(struct irq_domain *domain,unsigned int virq,unsigned int nr_irqs)/* Nothing to do */ static int its_sgi_irq_domain_activate(struct irq_domain *domain,struct irq_data *d, bool reserve)/* Write out the initial SGI configuration */ false );return 0 ;static void its_sgi_irq_domain_deactivate(struct irq_domain *domain,struct irq_data *d)struct its_vpe *vpe = irq_data_get_irq_chip_data(d);/* * The VSGI command is awkward : * * - To change the configuration , CLEAR must be set to false , * leaving the pending bit unchanged . * - To clear the pending bit , CLEAR must be set to true , leaving * the configuration unchanged . * * You just can ' t do both at once , hence the two commands below . false ;false );true );static const struct irq_domain_ops its_sgi_domain_ops = {static int its_vpe_id_alloc(void )return ida_alloc_max(&its_vpeid_ida, ITS_MAX_VPEID - 1 , GFP_KERNEL);static void its_vpe_id_free(u16 id)static int its_vpe_init(struct its_vpe *vpe)struct page *vpt_page;int vpe_id;/* Allocate vpe_id */ if (vpe_id < 0 )return vpe_id;/* Allocate VPT */ if (!vpt_page) {return -ENOMEM;if (!its_alloc_vpe_table(vpe_id)) {return -ENOMEM;0 );if (!gic_rdists->has_rvpeid)1 ;return 0 ;static void its_vpe_teardown(struct its_vpe *vpe)static void its_vpe_irq_domain_free(struct irq_domain *domain,unsigned int virq,unsigned int nr_irqs)struct its_vm *vm = domain->host_data;int i;for (i = 0 ; i < nr_irqs; i++) {struct irq_data *data = irq_domain_get_irq_data(domain,struct its_vpe *vpe = irq_data_get_irq_chip_data(data);if (bitmap_empty(vm->db_bitmap, vm->nr_db_lpis)) {static int its_vpe_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,unsigned int nr_irqs, void *args)struct irq_chip *irqchip = &its_vpe_irq_chip;struct its_vm *vm = args;unsigned long *bitmap;struct page *vprop_page;int base, nr_ids, i, err = 0 ;if (!bitmap)return -ENOMEM;if (nr_ids < nr_irqs) {return -ENOMEM;if (!vprop_page) {return -ENOMEM;if (gic_rdists->has_rvpeid)for (i = 0 ; i < nr_irqs; i++) {if (err)break ;if (err)break ;if (err)return err;static int its_vpe_irq_domain_activate(struct irq_domain *domain,struct irq_data *d, bool reserve)struct its_vpe *vpe = irq_data_get_irq_chip_data(d);struct its_node *its;/* Map the VPE to the first possible CPU */ /* * If we use the list map , we issue VMAPP on demand . . . Unless * we ' re on a GICv4 . 1 and we eagerly map the VPE on all ITSs * so that VSGIs can work . if (!gic_requires_eager_mapping())return 0 ;if (!is_v4(its))continue ;true );return 0 ;static void its_vpe_irq_domain_deactivate(struct irq_domain *domain,struct irq_data *d)struct its_vpe *vpe = irq_data_get_irq_chip_data(d);struct its_node *its;/* * If we use the list map on GICv4 . 0 , we unmap the VPE once no * VLPIs are associated with the VM . if (!gic_requires_eager_mapping())return ;if (!is_v4(its))continue ;false );/* * There may be a direct read to the VPT after unmapping the * vPE , to guarantee the validity of this , we make the VPT * memory coherent with the CPU caches here . if (find_4_1_its() && !atomic_read(&vpe->vmapp_count))static const struct irq_domain_ops its_vpe_domain_ops = {static int its_force_quiescent(void __iomem *base)1000000 ; /* 1s */ /* * GIC architecture specification requires the ITS to be both * disabled and quiescent for writes to GITS_BASER < n > or * GITS_CBASER to not have UNPREDICTABLE results . if ((val & GITS_CTLR_QUIESCENT) && !(val & GITS_CTLR_ENABLE))return 0 ;/* Disable the generation of all interrupts to this ITS */ /* Poll GITS_CTLR and wait until ITS becomes quiescent */ while (1 ) {if (val & GITS_CTLR_QUIESCENT)return 0 ;if (!count)return -EBUSY;1 );static bool __maybe_unused its_enable_quirk_cavium_22375(void *data)struct its_node *its = data;/* erratum 22375: only alloc 8MB table size (20 bits) */ 20 - 1 );return true ;static bool __maybe_unused its_enable_quirk_cavium_23144(void *data)struct its_node *its = data;return true ;static bool __maybe_unused its_enable_quirk_qdf2400_e0065(void *data)struct its_node *its = data;/* On QDF2400, the size of the ITE is 16Bytes */ 16 - 1 );return true ;static u64 its_irq_get_msi_base_pre_its(struct its_device *its_dev)struct its_node *its = its_dev->its;/* * The Socionext Synquacer SoC has a so - called ' pre - ITS ' , * which maps 32 - bit writes targeted at a separate window of * size ' 4 < < device_id_bits ' onto writes to GITS_TRANSLATER * with device ID taken from bits [ device_id_bits + 1 : 2 ] of * the window offset . return its->pre_its_base + (its_dev->device_id << 2 );static bool __maybe_unused its_enable_quirk_socionext_synquacer(void *data)struct its_node *its = data;2 ];if (!fwnode_property_read_u32_array(its->fwnode_handle,"socionext,synquacer-pre-its" ,0 ];1 ]) - 2 ;if (device_ids(its) > ids) {1 );/* the pre-ITS breaks isolation, so disable MSI remapping */ return true ;return false ;static bool __maybe_unused its_enable_quirk_hip07_161600802(void *data)struct its_node *its = data;/* * Hip07 insists on using the wrong address for the VLPI * page . Trick it into doing the right thing . . . return true ;static bool __maybe_unused its_enable_rk3588001(void *data)struct its_node *its = data;if (!of_machine_is_compatible("rockchip,rk3588" ) &&"rockchip,rk3588s" ))return false ;return true ;static bool its_set_non_coherent(void *data)struct its_node *its = data;return true ;static bool __maybe_unused its_enable_quirk_hip09_162100801(void *data)struct its_node *its = data;return true ;static bool __maybe_unused its_enable_rk3568002(void *data)if (!of_machine_is_compatible("rockchip,rk3566" ) &&"rockchip,rk3568" ))return false ;return true ;static const struct gic_quirk its_quirks[] = {#ifdef CONFIG_CAVIUM_ERRATUM_22375"ITS: Cavium errata 22375, 24313" ,0 xa100034c, /* ThunderX pass 1.x */ 0 xffff0fff,#endif #ifdef CONFIG_CAVIUM_ERRATUM_23144"ITS: Cavium erratum 23144" ,0 xa100034c, /* ThunderX pass 1.x */ 0 xffff0fff,#endif #ifdef CONFIG_QCOM_QDF2400_ERRATUM_0065"ITS: QDF2400 erratum 0065" ,0 x00001070, /* QDF2400 ITS rev 1.x */ 0 xffffffff,#endif #ifdef CONFIG_SOCIONEXT_SYNQUACER_PREITS/* * The Socionext Synquacer SoC incorporates ARM ' s own GIC - 500 * implementation , but with a ' pre - ITS ' added that requires * special handling in software . "ITS: Socionext Synquacer pre-ITS" ,0 x0001143b,0 xffffffff,#endif #ifdef CONFIG_HISILICON_ERRATUM_161600802"ITS: Hip07 erratum 161600802" ,0 x00000004,0 xffffffff,#endif #ifdef CONFIG_HISILICON_ERRATUM_162100801"ITS: Hip09 erratum 162100801" ,0 x00051736,0 xffffffff,#endif #ifdef CONFIG_ROCKCHIP_ERRATUM_3588001"ITS: Rockchip erratum RK3588001" ,0 x0201743b,0 xffffffff,#endif "ITS: non-coherent attribute" ,"dma-noncoherent" ,#ifdef CONFIG_ROCKCHIP_ERRATUM_3568002"ITS: Rockchip erratum RK3568002" ,0 x0201743b,0 xffffffff,#endif static void its_enable_quirks(struct its_node *its)if (is_of_node(its->fwnode_handle))static int its_save_disable(void )struct its_node *its;int err = 0 ;void __iomem *base;if (err) {"ITS@%pa: failed to quiesce: %d\n" ,goto err;if (err) {void __iomem *base;return err;static void its_restore_enable(void )struct its_node *its;int ret;void __iomem *base;int i;/* * Make sure that the ITS is disabled . If it fails to quiesce , * don ' t restore it since writing to CBASER or BASER < n > * registers is undefined according to the GIC v3 ITS * Specification . * * Firmware resuming with the ITS enabled is terminally broken . if (ret) {"ITS@%pa: failed to quiesce on resume: %d\n" ,continue ;/* * Writing CBASER resets CREADR to 0 , so make CWRITER and * cmd_write line up with it . 0 , base + GITS_CWRITER);/* Restore GITS_BASER from the value cache. */ for (i = 0 ; i < GITS_BASER_NR_REGS; i++) {struct its_baser *baser = &its->tables[i];if (!(baser->val & GITS_BASER_VALID))continue ;/* * Reinit the collection if it ' s stored in the ITS . This is * indicated by the col_id being less than the HCC field . * CID < HCC as specified in the GIC v3 Documentation . if (its->collections[smp_processor_id()].col_id <static struct syscore_ops its_syscore_ops = {static void __init __iomem *its_map_one(struct resource *res, int *err)void __iomem *its_base;if (!its_base) {"ITS@%pa: Unable to map ITS registers\n" , &res->start);return NULL;if (val != 0 x30 && val != 0 x40) {"ITS@%pa: No ITS detected, giving up\n" , &res->start);goto out_unmap;if (*err) {"ITS@%pa: Failed to quiesce, giving up\n" , &res->start);goto out_unmap;return its_base;return NULL;static int its_init_domain(struct its_node *its)struct irq_domain_info dom_info = {struct msi_domain_info *info;sizeof (*info), GFP_KERNEL);if (!info)return -ENOMEM;if (!msi_create_parent_irq_domain(&dom_info, &gic_v3_its_msi_parent_ops)) {return -ENOMEM;return 0 ;static int its_init_vpe_domain(void )struct its_node *its;int entries;if (gic_rdists->has_direct_lpi) {"ITS: Using DirectLPI for VPE invalidation\n" );return 0 ;/* Any ITS will do, even if not v4 */ struct its_node, entry);sizeof (*vpe_proxy.vpes),if (!vpe_proxy.vpes)return -ENOMEM;/* Use the last possible DevID */ 1 , 0 );false );if (!vpe_proxy.dev) {"ITS: Can't allocate GICv4 proxy device\n" );return -ENOMEM;0 ;"ITS: Allocated DevID %x as GICv4 proxy device (%d slots)\n" ,return 0 ;static int __init its_compute_its_list_map(struct its_node *its)int its_number;/* * This is assumed to be done early enough that we ' re * guaranteed to be single - threaded , hence no * locking . Should this change , we should address * this . if (its_number >= GICv4_ITS_LIST_MAX) {"ITS@%pa: No ITSList entry available!\n" ,return -EINVAL;if ((ctlr & GITS_CTLR_ITS_NUMBER) != (its_number << GITS_CTLR_ITS_NUMBER_SHIFT)) {if (test_and_set_bit(its_number, &its_list_map)) {"ITS@%pa: Duplicate ITSList entry %d\n" ,return -EINVAL;return its_number;static int __init its_probe_one(struct its_node *its)struct page *page;int err;if (is_v4(its)) {if (!(its->typer & GITS_TYPER_VMOVP)) {if (err < 0 )goto out;"ITS@%pa: Using ITS number %d\n" ,else {"ITS@%pa: Single VMOVP capable\n" , &its->phys_base);if (is_v4_1(its)) {if (!its->sgir_base) {goto out;"ITS@%pa: Using GICv4.1 mode %08x %08x\n" ,if (!page) {goto out_unmap_sgir;void *)page_address(page);if (err)goto out_free_cmd;if (err)goto out_free_tables;1 ) |if (its->flags & ITS_FLAGS_FORCE_NON_SHAREABLE)if ((tmp ^ baser) & GITS_CBASER_SHAREABILITY_MASK) {if (!(tmp & GITS_CBASER_SHAREABILITY_MASK)) {/* * The HW reports non - shareable , we must * remove the cacheability attributes as * well . "ITS: using cache flushing for cmd queue\n" );0 , its->base + GITS_CWRITER);if (is_v4(its))if (err)goto out_free_tables;return 0 ;if (its->sgir_base)"ITS@%pa: failed probing (%d)\n" , &its->phys_base, err);return err;static bool gic_rdists_supports_plpis(void )return !!(gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER) & GICR_TYPER_PLPIS);static int redist_disable_lpis(void )void __iomem *rbase = gic_data_rdist_rd_base();if (!gic_rdists_supports_plpis()) {"CPU%d: LPIs not supported\n" , smp_processor_id());return -ENXIO;if (!(val & GICR_CTLR_ENABLE_LPIS))return 0 ;/* * If coming via a CPU hotplug event , we don ' t need to disable * LPIs before trying to re - enable them . They are already * configured and all is well in the world . * * If running with preallocated tables , there is nothing to do . if ((gic_data_rdist()->flags & RD_LOCAL_LPI_ENABLED) ||return 0 ;/* * From that point on , we only try to do some damage control . "GICv3: CPU%d: Booted with LPIs enabled, memory probably corrupted\n" ,/* Disable LPIs */ /* Make sure any change to GICR_CTLR is observable by the GIC */ /* * Software must observe RWP = = 0 after clearing GICR_CTLR . EnableLPIs * from 1 to 0 before programming GICR_PEND { PROP } BASER registers . * Error out if we time out waiting for RWP to clear . while (readl_relaxed(rbase + GICR_CTLR) & GICR_CTLR_RWP) {if (!timeout) {"CPU%d: Timeout while disabling LPIs\n" ,return -ETIMEDOUT;1 );/* * After it has been written to 1 , it is IMPLEMENTATION * DEFINED whether GICR_CTLR . EnableLPI becomes RES1 or can be * cleared to 0 . Error out if clearing the bit failed . if (readl_relaxed(rbase + GICR_CTLR) & GICR_CTLR_ENABLE_LPIS) {"CPU%d: Failed to disable LPIs\n" , smp_processor_id());return -EBUSY;return 0 ;int its_cpu_init(void )if (!list_empty(&its_nodes)) {int ret;if (ret)return ret;return 0 ;static void rdist_memreserve_cpuhp_cleanup_workfn(struct work_struct *work)static DECLARE_WORK(rdist_memreserve_cpuhp_cleanup_work,static int its_cpu_memreserve_lpi(unsigned int cpu)struct page *pend_page;int ret = 0 ;/* This gets to run exactly once per CPU */ if (gic_data_rdist()->flags & RD_LOCAL_MEMRESERVE_DONE)return 0 ;if (WARN_ON(!pend_page)) {goto out;/* * If the pending table was pre - programmed , free the memory we * preemptively allocated . Otherwise , reserve that memory for * later kexecs . if (gic_data_rdist()->flags & RD_LOCAL_PENDTABLE_PREALLOCATED) {else {/* Last CPU being brought up gets to issue the cleanup */ if (!IS_ENABLED(CONFIG_SMP) ||return ret;/* Mark all the BASER registers as invalid before they get reprogrammed */ static int __init its_reset_one(struct resource *res)void __iomem *its_base;int err, i;if (!its_base)return err;for (i = 0 ; i < GITS_BASER_NR_REGS; i++)0 , its_base + GITS_BASER + (i << 3 ));return 0 ;static const struct of_device_id its_device_id[] = {"arm,gic-v3-its" , },static struct its_node __init *its_node_init(struct resource *res,struct fwnode_handle *handle, int numa_node)void __iomem *its_base;struct its_node *its;int err;if (!its_base)return NULL;"ITS %pR\n" , res);sizeof (*its), GFP_KERNEL);if (!its)goto out_unmap;return its;return NULL;static void its_node_destroy(struct its_node *its)static int __init its_of_probe(struct device_node *node)struct device_node *np;struct resource res;int err;/* * Make sure * all * the ITS are reset before we probe any , as * they may be sharing memory . If any of the ITS fails to * reset , don ' t even try to go any further , as this could * result in something even worse . for (np = of_find_matching_node(node, its_device_id); np;if (!of_device_is_available(np) ||"msi-controller" ) ||0 , &res))continue ;if (err)return err;for (np = of_find_matching_node(node, its_device_id); np;struct its_node *its;if (!of_device_is_available(np))continue ;if (!of_property_read_bool(np, "msi-controller" )) {"%pOF: no msi-controller property, ITS ignored\n" ,continue ;if (of_address_to_resource(np, 0 , &res)) {"%pOF: no regs?\n" , np);continue ;if (!its)return -ENOMEM;if (err) {return err;return 0 ;#ifdef CONFIG_ACPI#define ACPI_GICV3_ITS_MEM_SIZE (SZ_128K)#ifdef CONFIG_ACPI_NUMAstruct its_srat_map {/* numa node id */ /* GIC ITS ID */ static struct its_srat_map *its_srat_maps __initdata;static int its_in_srat __initdata;static int __init acpi_get_its_numa_node(u32 its_id)int i;for (i = 0 ; i < its_in_srat; i++) {if (its_id == its_srat_maps[i].its_id)return its_srat_maps[i].numa_node;return NUMA_NO_NODE;static int __init gic_acpi_match_srat_its(union acpi_subtable_headers *header,const unsigned long end)return 0 ;static int __init gic_acpi_parse_srat_its(union acpi_subtable_headers *header,const unsigned long end)int node;struct acpi_srat_gic_its_affinity *its_affinity;struct acpi_srat_gic_its_affinity *)header;if (!its_affinity)return -EINVAL;if (its_affinity->header.length < sizeof (*its_affinity)) {"SRAT: Invalid header length %d in ITS affinity\n" ,return -EINVAL;/* * Note that in theory a new proximity node could be created by this * entry as it is an SRAT resource allocation structure . * We do not currently support doing so . if (node == NUMA_NO_NODE || node >= MAX_NUMNODES) {"SRAT: Invalid NUMA node %d in ITS affinity\n" , node);return 0 ;"SRAT: PXM %d -> ITS %d -> Node %d\n" ,return 0 ;static void __init acpi_table_parse_srat_its(void )int count;sizeof (struct acpi_table_srat),0 );if (count <= 0 )return ;sizeof (struct its_srat_map),if (!its_srat_maps)return ;sizeof (struct acpi_table_srat),0 );/* free the its_srat_maps after ITS probing */ static void __init acpi_its_srat_maps_free(void )#else static void __init acpi_table_parse_srat_its(void ) { }static int __init acpi_get_its_numa_node(u32 its_id) { return NUMA_NO_NODE; }static void __init acpi_its_srat_maps_free(void ) { }#endif static int __init gic_acpi_parse_madt_its(union acpi_subtable_headers *header,const unsigned long end)struct acpi_madt_generic_translator *its_entry;struct fwnode_handle *dom_handle;struct its_node *its;struct resource res;int err;struct acpi_madt_generic_translator *)header;0 , sizeof (res));1 ;if (!dom_handle) {"ITS@%pa: Unable to allocate GICv3 ITS domain token\n" ,return -ENOMEM;if (err) {"ITS@%pa: Unable to register GICv3 ITS domain token (ITS ID %d) to IORT\n" ,goto dom_err;if (!its) {goto node_err;if (acpi_get_madt_revision() >= 7 &&if (!err)return 0 ;return err;static int __init its_acpi_reset(union acpi_subtable_headers *header,const unsigned long end)struct acpi_madt_generic_translator *its_entry;struct resource res;struct acpi_madt_generic_translator *)header;struct resource) {1 ,return its_reset_one(&res);static void __init its_acpi_probe(void )/* * Make sure * all * the ITS are reset before we probe any , as * they may be sharing memory . If any of the ITS fails to * reset , don ' t even try to go any further , as this could * result in something even worse . if (acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_TRANSLATOR,0 ) > 0 )0 );#else static void __init its_acpi_probe(void ) { }#endif int __init its_lpi_memreserve_init(void )int state;if (!efi_enabled(EFI_CONFIG_TABLES))return 0 ;if (list_empty(&its_nodes))return 0 ;"irqchip/arm/gicv3/memreserve:online" ,if (state < 0 )return state;return 0 ;int __init its_init(struct fwnode_handle *handle, struct rdists *rdists,struct irq_domain *parent_domain, u8 irq_prio)struct device_node *of_node;struct its_node *its;bool has_v4 = false ;bool has_v4_1 = false ;int err;1 );if (!itt_pool)return -ENOMEM;if (of_node)else if (list_empty(&its_nodes)) {"ITS: No ITS available, not enabling LPIs\n" );return -ENXIO;if (err)return err;/* Don't bother with inconsistent systems */ if (WARN_ON(!has_v4_1 && rdists->has_rvpeid))false ;if (has_v4 & rdists->has_vlpis) {const struct irq_domain_ops *sgi_ops;if (has_v4_1)else if (its_init_vpe_domain() ||false ;"ITS: Disabling GICv4 support\n" );return 0 ;
Messung V0.5 in Prozent C=97 H=95 G=95
¤ Dauer der Verarbeitung: 0.147 Sekunden
(vorverarbeitet am 2026-09-29)
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2026-10-10
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