Quelle t4fw_ri_api.h
Sprache: C
/* * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved. * * This software is available to you under a choice of one of two * licenses. You may choose to be licensed under the terms of the GNU * General Public License (GPL) Version 2, available from the file * COPYING in the main directory of this source tree, or the * OpenIB.org BSD license below: * * Redistribution and use in source and binary forms, with or * without modification, are permitted provided that the following * conditions are met: * * - Redistributions of source code must retain the above * copyright notice, this list of conditions and the following * disclaimer. * - Redistributions in binary form must reproduce the above * copyright notice, this list of conditions and the following * disclaimer in the documentation and/or other materials * provided with the distribution. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. #ifndef _T4FW_RI_API_H_#define _T4FW_RI_API_H_#include "t4fw_api.h" enum fw_ri_wr_opcode {/* IETF RDMAP v1.0 ... */ /* CHELSIO RI specific ... */ enum fw_ri_wr_flags {enum fw_ri_mpa_attrs {enum fw_ri_qp_caps {enum fw_ri_addr_type {enum fw_ri_mem_perms {enum fw_ri_stag_type {enum fw_ri_data_op {enum fw_ri_sgl_depth {struct fw_ri_dsge_pair {struct fw_ri_dsgl {struct fw_ri_dsge_pair sge[];struct fw_ri_sge {struct fw_ri_isgl {struct fw_ri_sge sge[];struct fw_ri_immd {struct fw_ri_tpte {#define FW_RI_TPTE_VALID_S 31#define FW_RI_TPTE_VALID_M 0x1#define FW_RI_TPTE_VALID_V(x) ((x) << FW_RI_TPTE_VALID_S)#define FW_RI_TPTE_VALID_G(x) \#define FW_RI_TPTE_VALID_F FW_RI_TPTE_VALID_V(1U)#define FW_RI_TPTE_STAGKEY_S 23#define FW_RI_TPTE_STAGKEY_M 0xff#define FW_RI_TPTE_STAGKEY_V(x) ((x) << FW_RI_TPTE_STAGKEY_S)#define FW_RI_TPTE_STAGKEY_G(x) \#define FW_RI_TPTE_STAGSTATE_S 22#define FW_RI_TPTE_STAGSTATE_M 0x1#define FW_RI_TPTE_STAGSTATE_V(x) ((x) << FW_RI_TPTE_STAGSTATE_S)#define FW_RI_TPTE_STAGSTATE_G(x) \#define FW_RI_TPTE_STAGSTATE_F FW_RI_TPTE_STAGSTATE_V(1U)#define FW_RI_TPTE_STAGTYPE_S 20#define FW_RI_TPTE_STAGTYPE_M 0x3#define FW_RI_TPTE_STAGTYPE_V(x) ((x) << FW_RI_TPTE_STAGTYPE_S)#define FW_RI_TPTE_STAGTYPE_G(x) \#define FW_RI_TPTE_PDID_S 0#define FW_RI_TPTE_PDID_M 0xfffff#define FW_RI_TPTE_PDID_V(x) ((x) << FW_RI_TPTE_PDID_S)#define FW_RI_TPTE_PDID_G(x) \#define FW_RI_TPTE_PERM_S 28#define FW_RI_TPTE_PERM_M 0xf#define FW_RI_TPTE_PERM_V(x) ((x) << FW_RI_TPTE_PERM_S)#define FW_RI_TPTE_PERM_G(x) \#define FW_RI_TPTE_REMINVDIS_S 27#define FW_RI_TPTE_REMINVDIS_M 0x1#define FW_RI_TPTE_REMINVDIS_V(x) ((x) << FW_RI_TPTE_REMINVDIS_S)#define FW_RI_TPTE_REMINVDIS_G(x) \#define FW_RI_TPTE_REMINVDIS_F FW_RI_TPTE_REMINVDIS_V(1U)#define FW_RI_TPTE_ADDRTYPE_S 26#define FW_RI_TPTE_ADDRTYPE_M 1#define FW_RI_TPTE_ADDRTYPE_V(x) ((x) << FW_RI_TPTE_ADDRTYPE_S)#define FW_RI_TPTE_ADDRTYPE_G(x) \#define FW_RI_TPTE_ADDRTYPE_F FW_RI_TPTE_ADDRTYPE_V(1U)#define FW_RI_TPTE_MWBINDEN_S 25#define FW_RI_TPTE_MWBINDEN_M 0x1#define FW_RI_TPTE_MWBINDEN_V(x) ((x) << FW_RI_TPTE_MWBINDEN_S)#define FW_RI_TPTE_MWBINDEN_G(x) \#define FW_RI_TPTE_MWBINDEN_F FW_RI_TPTE_MWBINDEN_V(1U)#define FW_RI_TPTE_PS_S 20#define FW_RI_TPTE_PS_M 0x1f#define FW_RI_TPTE_PS_V(x) ((x) << FW_RI_TPTE_PS_S)#define FW_RI_TPTE_PS_G(x) \#define FW_RI_TPTE_QPID_S 0#define FW_RI_TPTE_QPID_M 0xfffff#define FW_RI_TPTE_QPID_V(x) ((x) << FW_RI_TPTE_QPID_S)#define FW_RI_TPTE_QPID_G(x) \#define FW_RI_TPTE_NOSNOOP_S 30#define FW_RI_TPTE_NOSNOOP_M 0x1#define FW_RI_TPTE_NOSNOOP_V(x) ((x) << FW_RI_TPTE_NOSNOOP_S)#define FW_RI_TPTE_NOSNOOP_G(x) \#define FW_RI_TPTE_NOSNOOP_F FW_RI_TPTE_NOSNOOP_V(1U)#define FW_RI_TPTE_PBLADDR_S 0#define FW_RI_TPTE_PBLADDR_M 0x1fffffff#define FW_RI_TPTE_PBLADDR_V(x) ((x) << FW_RI_TPTE_PBLADDR_S)#define FW_RI_TPTE_PBLADDR_G(x) \#define FW_RI_TPTE_DCA_S 24#define FW_RI_TPTE_DCA_M 0x1f#define FW_RI_TPTE_DCA_V(x) ((x) << FW_RI_TPTE_DCA_S)#define FW_RI_TPTE_DCA_G(x) \#define FW_RI_TPTE_MWBCNT_PSTAG_S 0#define FW_RI_TPTE_MWBCNT_PSTAG_M 0xffffff#define FW_RI_TPTE_MWBCNT_PSTAT_V(x) \#define FW_RI_TPTE_MWBCNT_PSTAG_G(x) \enum fw_ri_res_type {enum fw_ri_res_op {struct fw_ri_res {union fw_ri_restype {struct fw_ri_res_sqrq {struct fw_ri_res_cq {struct fw_ri_res_srq {struct fw_ri_res_wr {struct fw_ri_res res[];#define FW_RI_RES_WR_NRES_S 0#define FW_RI_RES_WR_NRES_M 0xff#define FW_RI_RES_WR_NRES_V(x) ((x) << FW_RI_RES_WR_NRES_S)#define FW_RI_RES_WR_NRES_G(x) \#define FW_RI_RES_WR_FETCHSZM_S 26#define FW_RI_RES_WR_FETCHSZM_M 0x1#define FW_RI_RES_WR_FETCHSZM_V(x) ((x) << FW_RI_RES_WR_FETCHSZM_S)#define FW_RI_RES_WR_FETCHSZM_G(x) \#define FW_RI_RES_WR_FETCHSZM_F FW_RI_RES_WR_FETCHSZM_V(1U)#define FW_RI_RES_WR_STATUSPGNS_S 25#define FW_RI_RES_WR_STATUSPGNS_M 0x1#define FW_RI_RES_WR_STATUSPGNS_V(x) ((x) << FW_RI_RES_WR_STATUSPGNS_S)#define FW_RI_RES_WR_STATUSPGNS_G(x) \#define FW_RI_RES_WR_STATUSPGNS_F FW_RI_RES_WR_STATUSPGNS_V(1U)#define FW_RI_RES_WR_STATUSPGRO_S 24#define FW_RI_RES_WR_STATUSPGRO_M 0x1#define FW_RI_RES_WR_STATUSPGRO_V(x) ((x) << FW_RI_RES_WR_STATUSPGRO_S)#define FW_RI_RES_WR_STATUSPGRO_G(x) \#define FW_RI_RES_WR_STATUSPGRO_F FW_RI_RES_WR_STATUSPGRO_V(1U)#define FW_RI_RES_WR_FETCHNS_S 23#define FW_RI_RES_WR_FETCHNS_M 0x1#define FW_RI_RES_WR_FETCHNS_V(x) ((x) << FW_RI_RES_WR_FETCHNS_S)#define FW_RI_RES_WR_FETCHNS_G(x) \#define FW_RI_RES_WR_FETCHNS_F FW_RI_RES_WR_FETCHNS_V(1U)#define FW_RI_RES_WR_FETCHRO_S 22#define FW_RI_RES_WR_FETCHRO_M 0x1#define FW_RI_RES_WR_FETCHRO_V(x) ((x) << FW_RI_RES_WR_FETCHRO_S)#define FW_RI_RES_WR_FETCHRO_G(x) \#define FW_RI_RES_WR_FETCHRO_F FW_RI_RES_WR_FETCHRO_V(1U)#define FW_RI_RES_WR_HOSTFCMODE_S 20#define FW_RI_RES_WR_HOSTFCMODE_M 0x3#define FW_RI_RES_WR_HOSTFCMODE_V(x) ((x) << FW_RI_RES_WR_HOSTFCMODE_S)#define FW_RI_RES_WR_HOSTFCMODE_G(x) \#define FW_RI_RES_WR_CPRIO_S 19#define FW_RI_RES_WR_CPRIO_M 0x1#define FW_RI_RES_WR_CPRIO_V(x) ((x) << FW_RI_RES_WR_CPRIO_S)#define FW_RI_RES_WR_CPRIO_G(x) \#define FW_RI_RES_WR_CPRIO_F FW_RI_RES_WR_CPRIO_V(1U)#define FW_RI_RES_WR_ONCHIP_S 18#define FW_RI_RES_WR_ONCHIP_M 0x1#define FW_RI_RES_WR_ONCHIP_V(x) ((x) << FW_RI_RES_WR_ONCHIP_S)#define FW_RI_RES_WR_ONCHIP_G(x) \#define FW_RI_RES_WR_ONCHIP_F FW_RI_RES_WR_ONCHIP_V(1U)#define FW_RI_RES_WR_PCIECHN_S 16#define FW_RI_RES_WR_PCIECHN_M 0x3#define FW_RI_RES_WR_PCIECHN_V(x) ((x) << FW_RI_RES_WR_PCIECHN_S)#define FW_RI_RES_WR_PCIECHN_G(x) \#define FW_RI_RES_WR_IQID_S 0#define FW_RI_RES_WR_IQID_M 0xffff#define FW_RI_RES_WR_IQID_V(x) ((x) << FW_RI_RES_WR_IQID_S)#define FW_RI_RES_WR_IQID_G(x) \#define FW_RI_RES_WR_DCAEN_S 31#define FW_RI_RES_WR_DCAEN_M 0x1#define FW_RI_RES_WR_DCAEN_V(x) ((x) << FW_RI_RES_WR_DCAEN_S)#define FW_RI_RES_WR_DCAEN_G(x) \#define FW_RI_RES_WR_DCAEN_F FW_RI_RES_WR_DCAEN_V(1U)#define FW_RI_RES_WR_DCACPU_S 26#define FW_RI_RES_WR_DCACPU_M 0x1f#define FW_RI_RES_WR_DCACPU_V(x) ((x) << FW_RI_RES_WR_DCACPU_S)#define FW_RI_RES_WR_DCACPU_G(x) \#define FW_RI_RES_WR_FBMIN_S 23#define FW_RI_RES_WR_FBMIN_M 0x7#define FW_RI_RES_WR_FBMIN_V(x) ((x) << FW_RI_RES_WR_FBMIN_S)#define FW_RI_RES_WR_FBMIN_G(x) \#define FW_RI_RES_WR_FBMAX_S 20#define FW_RI_RES_WR_FBMAX_M 0x7#define FW_RI_RES_WR_FBMAX_V(x) ((x) << FW_RI_RES_WR_FBMAX_S)#define FW_RI_RES_WR_FBMAX_G(x) \#define FW_RI_RES_WR_CIDXFTHRESHO_S 19#define FW_RI_RES_WR_CIDXFTHRESHO_M 0x1#define FW_RI_RES_WR_CIDXFTHRESHO_V(x) ((x) << FW_RI_RES_WR_CIDXFTHRESHO_S)#define FW_RI_RES_WR_CIDXFTHRESHO_G(x) \#define FW_RI_RES_WR_CIDXFTHRESHO_F FW_RI_RES_WR_CIDXFTHRESHO_V(1U)#define FW_RI_RES_WR_CIDXFTHRESH_S 16#define FW_RI_RES_WR_CIDXFTHRESH_M 0x7#define FW_RI_RES_WR_CIDXFTHRESH_V(x) ((x) << FW_RI_RES_WR_CIDXFTHRESH_S)#define FW_RI_RES_WR_CIDXFTHRESH_G(x) \#define FW_RI_RES_WR_EQSIZE_S 0#define FW_RI_RES_WR_EQSIZE_M 0xffff#define FW_RI_RES_WR_EQSIZE_V(x) ((x) << FW_RI_RES_WR_EQSIZE_S)#define FW_RI_RES_WR_EQSIZE_G(x) \#define FW_RI_RES_WR_IQANDST_S 15#define FW_RI_RES_WR_IQANDST_M 0x1#define FW_RI_RES_WR_IQANDST_V(x) ((x) << FW_RI_RES_WR_IQANDST_S)#define FW_RI_RES_WR_IQANDST_G(x) \#define FW_RI_RES_WR_IQANDST_F FW_RI_RES_WR_IQANDST_V(1U)#define FW_RI_RES_WR_IQANUS_S 14#define FW_RI_RES_WR_IQANUS_M 0x1#define FW_RI_RES_WR_IQANUS_V(x) ((x) << FW_RI_RES_WR_IQANUS_S)#define FW_RI_RES_WR_IQANUS_G(x) \#define FW_RI_RES_WR_IQANUS_F FW_RI_RES_WR_IQANUS_V(1U)#define FW_RI_RES_WR_IQANUD_S 12#define FW_RI_RES_WR_IQANUD_M 0x3#define FW_RI_RES_WR_IQANUD_V(x) ((x) << FW_RI_RES_WR_IQANUD_S)#define FW_RI_RES_WR_IQANUD_G(x) \#define FW_RI_RES_WR_IQANDSTINDEX_S 0#define FW_RI_RES_WR_IQANDSTINDEX_M 0xfff#define FW_RI_RES_WR_IQANDSTINDEX_V(x) ((x) << FW_RI_RES_WR_IQANDSTINDEX_S)#define FW_RI_RES_WR_IQANDSTINDEX_G(x) \#define FW_RI_RES_WR_IQDROPRSS_S 15#define FW_RI_RES_WR_IQDROPRSS_M 0x1#define FW_RI_RES_WR_IQDROPRSS_V(x) ((x) << FW_RI_RES_WR_IQDROPRSS_S)#define FW_RI_RES_WR_IQDROPRSS_G(x) \#define FW_RI_RES_WR_IQDROPRSS_F FW_RI_RES_WR_IQDROPRSS_V(1U)#define FW_RI_RES_WR_IQGTSMODE_S 14#define FW_RI_RES_WR_IQGTSMODE_M 0x1#define FW_RI_RES_WR_IQGTSMODE_V(x) ((x) << FW_RI_RES_WR_IQGTSMODE_S)#define FW_RI_RES_WR_IQGTSMODE_G(x) \#define FW_RI_RES_WR_IQGTSMODE_F FW_RI_RES_WR_IQGTSMODE_V(1U)#define FW_RI_RES_WR_IQPCIECH_S 12#define FW_RI_RES_WR_IQPCIECH_M 0x3#define FW_RI_RES_WR_IQPCIECH_V(x) ((x) << FW_RI_RES_WR_IQPCIECH_S)#define FW_RI_RES_WR_IQPCIECH_G(x) \#define FW_RI_RES_WR_IQDCAEN_S 11#define FW_RI_RES_WR_IQDCAEN_M 0x1#define FW_RI_RES_WR_IQDCAEN_V(x) ((x) << FW_RI_RES_WR_IQDCAEN_S)#define FW_RI_RES_WR_IQDCAEN_G(x) \#define FW_RI_RES_WR_IQDCAEN_F FW_RI_RES_WR_IQDCAEN_V(1U)#define FW_RI_RES_WR_IQDCACPU_S 6#define FW_RI_RES_WR_IQDCACPU_M 0x1f#define FW_RI_RES_WR_IQDCACPU_V(x) ((x) << FW_RI_RES_WR_IQDCACPU_S)#define FW_RI_RES_WR_IQDCACPU_G(x) \#define FW_RI_RES_WR_IQINTCNTTHRESH_S 4#define FW_RI_RES_WR_IQINTCNTTHRESH_M 0x3#define FW_RI_RES_WR_IQINTCNTTHRESH_V(x) \#define FW_RI_RES_WR_IQINTCNTTHRESH_G(x) \#define FW_RI_RES_WR_IQO_S 3#define FW_RI_RES_WR_IQO_M 0x1#define FW_RI_RES_WR_IQO_V(x) ((x) << FW_RI_RES_WR_IQO_S)#define FW_RI_RES_WR_IQO_G(x) \#define FW_RI_RES_WR_IQO_F FW_RI_RES_WR_IQO_V(1U)#define FW_RI_RES_WR_IQCPRIO_S 2#define FW_RI_RES_WR_IQCPRIO_M 0x1#define FW_RI_RES_WR_IQCPRIO_V(x) ((x) << FW_RI_RES_WR_IQCPRIO_S)#define FW_RI_RES_WR_IQCPRIO_G(x) \#define FW_RI_RES_WR_IQCPRIO_F FW_RI_RES_WR_IQCPRIO_V(1U)#define FW_RI_RES_WR_IQESIZE_S 0#define FW_RI_RES_WR_IQESIZE_M 0x3#define FW_RI_RES_WR_IQESIZE_V(x) ((x) << FW_RI_RES_WR_IQESIZE_S)#define FW_RI_RES_WR_IQESIZE_G(x) \#define FW_RI_RES_WR_IQNS_S 31#define FW_RI_RES_WR_IQNS_M 0x1#define FW_RI_RES_WR_IQNS_V(x) ((x) << FW_RI_RES_WR_IQNS_S)#define FW_RI_RES_WR_IQNS_G(x) \#define FW_RI_RES_WR_IQNS_F FW_RI_RES_WR_IQNS_V(1U)#define FW_RI_RES_WR_IQRO_S 30#define FW_RI_RES_WR_IQRO_M 0x1#define FW_RI_RES_WR_IQRO_V(x) ((x) << FW_RI_RES_WR_IQRO_S)#define FW_RI_RES_WR_IQRO_G(x) \#define FW_RI_RES_WR_IQRO_F FW_RI_RES_WR_IQRO_V(1U)struct fw_ri_rdma_write_wr {/* * Use union for immediate data to be consistent with stack's 32 bit * data and iWARP spec's 64 bit data. union {struct {union {struct fw_ri_immd, immd_src);struct fw_ri_isgl, isgl_src);struct fw_ri_send_wr {union {struct fw_ri_immd, immd_src);struct fw_ri_isgl, isgl_src);#define FW_RI_SEND_WR_SENDOP_S 0#define FW_RI_SEND_WR_SENDOP_M 0xf#define FW_RI_SEND_WR_SENDOP_V(x) ((x) << FW_RI_SEND_WR_SENDOP_S)#define FW_RI_SEND_WR_SENDOP_G(x) \struct fw_ri_rdma_write_cmpl_wr {union fw_ri_cmpl {struct fw_ri_immd_cmpl {struct fw_ri_isgl isgl_src;union fw_ri_write {struct fw_ri_immd, immd_src);struct fw_ri_isgl, isgl_src);struct fw_ri_rdma_read_wr {struct fw_ri_recv_wr {struct fw_ri_isgl isgl;struct fw_ri_bind_mw_wr {#define FW_RI_BIND_MW_WR_QPBINDE_S 6#define FW_RI_BIND_MW_WR_QPBINDE_M 0x1#define FW_RI_BIND_MW_WR_QPBINDE_V(x) ((x) << FW_RI_BIND_MW_WR_QPBINDE_S)#define FW_RI_BIND_MW_WR_QPBINDE_G(x) \#define FW_RI_BIND_MW_WR_QPBINDE_F FW_RI_BIND_MW_WR_QPBINDE_V(1U)#define FW_RI_BIND_MW_WR_NS_S 5#define FW_RI_BIND_MW_WR_NS_M 0x1#define FW_RI_BIND_MW_WR_NS_V(x) ((x) << FW_RI_BIND_MW_WR_NS_S)#define FW_RI_BIND_MW_WR_NS_G(x) \#define FW_RI_BIND_MW_WR_NS_F FW_RI_BIND_MW_WR_NS_V(1U)#define FW_RI_BIND_MW_WR_DCACPU_S 0#define FW_RI_BIND_MW_WR_DCACPU_M 0x1f#define FW_RI_BIND_MW_WR_DCACPU_V(x) ((x) << FW_RI_BIND_MW_WR_DCACPU_S)#define FW_RI_BIND_MW_WR_DCACPU_G(x) \struct fw_ri_fr_nsmr_wr {#define FW_RI_FR_NSMR_WR_QPBINDE_S 6#define FW_RI_FR_NSMR_WR_QPBINDE_M 0x1#define FW_RI_FR_NSMR_WR_QPBINDE_V(x) ((x) << FW_RI_FR_NSMR_WR_QPBINDE_S)#define FW_RI_FR_NSMR_WR_QPBINDE_G(x) \#define FW_RI_FR_NSMR_WR_QPBINDE_F FW_RI_FR_NSMR_WR_QPBINDE_V(1U)#define FW_RI_FR_NSMR_WR_NS_S 5#define FW_RI_FR_NSMR_WR_NS_M 0x1#define FW_RI_FR_NSMR_WR_NS_V(x) ((x) << FW_RI_FR_NSMR_WR_NS_S)#define FW_RI_FR_NSMR_WR_NS_G(x) \#define FW_RI_FR_NSMR_WR_NS_F FW_RI_FR_NSMR_WR_NS_V(1U)#define FW_RI_FR_NSMR_WR_DCACPU_S 0#define FW_RI_FR_NSMR_WR_DCACPU_M 0x1f#define FW_RI_FR_NSMR_WR_DCACPU_V(x) ((x) << FW_RI_FR_NSMR_WR_DCACPU_S)#define FW_RI_FR_NSMR_WR_DCACPU_G(x) \struct fw_ri_fr_nsmr_tpte_wr {struct fw_ri_tpte tpte;struct fw_ri_inv_lstag_wr {enum fw_ri_type {enum fw_ri_init_p2ptype {enum fw_ri_init_rqeqid_srq {struct fw_ri_wr {union fw_ri {struct fw_ri_init {union fw_ri_init_p2p {struct fw_ri_rdma_write_wr write;struct fw_ri_rdma_read_wr read;struct fw_ri_send_wr send;struct fw_ri_fini {struct fw_ri_terminate {#define FW_RI_WR_MPAREQBIT_S 7#define FW_RI_WR_MPAREQBIT_M 0x1#define FW_RI_WR_MPAREQBIT_V(x) ((x) << FW_RI_WR_MPAREQBIT_S)#define FW_RI_WR_MPAREQBIT_G(x) \#define FW_RI_WR_MPAREQBIT_F FW_RI_WR_MPAREQBIT_V(1U)#define FW_RI_WR_P2PTYPE_S 0#define FW_RI_WR_P2PTYPE_M 0xf#define FW_RI_WR_P2PTYPE_V(x) ((x) << FW_RI_WR_P2PTYPE_S)#define FW_RI_WR_P2PTYPE_G(x) \#endif /* _T4FW_RI_API_H_ */
Messung V0.5 C=100 H=100 G=100
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2026-04-07
