ret = regmap_read(regmap, RM3100_REG_STATUS, &val); if (ret < 0) return ret;
if ((val & RM3100_STATUS_DRDY) != RM3100_STATUS_DRDY) { if (data->use_interrupt) {
ret = wait_for_completion_timeout(&data->measuring_done,
msecs_to_jiffies(data->conversion_time)); if (!ret) return -ETIMEDOUT;
} else { do {
usleep_range(1000, 5000);
ret = regmap_read(regmap, RM3100_REG_STATUS,
&val); if (ret < 0) return ret;
if (val & RM3100_STATUS_DRDY) break;
} while (--tries); if (!tries) return -ETIMEDOUT;
}
} return0;
}
staticint rm3100_read_mag(struct rm3100_data *data, int idx, int *val)
{ struct regmap *regmap = data->regmap;
u8 buffer[3]; int ret;
mutex_lock(&data->lock);
ret = regmap_write(regmap, RM3100_REG_POLL, BIT(4 + idx)); if (ret < 0) goto unlock_return;
ret = rm3100_wait_measurement(data); if (ret < 0) goto unlock_return;
ret = regmap_bulk_read(regmap, RM3100_REG_MX2 + 3 * idx, buffer, 3); if (ret < 0) goto unlock_return;
mutex_unlock(&data->lock);
staticint rm3100_set_samp_freq(struct iio_dev *indio_dev, int val, int val2)
{ struct rm3100_data *data = iio_priv(indio_dev); struct regmap *regmap = data->regmap; unsignedint cycle_count; int ret; int i;
mutex_lock(&data->lock); /* All cycle count registers use the same value. */
ret = regmap_read(regmap, RM3100_REG_CC_X, &cycle_count); if (ret < 0) goto unlock_return;
for (i = 0; i < RM3100_SAMP_NUM; i++) { if (val == rm3100_samp_rates[i][0] &&
val2 == rm3100_samp_rates[i][1]) break;
} if (i == RM3100_SAMP_NUM) {
ret = -EINVAL; goto unlock_return;
}
ret = regmap_write(regmap, RM3100_REG_TMRC, i + RM3100_TMRC_OFFSET); if (ret < 0) goto unlock_return;
/* Checking if cycle count registers need changing. */ if (val == 600 && cycle_count == 200) {
ret = rm3100_set_cycle_count(data, 100); if (ret < 0) goto unlock_return;
} elseif (val != 600 && cycle_count == 100) {
ret = rm3100_set_cycle_count(data, 200); if (ret < 0) goto unlock_return;
}
if (iio_buffer_enabled(indio_dev)) { /* Writing TMRC registers requires CMM reset. */
ret = regmap_write(regmap, RM3100_REG_CMM, 0); if (ret < 0) goto unlock_return;
ret = regmap_write(data->regmap, RM3100_REG_CMM,
(*indio_dev->active_scan_mask & 0x7) <<
RM3100_CMM_AXIS_SHIFT | RM3100_CMM_START); if (ret < 0) goto unlock_return;
}
mutex_unlock(&data->lock);
if (!irq)
data->use_interrupt = false; else {
data->use_interrupt = true;
init_completion(&data->measuring_done);
ret = devm_request_threaded_irq(dev,
irq,
rm3100_irq_handler,
rm3100_thread_fn,
IRQF_TRIGGER_HIGH |
IRQF_ONESHOT,
indio_dev->name,
indio_dev); if (ret < 0) {
dev_err(dev, "request irq line failed.\n"); return ret;
}
data->drdy_trig = devm_iio_trigger_alloc(dev, "%s-drdy%d",
indio_dev->name,
iio_device_id(indio_dev)); if (!data->drdy_trig) return -ENOMEM;
ret = devm_iio_trigger_register(dev, data->drdy_trig); if (ret < 0) return ret;
}
ret = devm_iio_triggered_buffer_setup(dev, indio_dev,
&iio_pollfunc_store_time,
rm3100_trigger_handler,
&rm3100_buffer_ops); if (ret < 0) return ret;
ret = regmap_read(regmap, RM3100_REG_TMRC, &tmp); if (ret < 0) return ret;
samp_rate_index = tmp - RM3100_TMRC_OFFSET; if (samp_rate_index < 0 || samp_rate_index >= RM3100_SAMP_NUM) {
dev_err(dev, "The value read from RM3100_REG_TMRC is invalid!\n"); return -EINVAL;
} /* Initializing max wait time, which is double conversion time. */
data->conversion_time = rm3100_samp_rates[samp_rate_index][2] * 2;
/* Cycle count values may not be what we want. */ if ((tmp - RM3100_TMRC_OFFSET) == 0)
rm3100_set_cycle_count(data, 100); else
rm3100_set_cycle_count(data, 200);
Die Informationen auf dieser Webseite wurden
nach bestem Wissen sorgfältig zusammengestellt. Es wird jedoch weder Vollständigkeit, noch Richtigkeit,
noch Qualität der bereit gestellten Informationen zugesichert.
Bemerkung:
Die farbliche Syntaxdarstellung und die Messung sind noch experimentell.