// SPDX-License-Identifier: GPL-2.0-only /* * DRM driver for Solomon SSD13xx OLED displays * * Copyright 2022 Red Hat Inc . * Author : Javier Martinez Canillas < javierm @ redhat . com > * * Based on drivers / video / fbdev / ssd1307fb . c * Copyright 2012 Free Electrons #include <linux/backlight.h>#include <linux/bitfield.h>#include <linux/bits.h>#include <linux/delay.h>#include <linux/gpio/consumer.h>#include <linux/property.h>#include <linux/pwm.h>#include <linux/regulator/consumer.h>#include <drm/clients/drm_client_setup.h>#include <drm/drm_atomic.h>#include <drm/drm_atomic_helper.h>#include <drm/drm_crtc_helper.h>#include <drm/drm_damage_helper.h>#include <drm/drm_edid.h>#include <drm/drm_fbdev_shmem.h>#include <drm/drm_format_helper.h>#include <drm/drm_framebuffer.h>#include <drm/drm_gem_atomic_helper.h>#include <drm/drm_gem_framebuffer_helper.h>#include <drm/drm_gem_shmem_helper.h>#include <drm/drm_managed.h>#include <drm/drm_modes.h>#include <drm/drm_rect.h>#include <drm/drm_probe_helper.h>#include "ssd130x.h" #define DRIVER_NAME "ssd130x" #define DRIVER_DESC "DRM driver for Solomon SSD13xx OLED displays" #define DRIVER_MAJOR 1 #define DRIVER_MINOR 0 #define SSD130X_PAGE_HEIGHT 8 #define SSD132X_SEGMENT_WIDTH 2 /* ssd13xx commands */ #define SSD13XX_CONTRAST 0 x81#define SSD13XX_SET_SEG_REMAP 0 xa0#define SSD13XX_SET_MULTIPLEX_RATIO 0 xa8#define SSD13XX_DISPLAY_OFF 0 xae#define SSD13XX_DISPLAY_ON 0 xaf#define SSD13XX_SET_SEG_REMAP_MASK GENMASK(0 , 0 )#define SSD13XX_SET_SEG_REMAP_SET(val) FIELD_PREP(SSD13XX_SET_SEG_REMAP_MASK, (val))/* ssd130x commands */ #define SSD130X_PAGE_COL_START_LOW 0 x00#define SSD130X_PAGE_COL_START_HIGH 0 x10#define SSD130X_SET_ADDRESS_MODE 0 x20#define SSD130X_SET_COL_RANGE 0 x21#define SSD130X_SET_PAGE_RANGE 0 x22#define SSD130X_SET_LOOKUP_TABLE 0 x91#define SSD130X_CHARGE_PUMP 0 x8d#define SSD130X_START_PAGE_ADDRESS 0 xb0#define SSD130X_SET_COM_SCAN_DIR 0 xc0#define SSD130X_SET_DISPLAY_OFFSET 0 xd3#define SSD130X_SET_CLOCK_FREQ 0 xd5#define SSD130X_SET_AREA_COLOR_MODE 0 xd8#define SSD130X_SET_PRECHARGE_PERIOD 0 xd9#define SSD130X_SET_COM_PINS_CONFIG 0 xda#define SSD130X_SET_VCOMH 0 xdb/* ssd130x commands accessors */ #define SSD130X_PAGE_COL_START_MASK GENMASK(3 , 0 )#define SSD130X_PAGE_COL_START_HIGH_SET(val) FIELD_PREP(SSD130X_PAGE_COL_START_MASK, (val) >> 4 )#define SSD130X_PAGE_COL_START_LOW_SET(val) FIELD_PREP(SSD130X_PAGE_COL_START_MASK, (val))#define SSD130X_START_PAGE_ADDRESS_MASK GENMASK(2 , 0 )#define SSD130X_START_PAGE_ADDRESS_SET(val) FIELD_PREP(SSD130X_START_PAGE_ADDRESS_MASK, (val))#define SSD130X_SET_COM_SCAN_DIR_MASK GENMASK(3 , 3 )#define SSD130X_SET_COM_SCAN_DIR_SET(val) FIELD_PREP(SSD130X_SET_COM_SCAN_DIR_MASK, (val))#define SSD130X_SET_CLOCK_DIV_MASK GENMASK(3 , 0 )#define SSD130X_SET_CLOCK_DIV_SET(val) FIELD_PREP(SSD130X_SET_CLOCK_DIV_MASK, (val))#define SSD130X_SET_CLOCK_FREQ_MASK GENMASK(7 , 4 )#define SSD130X_SET_CLOCK_FREQ_SET(val) FIELD_PREP(SSD130X_SET_CLOCK_FREQ_MASK, (val))#define SSD130X_SET_PRECHARGE_PERIOD1_MASK GENMASK(3 , 0 )#define SSD130X_SET_PRECHARGE_PERIOD1_SET(val) FIELD_PREP(SSD130X_SET_PRECHARGE_PERIOD1_MASK, (val))#define SSD130X_SET_PRECHARGE_PERIOD2_MASK GENMASK(7 , 4 )#define SSD130X_SET_PRECHARGE_PERIOD2_SET(val) FIELD_PREP(SSD130X_SET_PRECHARGE_PERIOD2_MASK, (val))#define SSD130X_SET_COM_PINS_CONFIG1_MASK GENMASK(4 , 4 )#define SSD130X_SET_COM_PINS_CONFIG1_SET(val) FIELD_PREP(SSD130X_SET_COM_PINS_CONFIG1_MASK, (val))#define SSD130X_SET_COM_PINS_CONFIG2_MASK GENMASK(5 , 5 )#define SSD130X_SET_COM_PINS_CONFIG2_SET(val) FIELD_PREP(SSD130X_SET_COM_PINS_CONFIG2_MASK, (val))#define SSD130X_SET_ADDRESS_MODE_HORIZONTAL 0 x00#define SSD130X_SET_ADDRESS_MODE_VERTICAL 0 x01#define SSD130X_SET_ADDRESS_MODE_PAGE 0 x02#define SSD130X_SET_AREA_COLOR_MODE_ENABLE 0 x1e#define SSD130X_SET_AREA_COLOR_MODE_LOW_POWER 0 x05/* ssd132x commands */ #define SSD132X_SET_COL_RANGE 0 x15#define SSD132X_SET_DEACTIVATE_SCROLL 0 x2e#define SSD132X_SET_ROW_RANGE 0 x75#define SSD132X_SET_DISPLAY_START 0 xa1#define SSD132X_SET_DISPLAY_OFFSET 0 xa2#define SSD132X_SET_DISPLAY_NORMAL 0 xa4#define SSD132X_SET_FUNCTION_SELECT_A 0 xab#define SSD132X_SET_PHASE_LENGTH 0 xb1#define SSD132X_SET_CLOCK_FREQ 0 xb3#define SSD132X_SET_GPIO 0 xb5#define SSD132X_SET_PRECHARGE_PERIOD 0 xb6#define SSD132X_SET_GRAY_SCALE_TABLE 0 xb8#define SSD132X_SELECT_DEFAULT_TABLE 0 xb9#define SSD132X_SET_PRECHARGE_VOLTAGE 0 xbc#define SSD130X_SET_VCOMH_VOLTAGE 0 xbe#define SSD132X_SET_FUNCTION_SELECT_B 0 xd5/* ssd133x commands */ #define SSD133X_SET_COL_RANGE 0 x15#define SSD133X_SET_ROW_RANGE 0 x75#define SSD133X_CONTRAST_A 0 x81#define SSD133X_CONTRAST_B 0 x82#define SSD133X_CONTRAST_C 0 x83#define SSD133X_SET_MASTER_CURRENT 0 x87#define SSD132X_SET_PRECHARGE_A 0 x8a#define SSD132X_SET_PRECHARGE_B 0 x8b#define SSD132X_SET_PRECHARGE_C 0 x8c#define SSD133X_SET_DISPLAY_START 0 xa1#define SSD133X_SET_DISPLAY_OFFSET 0 xa2#define SSD133X_SET_DISPLAY_NORMAL 0 xa4#define SSD133X_SET_MASTER_CONFIG 0 xad#define SSD133X_POWER_SAVE_MODE 0 xb0#define SSD133X_PHASES_PERIOD 0 xb1#define SSD133X_SET_CLOCK_FREQ 0 xb3#define SSD133X_SET_PRECHARGE_VOLTAGE 0 xbb#define SSD133X_SET_VCOMH_VOLTAGE 0 xbe#define MAX_CONTRAST 255 const struct ssd130x_deviceinfo ssd130x_variants[] = {0 x40,1 ,5 ,132 ,64 ,1 ,0 x34,1 ,7 ,132 ,64 ,0 x20,1 ,8 ,1 ,128 ,64 ,0 x20,2 ,12 ,1 ,128 ,39 ,0 x34,1 ,10 ,128 ,64 ,/* ssd132x family */ 480 ,128 ,128 ,80 ,128 ,128 ,/* ssd133x family */ 96 ,64 ,"DRM_SSD130X" );struct ssd130x_crtc_state {struct drm_crtc_state base;/* Buffer to store pixels in HW format and written to the panel */ struct ssd130x_plane_state {struct drm_shadow_plane_state base;/* Intermediate buffer to convert pixels from XRGB8888 to HW format */ static inline struct ssd130x_crtc_state *to_ssd130x_crtc_state(struct drm_crtc_state *state)return container_of(state, struct ssd130x_crtc_state, base);static inline struct ssd130x_plane_state *to_ssd130x_plane_state(struct drm_plane_state *state)return container_of(state, struct ssd130x_plane_state, base.base);static inline struct ssd130x_device *drm_to_ssd130x(struct drm_device *drm)return container_of(drm, struct ssd130x_device, drm);/* * Helper to write data ( SSD13XX_DATA ) to the device . static int ssd130x_write_data(struct ssd130x_device *ssd130x, u8 *values, int count)return regmap_bulk_write(ssd130x->regmap, SSD13XX_DATA, values, count);/* * Helper to write command ( SSD13XX_COMMAND ) . The fist variadic argument * is the command to write and the following are the command options . * * Note that the ssd13xx protocol requires each command and option to be * written as a SSD13XX_COMMAND device register value . That is why a call * to regmap_write ( . . . , SSD13XX_COMMAND , . . . ) is done for each argument . static int ssd130x_write_cmd(struct ssd130x_device *ssd130x, int count,/* u8 cmd, u8 option, ... */...) int ret;do {int );if (ret)goto out_end;while (--count);return ret;/* Set address range for horizontal/vertical addressing modes */ static int ssd130x_set_col_range(struct ssd130x_device *ssd130x,1 ;int ret;if (col_start == ssd130x->col_start && col_end == ssd130x->col_end)return 0 ;3 , SSD130X_SET_COL_RANGE, col_start, col_end);if (ret < 0 )return ret;return 0 ;static int ssd130x_set_page_range(struct ssd130x_device *ssd130x,1 ;int ret;if (page_start == ssd130x->page_start && page_end == ssd130x->page_end)return 0 ;3 , SSD130X_SET_PAGE_RANGE, page_start, page_end);if (ret < 0 )return ret;return 0 ;/* Set page and column start address for page addressing mode */ static int ssd130x_set_page_pos(struct ssd130x_device *ssd130x,int ret;3 , page, col_low, col_high);if (ret < 0 )return ret;return 0 ;static int ssd130x_pwm_enable(struct ssd130x_device *ssd130x)struct device *dev = ssd130x->dev;struct pwm_state pwmstate;if (IS_ERR(ssd130x->pwm)) {"Could not get PWM from firmware description!\n" );return PTR_ERR(ssd130x->pwm);50 , 100 );/* Enable the PWM */ "Using PWM %s with a %lluns period.\n" ,return 0 ;static void ssd130x_reset(struct ssd130x_device *ssd130x)if (!ssd130x->reset)return ;/* Reset the screen */ 1 );4 );0 );4 );static int ssd130x_power_on(struct ssd130x_device *ssd130x)struct device *dev = ssd130x->dev;int ret;if (ret) {"Failed to enable VCC: %d\n" , ret);return ret;if (ssd130x->device_info->need_pwm) {if (ret) {"Failed to enable PWM: %d\n" , ret);return ret;return 0 ;static void ssd130x_power_off(struct ssd130x_device *ssd130x)static int ssd130x_init(struct ssd130x_device *ssd130x)bool scan_mode;int ret;/* Set initial contrast */ 2 , SSD13XX_CONTRAST, ssd130x->contrast);if (ret < 0 )return ret;/* Set segment re-map */ 1 , seg_remap);if (ret < 0 )return ret;/* Set COM direction */ 1 , com_invdir);if (ret < 0 )return ret;/* Set multiplex ratio value */ 2 , SSD13XX_SET_MULTIPLEX_RATIO, ssd130x->height - 1 );if (ret < 0 )return ret;/* set display offset value */ 2 , SSD130X_SET_DISPLAY_OFFSET, ssd130x->com_offset);if (ret < 0 )return ret;/* Set clock frequency */ 1 ) |2 , SSD130X_SET_CLOCK_FREQ, dclk);if (ret < 0 )return ret;/* Set Area Color Mode ON/OFF & Low Power Display Mode */ if (ssd130x->area_color_enable || ssd130x->low_power) {0 ;if (ssd130x->area_color_enable)if (ssd130x->low_power)2 , SSD130X_SET_AREA_COLOR_MODE, mode);if (ret < 0 )return ret;/* Set precharge period in number of ticks from the internal clock */ 2 , SSD130X_SET_PRECHARGE_PERIOD, precharge);if (ret < 0 )return ret;/* Set COM pins configuration */ 1 );/* * The COM scan mode field values are the inverse of the boolean DT * property " solomon , com - seq " . The value 0 b means scan from COM0 to * COM [ N - 1 ] while 1 b means scan from COM [ N - 1 ] to COM0 . 2 , SSD130X_SET_COM_PINS_CONFIG, compins);if (ret < 0 )return ret;/* Set VCOMH */ 2 , SSD130X_SET_VCOMH, ssd130x->vcomh);if (ret < 0 )return ret;/* Turn on the DC-DC Charge Pump */ 4 );if (ssd130x->device_info->need_chargepump)2 );2 , SSD130X_CHARGE_PUMP, chargepump);if (ret < 0 )return ret;/* Set lookup table */ if (ssd130x->lookup_table_set) {int i;1 , SSD130X_SET_LOOKUP_TABLE);if (ret < 0 )return ret;for (i = 0 ; i < ARRAY_SIZE(ssd130x->lookup_table); i++) {if (val < 31 || val > 63 )"lookup table index %d value out of range 31 <= %d <= 63\n" ,1 , val);if (ret < 0 )return ret;/* Switch to page addressing mode */ if (ssd130x->page_address_mode)return ssd130x_write_cmd(ssd130x, 2 , SSD130X_SET_ADDRESS_MODE,/* Switch to horizontal addressing mode */ return ssd130x_write_cmd(ssd130x, 2 , SSD130X_SET_ADDRESS_MODE,static int ssd132x_init(struct ssd130x_device *ssd130x)int ret;/* Set initial contrast */ 2 , SSD13XX_CONTRAST, 0 x80);if (ret < 0 )return ret;/* Set column start and end */ 3 , SSD132X_SET_COL_RANGE, 0 x00,1 );if (ret < 0 )return ret;/* Set row start and end */ 3 , SSD132X_SET_ROW_RANGE, 0 x00, ssd130x->height - 1 );if (ret < 0 )return ret;/* * Horizontal Address Increment * Re - map for Column Address , Nibble and COM * COM Split Odd Even 2 , SSD13XX_SET_SEG_REMAP, 0 x53);if (ret < 0 )return ret;/* Set display start and offset */ 2 , SSD132X_SET_DISPLAY_START, 0 x00);if (ret < 0 )return ret;2 , SSD132X_SET_DISPLAY_OFFSET, 0 x00);if (ret < 0 )return ret;/* Set display mode normal */ 1 , SSD132X_SET_DISPLAY_NORMAL);if (ret < 0 )return ret;/* Set multiplex ratio value */ 2 , SSD13XX_SET_MULTIPLEX_RATIO, ssd130x->height - 1 );if (ret < 0 )return ret;/* Set phase length */ 2 , SSD132X_SET_PHASE_LENGTH, 0 x55);if (ret < 0 )return ret;/* Select default linear gray scale table */ 1 , SSD132X_SELECT_DEFAULT_TABLE);if (ret < 0 )return ret;/* Set clock frequency */ 2 , SSD132X_SET_CLOCK_FREQ, 0 x01);if (ret < 0 )return ret;/* Enable internal VDD regulator */ 2 , SSD132X_SET_FUNCTION_SELECT_A, 0 x1);if (ret < 0 )return ret;/* Set pre-charge period */ 2 , SSD132X_SET_PRECHARGE_PERIOD, 0 x01);if (ret < 0 )return ret;/* Set pre-charge voltage */ 2 , SSD132X_SET_PRECHARGE_VOLTAGE, 0 x08);if (ret < 0 )return ret;/* Set VCOMH voltage */ 2 , SSD130X_SET_VCOMH_VOLTAGE, 0 x07);if (ret < 0 )return ret;/* Enable second pre-charge and internal VSL */ 2 , SSD132X_SET_FUNCTION_SELECT_B, 0 x62);if (ret < 0 )return ret;return 0 ;static int ssd133x_init(struct ssd130x_device *ssd130x)int ret;/* Set color A contrast */ 2 , SSD133X_CONTRAST_A, 0 x91);if (ret < 0 )return ret;/* Set color B contrast */ 2 , SSD133X_CONTRAST_B, 0 x50);if (ret < 0 )return ret;/* Set color C contrast */ 2 , SSD133X_CONTRAST_C, 0 x7d);if (ret < 0 )return ret;/* Set master current */ 2 , SSD133X_SET_MASTER_CURRENT, 0 x06);if (ret < 0 )return ret;/* Set column start and end */ 3 , SSD133X_SET_COL_RANGE, 0 x00, ssd130x->width - 1 );if (ret < 0 )return ret;/* Set row start and end */ 3 , SSD133X_SET_ROW_RANGE, 0 x00, ssd130x->height - 1 );if (ret < 0 )return ret;/* * Horizontal Address Increment * Normal order SA , SB , SC ( e . g . RGB ) * COM Split Odd Even * 256 color format 2 , SSD13XX_SET_SEG_REMAP, 0 x20);if (ret < 0 )return ret;/* Set display start and offset */ 2 , SSD133X_SET_DISPLAY_START, 0 x00);if (ret < 0 )return ret;2 , SSD133X_SET_DISPLAY_OFFSET, 0 x00);if (ret < 0 )return ret;/* Set display mode normal */ 1 , SSD133X_SET_DISPLAY_NORMAL);if (ret < 0 )return ret;/* Set multiplex ratio value */ 2 , SSD13XX_SET_MULTIPLEX_RATIO, ssd130x->height - 1 );if (ret < 0 )return ret;/* Set master configuration */ 2 , SSD133X_SET_MASTER_CONFIG, 0 x8e);if (ret < 0 )return ret;/* Set power mode */ 2 , SSD133X_POWER_SAVE_MODE, 0 x0b);if (ret < 0 )return ret;/* Set Phase 1 and 2 period */ 2 , SSD133X_PHASES_PERIOD, 0 x31);if (ret < 0 )return ret;/* Set clock divider */ 2 , SSD133X_SET_CLOCK_FREQ, 0 xf0);if (ret < 0 )return ret;/* Set pre-charge A */ 2 , SSD132X_SET_PRECHARGE_A, 0 x64);if (ret < 0 )return ret;/* Set pre-charge B */ 2 , SSD132X_SET_PRECHARGE_B, 0 x78);if (ret < 0 )return ret;/* Set pre-charge C */ 2 , SSD132X_SET_PRECHARGE_C, 0 x64);if (ret < 0 )return ret;/* Set pre-charge level */ 2 , SSD133X_SET_PRECHARGE_VOLTAGE, 0 x3a);if (ret < 0 )return ret;/* Set VCOMH voltage */ 2 , SSD133X_SET_VCOMH_VOLTAGE, 0 x3e);if (ret < 0 )return ret;return 0 ;static int ssd130x_update_rect(struct ssd130x_device *ssd130x,struct drm_rect *rect, u8 *buf,unsigned int x = rect->x1;unsigned int y = rect->y1;unsigned int width = drm_rect_width(rect);unsigned int height = drm_rect_height(rect);unsigned int line_length = DIV_ROUND_UP(width, 8 );unsigned int page_height = SSD130X_PAGE_HEIGHT;unsigned int pages = DIV_ROUND_UP(height, page_height);struct drm_device *drm = &ssd130x->drm;0 ;int ret, i, j, k;0 , "y must be aligned to screen page\n" );/* * The screen is divided in pages , each having a height of 8 * pixels , and the width of the screen . When sending a byte of * data to the controller , it gives the 8 bits for the current * column . I . e , the first byte are the 8 bits of the first * column , then the 8 bits for the second column , etc . * * * Representation of the screen , assuming it is 5 bits * wide . Each letter - number combination is a bit that controls * one pixel . * * A0 A1 A2 A3 A4 * B0 B1 B2 B3 B4 * C0 C1 C2 C3 C4 * D0 D1 D2 D3 D4 * E0 E1 E2 E3 E4 * F0 F1 F2 F3 F4 * G0 G1 G2 G3 G4 * H0 H1 H2 H3 H4 * * If you want to update this screen , you need to send 5 bytes : * ( 1 ) A0 B0 C0 D0 E0 F0 G0 H0 * ( 2 ) A1 B1 C1 D1 E1 F1 G1 H1 * ( 3 ) A2 B2 C2 D2 E2 F2 G2 H2 * ( 4 ) A3 B3 C3 D3 E3 F3 G3 H3 * ( 5 ) A4 B4 C4 D4 E4 F4 G4 H4 if (!ssd130x->page_address_mode) {/* Set address range for horizontal addressing mode */ if (ret < 0 )return ret;if (ret < 0 )return ret;for (i = 0 ; i < pages; i++) {int m = page_height;/* Last page may be partial */ if (page_height * (y / page_height + i + 1 ) > ssd130x->height)for (j = 0 ; j < width; j++) {0 ;for (k = 0 ; k < m; k++) {8 ;8 )) & 1 ;/* * In page addressing mode , the start address needs to be reset , * and each page then needs to be written out separately . if (ssd130x->page_address_mode) {if (ret < 0 )return ret;if (ret < 0 )return ret;0 ;/* Write out update in one go if we aren't using page addressing mode */ if (!ssd130x->page_address_mode)return ret;static int ssd132x_update_rect(struct ssd130x_device *ssd130x,struct drm_rect *rect, u8 *buf,unsigned int x = rect->x1;unsigned int y = rect->y1;unsigned int segment_width = SSD132X_SEGMENT_WIDTH;unsigned int width = drm_rect_width(rect);unsigned int height = drm_rect_height(rect);unsigned int columns = DIV_ROUND_UP(width, segment_width);unsigned int rows = height;struct drm_device *drm = &ssd130x->drm;0 ;unsigned int i, j;int ret;0 , "x must be aligned to screen segment\n" );/* * The screen is divided in Segment and Common outputs , where * COM0 to COM [ N - 1 ] are the rows and SEG0 to SEG [ M - 1 ] are * the columns . * * Each Segment has a 4 - bit pixel and each Common output has a * row of pixels . When using the ( default ) horizontal address * increment mode , each byte of data sent to the controller has * two Segments ( e . g : SEG0 and SEG1 ) that are stored in the lower * and higher nibbles of a single byte representing one column . * That is , the first byte are SEG0 ( D0 [ 3 : 0 ] ) and SEG1 ( D0 [ 7 : 4 ] ) , * the second byte are SEG2 ( D1 [ 3 : 0 ] ) and SEG3 ( D1 [ 7 : 4 ] ) and so on . /* Set column start and end */ 3 , SSD132X_SET_COL_RANGE, x / segment_width, columns - 1 );if (ret < 0 )return ret;/* Set row start and end */ 3 , SSD132X_SET_ROW_RANGE, y, rows - 1 );if (ret < 0 )return ret;for (i = 0 ; i < height; i++) {/* Process pair of pixels and combine them into a single byte */ for (j = 0 ; j < width; j += segment_width) {1 ];0 xf0) | (n1 >> 4 );/* Write out update in one go since horizontal addressing mode is used */ return ret;static int ssd133x_update_rect(struct ssd130x_device *ssd130x,struct drm_rect *rect, u8 *data_array,unsigned int pitch)unsigned int x = rect->x1;unsigned int y = rect->y1;unsigned int columns = drm_rect_width(rect);unsigned int rows = drm_rect_height(rect);int ret;/* * The screen is divided in Segment and Common outputs , where * COM0 to COM [ N - 1 ] are the rows and SEG0 to SEG [ M - 1 ] are * the columns . * * Each Segment has a 8 - bit pixel and each Common output has a * row of pixels . When using the ( default ) horizontal address * increment mode , each byte of data sent to the controller has * a Segment ( e . g : SEG0 ) . * * When using the 256 color depth format , each pixel contains 3 * sub - pixels for color A , B and C . These have 3 bit , 3 bit and * 2 bits respectively . /* Set column start and end */ 3 , SSD133X_SET_COL_RANGE, x, columns - 1 );if (ret < 0 )return ret;/* Set row start and end */ 3 , SSD133X_SET_ROW_RANGE, y, rows - 1 );if (ret < 0 )return ret;/* Write out update in one go since horizontal addressing mode is used */ return ret;static void ssd130x_clear_screen(struct ssd130x_device *ssd130x, u8 *data_array)unsigned int pages = DIV_ROUND_UP(ssd130x->height, SSD130X_PAGE_HEIGHT);unsigned int width = ssd130x->width;int ret, i;if (!ssd130x->page_address_mode) {0 , width * pages);/* Set address range for horizontal addressing mode */ if (ret < 0 )return ;if (ret < 0 )return ;/* Write out update in one go if we aren't using page addressing mode */ else {/* * In page addressing mode , the start address needs to be reset , * and each page then needs to be written out separately . 0 , width);for (i = 0 ; i < pages; i++) {if (ret < 0 )return ;if (ret < 0 )return ;static void ssd132x_clear_screen(struct ssd130x_device *ssd130x, u8 *data_array)unsigned int columns = DIV_ROUND_UP(ssd130x->width, SSD132X_SEGMENT_WIDTH);unsigned int height = ssd130x->height;0 , columns * height);/* Write out update in one go since horizontal addressing mode is used */ static void ssd133x_clear_screen(struct ssd130x_device *ssd130x, u8 *data_array)const struct drm_format_info *fi = drm_format_info(DRM_FORMAT_RGB332);unsigned int pitch;if (!fi)return ;0 , ssd130x->width);0 , pitch * ssd130x->height);/* Write out update in one go since horizontal addressing mode is used */ static int ssd130x_fb_blit_rect(struct drm_framebuffer *fb,const struct iosys_map *vmap,struct drm_rect *rect,struct drm_format_conv_state *fmtcnv_state)struct ssd130x_device *ssd130x = drm_to_ssd130x(fb->dev);struct iosys_map dst;unsigned int dst_pitch;int ret = 0 ;/* Align y to display page boundaries */ unsigned int , round_up(rect->y2, SSD130X_PAGE_HEIGHT), ssd130x->height);8 );if (ret)return ret;return ret;static int ssd132x_fb_blit_rect(struct drm_framebuffer *fb,const struct iosys_map *vmap,struct drm_rect *rect, u8 *buf,struct drm_format_conv_state *fmtcnv_state)struct ssd130x_device *ssd130x = drm_to_ssd130x(fb->dev);unsigned int dst_pitch;struct iosys_map dst;int ret = 0 ;/* Align x to display segment boundaries */ unsigned int , round_up(rect->x2, SSD132X_SEGMENT_WIDTH),if (ret)return ret;return ret;static int ssd133x_fb_blit_rect(struct drm_framebuffer *fb,const struct iosys_map *vmap,struct drm_rect *rect, u8 *data_array,struct drm_format_conv_state *fmtcnv_state)struct ssd130x_device *ssd130x = drm_to_ssd130x(fb->dev);const struct drm_format_info *fi = drm_format_info(DRM_FORMAT_RGB332);unsigned int dst_pitch;struct iosys_map dst;int ret = 0 ;if (!fi)return -EINVAL;0 , drm_rect_width(rect));if (ret)return ret;return ret;static int ssd130x_primary_plane_atomic_check(struct drm_plane *plane,struct drm_atomic_state *state)struct drm_device *drm = plane->dev;struct ssd130x_device *ssd130x = drm_to_ssd130x(drm);struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane);struct ssd130x_plane_state *ssd130x_state = to_ssd130x_plane_state(plane_state);struct drm_shadow_plane_state *shadow_plane_state = &ssd130x_state->base;struct drm_crtc *crtc = plane_state->crtc;struct drm_crtc_state *crtc_state = NULL;const struct drm_format_info *fi;unsigned int pitch;int ret;if (crtc)false , false );if (ret)return ret;else if (!plane_state->visible)return 0 ;if (!fi)return -EINVAL;0 , ssd130x->width);if (plane_state->fb->format != fi) {void *buf;/* format conversion necessary; reserve buffer */ if (!buf)return -ENOMEM;if (!ssd130x_state->buffer)return -ENOMEM;return 0 ;static int ssd132x_primary_plane_atomic_check(struct drm_plane *plane,struct drm_atomic_state *state)struct drm_device *drm = plane->dev;struct ssd130x_device *ssd130x = drm_to_ssd130x(drm);struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane);struct ssd130x_plane_state *ssd130x_state = to_ssd130x_plane_state(plane_state);struct drm_shadow_plane_state *shadow_plane_state = &ssd130x_state->base;struct drm_crtc *crtc = plane_state->crtc;struct drm_crtc_state *crtc_state = NULL;const struct drm_format_info *fi;unsigned int pitch;int ret;if (crtc)false , false );if (ret)return ret;else if (!plane_state->visible)return 0 ;if (!fi)return -EINVAL;0 , ssd130x->width);if (plane_state->fb->format != fi) {void *buf;/* format conversion necessary; reserve buffer */ if (!buf)return -ENOMEM;if (!ssd130x_state->buffer)return -ENOMEM;return 0 ;static int ssd133x_primary_plane_atomic_check(struct drm_plane *plane,struct drm_atomic_state *state)struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane);struct drm_crtc *crtc = plane_state->crtc;struct drm_crtc_state *crtc_state = NULL;int ret;if (crtc)false , false );if (ret)return ret;else if (!plane_state->visible)return 0 ;return 0 ;static void ssd130x_primary_plane_atomic_update(struct drm_plane *plane,struct drm_atomic_state *state)struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane);struct drm_plane_state *old_plane_state = drm_atomic_get_old_plane_state(state, plane);struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(plane_state);struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, plane_state->crtc);struct ssd130x_crtc_state *ssd130x_crtc_state = to_ssd130x_crtc_state(crtc_state);struct ssd130x_plane_state *ssd130x_plane_state = to_ssd130x_plane_state(plane_state);struct drm_framebuffer *fb = plane_state->fb;struct drm_atomic_helper_damage_iter iter;struct drm_device *drm = plane->dev;struct drm_rect dst_clip;struct drm_rect damage;int idx;if (!drm_dev_enter(drm, &idx))return ;if (!drm_rect_intersect(&dst_clip, &damage))continue ;0 ], &dst_clip,static void ssd132x_primary_plane_atomic_update(struct drm_plane *plane,struct drm_atomic_state *state)struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane);struct drm_plane_state *old_plane_state = drm_atomic_get_old_plane_state(state, plane);struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(plane_state);struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, plane_state->crtc);struct ssd130x_crtc_state *ssd130x_crtc_state = to_ssd130x_crtc_state(crtc_state);struct ssd130x_plane_state *ssd130x_plane_state = to_ssd130x_plane_state(plane_state);struct drm_framebuffer *fb = plane_state->fb;struct drm_atomic_helper_damage_iter iter;struct drm_device *drm = plane->dev;struct drm_rect dst_clip;struct drm_rect damage;int idx;if (!drm_dev_enter(drm, &idx))return ;if (!drm_rect_intersect(&dst_clip, &damage))continue ;0 ], &dst_clip,static void ssd133x_primary_plane_atomic_update(struct drm_plane *plane,struct drm_atomic_state *state)struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane);struct drm_plane_state *old_plane_state = drm_atomic_get_old_plane_state(state, plane);struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(plane_state);struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, plane_state->crtc);struct ssd130x_crtc_state *ssd130x_crtc_state = to_ssd130x_crtc_state(crtc_state);struct drm_framebuffer *fb = plane_state->fb;struct drm_atomic_helper_damage_iter iter;struct drm_device *drm = plane->dev;struct drm_rect dst_clip;struct drm_rect damage;int idx;if (!drm_dev_enter(drm, &idx))return ;if (!drm_rect_intersect(&dst_clip, &damage))continue ;0 ], &dst_clip,static void ssd130x_primary_plane_atomic_disable(struct drm_plane *plane,struct drm_atomic_state *state)struct drm_device *drm = plane->dev;struct ssd130x_device *ssd130x = drm_to_ssd130x(drm);struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane);struct drm_crtc_state *crtc_state;struct ssd130x_crtc_state *ssd130x_crtc_state;int idx;if (!plane_state->crtc)return ;if (!drm_dev_enter(drm, &idx))return ;static void ssd132x_primary_plane_atomic_disable(struct drm_plane *plane,struct drm_atomic_state *state)struct drm_device *drm = plane->dev;struct ssd130x_device *ssd130x = drm_to_ssd130x(drm);struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane);struct drm_crtc_state *crtc_state;struct ssd130x_crtc_state *ssd130x_crtc_state;int idx;if (!plane_state->crtc)return ;if (!drm_dev_enter(drm, &idx))return ;static void ssd133x_primary_plane_atomic_disable(struct drm_plane *plane,struct drm_atomic_state *state)struct drm_device *drm = plane->dev;struct ssd130x_device *ssd130x = drm_to_ssd130x(drm);struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane);struct drm_crtc_state *crtc_state;struct ssd130x_crtc_state *ssd130x_crtc_state;int idx;if (!plane_state->crtc)return ;if (!drm_dev_enter(drm, &idx))return ;/* Called during init to allocate the plane's atomic state. */ static void ssd130x_primary_plane_reset(struct drm_plane *plane)struct ssd130x_plane_state *ssd130x_state;sizeof (*ssd130x_state), GFP_KERNEL);if (!ssd130x_state)return ;static struct drm_plane_state *ssd130x_primary_plane_duplicate_state(struct drm_plane *plane)struct drm_shadow_plane_state *new_shadow_plane_state;struct ssd130x_plane_state *old_ssd130x_state;struct ssd130x_plane_state *ssd130x_state;if (WARN_ON(!plane->state))return NULL;sizeof (*ssd130x_state), GFP_KERNEL);if (!ssd130x_state)return NULL;/* The buffer is not duplicated and is allocated in .atomic_check */ return &new_shadow_plane_state->base;static void ssd130x_primary_plane_destroy_state(struct drm_plane *plane,struct drm_plane_state *state)struct ssd130x_plane_state *ssd130x_state = to_ssd130x_plane_state(state);static const struct drm_plane_helper_funcs ssd130x_primary_plane_helper_funcs[] = {static const struct drm_plane_funcs ssd130x_primary_plane_funcs = {static enum drm_mode_status ssd130x_crtc_mode_valid(struct drm_crtc *crtc,const struct drm_display_mode *mode)struct ssd130x_device *ssd130x = drm_to_ssd130x(crtc->dev);if (mode->hdisplay != ssd130x->mode.hdisplay &&return MODE_ONE_SIZE;else if (mode->hdisplay != ssd130x->mode.hdisplay)return MODE_ONE_WIDTH;else if (mode->vdisplay != ssd130x->mode.vdisplay)return MODE_ONE_HEIGHT;return MODE_OK;static int ssd130x_crtc_atomic_check(struct drm_crtc *crtc,struct drm_atomic_state *state)struct drm_device *drm = crtc->dev;struct ssd130x_device *ssd130x = drm_to_ssd130x(drm);struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc);struct ssd130x_crtc_state *ssd130x_state = to_ssd130x_crtc_state(crtc_state);unsigned int pages = DIV_ROUND_UP(ssd130x->height, SSD130X_PAGE_HEIGHT);int ret;if (ret)return ret;if (!ssd130x_state->data_array)return -ENOMEM;return 0 ;static int ssd132x_crtc_atomic_check(struct drm_crtc *crtc,struct drm_atomic_state *state)struct drm_device *drm = crtc->dev;struct ssd130x_device *ssd130x = drm_to_ssd130x(drm);struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc);struct ssd130x_crtc_state *ssd130x_state = to_ssd130x_crtc_state(crtc_state);unsigned int columns = DIV_ROUND_UP(ssd130x->width, SSD132X_SEGMENT_WIDTH);int ret;if (ret)return ret;if (!ssd130x_state->data_array)return -ENOMEM;return 0 ;static int ssd133x_crtc_atomic_check(struct drm_crtc *crtc,struct drm_atomic_state *state)struct drm_device *drm = crtc->dev;struct ssd130x_device *ssd130x = drm_to_ssd130x(drm);struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc);struct ssd130x_crtc_state *ssd130x_state = to_ssd130x_crtc_state(crtc_state);const struct drm_format_info *fi = drm_format_info(DRM_FORMAT_RGB332);unsigned int pitch;int ret;if (!fi)return -EINVAL;if (ret)return ret;0 , ssd130x->width);if (!ssd130x_state->data_array)return -ENOMEM;return 0 ;/* Called during init to allocate the CRTC's atomic state. */ static void ssd130x_crtc_reset(struct drm_crtc *crtc)struct ssd130x_crtc_state *ssd130x_state;sizeof (*ssd130x_state), GFP_KERNEL);if (!ssd130x_state)return ;static struct drm_crtc_state *ssd130x_crtc_duplicate_state(struct drm_crtc *crtc)struct ssd130x_crtc_state *old_ssd130x_state;struct ssd130x_crtc_state *ssd130x_state;if (WARN_ON(!crtc->state))return NULL;sizeof (*ssd130x_state), GFP_KERNEL);if (!ssd130x_state)return NULL;/* The buffer is not duplicated and is allocated in .atomic_check */ return &ssd130x_state->base;static void ssd130x_crtc_destroy_state(struct drm_crtc *crtc,struct drm_crtc_state *state)struct ssd130x_crtc_state *ssd130x_state = to_ssd130x_crtc_state(state);/* * The CRTC is always enabled . Screen updates are performed by * the primary plane ' s atomic_update function . Disabling clears * the screen in the primary plane ' s atomic_disable function . static const struct drm_crtc_helper_funcs ssd130x_crtc_helper_funcs[] = {static const struct drm_crtc_funcs ssd130x_crtc_funcs = {static void ssd130x_encoder_atomic_enable(struct drm_encoder *encoder,struct drm_atomic_state *state)struct drm_device *drm = encoder->dev;struct ssd130x_device *ssd130x = drm_to_ssd130x(drm);int ret;if (ret)return ;if (ret)goto power_off;1 , SSD13XX_DISPLAY_ON);return ;return ;static void ssd132x_encoder_atomic_enable(struct drm_encoder *encoder,struct drm_atomic_state *state)struct drm_device *drm = encoder->dev;struct ssd130x_device *ssd130x = drm_to_ssd130x(drm);int ret;if (ret)return ;if (ret)goto power_off;1 , SSD13XX_DISPLAY_ON);return ;static void ssd133x_encoder_atomic_enable(struct drm_encoder *encoder,struct drm_atomic_state *state)struct drm_device *drm = encoder->dev;struct ssd130x_device *ssd130x = drm_to_ssd130x(drm);int ret;if (ret)return ;if (ret)goto power_off;1 , SSD13XX_DISPLAY_ON);return ;static void ssd130x_encoder_atomic_disable(struct drm_encoder *encoder,struct drm_atomic_state *state)struct drm_device *drm = encoder->dev;struct ssd130x_device *ssd130x = drm_to_ssd130x(drm);1 , SSD13XX_DISPLAY_OFF);static const struct drm_encoder_helper_funcs ssd130x_encoder_helper_funcs[] = {static const struct drm_encoder_funcs ssd130x_encoder_funcs = {static int ssd130x_connector_get_modes(struct drm_connector *connector)struct ssd130x_device *ssd130x = drm_to_ssd130x(connector->dev);struct drm_display_mode *mode;struct device *dev = ssd130x->dev;if (!mode) {"Failed to duplicated mode\n" );return 0 ;/* There is only a single mode */ return 1 ;static const struct drm_connector_helper_funcs ssd130x_connector_helper_funcs = {static const struct drm_connector_funcs ssd130x_connector_funcs = {static const struct drm_mode_config_funcs ssd130x_mode_config_funcs = {static const uint32_t ssd130x_formats[] = {static const struct drm_driver ssd130x_drm_driver = {static int ssd130x_update_bl(struct backlight_device *bdev)struct ssd130x_device *ssd130x = bl_get_data(bdev);int brightness = backlight_get_brightness(bdev);int ret;1 , SSD13XX_CONTRAST);if (ret < 0 )return ret;1 , ssd130x->contrast);if (ret < 0 )return ret;return 0 ;static const struct backlight_ops ssd130xfb_bl_ops = {static void ssd130x_parse_properties(struct ssd130x_device *ssd130x)struct device *dev = ssd130x->dev;if (device_property_read_u32(dev, "solomon,width" , &ssd130x->width))if (device_property_read_u32(dev, "solomon,height" , &ssd130x->height))if (device_property_read_u32(dev, "solomon,page-offset" , &ssd130x->page_offset))1 ;if (device_property_read_u32(dev, "solomon,col-offset" , &ssd130x->col_offset))0 ;if (device_property_read_u32(dev, "solomon,com-offset" , &ssd130x->com_offset))0 ;if (device_property_read_u32(dev, "solomon,prechargep1" , &ssd130x->prechargep1))2 ;if (device_property_read_u32(dev, "solomon,prechargep2" , &ssd130x->prechargep2))2 ;if (!device_property_read_u8_array(dev, "solomon,lookup-table" ,1 ;"solomon,segment-no-remap" );"solomon,com-seq" );"solomon,com-lrremap" );"solomon,com-invdir" );"solomon,area-color-enable" );"solomon,low-power" );127 ;/* Setup display timing */ if (device_property_read_u32(dev, "solomon,dclk-div" , &ssd130x->dclk_div))if (device_property_read_u32(dev, "solomon,dclk-frq" , &ssd130x->dclk_frq))static int ssd130x_init_modeset(struct ssd130x_device *ssd130x)enum ssd130x_family_ids family_id = ssd130x->device_info->family_id;struct drm_display_mode *mode = &ssd130x->mode;struct device *dev = ssd130x->dev;struct drm_device *drm = &ssd130x->drm;unsigned long max_width, max_height;struct drm_plane *primary_plane;struct drm_crtc *crtc;struct drm_encoder *encoder;struct drm_connector *connector;int ret;/* * Modesetting if (ret) {"DRM mode config init failed: %d\n" , ret);return ret;1 ;27 ;27 ;unsigned long , mode->hdisplay, DRM_SHADOW_PLANE_MAX_WIDTH);unsigned long , mode->vdisplay, DRM_SHADOW_PLANE_MAX_HEIGHT);24 ;/* Primary plane */ 0 , &ssd130x_primary_plane_funcs,if (ret) {"DRM primary plane init failed: %d\n" , ret);return ret;/* CRTC */ if (ret) {"DRM crtc init failed: %d\n" , ret);return ret;/* Encoder */ if (ret) {"DRM encoder init failed: %d\n" , ret);return ret;/* Connector */ if (ret) {"DRM connector init failed: %d\n" , ret);return ret;if (ret) {"DRM attach connector to encoder failed: %d\n" , ret);return ret;return 0 ;static int ssd130x_get_resources(struct ssd130x_device *ssd130x)struct device *dev = ssd130x->dev;"reset" , GPIOD_OUT_LOW);if (IS_ERR(ssd130x->reset))return dev_err_probe(dev, PTR_ERR(ssd130x->reset),"Failed to get reset gpio\n" );"vcc" );if (IS_ERR(ssd130x->vcc_reg))return dev_err_probe(dev, PTR_ERR(ssd130x->vcc_reg),"Failed to get VCC regulator\n" );return 0 ;struct ssd130x_device *ssd130x_probe(struct device *dev, struct regmap *regmap)struct ssd130x_device *ssd130x;struct backlight_device *bl;struct drm_device *drm;int ret;struct ssd130x_device, drm);if (IS_ERR(ssd130x))return ERR_PTR(dev_err_probe(dev, PTR_ERR(ssd130x),"Failed to allocate DRM device\n" ));if (ssd130x->device_info->page_mode_only)1 ;if (ret)return ERR_PTR(ret);if (IS_ERR(bl))return ERR_PTR(dev_err_probe(dev, PTR_ERR(bl),"Unable to register backlight device\n" ));if (ret)return ERR_PTR(ret);0 );if (ret)return ERR_PTR(dev_err_probe(dev, ret, "DRM device register failed\n" ));return ssd130x;void ssd130x_remove(struct ssd130x_device *ssd130x)void ssd130x_shutdown(struct ssd130x_device *ssd130x)"Javier Martinez Canillas <javierm@redhat.com>" );"GPL v2" );
Messung V0.5 in Prozent C=96 H=93 G=94
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