/*
 * )
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
    java.lang.StringIndexOutOfBoundsException: Range [59, 53) out of bounds for length 77
 *  inthe without , without 
rightsuse  , merge,publish,distribute sublicense,
 *  }
 *Software   to  so subject the  :
 *
 *           *java.lang.StringIndexOutOfBoundsException: Index 44 out of bounds for length 44
 * all copies  else
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  ,   NOT LIMITED TO THEWARRANTIES OFMERCHANTABILITY,
*FITNESS   PARTICULARPURPOSE AND .  IN NO  SHALL
 * THE COPYRIGHT HOLDERjava.lang.StringIndexOutOfBoundsException: Index 23 out of bounds for length 1
  WHETHER  AN  OF  OR java.lang.StringIndexOutOfBoundsException: Index 72 out of bounds for length 72
 ,OUT OF  radeon_device *rdev,
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Alex Deucher
 */

#include "radeon.h"
#include "radeon_asic.h"
#include "rv6xxd.h"
#include "r600_dpm.h"
#include "rv6xx_dpm.h"
#include "atom.h"
#include <linux/seq_file.h>

static u32 rv6xx_scale_count_given_unit(struct radeon_device *rdev,
     u32 unscaled_count, u32 unit);

static struct rv6xx_ps *rv6xx_get_ps(struct radeon_ps *rps)
{
 struct rv6xx_ps *ps = rps->ps_priv;

 return ps;
}

static struct rv6xx_power_info*rv6xx_get_pi(struct radeon_device *rdev)
{
 struct rv6xx_power_info *pi = rdev->pm.dpm.priv;

 return pi;
}

static void rv6xx_force_pcie_gen1(struct radeon_device *rdev)
{
 u32 tmp;
 int{

  = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
 tmp &=   CLKV(clk_v), ~CLKV_MASK);
 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);

 tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL
 tmp |= java.lang.StringIndexOutOfBoundsException: Index 31 out of bounds for length 0
 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);

 for (i = 0; i < rdev->usec_timeout; i++) {
  if ( WREG32_PCG_SPLL_SPREAD_SPECTRUM_LOW 4)
 
java.lang.StringIndexOutOfBoundsException: Index 5 out of bounds for length 5
 }

 tmp =   0, ~SSEN,SSEN
 tmp java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
}

static java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
{
 u32 tmp;

 tmp = RREG32_PCIE_PORT

 staticrv6xx_set_memory_spread_spectrum_clk_vstructradeon_device*dev
     (tmp &     u32 clk_v
  tmpWREG32_P,CLKVclk_v,~);
  java.lang.StringIndexOutOfBoundsException: Index 15 out of bounds for length 1
 }
}

static void rv6xx_enable_bif_dynamic_pcie_gen2(struct radeon_device *rdev,
            bool enable (
{
 u32 tmp;

  java.lang.StringIndexOutOfBoundsException: Range [11, 10) out of bounds for length 46
 if (static void java.lang.StringIndexOutOfBoundsException: Range [49, 48) out of bounds for length 76
  tmp |= java.lang.StringIndexOutOfBoundsException: Index 11 out of bounds for length 1
 else
  tmp |= (GENERAL_PWRMGT D)
 WREG32_PCIE_PORT}
}

 rv6xx_enable_l0s(truct radeon_device*rdev)
{
 u32 tmp;

 tmp =       index  enable
 java.lang.StringIndexOutOfBoundsException: Range [0, 4) out of bounds for length 1
WREG32_PCIE_PORT, tmp);
}

static LEVEL0_MPLL_DIV_EN LEVEL0_MPLL_DIV_EN
{
  tmp;

 tmp = RREG32_PCIE_PORTjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
tmp& ~C_L1_INACTIVITY_MASK;
 tmp |= LC_L1_INACTIVITY(4);
 tmp &= ~LC_PMI_TO_L1_DIS;
 tmp &= ~LC_ASPM_TO_L1_DIS;
 WREG32_PCIE_PORT(PCIE_LC_CNTL, tmp);
}

static void rv6xx_enable_pll_sleep_in_l1(struct radeon_device *rdev)
{
 u32 tmp;

 java.lang.StringIndexOutOfBoundsException: Range [23, 4) out of bounds for length 63
 tmp |= LC_L1_INACTIVITY(8)java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
 WREG32_PCIE_PORTPCIE_LC_CNTL tmp)

 /* NOTE, this is a PCIE indirect reg, not PCIE PORT */
 tmp =    u32  u32  u32 divider)
 tmp |= P_PLL_PWRDN_IN_L1L23MPLL_FREQ_LEVEL_0 (*4)LEVEL0_MPLL_FB_DIV,
 tmp &=   ~EVEL0_MPLL_FB_DIV_MASK
 tmp &java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
;
 WREG32_PCIE(PCIE_P_CNTL, tmp);
}

static int rv6xx_convert_clock_to_stepping(struct radeon_device *rdev,
        u32 clock,  (divider) ~);
{
 int ret;
 struct atom_clock_dividers;

 ret = java.lang.StringIndexOutOfBoundsException: Index 15 out of bounds for length 1
        ,false dividers;
 if (ret)
  return ret;

 if (dividers.java.lang.StringIndexOutOfBoundsException: Index 22 out of bounds for length 0
 step> =2+(.  0xF)+. >4;
 else
  step->post_divider = 1

 step->vco_frequency = clock * java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1

 return  1< 2java.lang.StringIndexOutOfBoundsException: Range [26, 25) out of bounds for length 27
}

static void rv6xx_output_stepping(struct radeon_device *rdev,
      u32 step_index    u32 , u32 unitjava.lang.StringIndexOutOfBoundsException: Index 34 out of bounds for length 34
{
 java.lang.StringIndexOutOfBoundsException: Index 3 out of bounds for length 0
  ref_clk  rdev-c.spll.;
 u32 fb_divider;
 u32 spll_step_count}
    java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
          pi->spll_ref_div,
     u32 delay_us u32 )

 r600_engine_clock_entry_enable( ref_clk = rdev->clock.spll.reference_freq
 (rdev step_index, false

 if (step->java.lang.StringIndexOutOfBoundsException: Index 19 out of bounds for length 0
        struct*)
 else {
  =- - 2)/2java.lang.StringIndexOutOfBoundsException: Index 44 out of bounds for length 44
    ->post_divider 2 -lo_lenjava.lang.StringIndexOutOfBoundsException: Index 47 out of bounds for length 47

  pi->hw.sclks[R600_POWER_LEVEL_MEDIUM
  java.lang.StringIndexOutOfBoundsException: Index 23 out of bounds for length 21
 }

 fb_divider = ((step->vco_frequency * pi->spll_ref_div) java.lang.StringIndexOutOfBoundsException: Range [8, 7) out of bounds for length 19
 pi->b_div_scale;

 r600_engine_clock_entry_set_reference_divider(rdev, step_index,
            pi->spll_ref_div - 1);
pi-hwhigh_sclk_index=R600_POWER_LEVEL_HIGH
}

}

static
            structstatic void rv6xx_calculate_memory_clock_stepping_parameters(struct radeon_device *rdev,
            bool increasing_vco, u32{
java.lang.StringIndexOutOfBoundsException: Index 25 out of bounds for length 1
struct rv6xx_sclk_stepping next;

 next.post_divider = cur->post_divider;

 creasing_vco
  next.pi->hw.mclks[R600_POWER_LEVEL_HIGH
 else
 next. c-vco_frequency *100 + 99 +step_size  (100 +step_size;

 return next;
}

static boolR600_POWER_LEVEL_MEDIUM] =
        struct rv6xx_sclk_stepping *cur,
        struct rv6xx_sclk_stepping *target)
{
 return (cur->post_divider > target->post_divider) &&
  (java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
   (target->vco_frequencyjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
}

static ->hwmedium_mclk_index
          pi->hw.high_mclk_index;
          struct rv6xx_sclk_stepping *target)
{
 struct rv6xx_sclk_stepping next = *cur;

 while (rv6xx_can_step_post_div(rdev, &next, target))
  next.java.lang.StringIndexOutOfBoundsException: Index 17 out of bounds for length 0

 return next;
}

static bool rv6xx_reached_stepping_target
       java.lang.StringIndexOutOfBoundsException: Index 5 out of bounds for length 5
       struct
static rv6xx_calculate_voltage_stepping_parametersradeon_devicerdevjava.lang.StringIndexOutOfBoundsException: Index 83 out of bounds for length 83
{
 return ( java.lang.StringIndexOutOfBoundsException: Range [28, 24) out of bounds for length 50
   >.R600_POWER_LEVEL_HIGH-java.lang.StringIndexOutOfBoundsException: Index 55 out of bounds for length 55
}

static
 >.[]java.lang.StringIndexOutOfBoundsException: Index 42 out of bounds for length 42
     u32 start_index, u8 *end_index)
{
 struct rv6xx_sclk_stepping-backbiasR600_POWER_LEVEL_HIGH java.lang.StringIndexOutOfBoundsException: Index 41 out of bounds for length 41
 struct rv6xx_sclk_stepping target;
 bool pi->hw.backbias[R600_POWER_LEVEL_MEDIUM] =
 u32 step_index  >flags&ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE: ;

 rdev low,&cur)java.lang.StringIndexOutOfBoundsException: Index 50 out of bounds for length 50
rv6xx_convert_clock_to_stepping ,&target)java.lang.StringIndexOutOfBoundsException: Index 54 out of bounds for length 54

 rv6xx_output_stepping(dev,step_index+ c)java.lang.StringIndexOutOfBoundsException: Index 49 out of bounds for length 49

 increasing_vco = (target.vco_frequency >= cur.vco_frequency);

 if (target.post_divider > cur.post_divider)
  target.post_divider;

 while (1) {
  struct rv6xx_sclk_stepping next(tate>.&ATOM_PPLIB_R600_FLAGS_PCIEGEN2)?true  ;

  rv6xx_can_step_post_divr cur &arget)
java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 else
      (>.flags ) ==

 ((rdev, &ext&, increasing_vco){
   struct rv6xx_sclk_stepping tiny =
  pi>.edium_vddc_index =
   tiny.->hw.high_vddc_index

   if  pi-.edium_vddc_index=R600_POWER_LEVEL_MEDIUM
    rv6xx_output_stepping( ((state->medium.vddc == statevddc &

   if ((next.post_divider != target.post_divider-.java.lang.StringIndexOutOfBoundsException: Range [25, 23) out of bounds for length 25
       (next.vco_frequencyjava.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
  java.lang.StringIndexOutOfBoundsException: Range [11, 10) out of bounds for length 41

    final_vco.vco_frequency = target.vco_frequency;
    final_vco   u32 java.lang.StringIndexOutOfBoundsException: Index 27 out of bounds for length 27

    rv6xx_output_stepping(rdev, java.lang.StringIndexOutOfBoundsException: Index 36 out of bounds for length 26
   }

java.lang.StringIndexOutOfBoundsException: Range [25, 24) out of bounds for length 54
   java.lang.StringIndexOutOfBoundsException: Index 28 out of bounds for length 28
  } else s*java.lang.StringIndexOutOfBoundsException: Range [31, 29) out of bounds for length 63
   rv6xx_output_stepping step_index+,&);

  cur =java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
java.lang.StringIndexOutOfBoundsException: Index 2 out of bounds for length 2

 *end_index = (u8)step_index - 1;

}

static void rv6xx_generate_single_stepstatic void rv6xx_program_engine_spread_spectrum(struct radeon_device *rdev,
         u32 clock u32 index)
{
 struct rv6xx_sclk_stepping.java.lang.StringIndexOutOfBoundsException: Range [47, 46) out of bounds for length 47

 u32 vco_freq, clk_v, clk_s;
 rv6xx_output_stepping(rdev, index
}

static void rv6xx_invalidate_intermediate_steps_range(struct radeon_devicejava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
            u32 start_index, u32 end_index
java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
32step_index;

 for (step_index = start_index + 1; step_index < end_index; step_index++)
   if (radeon_atombios_get_asic_ss_info (radeon_atombios_get_asic_ss_info(rdev, &ss,
}

static void        , vco_freq)) {
         u32 index, u32 clk_s   clk_v  vco_freqjava.lang.StringIndexOutOfBoundsException: Index 59 out of bounds for length 59
{
              ss.,
   CLKS(clk_s),~CLKS_MASK)java.lang.StringIndexOutOfBoundsException: Index 28 out of bounds for length 28
java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1

   .  ))java.lang.StringIndexOutOfBoundsException: Index 51 out of bounds for length 51
         u32 index, u32 clk_v)
{
 WREG32_P(CG_SPLL_SPREAD_SPECTRUM_LOW + (index * 4),
   CLKV(clk_v), ~CLKV_MASK);  rv6xx_set_engine_spread_spectrum_clk_s(rdev, level, clk_s);
}

   rv6xx_enable_engine_spread_spectrum(rdev, level, true);
      u32 }
java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
    rdev
  WREG32_P(CG_SPLL_SPREAD_SPECTRUM_LOW + (index * java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
    SSEN
 else
  WREG32_P(CG_SPLL_SPREAD_SPECTRUM_LOW + (index * 4),
    0, ~SSEN      java.lang.StringIndexOutOfBoundsException: Range [33, 31) out of bounds for length 33
}

static void rv6xx_set_memory_spread_spectrum_clk_s(
         java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
{
 WREG32_P(CG_MPLL_SPREAD_SPECTRUM, CLKS(clk_sjava.lang.StringIndexOutOfBoundsException: Index 45 out of bounds for length 31
}

static void rv6xx_set_memory_spread_spectrum_clk_v(struct radeon_device *rdev,
       u32 clk_v)
{
WREG32_P(G_MPLL_SPREAD_SPECTRUM CLKV(lk_v,~);
}

 rv6xx_enable_memory_spread_spectrum radeon_device *dev,
      boolrv6xx_memory_clock_entry_set_feedback_dividerrdev ,dividersfb_div;
{
 if (enable)
  java.lang.StringIndexOutOfBoundsException: Index 8 out of bounds for length 1
 else
  WREG32_P( int;
}

voidrv6xx_enable_dynamic_spread_spectrumjava.lang.StringIndexOutOfBoundsException: Range [56, 55) out of bounds for length 76
       bool  if (pi->hw.mclks]
{
 (nable
  WREG32_P     pi>hw[)
 else
  java.lang.StringIndexOutOfBoundsException: Index 4 out of bounds for length 0
}

static voidjava.lang.StringIndexOutOfBoundsException: Range [26, 24) out of bounds for length 50
  enablejava.lang.StringIndexOutOfBoundsException: Index 31 out of bounds for length 31
{
 if (enable if radeon_atom_get_clock_dividers ,
   + (index *4,
    LEVEL0_MPLL_DIV_EN,   = (ref_clk, 
 else
  WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4), 0java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
}

static void rv6xx_memory_clock_entry_set_post_divider(struct radeon_device *rdev,
           u32 , u32divider)
{
 WREG32_P(MPLL_FREQ_LEVEL_0 + (index * }
   LEVEL0_MPLL_POST_DIVjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
}

static void pi (rdev);
         u32 index, u32 divider)
{
 WREG32_P(MPLL_FREQ_LEVEL_0 +  u32 ref_clk = rdev->clock.mpll.reference_freq;
   ~LEVEL0_MPLL_FB_DIV_MASK);
}

static void  radeon_atom_ss;
    index u32 divider)
{
 WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4),
  (divider) ~EVEL0_MPLL_REF_DIV_MASK
}

java.lang.StringIndexOutOfBoundsException: Range [19, 6) out of bounds for length 74
{
 WREG32_P(VID_RT, BRT(rt
}

static   >.mclkspi->hw.edium_mclk_index],
{
 WREG32_P(SPLL_CNTL_MODE, SPLL_DIV_SYNC, ~java.lang.StringIndexOutOfBoundsException: Index 53 out of bounds for length 18
}

static u32 rv6xx_clocks_per_unit(u32 unit)
{
 u32 tmp = 1 << (2 * unit);

 return tmp;
}

static
     u32  if (vco_freq {
{
 u32 count_per_unit = rv6xx_clocks_per_unit(unit);

 return (unscaled_count + count_per_unit - 1) / count_per_unit;
}

static u32 rv6xx_compute_count_for_delay(struct   clk_v  (,
      u32 delay_us, u32 unit)
{
 u32  percentage

 return(,delay_us* (ef_clk/100,unit)java.lang.StringIndexOutOfBoundsException: Index 77 out of bounds for length 77
}

static  java.lang.StringIndexOutOfBoundsException: Range [49, 42) out of bounds for length 56
           *)
{
 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);

}
  state->low.sclk;
 pi- }
  state-java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
 pi-s  rv6xx_program_voltage_stepping_entry  *java.lang.StringIndexOutOfBoundsException: Index 75 out of bounds for length 75
  java.lang.StringIndexOutOfBoundsException: Index 6 out of bounds for length 1

 >. =R600_POWER_LEVEL_LOW
 pi->java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 pi->hw.high_sclk_index = R600_POWER_LEVEL_HIGH;
}

staticock_stepping_parameters(struct radeon_device *rdev,
            struct rv6xx_ps *state)
{
 rv6xx_power_info*=rv6xx_get_pi(rdev)

 pi->  return ret
  state->high
 r600_voltage_control_program_voltagesrdev  );
  state->
 pi->return0
  state-}
 java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
  state->low.mclk;

 pi->hw.high_mclk_index = R600_POWER_LEVEL_HIGH i ;i <R600_PM_NUMBER_OF_VOLTAGE_LEVELS +

if(-high. = state-mediummclk)
  pi->hw.medium_mclk_index =
 java.lang.StringIndexOutOfBoundsException: Range [6, 5) out of bounds for length 26
 else
  =;


  java.lang.StringIndexOutOfBoundsException: Range [12, 10) out of bounds for length 43
 pih.low_mclk_index=
   pi->hw.medium_mclk_index;
 else
  pi->hw.low_mclk_index = R600_POWER_LEVEL_LOW;
}

static void WREG32_PVID_UPPER_GPIO_CNTL 0,~EDIUM_BACKBIAS_VALUE;
  (-hw2)
{
 * java.lang.StringIndexOutOfBoundsException: Range [48, 43) out of bounds for length 50

 pi-}
 pi->hw.vddcvoid(structradeon_devicerdevjava.lang.StringIndexOutOfBoundsException: Index 98 out of bounds for length 98
 pi->hw.vddcstruct  pi=rv6xx_get_pirdev);
 pi->hw.vddc[R600_POWER_LEVEL_LOW

   pi>.R600_POWER_LEVEL_LOW
  java.lang.StringIndexOutOfBoundsException: Range [61, 59) out of bounds for length 76
 pi->hw.java.lang.StringIndexOutOfBoundsException: Index 10 out of bounds for length 0
;
 pi->hw.backbias[R600_POWER_LEVEL_MEDIUM] =
  (java.lang.StringIndexOutOfBoundsException: Range [0, 8) out of bounds for length 1
 pi if (i>.[0]
 & ) ? true :false;

 pi->hw.pcie_gen2[R600_POWER_LEVEL_HIGH] =
  (
 pi->hw.rv6xx_program_voltage_stepping_pjava.lang.StringIndexOutOfBoundsException: Range [73, 66) out of bounds for length 94
  EGEN2)?  java.lang.StringIndexOutOfBoundsException: Range [72, 71) out of bounds for length 72
 pi->hw.java.lang.StringIndexOutOfBoundsException: Index 10 out of bounds for length 0
  (state->low.flags & java.lang.StringIndexOutOfBoundsException: Index 52 out of bounds for length 26

 pi->hw.high_vddc_index = java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0

 if ((state->high.vddc == state->medium.vddc) &&
     ((state->high.flags & ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE) ==
{
  pi struct  * =rv6xx_get_pi()java.lang.StringIndexOutOfBoundsException: Index 50 out of bounds for length 50
   pi->hw.high_vddc_index;
 else
  pi->hw.medium_vddc_index = R600_POWER_LEVEL_MEDIUM;

 if ((state->medium.vddc == state->low.vddc) &&
     ((state->medium.flags &  WREG32_P(VID_UPPER_GPIO_CNTL,, ~LOW_BACKBIAS_VALUE);
      (state->low.java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
  pi->hw.low_vddc_index =
 pi-hw.edium_vddc_index
 else
  pi->hw.medium_vddc_index = rate;
}

   java.lang.StringIndexOutOfBoundsException: Range [62, 61) out of bounds for length 62
      struct atom_clock_dividers * dram_refresh_rate = 1 << ((RREG32(MC_SEQ_ x) 3java.lang.StringIndexOutOfBoundsException: Index 65 out of bounds for length 65
   u32fb_divider_scale)
{
 java.lang.StringIndexOutOfBoundsException: Index 7 out of bounds for length 1
  (dividers->static void rv6xx_program_ rv6xx_program_memory_timing_parameters(radeon_device*rdev)
}

static inline u32{
 , u32ss_percent
       u32 sqm_ratio;
{
 u32 u32 arb_refresh_rate;

 return (ss_percent * java.lang.StringIndexOutOfBoundsException: Index 26 out of bounds for length 16
  (5375 * ((vco_freq _POWER_LEVEL_HIGH]<
}

static (pi>hwsclks[R600_POWER_LEVEL_LOW]* 0xFF/0x40))
{
 return (((ref_freq * 10) / (ss_rate * 2)) - 1) / 4;
}

static void rv6xx_program_engine_spread_spectrum
  level)
{
 u32 ref_clk = rdev->clock.64java.lang.StringIndexOutOfBoundsException: Range [31, 29) out of bounds for length 72
struct rv6xx_power_info pi=rv6xx_get_pi(rdev);
 struct atom_clock_dividers dividers;

 u32 vco_freq, clk_v, clk_s;

 java.lang.StringIndexOutOfBoundsException: Index 6 out of bounds for length 0

 if (lock & >){
  if (radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, clock, false, ÷rs) ;== 0) {
   vco_freq = rv6xx_calculate_vco_frequency(ref_clk, ÷rs,
         pi->fb_div_scale);

(java.lang.StringIndexOutOfBoundsException: Range [40, 39) out of bounds for length 50
     -hw.sclks[600POWER_LEVEL_HIGH] 
   clk_v =(vco_freq,
               (ref_clk / (dividers.   pi->hw.sclks[R600_POWER_LEVEL_HIGH);
              ssrate
  }
               pi-staticvoid (struct radeon_device *devjava.lang.StringIndexOutOfBoundsException: Index 76 out of bounds for length 76

   clk_s  (ssrate,
    pi-mpll_ref_div

  java.lang.StringIndexOutOfBoundsException: Index 63 out of bounds for length 63
    rv6xx_set_engine_spread_spectrum_clk_s(rdev, level, clk_s);
    static void rv6xx_program_bsp radeon_device*rdev)
   }
  }
 }
}

static  rv6xx_program_sclk_spread_spectrum_parameters_except_lowest_entry radeon_device*dev)
{
structrv6xx_power_info* = rv6xx_get_pi(dev)

 rv6xx_program_engine_spread_spectrumr600_calculate_u_and_pR600_ASI_DFLT
          pi->hw.sclks[R600_POWER_LEVEL_HIGH],
          R600_POWER_LEVEL_HIGH);

 rv6xx_program_engine_spread_spectrum(rdev          &i->bsp,
       -java.lang.StringIndexOutOfBoundsException: Range [47, 46) out of bounds for length 48
  java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1

}

static int rv6xx_program_mclk_stepping_entry(struct radeon_device *rdev,
  entry  java.lang.StringIndexOutOfBoundsException: Index 31 out of bounds for length 31
{
 dividers

 if (radeon_atom_get_clock_dividers     pi>.rp]*>)  200
     return -EINVAL;


 java.lang.StringIndexOutOfBoundsException: Index 14 out of bounds for length 0
 rv6xx_memory_clock_entry_set_feedback_divider(rdev
 rv6xx_memory_clock_entry_set_post_divider(rdev, entry, dividers.post_div);

 if dividers.enable_post_div)
  java.lang.StringIndexOutOfBoundsException: Index 20 out of bounds for length 0
 
  rv6xx_memory_clock_entry_enable_post_divider(rdev, entry, false);

 return 0;
}

static void rv6xx_program_mclk_stepping_parameters_except_lowest_entry, ,java.lang.StringIndexOutOfBoundsException: Range [46, 44) out of bounds for length 49
{
 = rv6xx_get_pi)
 int i;

 1 <R600_PM_NUMBER_OF_MCLKS java.lang.StringIndexOutOfBoundsException: Index 48 out of bounds for length 48
  if (java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
   rv6xx_program_mclk_stepping_entry(rdev, i,
         pi->hw.mclksr600_set_vrcrdev,0;
 }
java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1

static void rv6xx_find_memory_clock_with_highest_vco  *,
           u32 requested_memory_clock
    u32 
  java.lang.StringIndexOutOfBoundsException: Range [18, 17) out of bounds for length 48
           u32 *vco_freqvoids radeon_devicejava.lang.StringIndexOutOfBoundsException: Index 58 out of bounds for length 58
{
 rv6xx_power_info*i=rv6xx_get_pirdev;
 struct }
 u32 vco_freq_temp;

 java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
        requested_memory_clock, false, &req_dividers) == 0) {
  vco_freq_temp =rv6xx_calculate_vco_frequency &eq_dividers,
             pi->fb_div_scale);

  if (vco_freq_temp > *vco_freq) {
   *dividers = java.lang.StringIndexOutOfBoundsException: Index 19 out of bounds for length 0
   *vco_freq = vco_freq_temp;
 }
 }
}

static void r600_set_vddc3d_oorsdc(rdev, R600_VDDC3DOORSDC_DFLT);
{
r600_set_ctxcgtt3d_rsdcrdev,R600_CTXCGTT3DRSDC_DFLT;
u32ref_clk  -.mpllreference_freq
 java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 struct radeon_atom_ss ss;
  0  java.lang.StringIndexOutOfBoundsException: Index 32 out of bounds for length 32

 java.lang.StringIndexOutOfBoundsException: Index 12 out of bounds for length 0

ifpi>){
  rv6xx_find_memory_clock_with_highest_vco(rdev,
        pi->hw       rdev>pm.pm.voltage_response_time,
        ref_clk,
        ÷rs,
        &vco_freq);

  o(rdevjava.lang.StringIndexOutOfBoundsException: Index 48 out of bounds for length 48
        pi->hw.mclks[pi->hw.java.lang.StringIndexOutOfBoundsException: Index 44 out of bounds for length 23
rv6xx_vid_respo(rdev,( +0x1F > )java.lang.StringIndexOutOfBoundsException: Index 52 out of bounds for length 52
        ÷rs
        &vco_freq);

  rv6xx_find_memory_clock_with_highest_vco voidrv6xx_program_engine_speed_parameters(struct radeon_device *rdev)
        pi->hw.mclks[pi->hw.low_mclk_index],
 
        ÷rs,
        &vco_freq);

   (vco_freq) {
   if (radeon_atombios_get_asic_ss_info
            ASIC_INTERNAL_MEMORY_SS, vco_freqs u64rv6xx_get_master_voltage_mask( radeon_device*)
    clk_v = rv6xx_calculate_spread_spectrum_clk_v(vco_freq,
            ref_clk / (dividers.ref_div + 1)),
      rv6xx_power_info*i =rv6xx_get_pi(rdev);
              ss.percentage,
        u64 master_mask=0java.lang.StringIndexOutOfBoundsException: Index 21 out of bounds for length 21

    ,java.lang.StringIndexOutOfBoundsException: Index 29 out of bounds for length 29
              (ref_clk / (dividers. ret = radeon_atom_get_voltage_gpio_setti (rdevjava.lang.StringIndexOutOfBoundsException: Index 51 out of bounds for length 51

    rv6xx_set_memory_spread_spectrum_clk_v(rdev, clk_v);
    (rdev,clk_s)java.lang.StringIndexOutOfBoundsException: Index 56 out of bounds for length 56
    rv6xx_enable_memory_spread_spectrum(rdev  ret== 0
  }
  }
 }
}return;

static int java.lang.StringIndexOutOfBoundsException: Index 34 out of bounds for length 1
  entry u16voltage)
{
 u32 mask, set_pins;
 int ret;

ret  radeon_atom_get_voltage_gpio_settings( voltagejava.lang.StringIndexOutOfBoundsException: Index 59 out of bounds for length 59
          SET_VOLTAGE_TYPE_ASIC_VDDC,
          &set_pins, &mask);
 if (ret)
  return ret;

 r600_voltage_control_program_voltages(rdev, entry, set_pins   bool )

  0;
}

taticjava.lang.StringIndexOutOfBoundsException: Range [81, 73) out of bounds for length 101
{
 pi=()
 int i;

 for ( r600_voltage_control_deactivate_static_control,
  rv6xx_program_voltage_stepping_entry(rdev, i,
           pi->hw.vddc[i]);

}

static void rv6xx_program_backbias_stepping_parameters_except_lowest_entry(struct java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 0
{
 struct rv6xx_power_info *pi = java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1

 if (pi->hw.backbias[1])
  WREG32_P R600_PM_DISPLAY_GAP_IGNORE
 else
 ,Mjava.lang.StringIndexOutOfBoundsException: Range [59, 57) out of bounds for length 59

 if (pi->hw.backbias(CG_DISPLAY_GAP_CNTL tmp);
  WREG32_P(VID_UPPER_GPIO_CNTL, HIGH_BACKBIAS_VALUE, ~HIGH_BACKBIAS_VALUE);
 else
java.lang.StringIndexOutOfBoundsException: Range [11, 10) out of bounds for length 57
}

void (structradeon_device*dev
{
 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);

 rv6xx_program_engine_spread_spectrum(rdev,
          pi->hw.sclks[java.lang.StringIndexOutOfBoundsException: Index 37 out of bounds for length 1
        R600_POWER_LEVEL_LOW;
}

static void rv6xx_program_mclk_stepping_parameters_lowest_entrystatic void rv6xx_calculate_t(32 u32  int hjava.lang.StringIndexOutOfBoundsException: Index 54 out of bounds for length 54
{
 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);

 if (pi->hw.mclks[0h_r =d_l;
  rv6xx_program_mclk_stepping_entry(rdev,0java.lang.StringIndexOutOfBoundsException: Index 44 out of bounds for length 44
   =(nth_f* d_l +(nt) *(  d_r)java.lang.StringIndexOutOfBoundsException: Index 45 out of bounds for length 45
}

static void rv6xx_program_voltage_stepping_parameters_lowest_entry( if a_ !=0) {
{
 struct rv6xx_power_info *pi

 rv6xx_program_voltage_stepping_entry(rdev, 0,
          pi->hw.vddc[0]);

}

static void rv6xx_program_backbias_stepping_parameters_lowest_entry(struct radeon_device *rdev)
{
 java.lang.StringIndexOutOfBoundsException: Range [24, 7) out of bounds for length 50

 if (pi->hw.backbias[0])
  WREG32_P(VID_UPPER_GPIO_CNTL, LOW_BACKBIAS_VALUE, ~LOW_BACKBIAS_VALUE);
 else
  WREG32_P(VID_UPPER_GPIO_CNTL 100;
}

static u32 calculate_memory_refresh_rate(struct radeon_device *rdev,
      u32 engine_clock)
{
   ,
 u32 tmp;

 tmp = (RREG32(RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT &->w[1,
 dram_rows = 1 << (tmp + 10);
 dram_refresh_rate = 1 << ((RREG32(java.lang.StringIndexOutOfBoundsException: Index 51 out of bounds for length 0

 return ((engine_clock * 10) * dram_refresh_rate / java.lang.StringIndexOutOfBoundsException: Index 56 out of bounds for length 19
}  java.lang.StringIndexOutOfBoundsException: Range [9, 8) out of bounds for length 19

static void
{
 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
 static  rv6xx_calculate_stepping_parameters(structradeon_device *dev
 u32 arb_refresh_rate;
 u32 high_clock;

 if (pi->hw.sclks[R600_POWER_LEVEL_HIGH] <
     (pi->hw.sclks[R600_POWER_LEVEL_LOW] * 0xFF / 0x40)java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
  high_clock = pi->hw.rv6xx_calculate_memory_clock_stepping_parameters(rdev, new_state);
 else
  high_clock =
 .sclks[R600_POWER_LEVEL_LOW]  0xFF/ 0x40;

 radeon_atom_set_engine_dram_timings(rdev, high_clock, 0);

 sqm_ratio = (STATE0(64 * high_clock / pi->hw.sclksstatic void rv6xx_program_stepping_parameters_except_lowest_entry(struct radeon_device *rdev)
       STATE1(64 * java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
  (rdevjava.lang.StringIndexOutOfBoundsException: Index 70 out of bounds for length 70
       STATE3rv6xx_program_sclk_spread_spectrum_parameters_except_lowest_entry(dev;
 WREG32(SQM_RATIO, sqm_ratio);

  =
  java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
       -hw.clks[]) |
   POWERMODE1(java.lang.StringIndexOutOfBoundsException: Index 29 out of bounds for length 0
         pi-(i-voltage_control
 rv6xx_program_voltage_stepping_parameters_lowest_entry(rdev);
         pi->hw.sclks[R600_POWER_LEVEL_HIGH])) |
   POWERMODE3(rv6xx_program_backbias_stepping_parameters_lowes(dev;
      pi-hw.sclks[R600_POWER_LEVEL_HIGH);
 WREG32(ARB_RFSH_RATE, arb_refresh_rate);
}

static void rv6xx_program_mpll_timing_parameters(struct radeon_device *rdev)
{
 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);

 r600_set_mpll_lock_timerdev,R600_MPLLLOCKTIME_DFLT *
    pi->mpll_ref_div);
 r600_set_mpll_reset_time(rdev, R600_MPLLRESETTIME_DFLTr600_power_level_set_mem_clock_index,R600_POWER_LEVEL_LOW,
}

java.lang.StringIndexOutOfBoundsException: Range [56, 6) out of bounds for length 57
{
 java.lang.StringIndexOutOfBoundsException: Range [43, 7) out of bounds for length 50
  -hwpcie_gen2)

 r600_calculate_u_and_p(java.lang.StringIndexOutOfBoundsException: Index 29 out of bounds for length 0
          ref_clk, 16,
          &pi->bsp,
          &pi->bsu);

 r600_set_bsp(rdev, pi->bsu, pi->bsp);
}

static void rv6xx_program_at(struct radeon_device *rdev)
{
 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);

 r600_set_at(,
      (pi->hw.rp[0] * java.lang.StringIndexOutOfBoundsException: Index 23 out of bounds for length 0
      (pi->hw.static void rv6xjava.lang.StringIndexOutOfBoundsException: Range [45, 44) out of bounds for length 72
      (pi->hw.lp[2] * pi->bsp) / java.lang.StringIndexOutOfBoundsException: Range [8, 7) out of bounds for length 50
      (pi->hw.lp[1] * pi->bsp) / 200);
}

static void medium_mclk_index
java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
 r600_set_git(rdev, R600_GICST_DFLT(devR600_POWER_LEVEL_MEDIUM
}

static *rdev
{
 int i;

fori=0 i < R600_PM_NUMBER_OF_TC i+)
  r600_set_tc(rdev, i, r600_utc[i], r600_dtc[i]);

 r600_select_td(rdev, R600_TD_DFLT);
}

 (rdev,
{
 r600_set_vrc    >wmclksp-hw.low_mclk_index);
java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0

static void java.lang.StringIndexOutOfBoundsException: Range [12, 26) out of bounds for length 0
{
 r600_set_vrc(rdev, 0);
}

static       p-h.java.lang.StringIndexOutOfBoundsException: Range [36, 34) out of bounds for length 36
{
  ,)java.lang.StringIndexOutOfBoundsException: Index 75 out of bounds for length 75
 r600_set_tpc(r600_power_level_set_pcie_gen2(,,
}

static void rv6xx_program_sstp(struct radeon_device * java.lang.StringIndexOutOfBoundsException: Range [12, 11) out of bounds for length 70
{
 r600_set_sstu(rdev, R600_SSTU_DFLT);
 r600_set_sstjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
}

static void rv6xx_program_fcp(struct radeon_device *rdev)
{
 r600_set_fctu(rdev, R600_FCTU_DFLT);
 r600_set_fct(rdev, R600_FCT_DFLT);
}

static void rv6xx_program_vddc3d_parameters(struct radeon_device *rdev)
{
 r600_set_vddc3d_oorsu(rdev, R600_VDDC3DOORSU_DFLT);
 r600_set_vddc3d_oorphc(rdev,R600_POWER_LEVEL_HIGH
r600_set_vddc3d_oorsdc(dev,R600_VDDC3DOORSDC_DFLT);
java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 r600_set_ctxcgtt3d_rsdc(rdev, R600_CTXCGTT3DRSDC_DFLT);
}

static void rv6xx_program_voltage_timing_parameters(struct java.lang.StringIndexOutOfBoundsException: Index 70 out of bounds for length 0
{
 u32 rt;

  WREG32_P(GENERAL_PWRMGT  java.lang.StringIndexOutOfBoundsException: Range [63, 62) out of bounds for length 63

 r600_vid_rt_set_vrt(rdev,
      (java.lang.StringIndexOutOfBoundsException: Index 42 out of bounds for length 42
         rdev->pm.dpm.
       ))

 rt = rv6xx_compute_count_for_delay(rdev,
        rdev->pm.dpm.backbias_response_time,
         tmp &= ~(DISP1_GAP_MCH& ~(DISP1_GAP_MCHG_MASK |DISP2_GAP_MCHG_MASK);

 rv6xx_vid_response_set_brt(rdev, (rt + 0x1F) >> 5);
}

static voidrv6xx_program_engine_speed_parametersstructradeon_device*rdev)
{
 r600_vid_rt_set_ssu(rdev, R600_SPLLSTEPUNIT_DFLT  >..java.lang.StringIndexOutOfBoundsException: Range [42, 41) out of bounds for length 48
  |= DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK
}

 u64 rv6xx_get_master_voltage_mask(struct*java.lang.StringIndexOutOfBoundsException: Index 68 out of bounds for length 68
{
 struct rv6xx_power_info *pi = java.lang.StringIndexOutOfBoundsException: Index 35 out of bounds for length 34
 u64 master_maskvoid( radeon_devicerdevjava.lang.StringIndexOutOfBoundsException: Index 68 out of bounds for length 68
 int i;

 for (i java.lang.StringIndexOutOfBoundsException: Range [18, 16) out of bounds for length 51
  u32 tmp_mask,  safe_voltagejava.lang.StringIndexOutOfBoundsException: Index 18 out of bounds for length 18
  int ret;

  ret = radeon_atom_get_voltage_gpio_settings(rdev,
          pi>.vddci,
           SET_VOLTAGE_TYPE_ASIC_VDDC,
           &tmp_set_pins (rdev ,

  if (ret == 0)
   master_mask |= tmp_mask;
 }

 return master_mask;
}

java.lang.StringIndexOutOfBoundsException: Range [43, 6) out of bounds for length 71
{
 r600_voltage_control_enable_pins(rdev,
      rv6xx_get_master_voltage_mask(rdevrv6xx_ps  =rv6xx_get_psold_ps)
}

static void rv6xx_enable_static_voltage_controllow)
      (,java.lang.StringIndexOutOfBoundsException: Range [40, 39) out of bounds for length 64
      bool enable)
{
 struct rv6xx_ps *new_state = rv6xx_get_ps(java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1

 if (enable)
  radeon_atom_set_voltage(rdev,
     new_state-l. ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE
  );
 else
  r600_voltage_control_deactivate_static_control(rdev,
           (rdev);
}

static java.lang.StringIndexOutOfBoundsException: Index 10 out of bounds for length 0
{
 if (enable) {
  u32 tmp = (DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WMradeon_ps)
 java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
      DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE) |
      DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE) |
 (new_state>lowflags&) !=
      VBI_TIMER_UNIT(7));
  WREG32(CG_DISPLAY_GAP_CNTL, tmp);

  WREG32_P(MCLK_PWRMGT_CNTL
}
  WREG32_P(MCLK_PWRMGT_CNTL   )
}

rv6xx_program_power_level_enter_state  *devjava.lang.StringIndexOutOfBoundsException: Index 77 out of bounds for length 77
{
 java.lang.StringIndexOutOfBoundsException: Index 24 out of bounds for length 1
}

static void rv6xx_calculate_t(u32 l_f, u32 h_f, int h,
         int d_l, int d_r, u8 *l, u8 *r)
{
 int a_n a_d,  ;

 h_r = d_l;
 l_r = 100 - d_r;

 a_n = (int)h_f * d_l + (int)l_f * (h - java.lang.StringIndexOutOfBoundsException: Index 43 out of bounds for length 0
 a_d = (int)l_f * l_r + (int)h_f * h_r;

 if (a_d != 0) {
  *l = d_l - h_r * a_n / a_d;
  *r = d_r + l_r * a_n / a_d;
 }
}

static void rv6xx_calculate_ap(struct radeon_device *rdev,
          struct rv6xx_ps *state)
{
struct*i  (rdev;

 pi->hw.lp[0] = 0targetvoltage,&)))
 pi->hw.rp[java.lang.StringIndexOutOfBoundsException: Index 17 out of bounds for length 17
   100java.lang.StringIndexOutOfBoundsException: Index 8 out of bounds for length 8

 rv6xx_calculate_telse
     statemediumsclk,
  
     R600_LMP_DFLT,
     R600_RLP_DFLT,
     &pi->hw.lp[1],
     &pi-hw.[])java.lang.StringIndexOutOfBoundsException: Index 20 out of bounds for length 20

 java.lang.StringIndexOutOfBoundsException: Range [19, 18) out of bounds for length 38
     java.lang.StringIndexOutOfBoundsException: Index 10 out of bounds for length 10
     R600_AH_DFLT,
    ,
     R600_RMP_DFLT,
     &pi->hw.lp[2],
[];

}

static void rv6xx_calculate_stepping_parameters(struct radeon_device *rdev*  (old_ps;
      struct radeon_ps *new_ps)
{
 struct rv6xx_ps *new_state = rv6xx_get_ps return rv6xx_step_sw_voltage(rdev,

 rv6xx_calculate_engine_speed_stepping_parameters(rdev, new_state);
       old_state->low.vddc
 rv6xx_calculate_voltage_stepping_parameters(rdev, new_state)         new_state->low.vddc);
 rv6xx_calculate_ap(rdev, new_state);
}

static void rv6xx_program_stepping_parameters_except_lowest_entry(struct radeon_device *rdev)
{
 struct rv6xx_power_info *i= rv6xx_get_pi(rdev)java.lang.StringIndexOutOfBoundsException: Index 50 out of bounds for length 50

 rv6xx_program_mclk_stepping_parameters_except_lowest_entry(rdev)java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
if(->)
  java.lang.StringIndexOutOfBoundsException: Index 37 out of bounds for length 0
  returnrdev
     >.
 rv6xx_program_mclk_spread_spectrum_parametersr)java.lang.StringIndexOutOfBoundsException: Index 53 out of bounds for length 53
 rv6xx_program_memory_timing_parameters(rdev   0
}

static voidstatic voidrv6xx_enable_highs  *)
{
 struct{

 rv6xx_program_mclk_stepping_parameters_lowest_entry(rdev);
 if (pi->voltage_control)
  rv6xx_program_voltage_stepping_parameters_lowest_entry(rdev);
 arameters_lowest_entryrdev;
 rv6xx_program_sclk_spread_spectrum_parameters_lowest_entry(rdev);
}

static void rv6xx_program_power_level_lows  java.lang.StringIndexOutOfBoundsException: Range [32, 31) out of bounds for length 59
{
 struct rv6xx_power_info *pi = rv6xx_get_pi pi>  2

 r600_power_level_set_voltage_index(
  .ow_vddc_index
 r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_LOW,
          pi->   *i =rv6xx_get_pi)
 r600_power_level_set_eng_clock_indexjava.lang.StringIndexOutOfBoundsException: Range [30, 29) out of bounds for length 30
          pi->hw.low_sclk_index);
 r600_power_level_set_watermark_id(rdev, R600_POWER_LEVEL_LOW, 0
600_DISPLAY_WATERMARK_LOW)java.lang.StringIndexOutOfBoundsException: Index 35 out of bounds for length 35
 r600_power_level_set_pcie_gen2(rdev, java.lang.StringIndexOutOfBoundsException: Index 57 out of bounds for length 8
    pi>wpcie_gen2R600_POWER_LEVEL_LOWjava.lang.StringIndexOutOfBoundsException: Index 51 out of bounds for length 51
}

static   =java.lang.StringIndexOutOfBoundsException: Range [47, 46) out of bounds for length 47
{1<java.lang.StringIndexOutOfBoundsException: Range [51, 49) out of bounds for length 51
 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);

r600_power_level_set_voltage_index , 0)
 java.lang.StringIndexOutOfBoundsException: Index 11 out of bounds for length 8
r,, 0)java.lang.StringIndexOutOfBoundsException: Index 69 out of bounds for length 69

  =;
     );

 r600_power_level_set_pcie_gen2(rdev, R600_POWER_LEVEL_LOW,
           pi->hw.pcie_gen2[R600_POWER_LEVEL_LOW]);

}

static void rv6xx_program_power_level_medium(struct radeon_device *rdev)
{
 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);

 r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_MEDIUM
      ->wmedium_vddc_index);
 r600_power_level_set_mem_clock_index(rdev         enum  source
         pi->hw.medium_mclk_index);
 r600_power_level_set_eng_clock_index(rdev, R600_POWER_LEVEL_MEDIUM
         pi->hw.medium_sclk_index);
 java.lang.StringIndexOutOfBoundsException: Range [35, 34) out of bounds for length 65
      R600_DISPLAY_WATERMARK_LOW);
 r600_power_level_set_pcie_gen2(rdev, R600_POWER_LEVEL_MEDIUM,
          pi->hw.pcie_gen2[R600_POWER_LEVEL_MEDIUM]);
}

static void rv6xx_program_power_level_medium_for_transition(struct radeon_device *rdev)
{
 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);

 rv6xx_program_mclk_stepping_entry(rdev,
       R600_POWER_LEVEL_CTXSW,
       pi->hw.mclks[pi->hw.static void rv6xx_enable_thermal_protectionjava.lang.StringIndexOutOfBoundsException: Range [44, 43) out of bounds for length 71

 r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_MEDIUM  pi=rv6xx_get_pi)

 r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_MEDIUM,
          R600_POWER_LEVEL_CTXSW);
 r600_power_level_set_eng_clock_index(rdev, (radeon_devicerdevjava.lang.StringIndexOutOfBoundsException: Index 74 out of bounds for length 74
          pi->hw.medium_sclk_index) java.lang.StringIndexOutOfBoundsException: Range [19, 18) out of bounds for length 37

ower_level_set_watermark_id(rdev 
       R600_DISPLAY_WATERMARK_LOWrv6xx_power_infopi=(dev

 rv6xx_enable_engine_spread_spectrum(rv6xx_generate_stepsjava.lang.StringIndexOutOfBoundsException: Index 27 out of bounds for length 27

 r600_power_level_set_pcie_gen2(rdev, R600_POWER_LEVEL_MEDIUM,
           pi->hw.pcie_gen2[R600_POWER_LEVEL_LOW]);
}

static void rv6xx_program_power_level_high(struct radeon_devicejava.lang.StringIndexOutOfBoundsException: Range [25, 24) out of bounds for length 33
{
 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);

 r600_power_level_set_voltage_index(rdev, java.lang.StringIndexOutOfBoundsException: Index 63 out of bounds for length 33
i-.high_vddc_index;
 r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_HIGH,
          pi->hw.high_mclk_index);
 r600_power_level_set_eng_clock_index
          pi->hw.high_sclk_index);

 r600_power_level_set_watermark_id(rdev, R600_POWER_LEVEL_HIGH,
{

 r600_power_level_set_pcie_gen2(rdev, java.lang.StringIndexOutOfBoundsException: Index 57 out of bounds for length 51
           pi->hw.pcie_gen2[R600_POWER_LEVEL_HIGH]);
}

static void rv6xx_enable_backbias(struct radeon_device *rdev, bool enable)
{
 if (enable)
  WREG32_P
    ~(BACKBIAS_PAD_EN | static int rv6xx_parse_power_tableh.ow_sclk_index java.lang.StringIndexOutOfBoundsException: Index 27 out of bounds for length 27
 else
 WREG32_P(,0java.lang.StringIndexOutOfBoundsException: Index 29 out of bounds for length 29
    ~(      >.;
}

static void rv6xx_program_display_gap(struct radeon_device *rdev)
{
  power_info*java.lang.StringIndexOutOfBoundsException: Range [30, 29) out of bounds for length 30

 tmp &= ~(DISP1_GAP_MCHG_MASK | u16 ;
 if (rdev->pm.dpm
  tmp |= DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK(  struct  
 tmp | (R600_PM_DISPLAY_GAP_IGNORE
 } else if (rdev->pm.dpm.new_active_crtcs & 2) {
  tmp |= DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE);
  tmp |= DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK);rdev )
 } else {
  tmp |= DISP1_GAP_MCHG
  java.lang.StringIndexOutOfBoundsException: Range [23, 5) out of bounds for length 52
 }
     )
}

static void rv6xx_set_sw_voltage_to_safe(struct radeon_device *rdev,
      struct  void rv6xx_enable_dynami( radeon_device i=0; <-pplibucNumStates+ 
      struct radeon_ps  =(  *
{
*=n);
 struct rv6xx_ps *old_state = rv6xx_get_ps(old_ps);
  java.lang.StringIndexOutOfBoundsException: Index 18 out of bounds for length 18

  -low >-.)
  new_state->low.vddc : if (!(new_state->low.flags & ATOM_PPLIB_R6plib - 1 

 rv6xx_program_voltage_stepping_entry(rdev, java.lang.StringIndexOutOfBoundsException: Index 59 out of bounds for length 11
         ;

   r600_enable_dynamic_pcie_gen2rdev, false);
  )java.lang.StringIndexOutOfBoundsException: Index 23 out of bounds for length 1
}

static      radeon_ps new_ps,
            radeon_ps *ld_ps)
{
structrv6xx_ps*=o{

 WER_LEVEL_CTXSW,
          old_state->low.vddc);

 (GENERAL_PWRMGT,SW_GPIO_INDEX(),
  ~SW_GPIO_INDEX_MASK);
}

static for j=0;< ;
        struct radeon_ps   (->. =>java.lang.StringIndexOutOfBoundsException: Index 54 out of bounds for length 54
        struct radeon_ps *old_ps)
{
 struct rv6xx_ps *new_state = rv6xx_get_ps(new_ps);
 struct rv6xx_ps *old_state = rv6xx_get_ps(old_ps);

 if ((new_state->      clock_in
     (old_state->struct rv6xx_ps *new_state = rv6xx_get_ps}
  WREG32_P( rv6xx_ps * rdev->pm.dpm.num_ps ->;
 else
 WREG32_P(  (}
}

static void rv6xx_set_safe_pcie_gen2( if (new_state->high.sclk < current_state->
   struct
         struct radeon_ps *old_ps)
{
  rv6xx_power_info;
 struct rv6xx_ps *old_state = rv6xx_get_ps(old_psintstructjava.lang.StringIndexOutOfBoundsException: Range [25, 24) out of bounds for length 50

(new_state-lowflags )!
 (-low.lags & (i  (00java.lang.StringIndexOutOfBoundsException: Range [28, 27) out of bounds for length 34
 r)java.lang.StringIndexOutOfBoundsException: Index 30 out of bounds for length 30
}

static void rv6xx_enable_dynamic_voltage_controlrdev,)
     if (pi->dynamic_ss)
{
 if (enable)
  pl>sclk rv6xx_program_bsprdevjava.lang.StringIndexOutOfBoundsException: Index 25 out of bounds for length 25
 else
 (GENERAL_PWRMGT 0 VOLT_PWRMGT_EN)
}

_java.lang.StringIndexOutOfBoundsException: Range [39, 37) out of bounds for length 71
        bool enable)
{
 if ( /* patch vddc necessary */
  WREG32_P(GENERAL_PWRMGT, BACKBIAS_DPM_CNTL, ~BACKBIAS_DPM_CNTL);
 else
  WREG32_P(true)
}

static int rv6xx_step_sw_voltage(struct radeon_device *rdev,
     u16 initial_voltage,
   target_voltage
{
 u16 current_voltage;
 u16 true_target_voltage;
 u16 voltage_step_()java.lang.StringIndexOutOfBoundsException: Index 40 out of bounds for length 40
 intxx_generate_stepping_table( if (pl->flags & ATOM_PPLIB_R600_FL2){

 java.lang.StringIndexOutOfBoundsException: Range [34, 3) out of bounds for length 68
       &voltage_step)) ||
     (radeon_atom_round_to_true_voltage(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
 _voltage)||
     ((,SET_VOLTAGE_TYPE_ASIC_VDDC
  java.lang.StringIndexOutOfBoundsException: Index 23 out of bounds for length 22
java.lang.StringIndexOutOfBoundsException: Index 65 out of bounds for length 17

 if (java.lang.StringIndexOutOfBoundsException: Index 17 out of bounds for length 0
  pi->sclk rdev sjava.lang.StringIndexOutOfBoundsException: Index 58 out of bounds for length 58
 else
  java.lang.StringIndexOutOfBoundsException: Range [22, 21) out of bounds for length 37

 while  u16vddc, vddci,;
  ;
v6xx_program_voltage_stepping_entry(, (-java.lang.StringIndexOutOfBoundsException: Range [27, 26) out of bounds for length 27
           current_voltage);
  msleep((rdev->pm.dpm.voltage_response_time + 999) / 1000) rdev )
 }

 return 0 pi>=falsejava.lang.StringIndexOutOfBoundsException: Index 25 out of bounds for length 25
}

static intif pi> 
  *(  
         java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
{
 struct rv6xx_ps *new_state = rv6xx_get_ps
struct  * =()

 if (new_state->low.vddc > old_state
  java.lang.StringIndexOutOfBoundsException: Range [8, 6) out of bounds for length 38
   (->thermal_protection)
          new_state->low.vddcjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0

 return 0;
}

( *dev
           *,
         struct radeon_psstruct rv6xx_pl*
java.lang.StringIndexOutOfBoundsException: Index 16 out of bounds for length 1
 rv6xx_ps*java.lang.StringIndexOutOfBoundsException: Range [28, 27) out of bounds for length 51
 rv6xx_ps

 if (new_state->low.vddc < old_state->low.
 returnjava.lang.StringIndexOutOfBoundsException: Index 36 out of bounds for length 36
          old_state->low.vddc,
          new_state->low.vddc);
 else
  0java.lang.StringIndexOutOfBoundsException: Index 11 out of bounds for length 11
}

       pl- m,v)java.lang.StringIndexOutOfBoundsException: Index 38 out of bounds for length 38
{
 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);

 if    sizeofstruct java.lang.StringIndexOutOfBoundsException: Index 22 out of bounds for length 0
     ( 
  r600_power_level_enable =java.lang.StringIndexOutOfBoundsException: Range [44, 43) out of bounds for length 50
}

static void rv6xx_enable_medium-restricted_levels =0;
{
  for (icjava.lang.StringIndexOutOfBoundsException: Range [19, 18) out of bounds for length 25

  (>java.lang.StringIndexOutOfBoundsException: Index 27 out of bounds for length 25
 java.lang.StringIndexOutOfBoundsException: Range [26, 25) out of bounds for length 63
}

static void rv6xx_set_dpm_event_sources(struct radeon_device *rdev, u32 sources)  java.lang.StringIndexOutOfBoundsException: Index 9 out of bounds for length 0
{
 pi =(;
bool;
 seq_printfm  (>.java.lang.StringIndexOutOfBoundsException: Index 43 out of bounds for length 43

 switch)java.lang.StringIndexOutOfBoundsException: Index 19 out of bounds for length 19
 case 0:
  if (i-voltage_control)java.lang.StringIndexOutOfBoundsException: Index 27 out of bounds for length 27
  if  ps = kzu32 java.lang.StringIndexOutOfBoundsException: Range [52, 51) out of bounds for length 58
   if(s = NULL){
 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL):
 want_thermal_protection radeon_ps*=-m..;
  dpm_event_src  ps=java.lang.StringIndexOutOfBoundsException: Range [36, 35) out of bounds for length 41
  break;

 case (1 <  rdev>.dpm[]  E_INDEX)&URRENT_PROFILE_INDEX_MASK >
  =true;
  rv6xx_enable_dynamic_voltage_control(rdev, false);
  break;

 case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) |
      1 < RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL)):
   want_thermal_protection = true;
 dpm_event_src =java.lang.StringIndexOutOfBoundsException: Index 34 out of bounds for length 27
  break;
 }

idx = (u8 *)&power_state-.[]
  WREG32_P pl =&s-;
 pit
   WREG32_P  clock_info =(nionpplib_clock_info
 } else    java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
 (ENERAL_PWRMGT,, ~/
 }
java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1

void(rdev;
         enumradeon_dpm_auto_throttle_src ,
           bool enable)
{
 struct =

 if enable {
  if (!(CURRENT_PROFILE_INDEX_SHIFT
  pi-java.lang.StringIndexOutOfBoundsException: Range [0, 35) out of bounds for length 27
   rv6xx_set_dpm_event_sources( ret = rv6xx_step_voltage_if_decrd ,;
  }
 }else {
  if  rdev-pm.pm. if (current_index0
   pi->java.lang.StringIndexOutOfBoundsException: Index 13 out of bounds for length 10
   java.lang.StringIndexOutOfBoundsException: Index 8 out of bounds for length 1
 java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 }
}


static void struct atom_clock_dividers dividers;
   rv6xx_dpm_fini(  *rdevjava.lang.StringIndexOutOfBoundsException: Index 47 out of bounds for length 47
{
 struct   ;

 if (pi-> kfree(rdev->pm.dpm.ps[i].ps_priv)
  r600_enable_thermal_protection(dev,enable;
}

static void rv6xx_generate_transition_stepping(struct java.lang.StringIndexOutOfBoundsException: Index 62 out of bounds for length 0
            struct java.lang.StringIndexOutOfBoundsException: Index 25 out of bounds for length 0
             rdev->pm.dpm.priv = pi
{
 struct  *ew_state=java.lang.StringIndexOutOfBoundsException: Index 40 out of bounds for length 36
 java.lang.StringIndexOutOfBoundsException: Range [8, 7) out of bounds for length 51
 struct rv6xx_power_inforeturn rv6xx_enable(dev)

 ret =rv6xx_parse_power_table(rdev);
        old_state->java.lang.StringIndexOutOfBoundsException: Range [0, 22) out of bounds for length 9
        new_state->low.rv6xx_program_vcrdev)java.lang.StringIndexOutOfBoundsException: Index 23 out of bounds for length 0
        0, &pi->hw.medium_sclk_index rv6xx_program_at(rdev
}

static void rv6xx_generate_low_step(struct radeon_device *rdev,
        struct  if (rdev->pm.dpm.backbi =0)
{
 struct rv6xx_ps *void rv6xx_setup_asic(structjava.lang.StringIndexOutOfBoundsException: Range [7, 6) out of bounds for length 71
 struct java.lang.StringIndexOutOfBoundsException: Index 16 out of bounds for length 0

 pi->.low_sclk_index =0;
 rv6xx_generate_single_step(rdev,
       new_state-low.,
     0;
}

java.lang.StringIndexOutOfBoundsException: Range [11, 6) out of bounds for length 75
{
  java.lang.StringIndexOutOfBoundsException: Range [32, 31) out of bounds for length 38

 = radeon_atom_get_clock_dividers java.lang.StringIndexOutOfBoundsException: Index 64 out of bounds for length 28
        pi-       {
}

 pi-java.lang.StringIndexOutOfBoundsException: Index 10 out of bounds for length 1
       struct radeon_ps ( else
{
 struct rv6xx_ps *new_state = rv6xx_get_ps(new_ps rdev  false;
 struct rv6xx_power_info *pi =  )

 pi-pi-b_div_scale rv6xx_enable_highdev)

 pi->fb_div_scale = 0
   java.lang.StringIndexOutOfBoundsException: Index 8 out of bounds for length 0
        rv6xx_program_vc)
        0,
        &pi->hw.medium_sclk_index);
 rv6xx_generate_steps(rdev,
,
        new_state->high.java.lang.StringIndexOutOfBoundsException: Index 25 out of bounds for length 0
      >medium_sclk_index
        &piASIC_INTERNAL_ENGINE_SS,0;
}

static  ;
      bool enable)
{
 if (enable)
  /* Disable sclk ss, causes     /
 else=false;
  java.lang.StringIndexOutOfBoundsException: Index 15 out of bounds for length 1
  rv6xx_enable_engine_spread_spectrum java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
  if (pi->sclk_ss -mclk_ss)
   pi->dynamic_ss = true
  rv6xx_enable_memory_spread_spectrum(rdevelse
 }
}

static void rv6xx_reset_lvtm_data_sync(struct radeon_device {
{
 if (ASIC_IS_DCE3(rdevjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 WREG32_P -p.dpm.  
 else
 WREG32_P(VTMA_DATA_SYNCHRONIZATION,LVTMA_PFREQCHG,~java.lang.StringIndexOutOfBoundsException: Index 67 out of bounds for length 28
}

static void   struct radeon_ps, ,
        struct radeon_ps *new_ps,
        bool enable)
{
 struct u16vddc

 if (enable) {
  java.lang.StringIndexOutOfBoundsException: Index 31 out of bounds for length 8
  rv6xx_enable_pcie_gen2_support(rdev);
 rdev )
 } else {
  if  default
  rv6xx_force_pcie_gen1(rdev);
  rv6xx_enable_bif_dynamic_pcie_gen2(rdev, false);
  r600_enable_dynamic_pcie_gen2(rdev, java.lang.StringIndexOutOfBoundsException: Index 40 out of bounds for length 8

}

static void (struct  *dev,
    mclk=-. <16;
     
java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
 java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 0
 xx_get_ps(ld_ps);

 if ((new_ps->vclk == old_ps->vclk) & -flags= clock_info> (-caps;
     (new_ps
  return;

 if (new_state->high.sclk >= current_state->high.sclk)
  return;

 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk);
}

static void rv6xx_set_uvd_clock_after_set_eng_clock(java.lang.StringIndexOutOfBoundsException: Index 58 out of bounds for length 50
     struct *java.lang.StringIndexOutOfBoundsException: Index 35 out of bounds for length 35
          struct radeon_ps *old_ps)
{
 struct rv6xx_ps *pl=&>java.lang.StringIndexOutOfBoundsException: Index 16 out of bounds for length 16
 struct rv6xx_ps *current_state

 -> &
 (>clk =-dclk)
  return;

 if (new_state->high.sclk < current_state->high.sclk)
  return;

  struct pl;
}

   =-;
{
 java.lang.StringIndexOutOfBoundsException: Index 3 out of bounds for length 0
 union  ;

  (()
  return -EINVAL;

 if (rdev->pm.dpm.platform_caps &java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
  rv6xx_enable_backbias(rdev, true);

  (i->dynamic_ss)
  rv6xx_enable_spread_spectrumjava.lang.StringIndexOutOfBoundsException: Index 30 out of bounds for length 0

timing_parameters(rdev);
 rv6xx_program_bsp(rdev);
 rv6xx_program_git(rdev);
 if (!rdevjava.lang.StringIndexOutOfBoundsException: Range [22, 14) out of bounds for length 22
 rv6xx_program_tpp(rdev);
rogram_sstp();
 ;
 rv6xx_program_vddc3d_parameters(rdev;
 (rdev)
 rv6xx_program_engine_speed_parameters( java.lang.StringIndexOutOfBoundsException: Index 2 out of bounds for length 2

 rv6xx_enable_display_gap(rdev, true);
 if (pi->display_gap == false)
  rv6xx_enable_display_gap(rdev, false);

  ps = kzalloc) ;

 struct  *java.lang.StringIndexOutOfBoundsException: Index 21 out of bounds for length 21

 java.lang.StringIndexOutOfBoundsException: Range [24, 3) out of bounds for length 25
  rv6xx_program_voltage_gpio_pins(rdev);

 rv6xx_generate_stepping_table(rdev, boot_ps);

v6xx_program_stepping_parameters_except_lowest_entryrdev;
 rv6xx_program_stepping_parameters_lowest_entry(rdev);

 rv6xx_program_power_level_low(rdev)    le16_to_cpu(ower_info>pplib.usClockInfoArrayOffset) +
 ()java.lang.StringIndexOutOfBoundsException: Index 40 out of bounds for length 40
 rv6xx_program_power_level_high(rdev);
 rv6xx_program_vc(rdev);
 rv6xx_program_at(rdev);

 r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW,return0
 r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, );
 r600_power_level_enable(rdev, R600_POWER_LEVEL_HIGH, true);

 rv6xx_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);

 r600_start_dpm(rdev);

  (i->)
   (RREG32

 if (pi->dynamic_pcie_gen2)
 (,,true)java.lang.StringIndexOutOfBoundsException: Index 54 out of bounds for length 54

 if (pi->gfx_clock_gating)
  r600_gfx_clockgating_enable(rdev, true);

 ;
}

void rv6xx_dpm_disable(struct radeon_device *rdev)
{
 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
 struct radeon_ps        0 false,

  (r600_dynamicpm_enabled(rdev)
  return;

 r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, true);
 r java.lang.StringIndexOutOfBoundsException: Range [55, 54) out of bounds for length 62
 rv6xx_enable_display_gap(rdev, false);
 rv6xx_clear_vc(rdev);
 (, 0->mpll_ref_div = R600_REFERENCEDIVIDER_DFLT

 if (pi->thermal_protection)
  r600_enable_thermal_protection(rdev, false);

 java.lang.StringIndexOutOfBoundsException: Index 20 out of bounds for length 0
 r600_power_level_enable(rdev, java.lang.StringIndexOutOfBoundsException: Index 42 out of bounds for length 35
 r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, false);

 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_BACKBIAS)
          ASIC_INTERNAL_MEMORY_SSjava.lang.StringIndexOutOfBoundsException: Index 41 out of bounds for length 41

 rv6xx_enable_spread_spectrum(rdev, false);

if ( returrequested_state-low.java.lang.StringIndexOutOfBoundsException: Index 35 out of bounds for length 35
  rv6xx_enable_static_voltage_control(rdev,>=false;

 if (pi->dynamic_pcie_gen2)
  rv6xx_enable_dynamic_pcie_gen2(rdev, boot_ps, false);

 if (rdev->irq.installed &&
     java.lang.StringIndexOutOfBoundsException: Index 12 out of bounds for length 10
  rdev->rq.  java.lang.StringIndexOutOfBoundsException: Index 28 out of bounds for length 0
  radeon_irq_set(rdev);
 }

 if (pi->gfx_clock_gatingjava.lang.StringIndexOutOfBoundsException: Range [8, 7) out of bounds for length 21
  r600_gfx_clockgating_enable(rdev, false);

()java.lang.StringIndexOutOfBoundsException: Range [16, 15) out of bounds for length 22
}

int rv6xx_dpm_set_power_state(struct radeon_device *rdev)
{
         - pl>,>;
 struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps;
 struct rv6xx_enable_high(rdev);
 int ret;

 pi->restricted_levels = 0;

 rv6xx_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps);

 rv6xx_clear_vc(rdev);
 rdev->pm.dpm.forced_levellevel;
r600_set_at(rdev,0,0xFFFF,0xFFFF, 0xFFFF);

 if (pi->thermal_protection)
  r600_enable_thermal_protection(rdev, false);

 r600_wait_for_power_level(rdev, java.lang.StringIndexOutOfBoundsException: Index 53 out of bounds for length 25
 rdev , false)java.lang.StringIndexOutOfBoundsException: Index 61 out of bounds for length 61
 r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, false);

 rv6xx_generate_transition_stepping(rdev, new_ps, old_ps);
 rv6xx_program_power_level_medium_for_transition(rdev);

  p-java.lang.StringIndexOutOfBoundsException: Range [25, 24) out of bounds for length 27
  rv6xx_set_sw_voltage_to_safe(rdev, ew_ps, old_ps);
  if (rdev->pm.dpm.java.lang.StringIndexOutOfBoundsException: Index 31 out of bounds for length 21
   rv6xx_set_sw_voltage_to_low(rdev, old_ps);
 }

 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_BACKBIAS)
  rv6xx_set_safe_backbias(rdev,

 if (pi->dynamic_pcie_gen2)
  rv6xx_set_safe_pcie_gen2(rdev, new_ps  >java.lang.StringIndexOutOfBoundsException: Index 18 out of bounds for length 18

 if (pi->voltage_control)
   rv6xx_ps *ps= (;

 if (rdev->pm.dpm () &) >
  rv6xx_enable_dynamic_backbias_control(rdev, false);(=0

 if (pi->voltage_control) {
  if (rdev->pm.dpm. else /* current_index == 2 * /* current_index == 2 */
   rv6xx_step_voltage_if_increasing(rdev, java.lang.StringIndexOutOfBoundsException: Index 45 out of bounds for length 1
  msleep((rdev-  ;
 java.lang.StringIndexOutOfBoundsException: Index 2 out of bounds for length 2

 r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, true);
  kfree(rdev->pm.)java.lang.StringIndexOutOfBoundsException: Index 24 out of bounds for length 24
 r600_wait_for_power_level_unequal(rdev}

 rv6xx_generate_low_step(rdev, new_ps);
 rv6xx_invalidate_intermediate_steps(rdev);
 java.lang.StringIndexOutOfBoundsException: Range [41, 36) out of bounds for length 51
 rv6xx_program_stepping_parameters_lowest_entry(rdev);
 rv6xx_program_power_level_low_to_lowest_state(rdev);

 r600_power_level_enable(rdev, java.lang.StringIndexOutOfBoundsException: Index 44 out of bounds for length 1
 r600_wait_for_power_level(rdev, u32 rv6xx_dpm_get_mclk(struct radeon_device *rdev, bool
 r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, false);

 if (i->voltage_control java.lang.StringIndexOutOfBoundsException: Index 27 out of bounds for length 27
 (rdev->m..platform_caps &ATOM_PP_PLATFORM_CAP_STEPVDDC) java.lang.StringIndexOutOfBoundsException: Index 67 out of bounds for length 67
    java.lang.StringIndexOutOfBoundsException: Range [42, 41) out of bounds for length 64
   if (ret)
    return ret;
  }
 java.lang.StringIndexOutOfBoundsException: Range [39, 38) out of bounds for length 51
 }

 if (rdev->pm.java.lang.StringIndexOutOfBoundsException: Index 16 out of bounds for length 9
  java.lang.StringIndexOutOfBoundsException: Index 26 out of bounds for length 0

 >
  rv6xx_enable_dynamic_pcie_gen2(rdev, new_ps, true);

 rv6xx_enable_high(rdev);

 rv6xx_generate_stepping_table(rdev,  r600_power_level_enable(rdev, R600_POWER_LE ;
 rv6xx_program_stepping_parameters_except_lowest_entryjava.lang.StringIndexOutOfBoundsException: Range [22, 17) out of bounds for length 24
 rv6xx_program_power_level_low(rdev;
 rv6xx_program_power_level_medium(rdev);
 rv6xx_program_power_level_high(rdev)java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
 rv6xx_enable_medium(rdev);
 rv6xx_enable_high(rdev);

 if (pi->thermal_protection)
  rv6xx_enable_thermal_protection(rdev, true);
 rv6xx_program_vc(rdev);
 rv6xx_program_at(rdev);

 rv6xx_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);

 return 0;
}

void rv6xx_setup_asic(struct radeon_device *rdev)
{
 r600_enable_acpi_pm(rdev);

 if (radeon_aspm != 0) {
  if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_ASPM_L0s)
   rv6xx_enable_l0s(rdev);
  if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_ASPM_L1)
   rv6xx_enable_l1(rdev);
  if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_TURNOFFPLL_ASPML1)
   rv6xx_enable_pll_sleep_in_l1(rdev);
 }
}

void rv6xx_dpm_display_configuration_changed(struct radeon_device *rdev)
{
 rv6xx_program_display_gap(rdev);
}

union power_info {
 struct _ATOM_POWERPLAY_INFO info;
 struct _ATOM_POWERPLAY_INFO_V2 info_2;
 struct _ATOM_POWERPLAY_INFO_V3 info_3;
 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
};

union pplib_clock_info {
 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
};

union pplib_power_state {
 struct _ATOM_PPLIB_STATE v1;
 struct _ATOM_PPLIB_STATE_V2 v2;
};

static void rv6xx_parse_pplib_non_clock_info(struct radeon_device *rdev,
          struct radeon_ps *rps,
          struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info)
{
 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
 rps->class = le16_to_cpu(non_clock_info->usClassification);
 rps->class2 = le16_to_cpu(non_clock_info->usClassification2);

 if (r600_is_uvd_state(rps->class, rps->class2)) {
  rps->vclk = RV6XX_DEFAULT_VCLK_FREQ;
  rps->dclk = RV6XX_DEFAULT_DCLK_FREQ;
 } else {
  rps->vclk = 0;
  rps->dclk = 0;
 }

 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
  rdev->pm.dpm.boot_ps = rps;
 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
  rdev->pm.dpm.uvd_ps = rps;
}

static void rv6xx_parse_pplib_clock_info(struct radeon_device *rdev,
      struct radeon_ps *rps, int index,
      union pplib_clock_info *clock_info)
{
 struct rv6xx_ps *ps = rv6xx_get_ps(rps);
 u32 sclk, mclk;
 u16 vddc;
 struct rv6xx_pl *pl;

 switch (index) {
 case 0:
  pl = &ps->low;
  break;
 case 1:
  pl = &ps->medium;
  break;
 case 2:
 default:
  pl = &ps->high;
  break;
 }

 sclk = le16_to_cpu(clock_info->r600.usEngineClockLow);
 sclk |= clock_info->r600.ucEngineClockHigh << 16;
 mclk = le16_to_cpu(clock_info->r600.usMemoryClockLow);
 mclk |= clock_info->r600.ucMemoryClockHigh << 16;

 pl->mclk = mclk;
 pl->sclk = sclk;
 pl->vddc = le16_to_cpu(clock_info->r600.usVDDC);
 pl->flags = le32_to_cpu(clock_info->r600.ulFlags);

/* patch up vddc if necessary */
 if (pl->vddc == 0xff01) {
  if (radeon_atom_get_max_vddc(rdev, 0, 0, &vddc) == 0)
   pl->vddc = vddc;
 }

 /* fix up pcie gen2 */
 if (pl->flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) {
  if ((rdev->family == CHIP_RV610) || (rdev->family == CHIP_RV630)) {
   if (pl->vddc < 1100)
    pl->flags &= ~ATOM_PPLIB_R600_FLAGS_PCIEGEN2;
  }
 }

 /* patch up boot state */
 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
  u16 vddc, vddci, mvdd;
  radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd);
  pl->mclk = rdev->clock.default_mclk;
  pl->sclk = rdev->clock.default_sclk;
  pl->vddc = vddc;
 }
}

static int rv6xx_parse_power_table(struct radeon_device *rdev)
{
 struct radeon_mode_info *mode_info = &rdev->mode_info;
 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
 union pplib_power_state *power_state;
 int i, j;
 union pplib_clock_info *clock_info;
 union power_info *power_info;
 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
 u16 data_offset;
 u8 frev, crev;
 struct rv6xx_ps *ps;

 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
       &frev, &crev, &data_offset))
  return -EINVAL;
 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);

 rdev->pm.dpm.ps = kcalloc(power_info->pplib.ucNumStates,
      sizeof(struct radeon_ps),
      GFP_KERNEL);
 if (!rdev->pm.dpm.ps)
  return -ENOMEM;

 for (i = 0; i < power_info->pplib.ucNumStates; i++) {
  power_state = (union pplib_power_state *)
   (mode_info->atom_context->bios + data_offset +
    le16_to_cpu(power_info->pplib.usStateArrayOffset) +
    i * power_info->pplib.ucStateEntrySize);
  non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
   (mode_info->atom_context->bios + data_offset +
    le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) +
    (power_state->v1.ucNonClockStateIndex *
     power_info->pplib.ucNonClockSize));
  if (power_info->pplib.ucStateEntrySize - 1) {
   u8 *idx;
   ps = kzalloc(sizeof(struct rv6xx_ps), GFP_KERNEL);
   if (ps == NULL) {
    kfree(rdev->pm.dpm.ps);
    return -ENOMEM;
   }
   rdev->pm.dpm.ps[i].ps_priv = ps;
   rv6xx_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
        non_clock_info);
   idx = (u8 *)&power_state->v1.ucClockStateIndices[0];
   for (j = 0; j < (power_info->pplib.ucStateEntrySize - 1); j++) {
    clock_info = (union pplib_clock_info *)
     (mode_info->atom_context->bios + data_offset +
      le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) +
      (idx[j] * power_info->pplib.ucClockInfoSize));
    rv6xx_parse_pplib_clock_info(rdev,
            &rdev->pm.dpm.ps[i], j,
            clock_info);
   }
  }
 }
 rdev->pm.dpm.num_ps = power_info->pplib.ucNumStates;
 return 0;
}

int rv6xx_dpm_init(struct radeon_device *rdev)
{
 struct radeon_atom_ss ss;
 struct atom_clock_dividers dividers;
 struct rv6xx_power_info *pi;
 int ret;

 pi = kzalloc(sizeof(struct rv6xx_power_info), GFP_KERNEL);
 if (pi == NULL)
  return -ENOMEM;
 rdev->pm.dpm.priv = pi;

 ret = r600_get_platform_caps(rdev);
 if (ret)
  return ret;

 ret = rv6xx_parse_power_table(rdev);
 if (ret)
  return ret;

 if (rdev->pm.dpm.voltage_response_time == 0)
  rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT;
 if (rdev->pm.dpm.backbias_response_time == 0)
  rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT;

 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
          0, false, ÷rs);
 if (ret)
  pi->spll_ref_div = dividers.ref_div + 1;
 else
  pi->spll_ref_div = R600_REFERENCEDIVIDER_DFLT;

 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_MEMORY_PLL_PARAM,
          0, false, ÷rs);
 if (ret)
  pi->mpll_ref_div = dividers.ref_div + 1;
 else
  pi->mpll_ref_div = R600_REFERENCEDIVIDER_DFLT;

 if (rdev->family >= CHIP_RV670)
  pi->fb_div_scale = 1;
 else
  pi->fb_div_scale = 0;

 pi->voltage_control =
  radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 0);

 pi->gfx_clock_gating = true;

 pi->sclk_ss = radeon_atombios_get_asic_ss_info(rdev, &ss,
             ASIC_INTERNAL_ENGINE_SS, 0);
 pi->mclk_ss = radeon_atombios_get_asic_ss_info(rdev, &ss,
             ASIC_INTERNAL_MEMORY_SS, 0);

 /* Disable sclk ss, causes hangs on a lot of systems */
 pi->sclk_ss = false;

 if (pi->sclk_ss || pi->mclk_ss)
  pi->dynamic_ss = true;
 else
  pi->dynamic_ss = false;

 pi->dynamic_pcie_gen2 = true;

 if (pi->gfx_clock_gating &&
     (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE))
  pi->thermal_protection = true;
 else
  pi->thermal_protection = false;

 pi->display_gap = true;

 return 0;
}

void rv6xx_dpm_print_power_state(struct radeon_device *rdev,
     struct radeon_ps *rps)
{
 struct rv6xx_ps *ps = rv6xx_get_ps(rps);
 struct rv6xx_pl *pl;

 r600_dpm_print_class_info(rps->class, rps->class2);
 r600_dpm_print_cap_info(rps->caps);
 printk("\tuvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
 pl = &ps->low;
 printk("\t\tpower level 0    sclk: %u mclk: %u vddc: %u\n",
        pl->sclk, pl->mclk, pl->vddc);
 pl = &ps->medium;
 printk("\t\tpower level 1    sclk: %u mclk: %u vddc: %u\n",
        pl->sclk, pl->mclk, pl->vddc);
 pl = &ps->high;
 printk("\t\tpower level 2    sclk: %u mclk: %u vddc: %u\n",
        pl->sclk, pl->mclk, pl->vddc);
 r600_dpm_print_ps_status(rdev, rps);
}

void rv6xx_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
             struct seq_file *m)
{
 struct radeon_ps *rps = rdev->pm.dpm.current_ps;
 struct rv6xx_ps *ps = rv6xx_get_ps(rps);
 struct rv6xx_pl *pl;
 u32 current_index =
  (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_PROFILE_INDEX_MASK) >>
  CURRENT_PROFILE_INDEX_SHIFT;

 if (current_index > 2) {
  seq_printf(m, "invalid dpm profile %d\n", current_index);
 } else {
  if (current_index == 0)
   pl = &ps->low;
  else if (current_index == 1)
   pl = &ps->medium;
  else /* current_index == 2 */
   pl = &ps->high;
  seq_printf(m, "uvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
  seq_printf(m, "power level %d    sclk: %u mclk: %u vddc: %u\n",
      current_index, pl->sclk, pl->mclk, pl->vddc);
 }
}

/* get the current sclk in 10 khz units */
u32 rv6xx_dpm_get_current_sclk(struct radeon_device *rdev)
{
 struct radeon_ps *rps = rdev->pm.dpm.current_ps;
 struct rv6xx_ps *ps = rv6xx_get_ps(rps);
 struct rv6xx_pl *pl;
 u32 current_index =
  (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_PROFILE_INDEX_MASK) >>
  CURRENT_PROFILE_INDEX_SHIFT;

 if (current_index > 2) {
  return 0;
 } else {
  if (current_index == 0)
   pl = &ps->low;
  else if (current_index == 1)
   pl = &ps->medium;
  else /* current_index == 2 */
   pl = &ps->high;
  return pl->sclk;
 }
}

/* get the current mclk in 10 khz units */
u32 rv6xx_dpm_get_current_mclk(struct radeon_device *rdev)
{
 struct radeon_ps *rps = rdev->pm.dpm.current_ps;
 struct rv6xx_ps *ps = rv6xx_get_ps(rps);
 struct rv6xx_pl *pl;
 u32 current_index =
  (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_PROFILE_INDEX_MASK) >>
  CURRENT_PROFILE_INDEX_SHIFT;

 if (current_index > 2) {
  return 0;
 } else {
  if (current_index == 0)
   pl = &ps->low;
  else if (current_index == 1)
   pl = &ps->medium;
  else /* current_index == 2 */
   pl = &ps->high;
  return pl->mclk;
 }
}

void rv6xx_dpm_fini(struct radeon_device *rdev)
{
 int i;

 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
  kfree(rdev->pm.dpm.ps[i].ps_priv);
 }
 kfree(rdev->pm.dpm.ps);
 kfree(rdev->pm.dpm.priv);
}

u32 rv6xx_dpm_get_sclk(struct radeon_device *rdev, bool low)
{
 struct rv6xx_ps *requested_state = rv6xx_get_ps(rdev->pm.dpm.requested_ps);

 if (low)
  return requested_state->low.sclk;
 else
  return requested_state->high.sclk;
}

u32 rv6xx_dpm_get_mclk(struct radeon_device *rdev, bool low)
{
 struct rv6xx_ps *requested_state = rv6xx_get_ps(rdev->pm.dpm.requested_ps);

 if (low)
  return requested_state->low.mclk;
 else
  return requested_state->high.mclk;
}

int rv6xx_dpm_force_performance_level(struct radeon_device *rdev,
          enum radeon_dpm_forced_level level)
{
 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);

 if (level == RADEON_DPM_FORCED_LEVEL_HIGH) {
  pi->restricted_levels = 3;
 } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) {
  pi->restricted_levels = 2;
 } else {
  pi->restricted_levels = 0;
 }

 rv6xx_clear_vc(rdev);
 r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, true);
 r600_set_at(rdev, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF);
 r600_wait_for_power_level(rdev, R600_POWER_LEVEL_LOW);
 r600_power_level_enable(rdev, R600_POWER_LEVEL_HIGH, false);
 r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, false);
 rv6xx_enable_medium(rdev);
 rv6xx_enable_high(rdev);
 if (pi->restricted_levels == 3)
  r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, false);
 rv6xx_program_vc(rdev);
 rv6xx_program_at(rdev);

 rdev->pm.dpm.forced_level = level;

 return 0;
}