/* * Copyright 2013 Red Hat Inc . * * Permission is hereby granted , free of charge , to any person obtaining a * copy of this software and associated documentation files ( the " Software " ) , * to deal in the Software without restriction , including without limitation * the rights to use , copy , modify , merge , publish , distribute , sublicense , * and / or sell copies of the Software , and to permit persons to whom the * Software is furnished to do so , subject to the following conditions : * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software . * * THE SOFTWARE IS PROVIDED " AS IS " , WITHOUT WARRANTY OF ANY KIND , EXPRESS OR * IMPLIED , INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY , * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT . IN NO EVENT SHALL * THE COPYRIGHT HOLDER ( S ) OR AUTHOR ( S ) BE LIABLE FOR ANY CLAIM , DAMAGES OR * OTHER LIABILITY , WHETHER IN AN ACTION OF CONTRACT , TORT OR OTHERWISE , * ARISING FROM , OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE . * * Authors : Ben Skeggs * Roy Spliet < rspliet @ eclipso . eu > #define gt215_ram(p) container_of((p), struct gt215_ram, base)#include "ram.h" #include "ramfuc.h" #include <core/memory.h>#include <core/option.h>#include <subdev/bios.h>#include <subdev/bios/M0205.h>#include <subdev/bios/rammap.h>#include <subdev/bios/timing.h>#include <subdev/clk/gt215.h>#include <subdev/gpio.h>struct gt215_ramfuc {struct ramfuc base;struct ramfuc_reg r_0x001610;struct ramfuc_reg r_0x001700;struct ramfuc_reg r_0x002504;struct ramfuc_reg r_0x004000;struct ramfuc_reg r_0x004004;struct ramfuc_reg r_0x004018;struct ramfuc_reg r_0x004128;struct ramfuc_reg r_0x004168;struct ramfuc_reg r_0x100080;struct ramfuc_reg r_0x100200;struct ramfuc_reg r_0x100210;struct ramfuc_reg r_0x100220[9 ];struct ramfuc_reg r_0x100264;struct ramfuc_reg r_0x1002d0;struct ramfuc_reg r_0x1002d4;struct ramfuc_reg r_0x1002dc;struct ramfuc_reg r_0x10053c;struct ramfuc_reg r_0x1005a0;struct ramfuc_reg r_0x1005a4;struct ramfuc_reg r_0x100700;struct ramfuc_reg r_0x100714;struct ramfuc_reg r_0x100718;struct ramfuc_reg r_0x10071c;struct ramfuc_reg r_0x100720;struct ramfuc_reg r_0x100760;struct ramfuc_reg r_0x1007a0;struct ramfuc_reg r_0x1007e0;struct ramfuc_reg r_0x100da0;struct ramfuc_reg r_0x10f804;struct ramfuc_reg r_0x1110e0;struct ramfuc_reg r_0x111100;struct ramfuc_reg r_0x111104;struct ramfuc_reg r_0x1111e0;struct ramfuc_reg r_0x111400;struct ramfuc_reg r_0x611200;struct ramfuc_reg r_mr[4 ];struct ramfuc_reg r_gpio[4 ];struct gt215_ltrain {enum {struct nvkm_memory *memory;struct gt215_ram {struct nvkm_ram base;struct gt215_ramfuc fuc;struct gt215_ltrain ltrain;static void struct gt215_ltrain *train)int i, lo, hi;8 ], bins[4 ] = {0 , 0 , 0 , 0 }, bin = 0 , qty = 0 ;for (i = 0 ; i < 8 ; i++) {for (lo = 0 ; lo < 0 x40; lo++) {if (!(vals[lo] & 0 x80000000))continue ;if (vals[lo] & (0 x101 << i))break ;if (lo == 0 x40)return ;for (hi = lo + 1 ; hi < 0 x40; hi++) {if (!(vals[lo] & 0 x80000000))continue ;if (!(vals[hi] & (0 x101 << i))) {break ;1 ) + lo;0 xf0) >> 4 ]++;0 x30;/* Find the best value for 0x1111e0 */ for (i = 0 ; i < 4 ; i++) {if (bins[i] > qty) {3 ;0 ;for (i = 0 ; i < 8 ; i++) {4 ));4 ) | 0 xf));0 x0f) << (i << 2 ));0 x02000000 | (bin * 0 x101);0 x0;/* * Link training for ( at least ) DDR3 static int struct gt215_ram *ram)struct gt215_ltrain *train = &ram->ltrain;struct gt215_ramfuc *fuc = &ram->fuc;struct nvkm_subdev *subdev = &ram->base.fb->subdev;struct nvkm_device *device = subdev->device;struct nvkm_bios *bios = device->bios;struct nvkm_clk *clk = device->clk;int ret, i;struct nvbios_M0205T M0205T = { 0 };unsigned int clk_current;unsigned long flags;unsigned long *f = &flags;if (nvkm_boolopt(device->cfgopt, "NvMemExec" , true ) != true )return -ENOSYS;/* XXX: Multiple partitions? */ 64 , sizeof (u32), GFP_KERNEL);if (!result)return -ENOMEM;/* Clock speeds for training and back */ if (M0205T.freq == 0 ) {return -ENOENT;if (ret)goto out;/* First: clock up/down */ 1000 );if (ret)goto out;/* Do this *after* calc, eliminates write in script */ 0 x111400, 0 x00000000);/* XXX: Magic writes that improve train reliability? */ 0 x100674, 0 x0000ffff, 0 x00000000);0 x1005e4, 0 x0000ffff, 0 x00000000);0 x100b0c, 0 x000000ff, 0 x00000000);0 x100c04, 0 x00000400);/* Now the training script */ 0 x001700);0 x100200, 0 x00000800, 0 x00000000);0 x611200, 0 x3300);0 x611200, 0 x00000003, 0 x00000000, 500000 );0 x001610, 0 x00000083, 0 x00000003);0 x100080, 0 x00000020, 0 x00000000);0 x10f804, 0 x80000000, 0 x00000000);0 x001700, 0 x00000000);/* Reset */ 0 x10f804, 0 x80000000, 0 x80000000);0 x10053c, 0 x0);0 x100720, train->r_100720);0 x1111e0, train->r_1111e0);0 x111400, train->r_111400);0 x100080);0 x100080, 0 x00000020, 0 x00000020);1000 );0 x001700, r1700);0 x001610, 0 x00000083, 0 x00000080);0 x611200, 0 x3330);0 x100200, 0 x00000800, 0 x00000800);true );true );/* Post-processing, avoids flicker */ 0 x616308, 0 x10, 0 x10);0 x616b08, 0 x10, 0 x10);64 );for (i = 0 ; i < 64 ; i++)"Train: %08x" , result[i]);"Train: %08x %08x %08x" , train->r_100720,return ret;if (ret == -EBUSY)return ret;static int struct gt215_ram *ram)static const u32 pattern[16 ] = {0 xaaaaaaaa, 0 xcccccccc, 0 xdddddddd, 0 xeeeeeeee,0 x00000000, 0 x11111111, 0 x44444444, 0 xdddddddd,0 x33333333, 0 x55555555, 0 x77777777, 0 x66666666,0 x99999999, 0 x88888888, 0 xeeeeeeee, 0 xbbbbbbbb,struct gt215_ltrain *train = &ram->ltrain;struct nvkm_device *device = ram->base.fb->subdev.device;struct nvkm_bios *bios = device->bios;struct nvbios_M0205E M0205E;int ret, i = 0 ;/* We support type "5" if (!nvbios_M0205Ep(bios, i, &ver, &hdr, &cnt, &len, &M0205E))return -ENOENT;if (M0205E.type != 5 )return 0 ;0 x01, 16 , 0 x8000,true , true , &ram->ltrain.memory);if (ret)return ret;0 x100538, 0 x10000000 | (addr >> 16 ));0 x1005a8, 0 x0000ffff);0 x10f800, 0 x00000001, 0 x00000001);for (i = 0 ; i < 0 x30; i++) {0 x10f8c0, (i << 8 ) | i);0 x10f900, pattern[i % 16 ]);for (i = 0 ; i < 0 x30; i++) {0 x10f8e0, (i << 8 ) | i);0 x10f920, pattern[i % 16 ]);/* And upload the pattern */ 0 x1700);0 x1700, addr >> 16 );for (i = 0 ; i < 16 ; i++)0 x700000 + (i << 2 ), pattern[i]);for (i = 0 ; i < 16 ; i++)0 x700100 + (i << 2 ), pattern[i]);0 x1700, r001700);0 x100720);0 x1111e0);0 x111400);return 0 ;static void struct gt215_ram *ram)/* * RAM reclocking #define T(t) cfg->timing_10_## tstatic int struct gt215_ram *ram, u32 *timing)struct nvbios_ramcfg *cfg = &ram->base.target.bios;struct nvkm_subdev *subdev = &ram->base.fb->subdev;struct nvkm_device *device = subdev->device;int tUNK_base, tUNK_40_0, prevCL;0 x100228);0 x10022c);0 x10023c);0 x100240);switch ((!T(CWL)) * ram->base.type) {case NVKM_RAM_TYPE_DDR2:1 ;break ;case NVKM_RAM_TYPE_GDDR3:0 xff000000) >> 24 ) + 1 ;break ;0 x000000ff) + 1 ;0 x00ff0000) >> 16 ) - prevCL;0 ] = (T(RP) << 24 | T(RAS) << 16 | T(RFC) << 8 | T(RC));1 ] = (T(WR) + 1 + T(CWL)) << 24 |18 ), 1 ) << 16 |1 + T(CWL)) << 8 |5 + T(CL) - T(CWL));2 ] = (T(CWL) - 1 ) << 24 |16 ) |8 ) |3 ] = (cur3 & 0 x00ff0000) |0 x30 + T(CL)) << 24 |0 xb + T(CL)) << 8 |1 );4 ] = T(20 ) << 24 |21 ) << 16 |13 ) << 8 |13 );5 ] = T(RFC) << 24 |16 |6 ), (T(CL) + 2 )) << 8 |6 ] = (0 x5a + T(CL)) << 16 |1 , (6 - T(CL) + T(CWL))) << 8 |0 x50 + T(CL) - T(CWL));7 ] = (cur7 & 0 xff000000) |16 ) |0 x202;8 ] = cur8 & 0 xffffff00;switch (ram->base.type) {case NVKM_RAM_TYPE_DDR2:case NVKM_RAM_TYPE_GDDR3:0 xff);if (tUNK_40_0 > 0 )8 ] |= T(CL);break ;default :break ;"Entry: 220: %08x %08x %08x %08x\n" ,0 ], timing[1 ], timing[2 ], timing[3 ]);" 230: %08x %08x %08x %08x\n" ,4 ], timing[5 ], timing[6 ], timing[7 ]);" 240: %08x\n" , timing[8 ]);return 0 ;#undef Tstatic void struct gt215_ramfuc *fuc)0 ], 0 x100, 0 x100);1000 );0 ], 0 x100, 0 x000);1000 );static void struct gt215_ramfuc *fuc, u32 *mr)1 ]);if (!(mr1_old & 0 x1)) {0 x1002d4, 0 x00000001);1 ], mr[1 ]);1000 );static void struct gt215_ramfuc *fuc, u32 *mr)1 ]);if (!(mr1_old & 0 x40)) {1 ], mr[1 ]);1000 );static void struct gt215_ramfuc *fuc, struct gt215_clk_info *mclk)0 x004004, mclk->pll);0 x004000, 0 x00000001, 0 x00000001);0 x004000, 0 x00000010, 0 x00000000);0 x004000, 0 x00020000, 0 x00020000, 64000 );0 x004000, 0 x00000010, 0 x00000010);static void struct gt215_ramfuc *fuc, u8 tag, u32 val)struct nvkm_gpio *gpio = fuc->base.fb->subdev.device->gpio;struct dcb_gpio_func func;int ret;if (nvkm_gpio_get(gpio, 0 , tag, DCB_GPIO_UNUSED) != val) {0 , tag, DCB_GPIO_UNUSED, &func);if (ret)return ;3 ;0 x7) << 2 ;if (gpio_val & (8 << sh))if (!(func.log[1 ] & 1 ))0 x3 << sh), ((val | 0 x2) << sh));20000 );static int struct nvkm_ram *base, u32 freq)struct gt215_ram *ram = gt215_ram(base);struct gt215_ramfuc *fuc = &ram->fuc;struct gt215_ltrain *train = &ram->ltrain;struct nvkm_subdev *subdev = &ram->base.fb->subdev;struct nvkm_device *device = subdev->device;struct nvkm_bios *bios = device->bios;struct gt215_clk_info mclk;struct nvkm_gpio *gpio = device->gpio;struct nvkm_ram_data *next;int ret, i;9 ];bool pll2pll;if (ram->ltrain.state == NVA3_TRAIN_ONCE)/* lookup memory config data relevant to the target frequency */ 1000 , &ver, &hdr, &cnt, &len,if (!data || ver != 0 x10 || hdr < 0 x05) {"invalid/missing rammap entry\n" );return -EINVAL;/* locate specific data set for the attached memory */ if (strap >= cnt) {"invalid ramcfg strap\n" );return -EINVAL;if (!data || ver != 0 x10 || hdr < 0 x09) {"invalid/missing ramcfg entry\n" );return -EINVAL;/* lookup memory timings, if bios says they're present */ if (next->bios.ramcfg_timing != 0 xff) {if (!data || ver != 0 x10 || hdr < 0 x17) {"invalid/missing timing entry\n" );return -EINVAL;0 x12, 0 x4000, freq, &mclk);if (ret < 0 ) {"failed mclk calculation\n" );return ret;if (ret)return ret;/* Determine ram-specific MR values */ 0 ] = ram_rd32(fuc, mr[0 ]);1 ] = ram_rd32(fuc, mr[1 ]);2 ] = ram_rd32(fuc, mr[2 ]);switch (ram->base.type) {case NVKM_RAM_TYPE_DDR2:break ;case NVKM_RAM_TYPE_DDR3:break ;case NVKM_RAM_TYPE_GDDR3:break ;default :break ;if (ret)return ret;/* XXX: 750MHz seems rather arbitrary */ if (freq <= 750000 ) {0 x10000000;0 x22222222;0 x00000010;else {0 x00000000;0 x00000000;0 x00000000;if (!next->bios.ramcfg_DLLoff)0 x00004000;/* pll2pll requires to switch to a safe clock first */ 0 x004000);0 x00000008)) && mclk.pll;/* Pre, NVIDIA does this outside the script */ if (next->bios.ramcfg_10_02_10) {0 x111104, 0 x00000600, 0 x00000000);else {0 x111100, 0 x40000000, 0 x40000000);0 x111104, 0 x00000180, 0 x00000000);/* Always disable this bit during reclock */ 0 x100200, 0 x00000800, 0 x00000000);/* If switching from non-pll to pll, lock before disabling FB */ if (mclk.pll && !pll2pll) {0 x004128, 0 x003f3141, mclk.clk | 0 x00000101);/* Start with disabling some CRTCs and PFIFO? */ 0 x611200, 0 x3300);0 x002504, 0 x1, 0 x1);10000 );0 x002504, 0 x10, 0 x10, 20000 ); /* XXX: or longer? */ 2000 );if (!next->bios.ramcfg_10_02_10) {if (ram->base.type == NVKM_RAM_TYPE_GDDR3)0 x111100, 0 x04020000, 0 x00020000);else 0 x111100, 0 x04020000, 0 x04020000);/* If we're disabling the DLL, do it now */ switch (next->bios.ramcfg_DLLoff * ram->base.type) {case NVKM_RAM_TYPE_DDR3:break ;case NVKM_RAM_TYPE_GDDR3:break ;if (next->bios.timing_10_ODT)0 x2e, 1 );/* Brace RAM for impact */ 0 x1002d4, 0 x00000001);0 x1002d0, 0 x00000001);0 x1002d0, 0 x00000001);0 x100210, 0 x00000000);0 x1002dc, 0 x00000001);2000 );if (device->chipset == 0 xa3 && freq <= 500000 )0 x100700, 0 x00000006, 0 x00000006);/* Alter FBVDD/Q, apparently must be done with PLL disabled, thus if (nvkm_gpio_get(gpio, 0 , 0 x18, DCB_GPIO_UNUSED) ==0 x004000) & 0 x9;if (data == 0 x1)0 x004000, 0 x8, 0 x8);if (data & 0 x1)0 x004000, 0 x1, 0 x0);0 x18, !next->bios.ramcfg_FBVDDQ);if (data & 0 x1)0 x004000, 0 x1, 0 x1);/* Fiddle with clocks */ /* There's 4 scenario's * pll - > pll : first switch to a 324 MHz clock , set up new PLL , switch * clk - > pll : Set up new PLL , switch * pll - > clk : Set up clock , switch /* Switch to regular clock - 324MHz */ if (pll2pll) {0 x004000, 0 x00000004, 0 x00000004);0 x004168, 0 x003f3141, 0 x00083101);0 x004000, 0 x00000008, 0 x00000008);0 x1110e0, 0 x00088000, 0 x00088000);0 x004018, 0 x00001000);if (mclk.pll) {0 x004000, 0 x00000105, 0 x00000105);0 x004018, 0 x00001000 | r004018);0 x100da0, r100da0);else {0 x004168, 0 x003f3141, mclk.clk | 0 x00000101);0 x004000, 0 x00000108, 0 x00000008);0 x1110e0, 0 x00088000, 0 x00088000);0 x004018, 0 x00009000 | r004018);0 x100da0, r100da0);20000 );if (next->bios.rammap_10_04_08) {0 x1005a0, next->bios.ramcfg_10_06 << 16 |8 |0 x1005a4, next->bios.ramcfg_10_08 << 8 |0 x10f804, next->bios.ramcfg_10_09_f0 << 20 |16 |0 x80000000);0 x10053c, 0 x00001000, 0 x00000000);else {if (train->state == NVA3_TRAIN_DONE) {0 x100080, 0 x1020);0 x111400, 0 xffffffff, train->r_111400);0 x1111e0, 0 xffffffff, train->r_1111e0);0 x100720, 0 xffffffff, train->r_100720);0 x10053c, 0 x00001000, 0 x00001000);0 x10f804, 0 x80000000, 0 x00000000);0 x100760, 0 x22222222, r100760);0 x1007a0, 0 x22222222, r100760);0 x1007e0, 0 x22222222, r100760);if (device->chipset == 0 xa3 && freq > 500000 ) {0 x100700, 0 x00000006, 0 x00000000);/* Final switch */ if (mclk.pll) {0 x1110e0, 0 x00088000, 0 x00011000);0 x004000, 0 x00000008, 0 x00000000);0 x1002dc, 0 x00000000);0 x1002d4, 0 x00000001);0 x100210, 0 x80000000);2000 );/* Set RAM MR parameters and timings */ for (i = 2 ; i >= 0 ; i--) {if (ram_rd32(fuc, mr[i]) != ram->base.mr[i]) {1000 );0 x100220[3 ], timing[3 ]);0 x100220[1 ], timing[1 ]);0 x100220[6 ], timing[6 ]);0 x100220[7 ], timing[7 ]);0 x100220[2 ], timing[2 ]);0 x100220[4 ], timing[4 ]);0 x100220[5 ], timing[5 ]);0 x100220[0 ], timing[0 ]);0 x100220[8 ], timing[8 ]);/* Misc */ 0 x100200, 0 x00001000, !next->bios.ramcfg_10_02_08 << 12 );/* XXX: A lot of "chipset"/"ram type" specific stuff...? */ 0 x100714) & ~0 xf0000130;0 x100718) & ~0 x00000100;0 x10071c) & ~0 x00000100;0 x111100) & ~0 x3a800000;/* NVA8 seems to skip various bits related to ramcfg_10_02_04 */ if (device->chipset == 0 xa8) {0 x08000000;if (!next->bios.ramcfg_10_02_04)0 x00000010;else {if (next->bios.ramcfg_10_02_04) {switch (ram->base.type) {case NVKM_RAM_TYPE_DDR2:case NVKM_RAM_TYPE_DDR3:0 x00000020;if (next->bios.ramcfg_10_02_10)0 x08000004;else 0 x00000024;break ;default :break ;else {switch (ram->base.type) {case NVKM_RAM_TYPE_DDR2:case NVKM_RAM_TYPE_DDR3:0 x00000024;0 x12800000;if (next->bios.ramcfg_10_02_10)0 x08000000;0 x00000010;break ;case NVKM_RAM_TYPE_GDDR3:0 x30000000;0 x00000020;break ;default :break ;8 ;if (next->bios.ramcfg_10_02_20)0 xf0000000;if (next->bios.ramcfg_10_02_02)0 x00000100;if (next->bios.ramcfg_10_02_01)0 x00000100;if (next->bios.timing_10_24 != 0 xff) {0 xf0000000;28 ;if (next->bios.ramcfg_10_02_10)0 x04020000;0 x100714, 0 xffffffff, unk714);0 x10071c, 0 xffffffff, unk71c);0 x100718, 0 xffffffff, unk718);0 x111100, 0 xffffffff, r111100);if (!next->bios.timing_10_ODT)0 x2e, 0 );/* Reset DLL */ if (!next->bios.ramcfg_DLLoff)if (ram->base.type == NVKM_RAM_TYPE_GDDR3) {31000 );else {14000 );if (ram->base.type == NVKM_RAM_TYPE_DDR3) {0 x100264, 0 x1);2000 );0 x100700);0 x100700, 0 x01000000, 0 x01000000);0 x100700, 0 x01000000, 0 x00000000);/* Re-enable FB */ 0 x611200, 0 x3330);/* Post fiddlings */ if (next->bios.rammap_10_04_02)0 x100200, 0 x00000800, 0 x00000800);if (next->bios.ramcfg_10_02_10) {0 x111104, 0 x00000180, 0 x00000180);0 x111100, 0 x40000000, 0 x00000000);else {0 x111104, 0 x00000600, 0 x00000600);if (mclk.pll) {0 x004168, 0 x00000001, 0 x00000000);0 x004168, 0 x00000100, 0 x00000000);else {0 x004000, 0 x00000001, 0 x00000000);0 x004128, 0 x00000001, 0 x00000000);0 x004128, 0 x00000100, 0 x00000000);return 0 ;static int struct nvkm_ram *base)struct gt215_ram *ram = gt215_ram(base);struct gt215_ramfuc *fuc = &ram->fuc;struct nvkm_device *device = ram->base.fb->subdev.device;bool exec = nvkm_boolopt(device->cfgopt, "NvMemExec" , true );if (exec) {0 x001534, 0 x2, 0 x2);true );/* Post-processing, avoids flicker */ 0 x002504, 0 x1, 0 x0);0 x001534, 0 x2, 0 x0);0 x616308, 0 x10, 0 x10);0 x616b08, 0 x10, 0 x10);else {false );return 0 ;static void struct nvkm_ram *base)struct gt215_ram *ram = gt215_ram(base);false );static int struct nvkm_ram *base)struct gt215_ram *ram = gt215_ram(base);return 0 ;static void *struct nvkm_ram *base)struct gt215_ram *ram = gt215_ram(base);return ram;static const struct nvkm_ram_funcint struct nvkm_fb *fb, struct nvkm_ram **pram)struct gt215_ram *ram;int ret, i;if (!(ram = kzalloc(sizeof (*ram), GFP_KERNEL)))return -ENOMEM;if (ret)return ret;0 x001610);0 x001700);0 x002504);0 x004000);0 x004004);0 x004018);0 x004128);0 x004168);0 x100080);0 x100200);0 x100210);for (i = 0 ; i < 9 ; i++)0 x100220 + (i * 4 ));0 x100264);0 x1002d0);0 x1002d4);0 x1002dc);0 x10053c);0 x1005a0);0 x1005a4);0 x100700);0 x100714);0 x100718);0 x10071c);0 x100720);0 x100760, 4 , ram->base.part_mask);0 x1007a0, 4 , ram->base.part_mask);0 x1007e0, 4 , ram->base.part_mask);0 x100da0, 4 , ram->base.part_mask);0 x10f804);0 x1110e0, 4 , ram->base.part_mask);0 x111100);0 x111104);0 x1111e0);0 x111400);0 x611200);if (ram->base.ranks > 1 ) {0 ] = ramfuc_reg2(0 x1002c0, 0 x1002c8);1 ] = ramfuc_reg2(0 x1002c4, 0 x1002cc);2 ] = ramfuc_reg2(0 x1002e0, 0 x1002e8);3 ] = ramfuc_reg2(0 x1002e4, 0 x1002ec);else {0 ] = ramfuc_reg(0 x1002c0);1 ] = ramfuc_reg(0 x1002c4);2 ] = ramfuc_reg(0 x1002e0);3 ] = ramfuc_reg(0 x1002e4);0 ] = ramfuc_reg(0 x00e104);1 ] = ramfuc_reg(0 x00e108);2 ] = ramfuc_reg(0 x00e120);3 ] = ramfuc_reg(0 x00e124);return 0 ;
Messung V0.5 in Prozent C=97 H=92 G=94
¤ Dauer der Verarbeitung: 0.21 Sekunden
(vorverarbeitet am 2026-10-07)
¤ *© Formatika GbR, Deutschland
