/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ /* Copyright (c) 2023 Imagination Technologies Ltd. */ #ifndef PVR_ROGUE_META_H#define PVR_ROGUE_META_H/***** The META HW register definitions in the file are updated manually *****/ #include <linux/bits.h>#include <linux/types.h>/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * META registers and MACROS * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * #define META_CR_CTRLREG_BASE(t) (0 x04800000U + (0 x1000U * (t)))#define META_CR_TXPRIVEXT (0 x048000E8)#define META_CR_TXPRIVEXT_MINIM_EN BIT(7 )#define META_CR_SYSC_JTAG_THREAD (0 x04830030)#define META_CR_SYSC_JTAG_THREAD_PRIV_EN (0 x00000004)#define META_CR_PERF_COUNT0 (0 x0480FFE0)#define META_CR_PERF_COUNT1 (0 x0480FFE8)#define META_CR_PERF_COUNT_CTRL_SHIFT (28 )#define META_CR_PERF_COUNT_CTRL_MASK (0 xF0000000)#define META_CR_PERF_COUNT_CTRL_DCACHEHITS (8 << META_CR_PERF_COUNT_CTRL_SHIFT)#define META_CR_PERF_COUNT_CTRL_ICACHEHITS (9 << META_CR_PERF_COUNT_CTRL_SHIFT)#define META_CR_PERF_COUNT_CTRL_ICACHEMISS \0 xA << META_CR_PERF_COUNT_CTRL_SHIFT)#define META_CR_PERF_COUNT_CTRL_ICORE (0 xD << META_CR_PERF_COUNT_CTRL_SHIFT)#define META_CR_PERF_COUNT_THR_SHIFT (24 )#define META_CR_PERF_COUNT_THR_MASK (0 x0F000000)#define META_CR_PERF_COUNT_THR_0 (0 x1 << META_CR_PERF_COUNT_THR_SHIFT)#define META_CR_PERF_COUNT_THR_1 (0 x2 << META_CR_PERF_COUNT_THR_1)#define META_CR_TxVECINT_BHALT (0 x04820500)#define META_CR_PERF_ICORE0 (0 x0480FFD0)#define META_CR_PERF_ICORE1 (0 x0480FFD8)#define META_CR_PERF_ICORE_DCACHEMISS (0 x8)#define META_CR_PERF_COUNT(ctrl, thr) \## ctrl << META_CR_PERF_COUNT_CTRL_SHIFT) | \#define META_CR_TXUXXRXDT_OFFSET (META_CR_CTRLREG_BASE(0 U) + 0 x0000FFF0U)#define META_CR_TXUXXRXRQ_OFFSET (META_CR_CTRLREG_BASE(0 U) + 0 x0000FFF8U)/* Poll for done. */ #define META_CR_TXUXXRXRQ_DREADY_BIT (0 x80000000U)/* Set for read. */ #define META_CR_TXUXXRXRQ_RDnWR_BIT (0 x00010000U)#define META_CR_TXUXXRXRQ_TX_S (12 )#define META_CR_TXUXXRXRQ_RX_S (4 )#define META_CR_TXUXXRXRQ_UXX_S (0 )/* Internal ctrl regs. */ #define META_CR_TXUIN_ID (0 x0)/* Data unit regs. */ #define META_CR_TXUD0_ID (0 x1)/* Data unit regs. */ #define META_CR_TXUD1_ID (0 x2)/* Address unit regs. */ #define META_CR_TXUA0_ID (0 x3)/* Address unit regs. */ #define META_CR_TXUA1_ID (0 x4)/* PC registers. */ #define META_CR_TXUPC_ID (0 x5)/* Macros to calculate register access values. */ #define META_CR_CORE_REG(thr, reg_num, unit) \#define META_CR_THR0_PC META_CR_CORE_REG(0 , 0 , META_CR_TXUPC_ID)#define META_CR_THR0_PCX META_CR_CORE_REG(0 , 1 , META_CR_TXUPC_ID)#define META_CR_THR0_SP META_CR_CORE_REG(0 , 0 , META_CR_TXUA0_ID)#define META_CR_THR1_PC META_CR_CORE_REG(1 , 0 , META_CR_TXUPC_ID)#define META_CR_THR1_PCX META_CR_CORE_REG(1 , 1 , META_CR_TXUPC_ID)#define META_CR_THR1_SP META_CR_CORE_REG(1 , 0 , META_CR_TXUA0_ID)#define SP_ACCESS(thread) META_CR_CORE_REG(thread, 0 , META_CR_TXUA0_ID)#define PC_ACCESS(thread) META_CR_CORE_REG(thread, 0 , META_CR_TXUPC_ID)#define META_CR_COREREG_ENABLE (0 x0000000U)#define META_CR_COREREG_STATUS (0 x0000010U)#define META_CR_COREREG_DEFR (0 x00000A0U)#define META_CR_COREREG_PRIVEXT (0 x00000E8U)#define META_CR_T0ENABLE_OFFSET \0 U) + META_CR_COREREG_ENABLE)#define META_CR_T0STATUS_OFFSET \0 U) + META_CR_COREREG_STATUS)#define META_CR_T0DEFR_OFFSET (META_CR_CTRLREG_BASE(0 U) + META_CR_COREREG_DEFR)#define META_CR_T0PRIVEXT_OFFSET \0 U) + META_CR_COREREG_PRIVEXT)#define META_CR_T1ENABLE_OFFSET \1 U) + META_CR_COREREG_ENABLE)#define META_CR_T1STATUS_OFFSET \1 U) + META_CR_COREREG_STATUS)#define META_CR_T1DEFR_OFFSET (META_CR_CTRLREG_BASE(1 U) + META_CR_COREREG_DEFR)#define META_CR_T1PRIVEXT_OFFSET \1 U) + META_CR_COREREG_PRIVEXT)#define META_CR_TXENABLE_ENABLE_BIT (0 x00000001U) /* Set if running */ #define META_CR_TXSTATUS_PRIV (0 x00020000U)#define META_CR_TXPRIVEXT_MINIM (0 x00000080U)#define META_MEM_GLOBAL_RANGE_BIT (0 x80000000U)#define META_CR_TXCLKCTRL (0 x048000B0)#define META_CR_TXCLKCTRL_ALL_ON (0 x55111111)#define META_CR_TXCLKCTRL_ALL_AUTO (0 xAA222222)#define META_CR_MMCU_LOCAL_EBCTRL (0 x04830600)#define META_CR_MMCU_LOCAL_EBCTRL_ICWIN (0 x3 << 14 )#define META_CR_MMCU_LOCAL_EBCTRL_DCWIN (0 x3 << 6 )#define META_CR_SYSC_DCPART(n) (0 x04830200 + (n) * 0 x8)#define META_CR_SYSC_DCPARTX_CACHED_WRITE_ENABLE (0 x1 << 31 )#define META_CR_SYSC_ICPART(n) (0 x04830220 + (n) * 0 x8)#define META_CR_SYSC_XCPARTX_LOCAL_ADDR_OFFSET_TOP_HALF (0 x8 << 16 )#define META_CR_SYSC_XCPARTX_LOCAL_ADDR_FULL_CACHE (0 xF)#define META_CR_SYSC_XCPARTX_LOCAL_ADDR_HALF_CACHE (0 x7)#define META_CR_MMCU_DCACHE_CTRL (0 x04830018)#define META_CR_MMCU_ICACHE_CTRL (0 x04830020)#define META_CR_MMCU_XCACHE_CTRL_CACHE_HITS_EN (0 x1)/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * META LDR Format * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * /* Block header structure. */ struct rogue_meta_ldr_block_hdr {/* High level data stream block structure. */ struct rogue_meta_ldr_l1_data_blk {4 ];/* High level data stream block structure. */ struct rogue_meta_ldr_l2_data_blk {4 ];/* Config command structure. */ struct rogue_meta_ldr_cfg_blk {4 ];/* Block type definitions */ #define ROGUE_META_LDR_COMMENT_TYPE_MASK (0 x0010U)#define ROGUE_META_LDR_BLK_IS_COMMENT(x) (((x) & ROGUE_META_LDR_COMMENT_TYPE_MASK) != 0 U)/* * Command definitions * Value Name Description * 0 LoadMem Load memory with binary data . * 1 LoadCore Load a set of core registers . * 2 LoadMMReg Load a set of memory mapped registers . * 3 StartThreads Set each thread PC and SP , then enable threads . * 4 ZeroMem Zeros a memory region . * 5 Config Perform a configuration command . #define ROGUE_META_LDR_CMD_MASK (0 x000FU)#define ROGUE_META_LDR_CMD_LOADMEM (0 x0000U)#define ROGUE_META_LDR_CMD_LOADCORE (0 x0001U)#define ROGUE_META_LDR_CMD_LOADMMREG (0 x0002U)#define ROGUE_META_LDR_CMD_START_THREADS (0 x0003U)#define ROGUE_META_LDR_CMD_ZEROMEM (0 x0004U)#define ROGUE_META_LDR_CMD_CONFIG (0 x0005U)/* * Config Command definitions * Value Name Description * 0 Pause Pause for x times 100 instructions * 1 Read Read a value from register - No value return needed . * Utilises effects of issuing reads to certain registers * 2 Write Write to mem location * 3 MemSet Set mem to value * 4 MemCheck check mem for specific value . #define ROGUE_META_LDR_CFG_PAUSE (0 x0000)#define ROGUE_META_LDR_CFG_READ (0 x0001)#define ROGUE_META_LDR_CFG_WRITE (0 x0002)#define ROGUE_META_LDR_CFG_MEMSET (0 x0003)#define ROGUE_META_LDR_CFG_MEMCHECK (0 x0004)/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * ROGUE FW segmented MMU definitions * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * /* All threads can access the segment. */ #define ROGUE_FW_SEGMMU_ALLTHRS (0 xf << 8 U)/* Writable. */ #define ROGUE_FW_SEGMMU_WRITEABLE (0 x1U << 1 U)/* All threads can access and writable. */ #define ROGUE_FW_SEGMMU_ALLTHRS_WRITEABLE \/* Direct map region 10 used for mapping GPU memory - max 8MB. */ #define ROGUE_FW_SEGMMU_DMAP_GPU_ID (10 U)#define ROGUE_FW_SEGMMU_DMAP_GPU_ADDR_START (0 x07000000U)#define ROGUE_FW_SEGMMU_DMAP_GPU_MAX_SIZE (0 x00800000U)/* Segment IDs. */ #define ROGUE_FW_SEGMMU_DATA_ID (1 U)#define ROGUE_FW_SEGMMU_BOOTLDR_ID (2 U)#define ROGUE_FW_SEGMMU_TEXT_ID (ROGUE_FW_SEGMMU_BOOTLDR_ID)/* * SLC caching strategy in S7 and volcanic is emitted through the segment MMU . * All the segments configured through the macro ROGUE_FW_SEGMMU_OUTADDR_TOP are * CACHED in the SLC . * The interface has been kept the same to simplify the code changes . * The bifdm argument is ignored ( no longer relevant ) in S7 and volcanic . #define ROGUE_FW_SEGMMU_OUTADDR_TOP_VIVT_SLC(pers, slc_policy, mmu_ctx) \0 x3)) << 52 ) | (((u64)((mmu_ctx) & 0 xFF)) << 44 ) | \0 x1)) << 40 ))#define ROGUE_FW_SEGMMU_OUTADDR_TOP_VIVT_SLC_CACHED(mmu_ctx) \0 x3, 0 x0, mmu_ctx)#define ROGUE_FW_SEGMMU_OUTADDR_TOP_VIVT_SLC_UNCACHED(mmu_ctx) \0 x0, 0 x1, mmu_ctx)/* * To configure the Page Catalog and BIF - DM fed into the BIF for Garten * accesses through this segment . #define ROGUE_FW_SEGMMU_OUTADDR_TOP_SLC(pc, bifdm) \0 xFU) << 44 U) | ((u64)((u64)(bifdm) & 0 xFU) << 40 U))#define ROGUE_FW_SEGMMU_META_BIFDM_ID (0 x7U)/* META segments have 4kB minimum size. */ #define ROGUE_FW_SEGMMU_ALIGN (0 x1000U)/* Segmented MMU registers (n = segment id). */ #define META_CR_MMCU_SEGMENT_N_BASE(n) (0 x04850000U + ((n) * 0 x10U))#define META_CR_MMCU_SEGMENT_N_LIMIT(n) (0 x04850004U + ((n) * 0 x10U))#define META_CR_MMCU_SEGMENT_N_OUTA0(n) (0 x04850008U + ((n) * 0 x10U))#define META_CR_MMCU_SEGMENT_N_OUTA1(n) (0 x0485000CU + ((n) * 0 x10U))/* * The following defines must be recalculated if the Meta MMU segments used * to access Host - FW data are changed * Current combinations are : * - SLC uncached , META cached , FW base address 0 x70000000 * - SLC uncached , META uncached , FW base address 0 xF0000000 * - SLC cached , META cached , FW base address 0 x10000000 * - SLC cached , META uncached , FW base address 0 x90000000 #define ROGUE_FW_SEGMMU_DATA_BASE_ADDRESS (0 x10000000U)#define ROGUE_FW_SEGMMU_DATA_META_CACHED (0 x0U)#define ROGUE_FW_SEGMMU_DATA_META_UNCACHED (META_MEM_GLOBAL_RANGE_BIT)#define ROGUE_FW_SEGMMU_DATA_META_CACHE_MASK (META_MEM_GLOBAL_RANGE_BIT)/* * For non - VIVT SLCs the cacheability of the FW data in the SLC is selected in * the PTEs for the FW data , not in the Meta Segment MMU , which means these * defines have no real effect in those cases . #define ROGUE_FW_SEGMMU_DATA_VIVT_SLC_CACHED (0 x0U)#define ROGUE_FW_SEGMMU_DATA_VIVT_SLC_UNCACHED (0 x60000000U)#define ROGUE_FW_SEGMMU_DATA_VIVT_SLC_CACHE_MASK (0 x60000000U)/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * ROGUE FW Bootloader defaults * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * #define ROGUE_FW_BOOTLDR_META_ADDR (0 x40000000U)#define ROGUE_FW_BOOTLDR_DEVV_ADDR_0 (0 xC0000000U)#define ROGUE_FW_BOOTLDR_DEVV_ADDR_1 (0 x000000E1)#define ROGUE_FW_BOOTLDR_DEVV_ADDR \32 ) | \#define ROGUE_FW_BOOTLDR_LIMIT (0 x1FFFF000)#define ROGUE_FW_MAX_BOOTLDR_OFFSET (0 x1000)/* Bootloader configuration offset is in dwords (512 bytes) */ #define ROGUE_FW_BOOTLDR_CONF_OFFSET (0 x80)/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * ROGUE META Stack * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * #define ROGUE_META_STACK_SIZE (0 x1000U)/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * ROGUE META Core memory * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * /* Code and data both map to the same physical memory. */ #define ROGUE_META_COREMEM_CODE_ADDR (0 x80000000U)#define ROGUE_META_COREMEM_DATA_ADDR (0 x82000000U)#define ROGUE_META_COREMEM_OFFSET_MASK (0 x01ffffffU)#define ROGUE_META_IS_COREMEM_CODE(a, b) \#define ROGUE_META_IS_COREMEM_DATA(a, b) \/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 2 nd thread * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * #define ROGUE_FW_THR1_PC (0 x18930000)#define ROGUE_FW_THR1_SP (0 x78890000)/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * META compatibility * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * #define META_CR_CORE_ID (0 x04831000)#define META_CR_CORE_ID_VER_SHIFT (16 U)#define META_CR_CORE_ID_VER_CLRMSK (0 XFF00FFFFU)#define ROGUE_CR_META_MTP218_CORE_ID_VALUE 0 x19#define ROGUE_CR_META_MTP219_CORE_ID_VALUE 0 x1E#define ROGUE_CR_META_LTP218_CORE_ID_VALUE 0 x1C#define ROGUE_CR_META_LTP217_CORE_ID_VALUE 0 x1F#define ROGUE_FW_PROCESSOR_META "META" #endif /* PVR_ROGUE_META_H */
Messung V0.5 in Prozent C=95 H=97 G=95
¤ Dauer der Verarbeitung: 0.12 Sekunden
(vorverarbeitet am 2026-09-29)
¤ *© Formatika GbR, Deutschland
